A power frequency small current leakage protection anti-low frequency conducted interference detection system and method

Abstract

The present application belongs to the technical field of charging piles, and particularly relates to a power frequency small current leakage protection anti-low frequency conducted interference detection system and method. The system comprises: a random phase shift frequency conversion oscillation module, which converts 10 kHz-150 kHz low frequency conducted interference into unstable equivalent low frequency signals by introducing random delay to control the magnetic core charging flip timing; a point frequency comb filter module, which filters and outputs the maximum effective value of the current signals of a plurality of preset power frequency harmonic points; and a power frequency current judgment module, which judges whether the effective value continuously exceeds a threshold value (such as 5 mA) and reaches a stable time (such as 50 ms) to distinguish between real leakage and interference. The method is realized based on the above system. The core advantage of the present application is that it can effectively avoid the misoperation caused by low frequency conducted interference, significantly improve the reliability of high sensitivity (5 mA) leakage protection in a complex electromagnetic environment (such as electric vehicle charging), and meet the requirements of strict safety standards such as UL2231.

Description

Technical Field

[0001] This invention relates to the field of charging piles, and more specifically, to a power frequency low current leakage protection anti-low frequency conducted interference detection system and method. Background Technology

[0002] This invention relates to the field of electrical safety protection technology, specifically to a residual current detection and protection technology applied to equipment such as electric vehicle charging piles, on-board chargers (OBC), and photovoltaic power generation systems, with a particular focus on a method and system for detecting low-frequency conducted interference in power frequency low-current leakage protection.

[0003] In applications such as electric vehicle charging, residual current protection devices operate in complex electromagnetic environments, often subjected to high-intensity radio frequency interference and low-frequency conducted interference from devices such as high-power switching power supplies. These interference signals couple into the signal acquisition circuit of the residual current detection sensor through conduction or radiation. Due to the limited resolution and dynamic range of the sensor acquisition system, interference signals may cause data distortion, leading to misjudgments by the protection circuit.

[0004] Currently, international safety standards (such as UL 2231) impose extremely stringent requirements on power frequency leakage current protection. Specifically, the UL 2231 CCID5 standard stipulates that the protection action threshold for 60Hz AC power frequency leakage current must be as low as 5mA. This stringent requirement poses a significant challenge to the anti-interference capability of the detection system. In practical applications, the small leakage currents generated by various factors (such as transformer core leakage flux, Y capacitor ground leakage, and ground discharge during OBC rectifier commutation) combined with the 10kHz to 150kHz low-frequency conducted interference generated by the switching power supply can easily cause the detection signal amplitude to exceed the threshold, even in the absence of actual power frequency leakage current, leading to malfunctions of the protection device (i.e., false alarms or tripping).

[0005] Existing residual current detection schemes mostly employ fixed-frequency fluxgate technology. Their typical operating mode involves periodically charging the detection core in the forward direction to saturation, then reversing to charge it in the reverse direction to saturation, and repeating this cycle. The core flaw of this scheme lies in its fixed sampling frequency and predictable phase. When the frequency of external low-frequency conducted interference encounters the inherent frequency or harmonic components of the sampling system, a stable equivalent low-frequency current (typically below 2kHz, possibly falling within the 10-100Hz range, or even precisely at the 50Hz or 60Hz power frequency) is generated due to "spectral aliasing" or "beat frequency" effects. This equivalent current is extremely similar in signal shape to the actual power frequency leakage current, making it impossible for subsequent processing circuits to effectively distinguish between them.

[0006] Especially during standard compliance testing, when performing continuous scanning tests on specific low-frequency interference points, if the dwell time at that frequency exceeds the sensor's de-jitter delay time, the fixed sampling scheme will almost inevitably cause malfunctions at that frequency, resulting in the product failing to pass stringent safety certifications.

[0007] Therefore, there is an urgent need for a new detection technology that can fundamentally distinguish between the real power frequency leakage current and the equivalent power frequency component generated by low-frequency conducted interference, thereby significantly improving the anti-interference capability and reliability of the system while meeting the requirements of extremely high sensitivity. Summary of the Invention

[0008] The purpose of this invention is to overcome the shortcomings of the prior art and provide a low-frequency conducted interference detection system and method for power frequency low current leakage protection. This system and method can effectively suppress the influence of low-frequency conducted interference of 10kHz~150kHz, accurately detect the real power frequency leakage signal, and avoid false operation.

[0009] To achieve the above objectives, the present invention provides the following technical solution: This invention provides a low-frequency conducted interference detection system for power frequency low-current leakage protection, characterized by comprising: a random phase-shifting frequency conversion oscillation module, a point-frequency comb filter module, and a power frequency current determination module. The random phase-shifting frequency conversion oscillation module controls the magnetic core coil to alternately charge in both forward and reverse directions with a random delay time, and collects the charging time each time the magnetic core is saturated, converting low-frequency conducted interference signals from 10kHz to 150kHz into equivalent low-frequency signals with continuously changing frequency and amplitude. The point-frequency comb filter module is connected to the random phase-shifting frequency conversion oscillation module and is used to filter current signals at multiple preset power frequency and harmonic frequency points, and output the maximum effective value of the current at the multiple frequency points. The power frequency current determination module is connected to the point-frequency comb filter module and is used to determine whether the maximum effective value of the current continuously exceeds a preset threshold and reaches a predetermined stabilization time, in order to distinguish between the actual power frequency leakage current and the equivalent current caused by interference.

[0010] Furthermore, the random phase-shift frequency conversion oscillation module includes: a bridge drive circuit, a state latch unit one, an edge transition catcher unit, a 16-bit random number generator unit, a random number latch unit, a 16-bit up counter unit two, and a 16-bit data comparator unit.

[0011] The bridge drive circuit is used to provide bidirectional charging current for the magnetic core coil; the output of the state latch unit is used to control the charging direction; the edge transition catcher unit is connected to the output of the state latch unit and is used to generate a trigger pulse when a state transition caused by magnetic core saturation is detected; the 16-bit random number generator unit is used to continuously generate random numbers.

[0012] The random number latch unit is connected to the 16-bit random number generator unit and the edge-triggered catcher unit, and is used to latch a random number on the rising edge of the trigger pulse.

[0013] The 16-bit up-counter unit 2 is connected to the edge-jumping catcher unit and is used to start counting on the falling edge of the trigger pulse; the 16-bit data comparator unit is connected to the random number latch unit and the 16-bit up-counter unit 2 and is used to output a flip pulse to the state latch unit 1 when the values ​​of the two are equal, so as to trigger the flip of the charging direction.

[0014] Furthermore, the random phase-shift frequency conversion oscillation module also includes: a 16-bit up-counter unit, a pulse width capture latch unit, and an arithmetic unit. The 16-bit up-counter unit is used to count the core charging time; the pulse width capture latch unit is connected to the 16-bit up-counter unit and the edge-jump capture unit, and is used to capture and latch the current charging time count value on the rising edge of the trigger pulse; the arithmetic unit is connected to the pulse width capture latch unit, and is used to calculate the duty cycle based on the charging time count value and convert it into a value representing the instantaneous current.

[0015] Furthermore, the point-frequency comb filter module is a digital filter, and its preset filter frequencies include 50Hz, 100Hz, 150Hz, 300Hz, 60Hz, 120Hz, 180Hz and 360Hz.

[0016] Furthermore, the power frequency current determination module includes: a filter channel current determination unit one and a 24-bit up-counter unit three. The filter channel current determination unit one is used to determine whether the effective current value of the first group of frequency points is greater than a first threshold. The 24-bit up-counter unit three is connected to the filter channel current determination unit one, and starts counting when any effective current value of the first group of frequency points is greater than the first threshold, and outputs a valid signal when the count reaches a first predetermined value. The first threshold is 5mA, and the first predetermined value corresponds to a duration of 50ms.

[0017] A method for detecting low-frequency conducted interference in power frequency low-current leakage protection includes the following steps: Random phase-shifting frequency conversion oscillation steps: By randomly delaying the timing of the forward and reverse charging of the magnetic core coil, the low-frequency conducted interference signal from 10kHz to 150kHz is randomized and converted into an equivalent low-frequency signal with constantly changing frequency and amplitude. The charging time of the magnetic core is collected to calculate the instantaneous current value. Point-frequency comb filtering steps: Perform digital filtering on the calculated current signal, calculate the effective current value of multiple preset power frequencies and their harmonic frequencies, and select the maximum value as the output; Power frequency current determination steps: Determine whether the maximum value continuously exceeds the preset current threshold and reaches a predetermined stabilization time. If so, it is determined to be a real power frequency leakage event and the protection action is triggered.

[0018] The beneficial effects of this invention are as follows: Strong anti-interference capability: By introducing a random phase shift mechanism, the concentrated low-frequency conducted interference energy is dispersed into a wide frequency band, making it impossible for it to form a stable equivalent signal that can simulate real power frequency leakage current, thus fundamentally solving the problem of malfunction at specific frequency points caused by fixed frequency sampling.

[0019] High detection accuracy: Combining point frequency comb filtering and power frequency current duration determination, it can accurately extract the true power frequency signal characteristics, effectively distinguish between interference and real faults, and meet the stringent requirements of UL2231 and other standards for low threshold (such as 5mA) and high reliability.

[0020] Wide applicability: The system design takes into account the power frequency harmonic components generated by various power consumption scenarios such as single-phase, three-phase, half-wave, and full-wave rectification. By setting multiple characteristic frequency points, it ensures the robustness of detection in different application environments.

[0021] Good real-time performance: The entire processing is based on hardware logic and digital filtering, with a fast response speed, which can meet the requirements of leakage current protection for fast action. Attached Figure Description

[0022] Figure 1 This is a schematic diagram illustrating the application of the system of the present invention.

[0023] Figure 2 This is a schematic diagram of the system of the present invention.

[0024] Figure 3 This is a partial structural diagram of the system of the present invention.

[0025] Figure 4 This is a schematic diagram of a point-frequency comb filter.

[0026] Figure 5 The timing diagram shows the process of reverse charging the magnetic core to saturation, with random delay, and then forward charging.

[0027] Figure 6 This is a timing diagram showing the process of charging the magnetic core to saturation in the forward direction, with a random delay, and then reversing the charging process. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0030] like Figure 1 As shown, the core of the power frequency low-current leakage protection and low-frequency conducted interference detection system is a dedicated integrated circuit chip U2. This chip integrates three major functional modules: I. Random Phase-Shift Frequency Conversion Oscillator Module: Composed of a bridge drive circuit, a state latch unit 1, an edge transition capture unit, a pulse width capture latch unit, a 16-bit random number generator unit, a random number latch unit, a 16-bit up-counter unit 2, and a 16-bit data comparator unit.

[0031] The 16-bit random number generator unit is composed of a linear feedback shift register (LFSR) or a pseudo-random number generator circuit. The internal register width is 16 bits, and it generates a periodic pseudo-random number sequence through polynomial feedback. The input is the system clock (48MHz), and the output is a 16-bit parallel random number. Its function is to generate a random delay reference value in each charge-flip cycle, ensuring that the oscillation period is not fixed at a certain frequency, thereby breaking down low-frequency interference and improving stability. It can use 256 sets of 16-bit pseudo-random numbers, stored in 256 registers represented by 16-bit fuses, and retrieves numbers according to a cyclic address from 0 to 255. Simulation can be performed using an MCU to define and call these 256 sets of pseudo-random numbers.

[0032] The random number latch unit is composed of a D flip-flop array or register unit, with a width of 16 bits. Its input is connected to the output of a 16-bit random number generator unit. Specifically, it can be constructed using a 74HC75 chip. One latch control pin, LE(G), is used. G=1 (high level): transparent mode, output Q follows input D; when G changes from 1 to 0 (falling edge), Q remains latched. Its function is to load the random number into the latch and keep it unchanged when the edge-triggered capture pulse rises. This prevents the random number from changing during the charging cycle, ensuring the stability of the delay determination.

[0033] 16-bit Up Counter Unit 1: Composed of a 16-bit binary adder circuit with a 48MHz clock source, featuring control logic for clearing on the rising edge and starting counting on the falling edge. Specifically, it can be constructed using a 74HC161 counter. CP is connected to the 48MHz system clock, and Q0~Q15 are output terminals. The counter increments by 1 on each rising edge of the system clock. Q0 toggles twice, Q1 toggles once, Q1 toggles twice, Q2 toggles once, and so on, requiring 2 to the power of 16 bits to toggle from 0 to the next all-zero state. It is used to measure the core charging time. The counter is cleared on the rising edge and starts counting on the falling edge, accumulating the count value throughout the entire period of core charging to saturation. The final value is sent to the pulse width capture latch unit, reflecting the forward or reverse charging time.

[0034] 16-bit Up Counter Unit Two: Also a 16-bit binary counter, its input is the system clock signal, and it has reset and count start control terminals. Its structure and working principle are the same as 16-bit Up Counter Unit One. It serves as the comparison object for random delay. After each random number is loaded, it starts counting from 0. When the count value equals the random number latch value, it triggers the data comparator to output a pulse, thereby realizing the random delay flip during the charging process.

[0035] 16-bit Data Comparator Unit: This is a 16-channel data comparator that can expand the 74HC85 chip to 16 channels. When A1=B1, A2=B2, ..., A16=B16, pin QA=B outputs a high level. Since the high level only lasts for one system clock cycle, a delay counter of 960 system clock cycles is added. The level returns to low only after the delay ends. When the two are equal, a "high-then-low" trigger pulse is output. This pulse serves as both a timing control signal for toggling and a trigger for updating the state latch unit, achieving random delay phase shift.

[0036] State latch unit 1: This is a D latch circuit with an enable pin (G pin). The input is connected to a comparator or control logic, and the output is Q and / or Q-not. Specifically, it is a 1-bit D-type latch with one latch control pin LE(G). G=0 (low level): transparent mode, output Q follows input D; G changes from 0 to 1 (rising edge), Q remains latched. Similar to the 74HC75 chip, but only one state latch is designed, with an additional NOT gate added to the LE pin for inversion. When G is low, Q output follows D input; when G is high, Q remains unchanged. It is used to lock the current direction state at the charging-flipping moment and use it to determine whether the magnetic core is currently charging in the forward or reverse direction.

[0037] State latch unit two: Also a D flip-flop structure, its input is connected to the output of state latch unit one, and its control is the comparator trigger pulse. Specifically, it is a 1-bit D-type latch with one latch control pin LE(G). G=1 (high level): transparent mode, output Q follows input D; when G changes from 1 to 0 (falling edge), Q remains latched. Similar to the 74HC75 chip, but only one state latch is designed, with no additional LE pin. During the delay flip, based on the result of state latch unit one, the conduction direction of the MOS bridge drive is controlled, thus determining whether the magnetic core enters the forward or reverse charging phase.

[0038] Edge transition catcher unit: Consists of a 2-bit shift latch and an XOR gate; specifically, an 8-bit 74HC164 shift latch can be used, with only QA, QB, and CLEAR pins fixed at high levels; AB connected as the input of the edge transition catcher unit, and CLOCK connected to the 48MHz system clock; the XOR gate chip can be a 74HC86, using only one set, with 1A connected to QA, 1B connected to QB, and 1Y as the output of the edge transition catcher unit. This unit can simultaneously capture the rising and falling edges of the input signal and output a short pulse when a transition is detected. The comparator output transitions when the magnetic core is charged to saturation point and outputs a pulse signal. This pulse triggers random number loading, counter clearing, charging time latching, and other operations to achieve boundary identification of the charging cycle.

[0039] The pulse width capture latch unit consists of two 16-bit D-type latches, which can use the 74HC75 chip. One latch stores the high-level duration, and the other stores the low-level duration. The validity of the latch clock input for each D-type latch is selected by the output level of the status latch unit. The selection of the D-type latch is determined by a NAND gate logic based on the system clock and the input level.

[0040] The module operates from a 48MHz clock source. The magnetic core coil L6 is driven by the chip's FD and RD pins via an external bridge driver circuit (containing P-MOS and N-MOS transistors) for forward and reverse charging. The charging current flows through sampling resistors R1 and R5.

[0041] When the magnetic core is fully charged, the voltage across the sampling resistor exceeds 300mV, causing comparator VC1 or VC2 to flip.

[0042] This flip signal is latched by the state latch unit, and the level change of its output Q is detected by the edge transition catcher unit, which outputs a high-then-low trigger pulse.

[0043] At the rising edge of the trigger pulse, the random number latch unit loads a 16-bit random number from the 16-bit random number generator unit, while the 16-bit up counter unit two is cleared, and the pulse width capture latch unit reads the current charging time value from the 16-bit up counter unit one.

[0044] At the falling edge of the trigger pulse, the aforementioned random number and charging time values ​​are locked, and the 16-bit up counter unit two begins to increment by 1 every clock cycle.

[0045] The 16-bit data comparator unit continuously compares the latched random number with the value of counter two. When the two are equal, a toggle pulse is output.

[0046] The rising edge of the flip pulse first latches the output of state latch unit one for approximately 20μs (providing drive stabilization time), then updates the output of state latch unit two, changing the drive levels of the FD and RD pins, thereby flipping the charging direction. Simultaneously, the arithmetic unit calculates and outputs the instantaneous current value based on the captured charging time.

[0047] This process repeats itself, making the saturation reversal time of the magnetic core no longer fixed but random, thus disrupting the synchronization relationship between external periodic interference and the sampling system.

[0048] II. Point-frequency comb filter module: It consists of filter channel current judgment unit 1, filter channel current judgment unit 2, 24-bit up counter unit 3 and 24-bit up counter unit 4.

[0049] Filter channel current judgment unit one: It consists of a comparator array and logic gate circuits, and the input is the effective value of the current at each frequency point. When the effective value of the current at all target frequency points is less than 5mA, the output is high level; if any frequency point exceeds 5mA, the output is low level, which is used as part of the power frequency current judgment signal.

[0050] Filter channel current judgment unit two: Similar to filter channel current judgment unit one, but the comparison threshold is set to 15mA. When the effective value of the current at all target frequency points is less than 15mA, a high level is output; if any frequency point exceeds 15mA, a low level is output to meet the judgment requirements of UL2231 CCID20.

[0051] 24-bit Up Counter Unit 3: Composed of a 24-bit binary counter, with a clear control terminal and output comparison logic. Used to time the duration of current under a 5mA threshold condition. When the count reaches 249F00 (approximately 50ms), a high level is output, indicating that the power frequency current is continuous; otherwise, it is considered interference.

[0052] 24-bit Up Counter Unit 4: The structure is the same as Unit 3, but the threshold and trigger conditions are different. It is used to time the duration of current under a 15mA threshold condition and outputs a high level when the current exceeds 50ms, for determining the power frequency current under the CCID20 standard.

[0053] This module receives instantaneous digital current signals from the arithmetic unit. It is a digital filter with eight bandpass filter channels configured in parallel internally, with center frequencies of 50Hz, 100Hz, 150Hz, 300Hz, 60Hz, 120Hz, 180Hz, and 360Hz. The module calculates the effective current (RMS) at these eight frequencies in real time and always selects the RMS value with the largest amplitude as its output.

[0054] III. Power Frequency Current Determination Module: This module contains two decision channels, corresponding to 5mA and 15mA thresholds respectively.

[0055] For the 5mA channel (filter channel current judgment unit one): it monitors the effective value of the frequency points (such as 50Hz, 60Hz, 100Hz, 120Hz) directly related to the 50Hz / 60Hz power frequency in the output of the point-frequency comb filter module. As long as the effective value of any frequency point is greater than 5mA, this unit will output a low level (effective signal).

[0056] This low-level signal enables the 24-bit up-counter unit three to start counting (counting clock is 48MHz). When the count value reaches 0x249F00 (corresponding to 50ms time), the counter outputs a high level (Y5), indicating that a real power frequency leakage current greater than 5mA has been detected for more than 50ms.

[0057] The 15mA channel (filter channel current judgment unit two and 24-bit up-counter unit four) operate on the same principle, only the threshold values ​​are different.

[0058] Ultimately, the Y5 and Y15 signals are output to the customer's application MCU to control the operation of protective actuators (such as relays).

[0059] A method for detecting low-frequency conducted interference in low-current leakage protection at power frequency, based on the system described in Embodiment 1, includes the following steps: S1. Random phase-shifting frequency conversion oscillation: Through the above-mentioned random delay and reversal mechanism, the magnetic core is driven and the current is collected, and the low-frequency conduction signal of 10KHZ~150KHZ is transformed into an equivalent low frequency or noise with multiple frequency changes, generating a frequency signal lower than the collection frequency, that is, a frequency signal less than 2KH.

[0060] Work process: 1.1 Assume that the reverse charging process of the magnetic core begins upon power-on. As the coil current gradually increases, it suddenly reaches a critical point, causing the magnetic core to saturate. The voltage across R1 then exceeds 300mV, resulting in comparator VC2 flipping to output a high level. The output Q of "State Latch Unit 1" experiences a level transition, changing from low to high (reverse charging saturation, pre-flipping to forward charging). The "Edge-Jump Capture Unit" detects this change and outputs a pulse that is first high and then low. The "edge jump catcher unit" outputs the rising edge: ① The "random number latch unit" follows the random value of the "16-bit random number generator unit"; ② Clear the value of the delay counter "16-bit up counter unit two" to prepare for delay counting; ③ Read the count value of the magnetic core charging time counter "16-bit Up Counter Unit 1" into the "Pulse Width Capture Latch Unit". Whether the captured magnetic core charging time is the forward charging time or the reverse charging time is indicated by the Q output status of "Status Latch Unit 1". Q equals high indicates that the previous charging was reverse, and Q equals low indicates that the previous charging was forward.

[0061] The "edge-jump catcher unit" outputs a falling edge and holds it low: ① The "random number latch unit" locks the random value and keeps it unchanged; ② The "16-bit up counter unit 2" counts, incrementing by 1 on each rising edge of the drive clock, and performs random delay counting; ③ "Pulse width capture latch unit" locks the captured core charging time value and keeps it unchanged.

[0062] ④ The “16-bit data comparator unit” continuously compares the values ​​of the “random number latch unit” and the “16-bit up counter unit two”.

[0063] 1.2 Random time-delayed flipping process, The "16-bit data comparator unit" continuously compares the values ​​of the "random number latch unit" and the "16-bit up counter unit two". When the two values ​​are equal, the "16-bit data comparator unit" outputs a pulse that goes high followed by low. The 16-bit data comparator unit outputs a rising edge and remains high: ① "State latch unit one" locks the original output unchanged, that is, it does not change with the value of the comparator at this time, giving the external drive circuit, comparator and selection circuit a waiting time (20uS) to stabilize. ② The output Q of “State Latch Unit Two” follows the change of the input D. D is determined by the locked state Q of “State Latch Unit One”. The inverse of Q makes the two sets of MOS driver transistors form a bridge drive. Since the input D of “State Latch Unit Two” is high at this time, pin 3 FD outputs a high voltage of 5V and pin 4 RD outputs a low voltage of 0V. The current flows out from pin 3 FD through R1, R7, L4, magnetic core L6, L5, R6, R5, and back to the inside of model U2 to AGND through pin 4 RD. The comparator output “Selector One” selects VC1 for magnetic saturation current acquisition because C is high at this time. Since the N terminal of VC1 is connected to pin 4 RD and the P terminal is connected to the sampling resistor R5, although P>N, there is an internal “-300mV” bias at the P terminal. When the coil just flips, the current is very small and the voltage across R5 is less than 300mV. Therefore, at this time, VC1 The output is low, and after passing through the inverter, it is output to the D input of "State Latch Unit 1" as a high level. This is exactly the same as the high level of the Q input of "State Latch Unit 1" at this time. When the G pin goes low, it will not change suddenly, ensuring that after the "16-bit data comparator unit" outputs a pulse that goes high and then low for a period of time, the output result of the selected comparator is the same as the output result of the previous comparator, so as to achieve seamless connection.

[0064] ③ The “Arithmetic Unit” reads the last positive and negative charging time of the magnetic core from the “Pulse Width Capture Latch Unit”, first calculates the duty cycle, and then converts it into a signed positive and negative instantaneous current and sends it to the point frequency comb filter. At the same time, with 0X2000 as the center, 100mA with a modulus of 4096 is converted into a 12-bit DAC value and the analog current value is output from the DAC.

[0065] The 16-bit data comparator unit outputs a falling edge and remains low: ① When “State Latch Unit 1” G is enabled, the output Q follows the input D, and Q remains at a high level. ② "State latch unit two" G is prohibited from updating output, output terminal Q is locked high level, Q is unlocked low level, so that the two sets of MOS driver transistors form a bridge drive, maintaining the output voltage of 5V high voltage at pin 3 FD and the output voltage of 0V low voltage at pin 4 RD. The current flows out from pin 3 FD through R1, R7, L4, magnetic core L6, L5, R6, R5, and then flows back to the inside of model U2 to AGND through pin 4 RD.

[0066] ③ The “Arithmetic Unit” sends the calculation results to the point frequency comb filter and the DAC module to output the analog current value.

[0067] 1.3 Forward charging process of the magnetic core As the coil current gradually increases, it suddenly reaches a critical point, causing the magnetic core to saturate. The voltage across R5 exceeds 300mV, resulting in comparator VC1 flipping to a high level. After passing through an inverter, the output is low, reaching input D of "State Latch Unit 1". At this time, due to the low level of G, "State Latch Unit 1" is in a state where the output Q follows the input of D. Therefore, the Q output changes from high to low (forward charging saturation, pre-flipping to reverse charging). The "Edge-Jump Capture Unit" detects this change and outputs a pulse that is first high and then low: The "edge jump catcher unit" outputs the rising edge: ① The "random number latch unit" follows the random value of the "16-bit random number generator unit"; ② Clear the value of the delay counter "16-bit up counter unit two" to prepare for delay counting; ③ Read the count value of the magnetic core charging time counter "16-bit Up Counter Unit 1" into the "Pulse Width Capture Latch Unit". Whether the captured magnetic core charging time is the forward charging time or the reverse charging time is indicated by the Q output status of "Status Latch Unit 1". Q equals high indicates that the previous charging was reverse, and Q equals low indicates that the previous charging was forward.

[0068] The "edge-jump catcher unit" outputs a falling edge and holds it low: ① The "random number latch unit" locks the random value and keeps it unchanged; ② The "16-bit up counter unit 2" counts, incrementing by 1 on each rising edge of the drive clock, and performs random delay counting; ③ "Pulse width capture latch unit" locks the captured core charging time value and keeps it unchanged.

[0069] ④ The “16-bit data comparator unit” continuously compares the values ​​of the “random number latch unit” and the “16-bit up counter unit two”.

[0070] 1.4 Random Time Delay Flipping Process The "16-bit data comparator unit" continuously compares the values ​​of the "random number latch unit" and the "16-bit up counter unit two". When the two values ​​are equal, the "16-bit data comparator unit" outputs a pulse that goes high followed by low. The 16-bit data comparator unit outputs a rising edge and remains high: ① "State latch unit one" locks the original output unchanged, that is, it does not change with the value of the comparator at this time, giving the external drive circuit, comparator and selection circuit a waiting time (20uS) to stabilize. ② The output Q of “State Latch Unit Two” follows the change of the input D. D is determined by the locked state Q of “State Latch Unit One”. The inverse of Q makes the two sets of MOS driver transistors form a bridge drive. Since the input D of “State Latch Unit Two” is low at this time, pin 3 FD outputs 0V low voltage and pin 4 RD outputs 5V high voltage. The current flows out from pin 4 RD through R5, R6, L5, magnetic core L6, L4, R7, R1, and returns to the inside of model U2 to AGND through pin 3 FD. The comparator output “Selector One” selects VC2 for magnetic saturation current acquisition since C is low at this time. Since the N terminal of VC2 is connected to pin 3 FD and the P terminal is connected to the sampling resistor R1, although P>N, there is an internal “-300mV” bias at the P terminal. When the coil just flips, the current is very small and the voltage across R1 is less than 300mV. Therefore, at this time, VC2 When the output is low, the D input of "State Latch Unit 1" is also low, which is exactly the same as the low level of the Q input of "State Latch Unit 1". When the G pin goes low, it will not change suddenly, ensuring that after the "16-bit data comparator unit" outputs a pulse that goes high and then low, the output result of the selected comparator is the same as the output result of the previous comparator, thus achieving seamless connection.

[0071] ③ The “Arithmetic Unit” reads the last positive and negative charging time of the magnetic core from the “Pulse Width Capture Latch Unit”, first calculates the duty cycle, and then converts it into a signed positive and negative instantaneous current and sends it to the point frequency comb filter. At the same time, with 0X2000 as the center, 100mA with a modulus of 4096 is converted into a 12-bit DAC value and the analog current value is output from the DAC.

[0072] The 16-bit data comparator unit outputs a falling edge and remains low: ① When “State Latch Unit 1” G is enabled, the output terminal Q follows the input terminal D, and Q remains at a low level. ② "State latch unit two" G is prohibited from updating output, output terminal Q is locked at low level, Q is unlocked at high level, so that the two sets of MOS driver transistors form a bridge drive, keeping the output voltage of 0V low voltage at pin 3 FD and the output voltage of 5V high voltage at pin 4 RD. The current flows out from pin 4 RD through R5, R6, L5, magnetic core L6, L4, R7, R1, and returns to the inside of model U2 to AGND through pin 3 FD.

[0073] ③ The “Arithmetic Unit” sends the calculation results to the point frequency comb filter and the DAC module to output the analog current value.

[0074] By continuously cycling through the four control steps 1.1, 1.2, 1.3, and 1.4, random phase-shifting frequency conversion oscillation is completed. This can transform low-frequency conduction signals of 10kHz to 150kHz into equivalent low-frequency (AC or DC below 2kHz) signals with continuously changing frequency and amplitude. However, for the power frequency of 50 / 60Hz, since the acquisition system frequency is 4 to 6kHz, the acquisition result is still a stable AC signal of 50 / 60Hz. This operation can make a clear characteristic difference between power frequency current and low-frequency conduction current.

[0075] S2. Point-frequency comb filtering: For the signal obtained in step S1, calculate the effective values ​​of 8 power frequency characteristic points in parallel and take the maximum value.

[0076] By using digital filters, based on 50Hz and 60Hz power frequency currents respectively, considering that single-phase half-wave rectification, full-wave rectification, three-phase half-wave rectification, and three-phase full-wave rectification may occur in use, and the CCID5 standard only requires 5mA operation for AC 60Hz, and the CCID20 standard only requires 15mA operation for AC 60Hz, other frequencies can allow larger trigger thresholds, so only the waveform anti-interference capability of small trigger values ​​such as AC 50Hz and 60Hz needs to be paid special attention to.

[0077] The center frequencies of the filter points are 50Hz, 100Hz, 150Hz, 300Hz, 60Hz, 120Hz, 180Hz, and 360Hz. The current at these frequencies is taken respectively. At any given time, the value with the largest amplitude among these 8 frequencies is taken as the average effective value of the two cycles and output.

[0078] S3. Power Frequency Current Determination: Determine whether the maximum value obtained in step S2 exceeds the set threshold (5mA or 15mA) and lasts for at least 50ms. If yes, execute the protection action; if no, determine it as interference and do not respond.

[0079] This function calculates the duration of the trigger values ​​AC50 / 60Hz 5mA and AC50 / 60Hz 15mA respectively. Under the random delay phase-shift acquisition mechanism, the equivalent low-frequency AC frequency and amplitude generated by the low-frequency conducted interference wave are constantly drifting and cannot be guaranteed to be continuously greater than the trigger value. Therefore, as long as the trigger value is continuously reached and maintained for more than 50ms, it can be determined that the acquired current is the power frequency current; otherwise, it can be considered as the equivalent current caused by the interference wave.

[0080] like Figure 5 and Figure 6The diagram illustrates the switching process of the magnetic core between forward and reverse charging, and how the random delay mechanism operates throughout the oscillation cycle. It reflects the timing relationships between units such as the 16-bit random number generator, random number latch, 16-bit counters one and two, 16-bit data comparator, state latches one and two, edge transition catcher, and pulse width capture latch. Specifically: 1. Charge the magnetic core to saturation → Edge detection When the current in the magnetic core coil gradually increases and reaches the saturation point, the output level of the analog comparator flips.

[0081] The flip is detected by the edge transition catcher unit, which immediately outputs a "high-then-low" pulse. This pulse serves as a timing reference signal, triggering multiple operations: the output of the random number generator is latched into the random number latch; the 16-bit up counter 2 is cleared and starts counting again; the current value of the 16-bit up counter 1 is read and sent to the pulse width capture latch to record the current charging time.

[0082] This step determines the end point of a complete charging cycle and prepares a random delay reference value for the next cycle.

[0083] 2. Random Delay Counting Process After the random number is latched, the 16-bit up-counter begins to increment. As the value of counter two gradually approaches the value of the random number latch, the 16-bit data comparator continuously compares the two. When they are equal, the comparator outputs a "high-then-low" pulse. This comparator pulse indicates that the "random delay time" has elapsed. In this way, a different delay is introduced before each charge flip, causing a random phase shift in the core charging oscillation cycle.

[0084] 3. State latch toggling and drive control After the comparator output pulse, state latch unit one locks or updates output Q, indicating the current direction (forward / reverse). State latch unit two receives the state signal and controls the MOS bridge drive circuit: if Q is high, the driver enters the forward charging phase; if Q is low, the driver enters the reverse charging phase. By randomly delaying and then triggering the latch to flip, the change in the core charging direction has random phase characteristics, breaking up the fixed frequency points of interference signals.

[0085] 4. Pulse Width Acquisition and Calculation At each toggle, the pulse width capture latch stores the current charging time (a count value indicating a sustained high or low level). This value is fed into the arithmetic logic unit (ALU) for duty cycle calculation and converted into a signed instantaneous current value. The result is output as an analog current via a DAC (Digital-to-Analog Converter) for subsequent frequency filtering. This step achieves the conversion from "time information" to "current information," ensuring that the final output reflects the true power frequency current while maintaining its ability to distinguish random disturbances.

[0086] 5. The entire timing cycle The timing diagram is divided into two cases: core reverse charging → saturation → random delay → flip to forward charging; core forward charging → saturation → random delay → flip to reverse charging. These two processes cycle repeatedly, with each flip involving: core charging saturation → edge detection → random number latching → counter comparison → random delay → state flip → entering the next charging direction. Through continuous cycling, the entire oscillation system forms a random phase-variable frequency oscillation, causing the input 10kHz~150kHz interference signal to appear as a continuously changing equivalent low-frequency signal (<2kHz) at the output. The actual power frequency 50 / 60Hz signal remains stable under this mechanism, thus distinguishing the interference from the actual signal.

[0087] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any ordinary changes and substitutions made by those skilled in the art within the scope of the technical solution of the present invention should be included within the protection scope of the present invention.

Claims

1. A low-frequency conducted interference detection system for power frequency low-current leakage protection, characterized in that, include: The random phase-shifting frequency conversion oscillation module is used to control the magnetic core coil to perform alternating forward and reverse charging with random delay time, and to collect the charging time each time the magnetic core is saturated, converting the low-frequency conducted interference signal from 10kHz to 150kHz into an equivalent low-frequency signal with constantly changing frequency and amplitude. The point frequency comb filter module is connected to the random phase-shift frequency conversion oscillation module and is used to filter the current signals of multiple preset power frequency and harmonic frequency points, and output the maximum value of the effective current value among the multiple frequency points. The power frequency current determination module is connected to the point frequency comb filter module and is used to determine whether the maximum value of the effective value of the current continues to exceed a preset threshold and reaches a predetermined stabilization time, so as to distinguish between the real power frequency leakage current and the equivalent current caused by interference. The random phase-shift frequency conversion oscillation module includes: A bridge drive circuit is used to provide bidirectional charging current to the magnetic core coil; State latch unit one, the output of which is used to control the charging direction; An edge transition catcher unit is connected to the output of the state latch unit 1 and is used to generate a trigger pulse when a state transition caused by core saturation is detected. A 16-bit random number generator unit is used to continuously generate random numbers; A random number latch unit, connected to the 16-bit random number generator unit and the edge-jumping catcher unit, is used to latch a random number on the rising edge of the trigger pulse; The second 16-bit up-counter unit is connected to the edge transition catcher unit and is used to start counting on the falling edge of the trigger pulse; A 16-bit data comparator unit, connected to the random number latch unit and the second 16-bit up counter unit, is used to output a flip pulse to the first state latch unit when the values ​​of the two are equal, so as to trigger the flip of the charging direction.

2. The system according to claim 1, characterized in that, The random phase-shift frequency conversion oscillation module further includes: 16-bit up-counter unit one, used to count the charging time of the magnetic core; A pulse width capture latch unit, connected to the 16-bit up counter unit and the edge transition capture unit, is used to capture and latch the current charging time count value at the rising edge of the trigger pulse. An arithmetic unit, connected to the pulse width capture latch unit, is used to calculate the duty cycle based on the charging time count value and convert it into a value representing the instantaneous current.

3. The system according to claim 1, characterized in that, The bridge drive circuit includes a P-MOS transistor and an N-MOS transistor controlled by state latch unit two, and the input of state latch unit two is determined by the output state of state latch unit one.

4. The system according to claim 1, characterized in that, The point-frequency comb filter module is a digital filter, and its preset filter frequencies include at least 50Hz, 100Hz, 150Hz, 300Hz, 60Hz, 120Hz, 180Hz and 360Hz.

5. The system according to claim 1, characterized in that, The power frequency current determination module includes: The filter channel current judgment unit 1 is used to determine whether the effective value of the current at the first group of frequency points is greater than the first threshold. The 24-bit up-counter unit three is connected to the filter channel current judgment unit one. When any effective current value in the first group of frequency points is greater than the first threshold, it starts counting and outputs an effective signal when the count reaches the first predetermined value, indicating that a continuous real power frequency leakage current has been detected.

6. The system according to claim 5, characterized in that, The power frequency current determination module also includes: The second filter channel current judgment unit is used to determine whether the effective value of the current at the second group of frequency points is greater than the second threshold. The 24-bit up-counter unit four is connected to the filter channel current judgment unit two. It starts counting when any effective current value in the second group of frequency points is greater than the second threshold, and outputs an effective signal when the count reaches the second predetermined value. Wherein, the first threshold is 5mA, the second threshold is 15mA, and both the first and second predetermined values ​​correspond to a duration of 50ms.

7. A detection method using the low-frequency conducted interference detection system for power frequency low-current leakage protection as described in any one of claims 1-6, characterized in that, Includes the following steps: Random phase-shifting frequency conversion oscillation steps: By randomly delaying the timing of the forward and reverse charging of the magnetic core coil, the low-frequency conducted interference signal from 10kHz to 150kHz is randomized and converted into an equivalent low-frequency signal with constantly changing frequency and amplitude. The charging time of the magnetic core is collected to calculate the instantaneous current value. Point-frequency comb filtering steps: Perform digital filtering on the calculated current signal, calculate the effective current value of multiple preset power frequencies and their harmonic frequencies, and select the maximum value as the output; Power frequency current determination steps: Determine whether the maximum value continuously exceeds the preset current threshold and reaches a predetermined stabilization time. If so, it is determined to be a real power frequency leakage event and the protection action is triggered.

8. The method according to claim 7, characterized in that, The random phase-shift frequency conversion oscillation step specifically includes: When the magnetic core is fully charged, an edge trigger pulse is generated. At the rising edge of the trigger pulse, a random number is captured and a delay counter is cleared. At the falling edge of the trigger pulse, the random number is locked and the delay counter is started to count; The count value of the delay counter is compared with a locked random number; When the two are equal, a flip signal is generated to control the charging direction of the magnetic core coil to flip, and a fixed stable delay time is introduced.

9. The method according to claim 7, characterized in that, The preset current thresholds include 5mA and 15mA, and the predetermined settling time is 50ms; the method is applicable to leakage protection devices that meet the CCID5 or CCID20 requirements in the UL2231 standard.

Images