An implementation method of sidelobe cancellation algorithm based on FPGA and HLS

Abstract

The application relates to the technical field of digital signal processing, in particular to an implementation method of a sidelobe cancellation algorithm based on FPGA and HLS. Complex operations such as matrix inversion in the sidelobe cancellation algorithm are implemented through HLS, HLS adopts the programming mode of C / C++, and can quickly realize iteration and upgrading of IP configuration. Other operations in the sidelobe cancellation algorithm are implemented through FPGA, so that the relationship between the consumed resources and processing delay of large data processing is balanced. The collaborative work of FPGA and HLS can improve the development efficiency while meeting the requirements of strong processing performance and strong real-time performance. In the implementation process of the sidelobe cancellation algorithm, the number of channels, the number of sampling points, the dimension of matrix inversion and other parameters can be controlled through parameter configuration, and the sidelobe cancellation algorithm has the characteristics of high real-time performance, strong universality and fast development efficiency, and can be widely applied to radar digital array signal processing machine products.

Description

Technical Field

[0001] The embodiments of this application relate to the field of digital signal processing technology, and in particular to an implementation method of a sidelobe cancellation algorithm based on FPGA and HLS. Background Technology

[0002] Sidelobe cancellation is a technique that involves adding several auxiliary antennas near the main antenna and weighted summing the interference signals received by these antennas to create a null point in the direction of interference, thereby canceling out antenna sidelobe interference. For multi-functional, multi-task array radars, considering that different functions and tasks may result in multiple main and auxiliary channels, coupled with the real-time requirements of different radar repetition frequency periods, sidelobe cancellation algorithms can be implemented using FPGAs. FPGAs possess powerful real-time and parallel processing capabilities, which can improve the speed of sidelobe cancellation.

[0003] However, the implementation of sidelobe cancellation algorithms involves complex calculations such as matrix inversion. If pure FPGA is used to develop multi-functional, multi-tasking radar equipment, it will inevitably face problems such as long development cycles and difficulties in upgrading. Furthermore, in scenarios with a large number of channels, large data volumes, and high real-time processing requirements, traditional implementation methods using DSPs or CPU + GPUs often cannot simultaneously meet the demands for strong processing performance and real-time performance. Therefore, improving development efficiency while achieving strong real-time and processing performance is a key focus of radar algorithm design research, addressing future development needs. Summary of the Invention

[0004] In view of this, the embodiments of this application propose an implementation method of the sidelobe cancellation algorithm based on FPGA and HLS, which can improve development efficiency while meeting the requirements of strong processing performance and strong real-time performance. In the implementation process of the sidelobe cancellation algorithm, parameters such as the number of channels, the number of sampling points, and the matrix inversion dimension can be controlled by parameters. It has the characteristics of high real-time performance, strong versatility, and fast development efficiency, and can be widely used in radar digital array signal processor products.

[0005] To achieve the above objectives, embodiments of this application propose an implementation method for a sidelobe cancellation algorithm based on FPGA and HLS, applicable to multi-functional, multi-task array radar. The method includes: receiving and buffering main channel array manifold data and auxiliary channel array manifold data transmitted by a digital beamforming unit; generating the required number of sampling points based on the configured number of sub-channels and weighting coefficients; rearranging and truncating the array manifold data based on the required number of sampling points; and then sending the truncated data to the buffer interval of each sub-channel; reading out the truncated data from all sub-channels in the auxiliary and main channels using time-division multiplexing; then, according to the number of time-division multiplexing cycles, reading out the truncated data from all sub-channels in the auxiliary channel in parallel and cyclically; performing matrix multiplication on the sub-channel data read out twice to obtain autocorrelation and cross-correlation processing results; and generating a matrix inversion module based on Cholesky decomposition using an HLS tool, and combining the autocorrelation processing results and the matrix inversion... The dimension input is fed into the matrix inversion module to obtain the autocorrelation matrix inversion result. The processing time for the matrix inversion of the largest dimension is less than the radar repetition rate period. Each element of each row in the autocorrelation matrix inversion result is latched. When the last element of each row is latched, the cross-correlation result is read out. The elements of each row of the autocorrelation matrix inversion result are multiplied by the elements of each column of the cross-correlation matrix to obtain the weight coefficient formation result. The auxiliary channel array manifold data is read out from the buffer interval. According to the number of sub-channels in the auxiliary channel, the elements of each channel are latched twice. When the element of the last channel is latched, the weight coefficient is read out. The number of reads is equal to the total number of sampling points of the array manifold data. The matrix multiplication operation between the auxiliary channel data and the weight coefficient formation result under all sampling points is realized. Finally, the main channel array manifold data is read out from the buffer interval and subtracted to obtain the sidelobe cancellation formation result.

[0006] To achieve the above objectives, embodiments of this application also propose an implementation system for a sidelobe cancellation algorithm based on FPGA and HLS, applicable to multi-functional, multi-task array radar. The system includes: a data caching and rearrangement module, used to receive and cache the main channel array manifold data and auxiliary channel array manifold data transmitted by the digital beamforming unit; generate the required number of sampling points based on the configured number of sub-channels and weighting coefficients; rearrange and truncate the array manifold data based on the required number of sampling points; and then send the data to the buffer interval of each sub-channel; an autocorrelation and cross-correlation processing module, used to read out the truncated data from all sub-channels in the auxiliary and main channels using time-division multiplexing; then, based on the number of time-division multiplexing cycles, read out the truncated data from all sub-channels in the auxiliary channel in parallel and cyclically; perform matrix multiplication on the sub-channel data read out twice to obtain the autocorrelation and cross-correlation processing results; and an autocorrelation matrix inversion module, used to generate a matrix inversion module based on Cholesky decomposition using HLS tools, and then perform autocorrelation matrix inversion on the autocorrelation matrix. The processing results and matrix inversion dimensions are input into the matrix inversion module to obtain the autocorrelation matrix inversion result. The processing time for the matrix inversion of the largest dimension is less than the radar repetition rate period. The weight coefficient forming module is used to latch each element of each row in the autocorrelation matrix inversion result. When the last element of each row is latched, the cross-correlation result is read out, and the elements of each row of the autocorrelation matrix inversion result are multiplied by the elements of each column of the cross-correlation matrix to obtain the weight coefficient forming result. The sidelobe cancellation forming module is used to read the auxiliary channel array manifold data from the buffer interval. According to the number of sub-channels in the auxiliary channel, the elements of each channel are latched twice. When the element of the last channel is latched, the weight coefficient is read out. The number of reads is equal to the total number of sampling points of the array manifold data. The matrix multiplication operation between the auxiliary channel data and the weight coefficient forming result under all sampling points is realized. Finally, the main channel array manifold data is read out from the buffer interval and subtracted to obtain the sidelobe cancellation forming result.

[0007] To achieve the above objectives, embodiments of this application also propose an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to execute an implementation method of a sidelobe cancellation algorithm based on FPGA and HLS as described above.

[0008] To achieve the above objectives, embodiments of this application also propose a computer-readable storage medium storing a computer program that, when executed by a processor, enables the implementation of a sidelobe cancellation algorithm based on FPGA and HLS as described above.

[0009] This application proposes a method for implementing a sidelobe cancellation algorithm based on FPGA and HLS. Addressing the challenges of large numbers of channels, large sampling volumes, rapid data rate changes, and high real-time requirements in array radar, traditional DSP or CPU+GPU processing methods cannot simultaneously meet the demands for strong processing performance and real-time capabilities. While FPGA-only implementations suffer from long development cycles and difficulties in upgrading, this application introduces HLS to assist in implementing the sidelobe cancellation algorithm on the FPGA. Complex operations such as matrix inversion in the sidelobe cancellation algorithm are implemented using HLS, which employs C / C++ programming, resulting in rapid development efficiency and enabling quick IP configuration iteration and upgrades. Other operations in the sidelobe cancellation algorithm are implemented using the FPGA, thus balancing the resource consumption and processing latency associated with processing large amounts of data. The collaborative work of FPGA and HLS can improve development efficiency while meeting the requirements of strong processing performance and strong real-time performance. In the implementation of the sidelobe cancellation algorithm, parameters such as the number of channels, the number of sampling points, and the matrix inversion dimension can all be controlled through parameter configuration. It has the characteristics of high real-time performance, strong versatility, and fast development efficiency, and can be widely used in radar digital array signal processor products.

[0010] Optionally, the operating clock frequency of both the FPGA and HLS is configured to be F, the data rate of a single channel is S, the maximum number of downlink sub-channels is U=F / S, the number of effective sub-channels in the main channel is M, the number of effective sub-channels in the auxiliary channel is N, and M and N are not greater than U. The radar repetition frequency period is configured to be T, the number of data transmitted per channel is L, the number of sampling points required to generate weight coefficients is K, and the maximum matrix inversion dimension in the HLS is V.

[0011] The FPGA receives the main channel array manifold data and the auxiliary channel array manifold data sent by the digital beamforming unit. The main channel array manifold data contains U sub-channel data of L downlink data, with M being the number of effective sub-channels. The auxiliary channel array manifold data contains U sub-channel data of L downlink data, with N being the number of effective sub-channels.

[0012] The main-channel array manifold data and the auxiliary-channel array manifold data are respectively stored in their corresponding DDR memories. At the same time, according to the maximum number of channels U and the number of data transmitted in a single channel L, the array manifold data is rearranged. After intercepting the data corresponding to the required number of sampling points K generated by the number of effective sub-channels and the weight coefficients, they are stored in the BRAM caches of their respective sub-channels. That is, the K data corresponding to the first sub-channel in the main channel are sent to the first dual-port RAM, and so on. The K data corresponding to the Mth sub-channel in the main channel are sent to the Mth dual-port RAM. The processing method of the sub-channels in the auxiliary channel is the same as that of the sub-channels in the main channel. The number of BRAMs to be instantiated for the main channel and the auxiliary channel is based on the maximum number of channels that can be generated by the minimum data rate transmitted in a single channel.

[0013] Optionally, the intercepted data of all sub-channels in the main channel and all sub-channels in the auxiliary channel are read out at the same time, so as to realize the autocorrelation processing of the auxiliary channel and the auxiliary channel, and the cross-correlation processing of the auxiliary channel and the main channel. In the case of a large number of channels and a large number of internal arithmetic units of the device consumed by full parallel processing, a time-division multiplexing processing method is adopted;

[0014] When performing cross-correlation processing, the number of time-division multiplexing is P, P = M / n, where n is the number of sub-channels in the main channel read in parallel during a single time-division multiplexing. P satisfies (P×K) / F < T, so as to achieve pipelining at the radar repetition period level. The number of loop readings of N auxiliary sub-channels is also P times. During each time-division multiplexing period, the first row of the multiplier module is multiplied and accumulated with the corresponding elements of the first row to the nth row of the multiplicand module, and so on, until the Nth row of the multiplier module is multiplied and accumulated with the corresponding elements of the first row to the nth row of the multiplicand module, so as to obtain the cross-correlation processing result, and the cross-correlation processing result is stored in the cache area;

[0015] The implementation method of the autocorrelation processing result is the same as that of the cross-correlation processing result.

[0016] Optionally, the HLS tool is developed using C / C++ programming. By calling the Cholesky inverse function in the math function library and inputting the original data, data type, and matrix inversion dimension, the inverse result of the input data can be obtained. After optimizing the interfaces, arrays, functions, and loops, the processing delay is viewed through the synthesis of the HLS tool to generate a matrix inversion IP core, allowing the FPGA to call;

[0017] Matrix inversion operations implemented using the HLS tool need to be mapped to hardware resources, and the size of the inverted matrix cannot be dynamically changed each time. Therefore, the matrix inversion dimension needs to be set according to the radar repetition frequency period T. The maximum matrix inversion dimension that can be achieved within T is set to V to realize pipelined processing at the repetition frequency period level. The input matrix inversion dimension is no greater than V. When the input matrix inversion dimension is less than V, 1s are filled in the main diagonal of the remaining matrix to ensure the correctness of the inversion operation.

[0018] Optionally, the weight coefficients are formed by FPGA. Taking the first row of the autocorrelation matrix inversion result as an example, each element of the first row is latched in a register. After the last element of the first row is latched, the cross-correlation processing result is read out in parallel. In the vertical direction at each time step, all elements of the first row of the autocorrelation matrix inversion result are multiplied and accumulated with each column element of the cross-correlation processing result. This process continues until all elements of the Nth row of the autocorrelation matrix inversion result are multiplied and accumulated with each column element of the cross-correlation result to obtain the weight coefficients. The weight coefficients are then stored in the cache area.

[0019] The process of multiplying and accumulating the corresponding N rows of data from the autocorrelation matrix inversion result with the cross-correlation processing result is also implemented using a time-division multiplexing method.

[0020] Optionally, the auxiliary channel array manifold data is read out sequentially from DDR memory and smoothly output through FIFO buffer. Based on the number N of effective sub-channels in the auxiliary channel, the L downlink data corresponding to each sub-channel in the N channels are latched. After the latching of the Nth sub-channel in each downlink data is completed, the L downlink data corresponding to the N sub-channels are latched again, so that the N sub-channels are output in parallel at the same time. At the same time, the weight coefficient formation results are output in parallel at the same time. The number of times the same set of weight coefficient formation results are output is equal to the number L of downlink data in a single channel.

[0021] In the vertical direction, the data of the N effective auxiliary sub-channels for the first downlink data point are multiplied and accumulated with each column of the weight coefficient result. This process continues until the data of the N effective auxiliary sub-channels for the Lth downlink data point are multiplied and accumulated with each column of the weight coefficient result. Finally, the cancellation factor result of the product of the L downlink data and the weight coefficient result for the N auxiliary sub-channels is obtained. At the same time, the main channel array manifold data in the DDR memory is read out sequentially and output smoothly through FIFO buffer. The data is then subtracted from the cancellation factor result to obtain the sidelobe cancellation result.

[0022] Optionally, when the radar repetition frequency period is short, when storing the main channel array manifold data and the auxiliary channel array manifold data in DDR memory, it is also necessary to read out the array manifold data stored in the previous one or more radar repetition frequency periods, that is, to perform read-write arbitration processing on the DDR memory.

[0023] In order to achieve real-time processing at the radar repetition period level, the time consumed by autocorrelation processing and cross-correlation processing, autocorrelation matrix inversion, and weight coefficient formation must all be less than the radar repetition period T.

[0024] When the maximum number of channels corresponding to the data rate, the number of effective channels, the number of data transmitted per channel, and the number of sampling points required to generate weight coefficients change, the parameters are configured in real time to complete different forms of sidelobe cancellation processing. When the maximum inverse dimension of the matrix changes, it is necessary to quickly iterate and upgrade the IP configuration through HLS. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies of this application will be briefly introduced below. Obviously, the following drawings are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. The drawings described herein are only used to explain this application and are not intended to limit this application.

[0026] Figure 1 This is a flowchart of an implementation method of a sidelobe cancellation algorithm based on FPGA and HLS, provided in one embodiment of this application.

[0027] Figure 2 This is a schematic diagram illustrating the details of an implementation method of a sidelobe cancellation algorithm based on FPGA and HLS, provided in one embodiment of this application.

[0028] Figure 3 This is a schematic diagram of an array manifold rearrangement process provided in one embodiment of this application;

[0029] Figure 4 This is a schematic diagram of autocorrelation processing and cross-correlation processing provided in one embodiment of this application;

[0030] Figure 5 This is a schematic diagram of the matrix inversion process provided in one embodiment of this application;

[0031] Figure 6 This is a schematic diagram of the weight coefficient formation process provided in one embodiment of this application;

[0032] Figure 7 This is a schematic diagram of the cancellation factor generation process provided in one embodiment of this application;

[0033] Figure 8 This is a schematic diagram of the DDR memory read / write arbitration process provided in one embodiment of this application;

[0034] Figure 9 This is a schematic diagram of a side-lobe elimination flow water treatment process provided in one embodiment of this application;

[0035] Figure 10 This is a schematic diagram of the structure of an implementation system for a sidelobe cancellation algorithm based on FPGA and HLS, provided in another embodiment of this application.

[0036] Figure 11 This is a schematic diagram of the structure of an electronic device provided in another embodiment of this application. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. Those skilled in the art will understand that many technical details have been presented in the embodiments of this application to facilitate better understanding. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this application. The following embodiments can be combined with and referenced by each other without contradiction.

[0038] One embodiment of this application proposes an implementation method for a sidelobe cancellation algorithm based on FPGA and HLS. The implementation details of the sidelobe cancellation algorithm based on FPGA and HLS proposed in this embodiment are described in detail below. The following content is only for the convenience of understanding the implementation details provided and is not necessary for implementing this solution.

[0039] The specific process of the sidelobe cancellation algorithm based on FPGA and HLS proposed in this embodiment can be described as follows: Figure 1 As shown, its visual details can be as follows Figure 2 As shown, the method includes:

[0040] Step 11: Receive and buffer the main channel array manifold data and auxiliary channel array manifold data sent by the digital beamforming unit. Generate the required number of sampling points according to the configured number of sub-channels and weighting coefficients. Rearrange and truncate the array manifold data based on the required number of sampling points and then send it into the buffer interval of each sub-channel.

[0041] In its implementation, the sidelobe cancellation algorithm proposed in this embodiment is implemented using both an FPGA processing platform and an HLS processing platform. First, the FPGA receives and buffers the main channel array manifold data and auxiliary channel array manifold data sent by the digital beamforming unit. Then, based on the configured number of sub-channels and weighting coefficients, the required number of sampling points is generated. The array manifold data is then rearranged and truncated based on the required number of sampling points, and finally sent to the buffer interval of each sub-channel.

[0042] In one example, the operating clock frequency of both the FPGA and HLS processing platforms is configured as F, the data rate of a single channel is S, the maximum number of downlink sub-channels is U, and U = F / S. Let the number of effective sub-channels in the main channel be M, and the number of effective sub-channels in the auxiliary channel be N, where M and N are not greater than U. The radar repetition frequency period is configured as T, the number of data transmitted per channel is L, the number of sampling points required to generate the weight coefficients is set to K, and the maximum matrix inversion dimension in the HLS processing platform is V.

[0043] In one example, the FPGA receives main channel array manifold data and auxiliary channel array manifold data transmitted by the digital beamforming unit, such as... Figure 3 As shown, the main channel array manifold data contains U sub-channel data of L downlink data, with M being the number of effective sub-channels. The auxiliary channel array manifold data contains U sub-channel data of L downlink data, with N being the number of effective sub-channels. The main channel array manifold data and the auxiliary channel array manifold data are stored in their respective DDR memory. At the same time, the array manifold data is rearranged according to the maximum number of channels U and the number of data transmitted per channel L. The data corresponding to the number of effective sub-channels and the number of sampling points K required to generate the weight coefficients are extracted and stored in the BRAM cache of their respective sub-channels. That is, the K data corresponding to the first sub-channel in the main channel are sent to the first dual-port RAM, the K data corresponding to the second sub-channel in the main channel are sent to the second dual-port RAM, and so on. The K data corresponding to the Mth sub-channel in the main channel are sent to the Mth dual-port RAM. The sub-channels in the auxiliary channel are processed in the same way as the sub-channels in the main channel. The number of BRAMs that need to be instantiated for the main channel and the auxiliary channel is based on the maximum number of channels that can be generated by the minimum data rate transmitted per channel, so as to increase the versatility of the processing.

[0044] Step 12: Read out the intercepted data of all sub-channels in the auxiliary channel and the main channel in a time-division multiplexing manner. Then, according to the number of time-division multiplexing times, read out the intercepted data of all sub-channels in the auxiliary channel in parallel and cyclically. Perform matrix multiplication on the sub-channel data read out twice to obtain the autocorrelation processing result and the cross-correlation processing result.

[0045] In a specific implementation, after rearranging and intercepting the array manifold data and sending it to the buffer intervals of each sub-channel, the intercepted data of all sub-channels in the auxiliary channel and the main channel needs to be read out in a time-division multiplexing manner, and then the intercepted data of all sub-channels in the auxiliary channel is read out in parallel and cyclically according to the number of time-division multiplexing times. Subsequently, the sub-channel data read out twice is subjected to matrix multiplication operation to obtain the autocorrelation processing result and the cross-correlation processing result.

[0046] In one example, by reading out the intercepted data of all sub-channels in the main channel and all sub-channels in the auxiliary channel at the same time, the autocorrelation processing between the auxiliary channels and the cross-correlation processing between the auxiliary channel and the main channel can be achieved. When the number of channels is large and the internal arithmetic units of the devices consumed by full parallel processing are relatively many, a time-division multiplexing processing method can be adopted to save resources.

[0047] As Figure 4 shown, when performing cross-correlation processing, the number of time-division multiplexing times is P, P = M / n, where n is the number of sub-channels in the main channel read in parallel during a single time-division multiplexing, and P satisfies (P×K) / F < T, so as to achieve pipelining processing at the radar repetition frequency period level. The number of cyclic readings of N auxiliary sub-channels is also P times. In each time-division multiplexing cycle, the first row of the multiplier module is multiplied and accumulated with the corresponding elements of the first row to the nth row of the multiplicand module respectively, and then the second row of the multiplier module is multiplied and accumulated with the corresponding elements of the first row to the nth row of the multiplicand module respectively, and so on, until the Nth row of the multiplier module is multiplied and accumulated with the corresponding elements of the first row to the nth row of the multiplicand module respectively, thereby obtaining the cross-correlation processing result and storing the cross-correlation processing result in the buffer interval. The implementation method of the autocorrelation processing result is the same as that of the cross-correlation processing result.

[0048] Step 13: Generate a matrix inversion module based on Cholesky decomposition through the HLS tool, input the autocorrelation processing result and the matrix inversion dimension into the matrix inversion module, and obtain the autocorrelation matrix inversion result, where the matrix inversion processing time of the largest dimension is less than the radar repetition frequency period.

[0049] In a specific implementation, complex operations such as matrix inversion in the sidelobe cancellation algorithm are implemented through HLS. A matrix inversion module based on Cholesky decomposition is generated through the HLS tool, and the autocorrelation processing result and the matrix inversion dimension are input into the matrix inversion module to obtain the autocorrelation matrix inversion result; among them, the matrix inversion processing time of the largest dimension is less than the radar repetition frequency period.

[0050] In one example, before performing matrix inversion on the autocorrelation processing results, a fixed-point to floating-point conversion can be performed to increase the accuracy of matrix inversion. However, the matrix operation module is quite complex. To improve development efficiency, this embodiment chooses to implement it using the HLS tool. The HLS tool is developed using C / C++ programming. It calls the Cholesky inversion function from the mathematical function library, inputting the original data, data type, and matrix inversion dimension to obtain the inversion result. After optimizing the interface, arrays, functions, and loops, the processing latency can be viewed through the comprehensive implementation function of the HLS tool, generating a matrix inversion IP core that can be called by the FPGA.

[0051] Matrix inversion operations implemented using HLS tools require mapping to hardware resources and cannot dynamically change the size of the inverted matrix for each operation. Therefore, the matrix inversion dimension needs to be set according to the radar repetition frequency period T, with the maximum achievable matrix inversion dimension within T set to V, to achieve pipelined processing at the repetition frequency period level. The input matrix inversion dimension is no greater than V. When the input matrix inversion dimension is less than V, 1s are padded to the main diagonal of the remaining matrix. Figure 5 As shown, this is to ensure the correctness of the inverse operation.

[0052] Step 14: Latch each element of each row in the inverse of the autocorrelation matrix. When the last element of each row is latched, read out the cross-correlation result. Multiply each element of each row in the inverse of the autocorrelation matrix with each element of each column of the cross-correlation matrix to obtain the weight coefficients.

[0053] In the specific implementation, after obtaining the inverse result of the autocorrelation matrix, it is necessary to latch each element of each row in the inverse result of the autocorrelation matrix. When the last element of each row is latched, the cross-correlation result is read out, and the elements of each row of the inverse result of the autocorrelation matrix are multiplied with the elements of each column of the cross-correlation matrix to obtain the weight coefficient formation result.

[0054] In one example, to better balance the relationship between resources and latency, the weighting coefficient formation process is still implemented by the FPGA. For example... Figure 6 As shown, taking the first row of the autocorrelation matrix inversion result as an example, each element of the first row is latched in a register. After the last element of the first row is latched, the cross-correlation processing result is read out in parallel. In the vertical direction at each time step, all elements of the first row of the autocorrelation matrix inversion result are multiplied and accumulated with each column element of the cross-correlation processing result. This process continues until all elements of the Nth row of the autocorrelation matrix inversion result are multiplied and accumulated with each column element of the cross-correlation result to obtain the weight coefficient formation result. The weight coefficient formation result is then stored in the cache area.

[0055] In order to save multiplier resources, the process of multiplying and accumulating the corresponding N rows of data from the autocorrelation matrix inversion result with the cross-correlation processing result can also be implemented using a time-division multiplexing method.

[0056] Step 15: Read the auxiliary channel array manifold data from the buffer interval. Based on the number of sub-channels in the auxiliary channel, perform a second latch on the elements of each channel. When the element latch of the last channel ends, read out the weight coefficients. The number of reads is equal to the total number of sampling points of the array manifold data. Perform matrix multiplication operation on the auxiliary channel data and weight coefficients under all sampling points. Finally, read out the main channel array manifold data from the buffer interval and perform subtraction to obtain the sidelobe cancellation result.

[0057] In the specific implementation, after generating the weight coefficients (weight coefficient matrix), the auxiliary channel array manifold data needs to be read from the buffer interval. Based on the number of sub-channels in the auxiliary channel, the elements of each channel are latched twice. When the element latch of the last channel ends, the weight coefficients are read out. The number of reads is equal to the total number of sampling points of the array manifold data. The matrix multiplication operation between the auxiliary channel data and the weight coefficients under all sampling points is realized. Finally, the main channel array manifold data is read from the buffer interval and the difference is processed to obtain the sidelobe cancellation result.

[0058] In one example, after the weight coefficient matrix is ​​generated, the auxiliary channel array manifold data is read sequentially from DDR memory and smoothly output using a FIFO buffer. Based on the number N effective sub-channels in the auxiliary channels, L data points corresponding to each of the N sub-channels are latched. After the latching of the Nth sub-channel in each set of data points is completed, the L data points corresponding to the N sub-channels are latched again, ensuring that the N sub-channels output in parallel at the same time. Figure 7 As shown. At the same time, the weight coefficient formation results are output in parallel at the same moment, and the number of times the same set of weight coefficient formation results are output is equal to the number of data L transmitted by a single channel.

[0059] Then, in the vertical direction, the data of the N effective auxiliary sub-channels for the first downlink data point are multiplied and accumulated with each column of the weight coefficient result. This process is repeated until the data of the N effective auxiliary sub-channels for the Lth downlink data point are multiplied and accumulated with each column of the weight coefficient result. Finally, the cancellation factor result of the product of the L downlink data and the weight coefficient result for the N auxiliary sub-channels is obtained. At the same time, the main channel array manifold data in the DDR memory is read out sequentially and output smoothly through FIFO buffer. The data is then subtracted from the cancellation factor result to obtain the sidelobe cancellation result.

[0060] In one example, when the radar repetition frequency period is short, when storing the main channel array manifold data and auxiliary channel array manifold data in DDR memory, it is also necessary to read out the array manifold data stored in the previous one or more radar repetition frequency periods. This involves performing read / write arbitration processing on the DDR memory. Figure 8 As shown. To achieve real-time processing at the radar repetition rate period level, the time consumed by autocorrelation processing, cross-correlation processing, autocorrelation matrix inversion, and weight coefficient formation must all be less than the radar repetition rate period T, such as... Figure 9 As shown. When the maximum number of channels corresponding to the data rate, the number of effective channels, the number of data transmitted per channel, and the number of sampling points required to generate weight coefficients change, these parameters can be configured in real time to complete different forms of sidelobe cancellation processing. When the maximum inverse dimension of the matrix changes, it is necessary to quickly iterate and upgrade the IP configuration through HLS.

[0061] This embodiment proposes an implementation method for a sidelobe cancellation algorithm based on FPGA and HLS. Addressing the challenges of large array radar channels, high sampling rates, rapid data rate changes, and stringent real-time requirements, traditional DSP or CPU+GPU processing methods cannot simultaneously meet the demands for high processing performance and real-time performance. While FPGA-only implementations suffer from long development cycles and difficult upgrades, HLS is introduced to assist in implementing the sidelobe cancellation algorithm on the FPGA. Complex operations such as matrix inversion in the sidelobe cancellation algorithm are implemented using HLS, which employs C / C++ programming, resulting in rapid development efficiency and enabling quick IP configuration iteration and upgrades. Other operations in the sidelobe cancellation algorithm are implemented using the FPGA, thus balancing the resource consumption and processing latency associated with large-scale data processing. The collaborative work of FPGA and HLS can improve development efficiency while meeting the requirements of strong processing performance and strong real-time performance. In the implementation of the sidelobe cancellation algorithm, parameters such as the number of channels, the number of sampling points, and the matrix inversion dimension can all be controlled through parameter configuration. It has the characteristics of high real-time performance, strong versatility, and fast development efficiency, and can be widely used in radar digital array signal processor products.

[0062] The steps described above are for clarity only. In implementation, they can be combined into one step, or some steps can be broken down into multiple steps, as long as they involve the same logical relationship, they are all within the scope of protection of this application. Adding insignificant modifications or introducing insignificant designs to the algorithm or process, without changing the core design of the algorithm and process, are also within the scope of protection of this application.

[0063] Another embodiment of this application proposes an implementation system for a sidelobe cancellation algorithm based on FPGA and HLS, which is suitable for multi-functional and multi-tasking array radar. The details of the implementation system for the sidelobe cancellation algorithm based on FPGA and HLS proposed in this embodiment are described below. The following content is only for the convenience of understanding the implementation details provided and is not necessary for implementing this example.

[0064] The specific structure of the implementation system of the sidelobe cancellation algorithm based on FPGA and HLS proposed in this embodiment can be as follows: Figure 10 As shown, it includes: a data caching and rearrangement truncation module 21, an autocorrelation and cross-correlation processing module 22, an autocorrelation matrix inversion module 23, a weight coefficient formation module 24, and a sidelobe cancellation formation module 25.

[0065] The data caching and rearrangement module 21 is used to receive and cache the main channel array manifold data and auxiliary channel array manifold data sent by the digital beamforming unit, generate the required number of sampling points according to the configured number of sub-channels and weight coefficients, rearrange and truncate the array manifold data based on the required number of sampling points, and then send it into the buffer interval of each sub-channel.

[0066] The autocorrelation and cross-correlation processing module 22 is used to read out the intercepted data of all sub-channels in the auxiliary channel and the main channel in a time-division multiplexing manner, and then read out the intercepted data of all sub-channels in the auxiliary channel in parallel and cyclically according to the number of time-division multiplexing. The sub-channel data read out twice are subjected to matrix multiplication to obtain the autocorrelation processing result and the cross-correlation processing result.

[0067] The autocorrelation matrix inversion module 23 is used to generate a matrix inversion module based on Cholesky decomposition using the HLS tool. The autocorrelation processing result and the matrix inversion dimension are input into the matrix inversion module to obtain the autocorrelation matrix inversion result. The processing time for the matrix inversion of the largest dimension is less than the radar repetition rate period.

[0068] The weight coefficient forming module 24 is used to latch each element of each row in the result of the autocorrelation matrix inversion. When the last element of each row is latched, the cross-correlation result is read out, and the elements of each row of the autocorrelation matrix inversion result are multiplied with the elements of each column of the cross-correlation matrix to obtain the weight coefficient forming result.

[0069] The sidelobe cancellation forming module 25 is used to read the auxiliary channel array manifold data from the buffer interval, perform secondary latching on the elements of each channel according to the number of sub-channels in the auxiliary channel, and read out the weight coefficients when the element latching of the last channel ends. The number of reads is equal to the total number of sampling points of the array manifold data. The matrix multiplication operation of the auxiliary channel data and the weight coefficients under all sampling points is realized. Finally, the main channel array manifold data is read out from the buffer interval and the difference is processed to obtain the sidelobe cancellation forming result.

[0070] It is not difficult to see that this embodiment is a system embodiment corresponding to the above method embodiments, and this embodiment can be implemented in conjunction with the above method embodiments. The relevant technical details and technical effects mentioned in the above method embodiments are still valid in this embodiment, and will not be repeated here to reduce repetition. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the above method embodiments.

[0071] It is worth mentioning that all modules and units involved in this embodiment are logical modules. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this application, this embodiment does not introduce units that are not closely related to solving the technical problems proposed in this application; however, this does not mean that other units do not exist in this embodiment.

[0072] Another embodiment of this application provides an electronic device, such as Figure 11 As shown, it includes: at least one processor 31; and a memory 32 communicatively connected to the at least one processor 31; wherein the memory 32 stores instructions executable by the at least one processor 31, the instructions being executed by the at least one processor 31 to enable the at least one processor 31 to execute an implementation method of a sidelobe cancellation algorithm based on FPGA and HLS as described in the above method embodiment.

[0073] The memory and processor are connected via a bus, which includes any number of interconnecting buses and bridges, connecting various circuits of one or more processors and memories. The bus can also connect various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and will not be described further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium.

[0074] The processor manages the bus and general processing, and also provides various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory is used to store data used by the processor during operation.

[0075] Another embodiment of this application proposes a computer-readable storage medium storing a computer program that, when executed by a processor, can implement a sidelobe cancellation algorithm based on FPGA and HLS as described in the above method embodiments.

[0076] That is, those skilled in the art will understand that all or part of the steps in the above method embodiments can be implemented by a program instructing related hardware. The program is stored in a storage medium and includes several instructions to cause a device (such as a microcontroller, chip, etc.) or processor to execute all or part of the steps of the method described in the method embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory, random access memory, magnetic disks, or optical disks.

[0077] Those skilled in the art will understand that the above embodiments are specific implementations of this application, and in practical applications, various changes can be made in form and detail without departing from the spirit and scope of this application. For those skilled in the art, several improvements and modifications can be made without departing from the principles of this application, and these improvements and modifications are also considered to be within the scope of protection of this application.

Claims

1. A method for implementing a sidelobe cancellation algorithm based on FPGA and HLS, applicable to multi-functional, multi-task array radar, characterized in that, The method includes: The system receives and buffers the main channel array manifold data and auxiliary channel array manifold data sent by the digital beamforming unit. It generates the required number of sampling points based on the configured number of sub-channels and weighting coefficients, rearranges and truncates the array manifold data based on the required number of sampling points, and then sends it into the buffer interval of each sub-channel. The intercepted data from all sub-channels in the auxiliary channel and the main channel are read out in a time-division multiplexing manner. Then, according to the number of time-division multiplexing times, the intercepted data from all sub-channels in the auxiliary channel are read out in parallel and cyclically. The sub-channel data read out twice are subjected to matrix multiplication to obtain the autocorrelation processing result and the cross-correlation processing result. A matrix inversion module based on Cholesky decomposition is generated using the HLS tool. The autocorrelation processing result and the matrix inversion dimension are input into the matrix inversion module to obtain the autocorrelation matrix inversion result. The processing time for the matrix inversion with the largest dimension is less than the radar repetition rate period. Latch each element of each row in the inverse of the autocorrelation matrix. When the last element of each row is latched, read out the cross-correlation result. Multiply each element of each row in the inverse of the autocorrelation matrix with each element of each column of the cross-correlation matrix to obtain the weight coefficients. The auxiliary channel array manifold data is read from the buffer interval. Based on the number of sub-channels in the auxiliary channel, the elements of each channel are latched twice. When the element latch of the last channel ends, the weight coefficients are read out. The number of reads is equal to the total number of sampling points of the array manifold data. The matrix multiplication operation of the auxiliary channel data and the weight coefficients under all sampling points is realized. Finally, the main channel array manifold data is read from the buffer interval and the difference is processed to obtain the sidelobe cancellation result.

2. The implementation method of the sidelobe cancellation algorithm based on FPGA and HLS according to claim 1, characterized in that, The FPGA and HLS are configured with operating clock frequencies of F, data rate of a single channel downlink is S, maximum number of downlink sub-channels is U=F / S, number of effective sub-channels in the main channel is M, number of effective sub-channels in the auxiliary channel is N, M and N are not greater than U, radar repetition frequency period is configured as T, number of data downlinks per channel is L, number of sampling points required to generate weight coefficients is K, and maximum matrix inversion dimension in HLS is V; The FPGA receives the main channel array manifold data and the auxiliary channel array manifold data sent by the digital beamforming unit. The main channel array manifold data contains U sub-channel data of L downlink data, with M being the number of effective sub-channels. The auxiliary channel array manifold data contains U sub-channel data of L downlink data, with N being the number of effective sub-channels. The main channel array manifold data and the auxiliary channel array manifold data are stored in their respective DDR memory. At the same time, the array manifold data is rearranged according to the maximum number of channels U and the number of data transmitted per channel L. The data corresponding to the number of effective sub-channels and the number of sampling points K required to generate the weight coefficients are extracted and stored in the BRAM cache of their respective sub-channels. That is, the K data corresponding to the first sub-channel in the main channel are sent to the first dual-port RAM, and so on. The K data corresponding to the Mth sub-channel in the main channel are sent to the Mth dual-port RAM. The sub-channels in the auxiliary channel are processed in the same way as the sub-channels in the main channel. The number of BRAMs that need to be instantiated for the main channel and the auxiliary channel is based on the maximum number of channels that can be generated by the minimum data rate transmitted per channel.

3. The implementation method of the sidelobe cancellation algorithm based on FPGA and HLS according to claim 2, characterized in that, By reading the data captured from all sub-channels in the main channel and all sub-channels in the auxiliary channel at the same time, the autocorrelation processing of the auxiliary channel and the cross-correlation processing of the auxiliary channel and the main channel can be realized. When there are many channels and the internal computing units of the device are large, the time-division multiplexing processing method is adopted. When performing cross-correlation processing, the number of time-division multiplexing operations is P, where P = M / n, and n is the number of sub-channels in the main channel for parallel reading in a single time-division multiplexing operation. P satisfies (P×K) / F < T, thereby realizing pipelined processing at the radar repetition frequency cycle level. The number of cyclic readings of the N auxiliary sub-channels is also P. In each time-division multiplexing cycle, the first row of the multiplier module is multiplied by the corresponding elements of the first row to the nth row of the multiplicand module and accumulated. This process continues until the Nth row of the multiplier module is multiplied by the corresponding elements of the first row to the nth row of the multiplicand module and accumulated, thus obtaining the cross-correlation processing result. The cross-correlation processing result is then stored in the buffer area. The autocorrelation processing results are implemented in the same way as the cross-correlation processing results.

4. The implementation method of the sidelobe cancellation algorithm based on FPGA and HLS according to claim 2, characterized in that, The HLS tool is developed using C / C++ programming. It calls the Cholesky inversion function in the mathematical function library. By inputting the original data, data type, and matrix inversion dimension, it can obtain the inversion result of the input data. After optimizing the interface, array, function, and loop, the processing latency can be viewed through the comprehensive implementation function of the HLS tool, and a matrix inversion IP core can be generated, which can be called by FPGA. Matrix inversion operations implemented using the HLS tool need to be mapped to hardware resources, and the size of the inverted matrix cannot be dynamically changed each time. Therefore, the matrix inversion dimension needs to be set according to the radar repetition frequency period T. The maximum matrix inversion dimension that can be achieved within T is set to V to realize pipelined processing at the repetition frequency period level. The input matrix inversion dimension is no greater than V. When the input matrix inversion dimension is less than V, 1s are filled in the main diagonal of the remaining matrix to ensure the correctness of the inversion operation.

5. The implementation method of the sidelobe cancellation algorithm based on FPGA and HLS according to claim 1, characterized in that, The weight coefficients are formed by FPGA. Taking the first row of the autocorrelation matrix inversion result as an example, each element of the first row is latched in a register. After the last element of the first row is latched, the cross-correlation result is read out in parallel. In the vertical direction at each time step, all elements of the first row of the autocorrelation matrix inversion result are multiplied and accumulated with each column element of the cross-correlation result. This process continues until all elements of the Nth row of the autocorrelation matrix inversion result are multiplied and accumulated with each column element of the cross-correlation result to obtain the weight coefficients. The weight coefficients are then stored in the cache area. The process of multiplying and accumulating the corresponding N rows of data from the autocorrelation matrix inversion result with the cross-correlation processing result is also implemented using a time-division multiplexing method.

6. The implementation method of the sidelobe cancellation algorithm based on FPGA and HLS according to claim 5, characterized in that, The auxiliary channel array manifold data is read out sequentially from DDR memory and smoothly output through FIFO buffer. Based on the number N of effective sub-channels in the auxiliary channel, L of the downlink data corresponding to each sub-channel in the N channels are latched. After the latching of the Nth sub-channel in each downlink data is completed, the L downlink data corresponding to the N sub-channels are latched again, so that the N sub-channels are output in parallel at the same time. At the same time, the weight coefficient formation results are output in parallel at the same time. The number of times the same set of weight coefficient formation results are output is equal to the number L of downlink data in a single channel. In the vertical direction, the data of the N effective auxiliary sub-channels for the first downlink data point are multiplied and accumulated with each column of the weight coefficient result. This process continues until the data of the N effective auxiliary sub-channels for the Lth downlink data point are multiplied and accumulated with each column of the weight coefficient result. Finally, the cancellation factor result of the product of the L downlink data and the weight coefficient result for the N auxiliary sub-channels is obtained. At the same time, the main channel array manifold data in the DDR memory is read out sequentially and output smoothly through FIFO buffer. The data is then subtracted from the cancellation factor result to obtain the sidelobe cancellation result.

7. The implementation method of the sidelobe cancellation algorithm based on FPGA and HLS according to claim 6, characterized in that, When the radar repetition frequency period is short, when storing the main channel array manifold data and the auxiliary channel array manifold data in DDR memory, it is also necessary to read out the array manifold data stored in the previous one or more radar repetition frequency periods, that is, to perform read and write arbitration processing on the DDR memory. In order to achieve real-time processing at the radar repetition period level, the time consumed by autocorrelation processing and cross-correlation processing, autocorrelation matrix inversion, and weight coefficient formation must all be less than the radar repetition period T. When the maximum number of channels corresponding to the data rate, the number of effective channels, the number of data transmitted per channel, and the number of sampling points required to generate weight coefficients change, the parameters are configured in real time to complete different forms of sidelobe cancellation processing. When the maximum inverse dimension of the matrix changes, it is necessary to quickly iterate and upgrade the IP configuration through HLS.

8. A system for implementing a sidelobe cancellation algorithm based on FPGA and HLS, suitable for multi-functional, multi-task array radar, characterized in that... The system includes: The data caching and rearrangement module is used to receive and cache the main channel array manifold data and auxiliary channel array manifold data sent by the digital beamforming unit, generate the required number of sampling points according to the configured number of sub-channels and weighting coefficients, rearrange and truncate the array manifold data based on the required number of sampling points, and then send it into the buffer interval of each sub-channel. The autocorrelation and cross-correlation processing module is used to read out the intercepted data of all sub-channels in the auxiliary channel and the main channel in a time-division multiplexing manner, and then read out the intercepted data of all sub-channels in the auxiliary channel in parallel and cyclically according to the number of time-division multiplexing. The sub-channel data read out twice are subjected to matrix multiplication to obtain the autocorrelation processing result and the cross-correlation processing result. The autocorrelation matrix inversion module is used to generate a matrix inversion module based on Cholesky decomposition using the HLS tool. The autocorrelation processing result and the matrix inversion dimension are input into the matrix inversion module to obtain the autocorrelation matrix inversion result. The processing time for the matrix inversion of the largest dimension is less than the radar repetition rate period. The weight coefficient forming module is used to latch each element of each row in the result of the autocorrelation matrix inversion. When the last element of each row is latched, the cross-correlation result is read out, and the elements of each row of the autocorrelation matrix inversion result are multiplied with the elements of each column of the cross-correlation matrix to obtain the weight coefficient forming result. The sidelobe cancellation forming module is used to read the auxiliary channel array manifold data from the buffer interval, perform secondary latching on the elements of each channel according to the number of sub-channels in the auxiliary channel, and read out the weight coefficients when the element latching of the last channel ends. The number of reads is equal to the total number of sampling points of the array manifold data. The matrix multiplication operation of the auxiliary channel data and the weight coefficients formed under all sampling points is realized. Finally, the main channel array manifold data is read out from the buffer interval and subtracted to obtain the sidelobe cancellation forming result.

9. An electronic device, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed, enable the at least one processor to perform an implementation method of a sidelobe cancellation algorithm based on FPGA and HLS as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it can implement the sidelobe cancellation algorithm based on FPGA and HLS as described in any one of claims 1 to 7.

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