Clock calibration method, computer device, readable storage medium and program product

Abstract

The application relates to a clock calibration method, a computer device, a readable storage medium and a program product; a sleep clock count value of a control chip is acquired; in the case that the control chip is in a sleep state, the RC calibration circuit is charged and a sleep timer is triggered to perform clock counting by the control chip; if a first actual clock count value of the sleep timer reaches the sleep clock count value, the charging of the RC calibration circuit is stopped, and an actual charging time of the RC calibration circuit is determined; the sleep timer is calibrated according to the actual charging time and the sleep clock count value; the calibration operation can be completed in the sleep process of the control chip, multiple requirements of low power consumption, high precision and low cost are considered, and the problems of large sleep timing error and inaccurate system wake-up caused by unstable clock source, environmental change and other factors are avoided.

Description

Technical Field

[0001] This application relates to the field of chip clock calibration technology, and in particular to a clock calibration method, computer equipment, readable storage medium, and program product. Background Technology

[0002] With changes in the economic environment and intensified market competition, various industries are increasingly demanding higher standards for product cost control. This is especially true for mass-produced products, where even minor optimizations in hardware costs can yield significant economic benefits. Against this backdrop, domestic chip production has become a crucial means of reducing hardware costs, particularly in applications with high product shipment volumes. Using domestically produced chips not only helps reduce procurement costs but also enhances the self-control and autonomy of the supply chain. However, some low-cost chips based on the 51 microcontroller core suffer from significant issues with low-speed clock accuracy. They are significantly affected by factors such as temperature and voltage, with some models exhibiting deviations as high as ±50%, and these deviations are irregular between chips, severely impacting system timing stability. Traditional solutions often use high-speed clocks or external RTCs and high-precision crystal oscillators for calibration. However, the high cost of external components limits their application in low-cost scenarios.

[0003] There is currently no effective solution to the problem that low-cost chips in related technologies struggle to balance clock calibration accuracy and hardware cost during clock calibration. Summary of the Invention

[0004] Therefore, it is necessary to provide a clock calibration method, computer equipment, readable storage medium, and program product to address the aforementioned technical problems.

[0005] In a first aspect, this application provides a clock calibration method applied to a control chip, the control chip including a sleep timer; the method includes:

[0006] Obtain the sleep clock count value of the control chip;

[0007] When the control chip is in sleep mode, the RC calibration circuit is charged by the control chip and the sleep timer is triggered to count clock cycles.

[0008] If the first actual clock count value of the sleep timer is detected to reach the sleep clock count value, then the charging of the RC calibration circuit is stopped, and the actual charging time of the RC calibration circuit is determined.

[0009] The sleep timer is clock-calibrated based on the actual charging time and the sleep clock count value.

[0010] In one embodiment, obtaining the sleep clock count value of the control chip includes:

[0011] Obtain the pre-calibrated low-speed clock cycle and sleep reference time;

[0012] The sleep clock count value is determined based on the pre-calibrated low-speed clock cycle and the sleep reference time.

[0013] In one embodiment, obtaining the pre-calibrated low-speed clock period includes:

[0014] After each power-on, if the control chip receives the first data frame sent by the external host, it enters a sleep state and triggers the sleep timer to count the clock.

[0015] Until the control chip receives the next data frame, it exits the sleep state and reads the clock count value of the sleep timer to obtain the second actual clock count value;

[0016] The first actual low-speed clock cycle corresponding to the sleep timer is determined based on the data frame transmission period corresponding to the external host and the second actual clock count value.

[0017] Based on the first actual low-speed clock cycle, the low-speed clock corresponding to the sleep timer is pre-calibrated to obtain the pre-calibrated low-speed clock cycle.

[0018] In one embodiment, the RC calibration circuit includes a capacitor and a resistor; the resistor and the capacitor are connected in series between a preset interface of the control chip and ground; determining the actual charging time of the RC calibration circuit includes:

[0019] The voltage of the capacitor is sampled to obtain the target voltage sample value;

[0020] Based on the target voltage sampling value, a target charging time matching the target voltage sampling value is determined from a preset charging characteristic mapping table;

[0021] The target charging time is determined as the actual charging time of the RC calibration circuit.

[0022] In one embodiment, the control chip is equipped with a high-speed timer; the voltage of the capacitor is sampled to obtain a target voltage sample value, including:

[0023] The charging voltage of the capacitor is sampled to obtain the actual voltage sample value;

[0024] Obtain the voltage compensation parameters corresponding to the capacitor;

[0025] Based on the voltage compensation parameters, voltage compensation is performed on the actual voltage sample value to obtain the target voltage sample value.

[0026] In one embodiment, the preset charging characteristic mapping table includes a correspondence between multiple charging times and multiple theoretical voltage sample values; obtaining the voltage compensation parameters corresponding to the capacitor includes:

[0027] When the control chip is in a non-sleep state, the capacitor is charged through the control chip;

[0028] The charging time of the capacitor is timed by a preset reference clock until the charging time of the capacitor reaches the preset time. The charging voltage of the capacitor is then sampled to obtain the initial voltage sampling value to be calibrated.

[0029] The target theoretical voltage sampling value corresponding to the preset timing time is determined from the preset charging characteristic mapping table;

[0030] The voltage compensation parameters are determined based on the voltage sampling value deviation between the initial voltage sampling value to be calibrated and the target theoretical voltage sampling value.

[0031] In one embodiment, clock calibration of the sleep timer based on the actual charging time and the sleep clock count value includes:

[0032] Obtain the hibernation baseline time;

[0033] The second actual low-speed clock cycle is determined based on the actual charging time and the sleep clock count value.

[0034] The first calibration clock count value is determined based on the second actual low-speed clock cycle and the sleep reference time;

[0035] The sleep timer is clock-calibrated based on the first calibration clock count value.

[0036] In one embodiment, the method further includes:

[0037] When the control chip is in a non-sleep state, the program execution time required for the control chip to enter a sleep state is calculated using a high-speed timer in the control chip.

[0038] The program execution clock count value is determined based on the program execution time and the high-speed clock period of the high-speed timer;

[0039] The difference between the first calibration clock count value and the program execution clock count value is determined as the second calibration clock count value;

[0040] The sleep timer is clock-calibrated based on the second calibration clock count value.

[0041] Secondly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method described in any of the embodiments of the first aspect above.

[0042] Thirdly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any of the embodiments of the first aspect above.

[0043] Fourthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method described in any of the embodiments of the first aspect above.

[0044] The aforementioned clock calibration method, computer equipment, readable storage medium, and program product: The method acquires the sleep clock count value of the control chip; while the control chip is in sleep mode, it charges the RC calibration circuit and triggers a sleep timer to count clocks; if the first actual clock count value of the sleep timer reaches the sleep clock count value, charging the RC calibration circuit stops, and the actual charging time of the RC calibration circuit is determined; based on the actual charging time and the sleep clock count value, the sleep timer is clock-calibrated. Clock calibration based on the RC calibration circuit eliminates the need for external high-cost crystal oscillators or RTC modules, effectively reducing hardware costs and system complexity. Simultaneously, it enables calibration operations during the control chip's sleep state, balancing low power consumption, high precision, and low cost, and avoiding problems such as large sleep timing errors and inaccurate system wake-up due to unstable clock sources and environmental changes. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a flowchart illustrating a clock calibration method in one embodiment;

[0047] Figure 2 This is a schematic diagram of the RC calibration circuit in one embodiment;

[0048] Figure 3 This is a flowchart illustrating the steps for obtaining the pre-calibrated low-speed clock cycle in one embodiment.

[0049] Figure 4 This is a flowchart illustrating the steps for determining the actual charging time in one embodiment;

[0050] Figure 5 This is a flowchart illustrating the steps for obtaining voltage compensation parameters in one embodiment;

[0051] Figure 6 This is a flowchart illustrating the clock calibration steps for a sleep timer in one embodiment;

[0052] Figure 7 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0054] With changes in the economic environment and intensified market competition, various industries are increasingly demanding higher standards for product cost control. This is especially true for mass-produced products, where even minor optimizations in hardware costs can yield significant economic benefits. Against this backdrop, chip localization has become a crucial means of reducing hardware costs, particularly in applications with large product shipment volumes. Using domestically produced chips not only helps reduce procurement costs but also enhances the self-controllability of the supply chain. However, some low-cost chips based on the 51 microcontroller core suffer from significant issues with low-speed clock accuracy. These accuracy issues are significantly affected by factors such as temperature and voltage, with some models exhibiting deviations as high as ±50%, and the deviations between chips are irregular, severely impacting system timing stability. Traditional solutions often use high-speed clocks or external RTCs and high-precision crystal oscillators for calibration. However, the high cost of external components limits their application in low-cost scenarios. Therefore, this application provides a clock calibration method that aims to effectively solve the clock deviation problem caused by poor low-speed clock accuracy in control chips, improving system timing accuracy and operational reliability, while balancing low-cost and low-power design.

[0055] In one embodiment, such as Figure 1 As shown, Figure 1This is a flowchart illustrating a clock calibration method in one embodiment. The clock calibration method is applied to a control chip, which includes a sleep timer. The control chip may include, but is not limited to, a 51-core control chip, and is not specifically limited here. The sleep timer is used to count based on a low-speed clock source after the control chip enters a sleep state, and triggers a wake-up when a pre-designed value is reached. In an exemplary embodiment, when the control chip is a CMS8S69xx series microchip, the sleep timer is a WUT (Wake-up Timer). It is understood that because the low-speed clock source (such as an internal RC oscillator) of this type of control chip has a large frequency deviation (up to ±50%) over a wide temperature range, the timing accuracy of the WUT timer cannot be guaranteed, making it difficult to ensure that the control chip is accurately woken up at a predetermined time, affecting the reliable execution of system timing tasks and the real-time performance of communication responses. Based on this, the clock calibration method provided in this application can effectively solve the clock deviation problem caused by the poor accuracy of the low-speed clock in the control chip while taking into account low cost and low power consumption design. The clock calibration method includes the following steps:

[0056] Step S101: Obtain the sleep clock count value of the control chip.

[0057] The sleep clock count value refers to the pre-corrected count target value preset by the control chip for the sleep timer before entering sleep mode.

[0058] In an exemplary embodiment, the sleep clock count value = sleep reference time / pre-calibrated low-speed clock cycle; whereby the sleep reference time refers to the target sleep duration that the system expects the control chip to maintain in low-power sleep mode. The sleep reference time needs to be set according to specific application requirements, for example, it can be 25ms, and is not specifically limited here.

[0059] It should be noted that, since the low-speed clock frequency is affected by factors such as temperature and voltage and has a large deviation (e.g., ±50%), if the sleep clock count is calculated directly based on the theoretical low-speed clock cycle, the actual sleep time will deviate significantly from the expected target. Therefore, calculating the sleep clock count based on the pre-calibrated low-speed clock cycle can provide a reliable data basis that conforms to the actual situation for subsequent clock calibration.

[0060] In step S102, while the control chip is in sleep mode, the RC calibration circuit is charged by the control chip and the sleep timer is triggered to count clock cycles.

[0061] The RC calibration circuit includes a capacitor and a resistor; the resistor and capacitor are connected in series between a preset interface of the control chip and ground; the preset interface is used to provide a charging voltage to the RC calibration circuit. In an exemplary embodiment, the working principle diagram of the RC calibration circuit is as follows: Figure 2 As shown, the RC calibration circuit includes a capacitor C1 and a resistor R1. Resistor R1 and capacitor C1 are connected in series between the preset interface of the control chip and ground, forming a charging and discharging loop. The ADC (Analog-to-Digital Converter) is used for analog-to-digital conversion to acquire the voltage across the capacitor. The values ​​of resistor R1 and capacitor C1 need to be set according to the actual calibration requirements and are not specifically limited here; for example, R1 = 100KΩ, C1 = 0.1uF.

[0062] Step S103: If the first actual clock count value of the sleep timer is detected to reach the sleep clock count value, then stop charging the RC calibration circuit and determine the actual charging time of the RC calibration circuit.

[0063] One method for determining the actual charging time of the RC calibration circuit is to determine the actual charging time by detecting the voltage across the capacitor at the end of charging, based on the charging voltage response characteristics of the RC calibration circuit. It should be noted that during charging, the capacitor's charging voltage V... C The variation of (t) with time follows the formula below:

[0064] V C (t) = V0(1-e -t / τ );

[0065] Where τ = R1 × C1; V C (t) represents the voltage of capacitor C1 at charging time t; V0 represents the voltage output by the preset interface of the control chip, i.e., the voltage of VCC (e.g., VCC=5V).

[0066] Step S104: Based on the actual charging time and the sleep clock count value, perform clock calibration on the sleep timer.

[0067] In an exemplary embodiment, assuming the sleep clock count value of the control chip is n; when the control chip is in sleep mode, the output of the preset interface of the control chip is configured to a high level to charge the capacitor and trigger the sleep timer to count the clock until the first actual clock count value of the sleep timer reaches the sleep clock count value n. Then, the output of the preset interface of the control chip is configured to a low level to stop charging the capacitor. At the same time, the actual charging time of the RC calibration circuit is determined to be m us. Further, based on the actual charging time m us and the sleep clock count value n, the current actual low-speed clock period T = m / n us can be calculated. Further, assuming the sleep reference time is 25ms, the calibration clock count value X = 25000 / T can be calculated based on the current actual low-speed clock period T = m / n us. Then, based on the calibration clock count value X = 25000 / T, the sleep timer is clock calibrated to ensure the timing accuracy of the sleep timer, thereby ensuring that the control chip can be accurately woken up at the predetermined time.

[0068] It is understood that the clock calibration process in this embodiment is performed when the control chip enters a low-power sleep state (such as STOP mode), which can make full use of the limited resources during the sleep period and realize real-time calibration of clock deviation, fully taking into account the low-power design requirements of the system.

[0069] In this embodiment, clock calibration is achieved based on an RC calibration circuit, eliminating the need for external high-cost crystal oscillators or RTC modules, effectively reducing hardware costs and system complexity. At the same time, the calibration operation can be completed during the control chip's sleep process, taking into account multiple requirements of low power consumption, high precision, and low cost, and avoiding problems such as large sleep timing errors and inaccurate system wake-up caused by unstable clock sources, environmental changes, and other factors.

[0070] In one embodiment, obtaining the sleep clock count value of the control chip includes the following steps:

[0071] Step 1: Obtain the pre-calibrated low-speed clock cycle and sleep reference time.

[0072] Step 2: Determine the sleep clock count value based on the pre-calibrated low-speed clock cycle and sleep reference time.

[0073] The pre-calibrated low-speed clock cycle refers to the low-speed clock cycle after initial calibration each time the control chip is powered on.

[0074] The sleep reference time refers to the target sleep duration that the system expects the control chip to maintain in low-power sleep mode. It should be noted that the sleep reference time needs to be set according to specific application requirements; for example, the sleep reference time can be 25ms, and no specific limitation is made here.

[0075] The sleep clock count value refers to the pre-corrected count target value preset by the control chip for the sleep timer before entering sleep mode.

[0076] For example, assuming the sleep reference time is 25ms and the pre-calibrated low-speed clock period is T0, the sleep clock count value n = 25000 / T0 can be obtained.

[0077] It should be noted that although the low-speed clock has been pre-calibrated, its period T0 may still have residual deviations under actual operating conditions (such as temperature and voltage changes). This means that the sleep clock count calculated based on the pre-calibrated low-speed clock period cannot completely guarantee that the actual sleep duration is exactly equal to the sleep reference time. To ensure that the actual sleep duration is highly consistent with the set sleep reference time, the sleep clock count needs to be further corrected to achieve high-precision clock calibration of the sleep timer.

[0078] In this embodiment, by obtaining the pre-calibrated low-speed clock period and the set sleep reference time, and calculating and determining the sleep clock count value based on the two, preliminary accuracy optimization of the sleep timer is achieved without relying on an external high-precision clock source.

[0079] In one embodiment, such as Figure 3 As shown, Figure 3 This is a flowchart illustrating the steps for obtaining the pre-calibrated low-speed clock cycle in one embodiment; obtaining the pre-calibrated low-speed clock cycle includes the following steps:

[0080] Step S301: After each power-on, if the control chip receives the first data frame sent by the external host, it enters a sleep state and triggers the sleep timer to count the clock.

[0081] The external host can be, but is not limited to, a host computer or main control device with data communication and control functions; the external host is connected to the control chip.

[0082] It should be noted that in this embodiment, the data frame transmission period of the external host has high time accuracy. Since the UART communication frames on the external host side are driven by its internal high-precision clock source and transmitted according to a fixed timing mechanism, the time interval between adjacent data frames remains highly stable. Specifically, the time interval from the end of the current data frame to the arrival of the start bit of the next frame is a fixed value, denoted as T2. For example, if the external host is set to send one frame of communication data every 100 ms, then this time interval T2 = 100 ms; it remains strictly constant on the host side and is not affected by significant clock drift. This stable transmission period characteristic makes the data frame transmission period T2 an important reference benchmark for clock synchronization and calibration during the initial power-up of the control chip.

[0083] Step S302 continues until the control chip receives the next data frame, exits the sleep state, and reads the clock count value of the sleep timer to obtain the second actual clock count value.

[0084] The second actual clock count value refers to the number of clock pulses actually accumulated by the sleep timer based on the low-speed clock source from the time the control chip receives the first data frame and enters sleep mode until it is woken up by external communication.

[0085] Step S303: Determine the first actual low-speed clock cycle corresponding to the sleep timer based on the data frame transmission period corresponding to the external host and the second actual clock count value.

[0086] Step S304: Based on the first actual low-speed clock cycle, perform clock pre-calibration on the low-speed clock corresponding to the sleep timer to obtain the pre-calibrated low-speed clock cycle.

[0087] For example, the RXD pin of the control chip is configured to trigger on an interrupt (e.g., falling edge) to detect the start bit of a data frame sent by an external host. After power-on initialization, the control chip receives the first data frame sent by the external host through the RXD pin. After fully receiving and processing the frame data, it enters a low-power sleep state (e.g., STOP mode) and starts a sleep timer (e.g., WUT) to begin counting based on an internal low-speed clock. When the external host sends the next data frame according to a fixed data frame transmission period T2, the start bit (falling edge) of the data frame triggers an interrupt through the RXD pin, waking the chip from sleep mode. After waking up, the program immediately reads the current count value of the sleep timer, which is recorded as the second actual clock count value a. Based on this, according to the data frame transmission period T2 corresponding to the external host and the second actual clock count value a, the first actual low-speed clock period corresponding to the sleep timer can be determined to be T2 / a.

[0088] Furthermore, to ensure the accuracy of the first actual low-speed clock cycle, the first actual low-speed clock cycle can be calibrated multiple times by software filtering. The specific calibration method can be found in the software calibration method in the prior art, and will not be elaborated here.

[0089] It should be noted that the low-speed clock cycle pre-calibration method described in this embodiment is performed only once during the power-on initialization phase of the control chip. During this process, the control chip enters a sleep state after receiving and processing the first data frame. At this time, the RXD pin is configured in edge-interrupt mode to detect the start bit of the next frame. When the host sends the second data frame, the falling edge of its start bit can trigger the chip to wake up. However, since the control chip is in a sleep state and the UART is not yet ready, it cannot complete the reception of this frame's data, and therefore, this frame's data will inevitably be lost. To avoid communication frame loss affecting normal system operation, the low-speed clock cycle pre-calibration is performed only once after the control chip powers on, and this calibration process is not repeated during subsequent normal operation, ensuring stable and reliable data interaction with the external host.

[0090] In this embodiment, the high-precision data frame transmission period of the external host is used as a time reference, and clock calibration of the internal low-speed clock during the power-on initialization phase can be achieved without additional hardware, laying the foundation for further clock calibration.

[0091] In one embodiment, such as Figure 4 As shown, Figure 4 This is a flowchart illustrating the steps for determining the actual charging time in one embodiment; determining the actual charging time of the RC calibration circuit includes the following steps:

[0092] Step S401: Sample the voltage of the capacitor to obtain the target voltage sample value.

[0093] In one exemplary embodiment, the control chip is equipped with a high-speed timer; it should be noted that the high-speed timer has a high-precision, high-speed clock source; sampling the voltage of the capacitor to obtain the target voltage sample value includes the following steps:

[0094] Step 1: Sample the charging voltage of the capacitor to obtain the actual voltage sample value.

[0095] The actual voltage sample value refers to the raw voltage data obtained by sampling the voltage across the capacitor through the ADC (analog-to-digital converter) built into the control chip.

[0096] Step 2: Obtain the voltage compensation parameters corresponding to the capacitor.

[0097] Among them, the voltage compensation parameter is used to correct the error of the actual voltage sampling value and compensate for systematic measurement deviations and RC device deviations.

[0098] Step 3: Perform voltage compensation on the actual voltage sample value according to the voltage compensation parameters to obtain the target voltage sample value.

[0099] Step S402: Based on the target voltage sampling value, determine the target charging time that matches the target voltage sampling value from the preset charging characteristic mapping table.

[0100] Step S403: The target charging time is determined as the actual charging time of the RC calibration circuit.

[0101] The preset charging characteristic mapping table includes the correspondence between multiple charging times and multiple theoretical voltage sample values.

[0102] Understandably, by establishing a pre-defined correspondence between theoretical voltage sampling values ​​and charging times, and storing it in the control chip in the form of a preset charging characteristic mapping table, the target charging time can be directly obtained by looking up the table after the target voltage sampling value is detected. This avoids the computational overhead and delay caused by real-time calculation of charging time, reduces the computational overhead of clock calibration, and improves the system response speed and energy efficiency.

[0103] In an exemplary embodiment, the preset charging characteristic mapping table can be established based on the following formula:

[0104] V C (t) = V0(1-e -t / τ );

[0105] Where τ = R1 × C1, V C (t) represents the voltage of capacitor C1 at charging time t; V0 represents the voltage output by the preset interface of the control chip, i.e., the voltage of VCC (e.g., VCC=5V).

[0106] Taking a time scale of 50us as an example, that is, when time t is equal to 50us, 100us, 150us, ..., it corresponds to a V. C (t) Voltage value, V C (t) The voltage value is converted into an ADC sample value and stored in a table, resulting in the preset charging characteristic mapping table shown in Table 1. Furthermore, based on the target voltage sample value, the target charging time matching the target voltage sample value can be determined from the preset charging characteristic mapping table by looking up the table, reducing the computational cost of the control chip. It is understood that the smaller the scale of time t, the smaller the clock calibration error. The scale of time t can be set according to actual calibration requirements, and no specific limitation is made here.

[0107] Table 1 Preset Charging Characteristic Mapping Table

[0108]

[0109] It should be noted that, according to the preset charging characteristic mapping table shown in Table 1, the capacitor charging voltage gradually decreases over time, especially after exceeding 2τ (i.e., twice the time constant), the voltage change tends to saturate, and the time resolution capability decreases significantly. Therefore, to ensure the sensitivity and accuracy of charging time measurement, the charging interval within the range of 0 to 2τ is preferred as the calibration working interval.

[0110] Furthermore, to ensure accurate matching of actual charging time under all operating conditions, the preset charging characteristic mapping table should cover the maximum time drift range caused by low-speed clock deviation. For example, if the theoretically set sleep reference time is 5 ms, the actual sleep time may fluctuate between 2.5 ms and 7.5 ms because the frequency deviation of the low-speed clock can reach ±50% under wide temperature and variable voltage conditions. Therefore, the corresponding RC charging time measurement range should cover this range as much as possible.

[0111] In this embodiment, by pre-establishing the correspondence between theoretical voltage sampling values ​​and charging times and storing it in the control chip in the form of a preset charging characteristic mapping table, the target charging time can be directly obtained by looking up the table after detecting the target voltage sampling value. This avoids the computational overhead of real-time calculation of charging time, reduces the computational overhead of clock calibration, and improves system response speed and energy efficiency. Simultaneously, by obtaining voltage compensation parameters to correct errors in actual voltage sampling values, systematic measurement deviations can be effectively compensated, further ensuring the reliability of clock calibration.

[0112] In one embodiment, such as Figure 5 As shown, Figure 5 This is a flowchart illustrating the steps for obtaining voltage compensation parameters in one embodiment; obtaining the voltage compensation parameters corresponding to the capacitor includes the following steps:

[0113] Step S501: When the control chip is in a non-sleep state, the capacitor is charged through the control chip.

[0114] Step S502: The charging time of the capacitor is timed using a preset reference clock until the charging time reaches the preset timing time. The charging voltage of the capacitor is sampled to obtain the initial voltage sampling value to be calibrated.

[0115] The preset reference clock is either a high-speed clock source corresponding to the high-speed timer of the control chip, or the preset reference clock is provided by an external host.

[0116] It should be noted that the RC calibration circuit is composed of resistors and capacitors of conventional precision, and these discrete components have inherent tolerances. The precision of ordinary resistors and capacitors is generally ±5% or ±10%, and even under the same nominal value, the actual parameters may have significant deviations. While high-precision components (such as ±0.1%) can reduce errors, their cost increases significantly, which is not conducive to achieving the overall cost reduction goal of the product.

[0117] Therefore, to balance cost and calibration accuracy, it is necessary to further compensate for errors in RC calibration circuits that use conventional precision RC components. Generally, the control chip (such as a microcontroller based on the 51 core) and the external host are equipped with a high-precision, high-speed clock source with good frequency stability and small clock deviation, which can be used to assist in calibrating the RC calibration circuit.

[0118] The preset timing time needs to be set according to the actual calibration requirements, and there is no specific limit here. For example, the preset timing time can be 5 ms.

[0119] The initial voltage sample value to be calibrated refers to the raw voltage data directly acquired from the two ends of the capacitor in the RC calibration circuit through the ADC (analog-to-digital converter) before voltage compensation.

[0120] Step S503: Determine the target theoretical voltage sampling value corresponding to the preset timing time from the preset charging characteristic mapping table.

[0121] In other exemplary embodiments, the method for determining the target theoretical voltage sample value may also be: substituting a preset timing period into the formula V C (t) = V0(1-e -t / τ In the calculation, the corresponding target theoretical voltage sampling value is obtained directly. The method for determining the target theoretical voltage sampling value can be adapted according to actual needs, and no specific limitation is made here.

[0122] Step S504: Determine the voltage compensation parameters based on the voltage sampling value deviation between the initial voltage sampling value to be calibrated and the target theoretical voltage sampling value.

[0123] For example, when the control chip is in a non-sleep state, the output of the preset interface of the control chip is configured to a high level to charge the capacitor. The charging time of the capacitor is timed using a preset reference clock until the charging time reaches a preset timing period (e.g., 5 ms). The charging voltage of the capacitor is sampled to obtain the initial voltage sample value to be calibrated. The target theoretical voltage sample value corresponding to the preset timing period is determined from a preset charging characteristic mapping table. Voltage compensation parameters are determined based on the voltage sample value deviation between the initial voltage sample value to be calibrated and the target theoretical voltage sample value.

[0124] It should be noted that the acquisition and updating of the aforementioned voltage compensation parameters can be performed periodically, for example, by triggering a voltage compensation parameter acquisition process once during a system periodic wake-up window. By periodically acquiring the voltage response characteristics of the RC circuit under the current environment and combining this with recalculating the voltage compensation parameters, measurement deviations caused by factors such as temperature drift, voltage fluctuations, or device aging can be effectively compensated.

[0125] In this embodiment, by combining the high-speed timer inside the control chip or the high-precision time reference provided by the external host, the parameter deviation of conventional RC devices can be effectively compensated without adding high-cost precision components, thus achieving low-cost and high-reliability clock calibration.

[0126] In one embodiment, such as Figure 6 As shown, Figure 6 This is a flowchart illustrating the clock calibration steps for a sleep timer in one embodiment; the sleep timer is clock calibrated based on the actual charging time and the sleep clock count value, including the following steps:

[0127] Step S601: Obtain the sleep reference time.

[0128] Step S602: Determine the second actual low-speed clock cycle based on the actual charging time and the sleep clock count value.

[0129] For example, the ratio of the actual charging time to the sleep clock count value is determined as the second actual low-speed clock cycle, that is, the second actual low-speed clock cycle = actual charging time / sleep clock count value.

[0130] Step S603: Determine the first calibration clock count value based on the second actual low-speed clock cycle and the sleep reference time.

[0131] For example, the ratio of the sleep reference time to the second actual low-speed clock cycle is determined as the first calibration clock count value, that is, the first calibration clock count value = sleep reference time / second actual low-speed clock cycle.

[0132] Step S604: Perform clock calibration on the hibernation timer based on the first calibration clock count value.

[0133] For example, the sleep clock count value is updated to the first calibration clock count value to achieve clock calibration of the sleep timer and ensure that the actual sleep duration of the control chip is consistent with the preset sleep reference time.

[0134] It should be noted that the core purpose of clock calibration is to ensure that the actual sleep duration of the control chip is consistent with the preset sleep reference time. Since the sleep reference time is a fixed target value set according to application requirements, while the actual period of the low-speed clock is time-varying due to environmental factors such as temperature and voltage, it is a dynamic variable. Therefore, if the sleep clock count value used for sleep timing is still calculated using a clock period that has not been corrected in real time, timing deviations will accumulate.

[0135] Therefore, it is necessary to dynamically calculate and set the corresponding first calibration clock count value based on the low-speed clock cycle that reflects the current working conditions in real time, and to calibrate the sleep timer. By incorporating the second actual low-speed clock cycle and the first calibration clock count value into the calibration logic, adaptive adjustment of the count value is achieved, ensuring that the sleep reference time is continuously approached under different operating conditions. Ultimately, this achieves a high degree of consistency between the actual sleep time and the sleep reference time, improving the accuracy and reliability of the system's timing control.

[0136] In one embodiment, the clock calibration method further includes the following steps:

[0137] Step 1: When the control chip is not in sleep mode, calculate the program execution time required for the control chip to enter sleep mode using the high-speed timer in the control chip.

[0138] Among them, program execution time refers to the time consumed by the control chip from triggering sleep mode to actually entering the sleep state.

[0139] Step 2: Determine the program execution clock count value based on the program execution time and the high-speed clock cycle of the high-speed timer.

[0140] Step 3: Determine the difference between the first calibration clock count value and the program execution clock count value as the second calibration clock count value.

[0141] Step 4: Perform clock calibration on the hibernation timer based on the second calibration clock count value.

[0142] For example, when the control chip is in a non-sleep state, a high-speed timer is activated. The high-speed timer is used to calculate the program execution time required for the control chip to go from triggering sleep to actually entering the sleep state. The ratio of the program execution time to the high-speed clock cycle of the high-speed timer is determined as the program execution clock count value. Further, the difference between the first calibration clock count value and the program execution clock count value is determined as the second calibration clock count value. The sleep clock count value is updated to the second calibration clock count value to achieve clock calibration of the sleep timer.

[0143] In this embodiment, the timing deviation caused by software execution delay is further compensated, and the time control accuracy of the system in sleep mode is further improved.

[0144] In a specific embodiment, taking the CMS8S69xx series microchip as an example (the following descriptions are all actual chip conditions, and the chip datasheet can be consulted): (1) In order to minimize the power consumption of the product, the STOP sleep mode of the chip needs to be used. However, in this sleep mode, except for the LVD module (low voltage detection module) and LSE module (external low-speed clock timer), all other circuits are turned off, and the digital circuits do not work. Among them, the LSE module requires an external crystal oscillator to work; UART and other circuits cannot work during sleep, and the product application layer must be woken up from sleep and work under a high-speed clock. The high-speed clock and the low-speed clock cannot work at the same time. (2) Sleep wake-up can only be woken up by external edge interrupt, WUT timer wake-up, and LSE timer wake-up; among them, the WUT wake-up timer can only work when entering the STOP sleep mode, using a low-speed clock, and the sleep time is determined according to the count value set by WUT. Moreover, WUT has no interrupt, and can only be woken up from the STOP sleep mode when WUT counts to the set value. In addition, WUT uses a low-speed clock, and the clock deviation range of the low-speed clock in the range of -40℃ to 105℃ is ±50%. LSE has an interrupt wake-up function, but it requires an external crystal oscillator to work.

[0145] In summary, the 51-core chip has the following problems: (1) The low-speed clock deviation can reach up to 50% and -50%, which is extremely large and poses a significant risk to device stability. Clock calibration is necessary. (2) Key peripherals cannot work during sleep mode and must be woken up before they can work. Therefore, serial communication frames are sent between the master and slave devices at regular intervals. So, during serial communication, the device must be woken up in advance to ensure that no frames are lost. If the clock deviation is large, the counting will be inaccurate, and it is easy to lose frames in serial communication if the device is not woken up in advance. In order to ensure that no frames are lost, the device needs to be woken up in advance for a long time, but this will greatly increase the power consumption of the product. (3) The high-speed clock and the low-speed clock cannot work at the same time, and the high-speed clock cannot be used to calibrate the low-speed clock. (4) There is no timer interrupt during sleep mode. The sleep time is determined by a specific timer setting value. Because the low-speed clock deviation is large, the time deviation represented by each count value is large, resulting in a large deviation in the sleep time. Because there is no available timer during sleep, the product's scheduled tasks can only use the sleep time as a time base and accumulate counts. For example, if the WUT is theoretically set to sleep once every 25ms, the timer can be based on the number of sleeps of the WUT. For example, if the application layer task is executed once every 2 seconds, it is necessary to wait 2000ms / 25ms=80 times and accumulate 80 times to execute the application layer task once. If the 25ms clock deviation is large, the execution time deviation of the application layer task will be large, affecting the product's functionality.

[0146] Although this chip has certain limitations in performance, it has a significant cost advantage compared to similar products, which can greatly reduce the overall hardware cost. Therefore, in application scenarios where cost is limited, this chip is the preferred solution. Based on the clock calibration method described in the above embodiments, the key problem of large low-speed clock deviation can be effectively solved, thereby ensuring the stable operation and long-term reliability of the product under all operating conditions.

[0147] In one specific embodiment, taking any power-on of the control chip as an example, the clock calibration method is described as follows: After the control chip is powered on, if the control chip receives the first data frame sent by the external host, it enters a sleep state and triggers a sleep timer to count the clock. Until the control chip receives the next data frame, it exits the sleep state and reads the clock count value of the sleep timer to obtain the second actual clock count value. Based on the data frame transmission period corresponding to the external host and the second actual clock count value, the first actual low-speed clock period corresponding to the sleep timer is determined. Based on the first actual low-speed clock period, the low-speed clock corresponding to the sleep timer is pre-calibrated to obtain the pre-calibrated low-speed clock period.

[0148] Furthermore, when the control chip is in a non-sleep state, the capacitor is charged through the control chip; the charging time of the capacitor is timed by a preset reference clock until the charging time of the capacitor reaches the preset timing time, the charging voltage of the capacitor is sampled to obtain the initial voltage sample value to be calibrated; the target theoretical voltage sample value corresponding to the preset timing time is determined from the preset charging characteristic mapping table; the voltage compensation parameters are determined based on the voltage sample value deviation between the initial voltage sample value to be calibrated and the target theoretical voltage sample value.

[0149] Further, the sleep reference time is obtained; based on the pre-calibrated low-speed clock cycle and the sleep reference time, the sleep clock count value is determined. While the control chip is in sleep mode, the RC calibration circuit is charged via the control chip, triggering the sleep timer to count clock signals. If the first actual clock count value of the sleep timer reaches the sleep clock count value, charging of the RC calibration circuit is stopped, and the charging voltage of the capacitor is sampled to obtain the actual voltage sample value. Voltage compensation is performed on the actual voltage sample value according to the voltage compensation parameters to obtain the target voltage sample value. Based on the target voltage sample value, the target charging time matching the target voltage sample value is determined from a preset charging characteristic mapping table. The target charging time is determined as the actual charging time of the RC calibration circuit. The sleep timer is clock-calibrated based on the actual charging time and the sleep clock count value.

[0150] It is understandable that the aforementioned pre-calibration process for the low-speed clock cycle is only performed once during the power-on initialization phase of the control chip to determine the sleep clock count value. The subsequent voltage compensation parameter determination process and the sleep timer clock calibration process can be dynamically updated periodically or on demand according to changes in the system operating environment (such as temperature fluctuations, voltage drift, etc.).

[0151] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0152] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 7 As shown, this computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operating system and computer programs stored in the non-volatile storage media. The database stores clock calibration-related data. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements a clock calibration method.

[0153] Those skilled in the art will understand that Figure 7 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0154] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0155] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0156] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0157] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0158] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0159] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0160] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A clock calibration method, characterized in that, The method is applied to a control chip, wherein the control chip includes a sleep timer; the method includes: Obtain the sleep clock count value of the control chip; When the control chip is in sleep mode, the RC calibration circuit is charged by the control chip and the sleep timer is triggered to count clock cycles. If the first actual clock count value of the sleep timer is detected to reach the sleep clock count value, then the charging of the RC calibration circuit is stopped, and the actual charging time of the RC calibration circuit is determined. The sleep timer is clock-calibrated based on the actual charging time and the sleep clock count value. The RC calibration circuit includes a capacitor and a resistor; the resistor and the capacitor are connected in series between a preset interface of the control chip and ground; determining the actual charging time of the RC calibration circuit includes: The charging voltage of the capacitor is sampled to obtain the actual voltage sample value; Obtain the voltage compensation parameters corresponding to the capacitor; Based on the voltage compensation parameters, voltage compensation is performed on the actual voltage sample value to obtain the target voltage sample value; Based on the target voltage sampling value, a target charging time matching the target voltage sampling value is determined from a preset charging characteristic mapping table; The target charging time is determined as the actual charging time of the RC calibration circuit.

2. The method according to claim 1, characterized in that, The step of obtaining the sleep clock count value of the control chip includes: Obtain the pre-calibrated low-speed clock cycle and sleep reference time; The sleep clock count value is determined based on the pre-calibrated low-speed clock cycle and the sleep reference time.

3. The method according to claim 2, characterized in that, The process of obtaining the pre-calibrated low-speed clock period includes: After each power-on, if the control chip receives the first data frame sent by the external host, it enters a sleep state and triggers the sleep timer to count the clock. Until the control chip receives the next data frame, it exits the sleep state and reads the clock count value of the sleep timer to obtain the second actual clock count value; The first actual low-speed clock cycle corresponding to the sleep timer is determined based on the data frame transmission period corresponding to the external host and the second actual clock count value. Based on the first actual low-speed clock cycle, the low-speed clock corresponding to the sleep timer is pre-calibrated to obtain the pre-calibrated low-speed clock cycle.

4. The method according to claim 1, characterized in that, The preset charging characteristic mapping table includes the correspondence between multiple charging times and multiple theoretical voltage sample values; obtaining the voltage compensation parameters corresponding to the capacitor includes: When the control chip is in a non-sleep state, the capacitor is charged through the control chip; The charging time of the capacitor is timed by a preset reference clock until the charging time of the capacitor reaches the preset time. The charging voltage of the capacitor is then sampled to obtain the initial voltage sampling value to be calibrated. The target theoretical voltage sampling value corresponding to the preset timing time is determined from the preset charging characteristic mapping table; The voltage compensation parameters are determined based on the voltage sampling value deviation between the initial voltage sampling value to be calibrated and the target theoretical voltage sampling value.

5. The method according to claim 1, characterized in that, The step of clock calibration of the sleep timer based on the actual charging time and the sleep clock count value includes: Obtain the hibernation baseline time; The second actual low-speed clock cycle is determined based on the actual charging time and the sleep clock count value. The first calibration clock count value is determined based on the second actual low-speed clock cycle and the sleep reference time; The sleep timer is clock-calibrated based on the first calibration clock count value.

6. The method according to claim 5, characterized in that, The method further includes: When the control chip is in a non-sleep state, the program execution time required for the control chip to enter a sleep state is calculated using a high-speed timer in the control chip. The program execution clock count value is determined based on the program execution time and the high-speed clock period of the high-speed timer; The difference between the first calibration clock count value and the program execution clock count value is determined as the second calibration clock count value; The sleep timer is clock-calibrated based on the second calibration clock count value.

7. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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