Display panel and display device

Abstract

The application relates to a display panel and a display device; the display panel comprises a plurality of pixel driving circuits, the pixel driving circuit comprises a driving transistor, a compensation transistor and a first connecting line, the gate of the driving transistor and the source of the compensation transistor are connected to a first node; the compensation transistor further comprises a compensation active part, the first connecting line is connected between the compensation active part and the gate of the driving transistor; wherein the display panel further comprises a first control signal line connected to the gate of the compensation transistor, the first connecting line and the first control signal line are intersected and overlapped in the thickness direction of the display panel, and the intersected and overlapped part forms a voltage stabilizing capacitor; the application can reduce the leakage current generated at the first node of the compensation transistor in the off state, plays a voltage stabilizing role on the gate potential of the driving transistor, improves the phenomenon of the leakage current generated by the compensation transistor, and improves the display uniformity of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the development of the LCD field, the advantages of organic light-emitting diode (OLED) display panels, such as self-illumination and thinness, have been increasingly used in products such as TVs, mobile phones, and laptops.

[0003] Since OLED display panels are current-driven, when the threshold voltage Vth of the thin film transistor (TFT) shifts, the current drive of the OLED will become unstable and change, resulting in uneven brightness. For example, in the pixel driving circuit of an OLED display panel, the compensation transistor connected to the gate of the driving transistor is prone to leakage current, which leads to unstable gate voltage of the driving transistor and causes uneven display. Summary of the Invention

[0004] This application provides a display panel and display device that can improve the leakage current phenomenon of compensation transistors and improve the display uniformity of the display panel.

[0005] This application provides a display panel, which includes multiple pixel driving circuits. Each pixel driving circuit includes a driving transistor, a compensation transistor, and a first connection line. The gate of the driving transistor and the source of the compensation transistor are both connected to a first node.

[0006] The compensation transistor further includes a compensation active part, and the first connection line is connected between the compensation active part and the gate of the driving transistor.

[0007] The display panel further includes a first control signal line connected to the gate of the compensation transistor. The first connection line and the first control signal line overlap along the thickness direction of the display panel, and the overlapping portion forms a voltage stabilizing capacitor.

[0008] In one embodiment of this application, a plurality of pixel driving circuits are arranged along a first direction and a second direction, and the first direction and the second direction intersect each other;

[0009] The display panel includes:

[0010] substrate;

[0011] A first semiconductor layer is disposed on the substrate, and the first semiconductor layer includes the compensation active portion and the driving active portion of the driving transistor.

[0012] The first control signal line extends along the first direction, the compensation active part and the driving active part both extend along the second direction, and the compensation active part is located on one side of the driving active part along the second direction and is connected to the driving active part.

[0013] In one embodiment of this application, the first connecting line extends along the second direction, and the first connecting line is located on one side of the compensation active part along the first direction and is connected to the compensation active part.

[0014] In one embodiment of this application, the pixel driving circuit further includes a first light-emitting control transistor and a switching transistor, wherein the source of the first light-emitting control transistor and the drain of the driving transistor are connected to a second node, and the source of the switching transistor and the source of the driving transistor are connected to a third node.

[0015] The display panel also includes:

[0016] A second semiconductor layer is disposed between the substrate and the first semiconductor layer. The second semiconductor layer includes a switching active portion of the switching transistor and a first light-emitting control active portion of the first light-emitting control transistor. The switching active portion and the first light-emitting control active portion are located on opposite sides of the driving active portion along the second direction.

[0017] The first light-emitting control active part is located on the side of the compensation active part away from the first connecting line.

[0018] In one embodiment of this application, the first light-emitting control active part is disposed near the connection between the compensation active part and the driving active part, and a first via and a second via are formed in the display panel. The first via is disposed corresponding to the connection between the compensation active part and the driving active part, and the second via is disposed corresponding to the first light-emitting control active part.

[0019] The display panel also includes:

[0020] A first conductive layer is disposed on the side of the first semiconductor layer away from the substrate, and the first conductive layer includes the first connecting line and the second connecting line;

[0021] The second connecting line is connected to the compensation active part and the driving active part through the first via, and the second connecting line is connected to the first light-emitting control active part through the second via.

[0022] In one embodiment of this application, the second connecting line and the first control signal line do not overlap along the thickness direction of the display panel.

[0023] In one embodiment of this application, the display panel further includes a first power signal line and a first light emission control signal line, and the first conductive layer further includes a third connecting line, the third connecting line being connected between the first power signal line and the first light emission control active part, and the first light emission control signal line and the first light emission control active part overlapping along the thickness direction of the display panel.

[0024] The first power signal line and the first light emission control signal line both extend along the first direction, and the first power signal line and the first light emission control signal line are located on opposite sides of the first control signal line along the second direction.

[0025] In one embodiment of this application, the first light-emitting control active part is located on the side of the first control signal line away from the first power signal line.

[0026] In one embodiment of this application, a protrusion is connected to the first power signal line, the protrusion extends along the second direction and is located on the side of the compensated active portion away from the substrate.

[0027] In one embodiment of this application, the protrusion at least partially overlaps with the voltage regulator capacitor along the thickness direction of the display panel.

[0028] In one embodiment of this application, the first light-emitting control active part includes a first sub-part connected to the third connecting line, a second sub-part connected to the second connecting line, and a third sub-part connected between the first sub-part and the second sub-part;

[0029] In two adjacent pixel driving circuits along the first direction, the first light-emitting active part in one pixel driving circuit shares a first sub-part with the first light-emitting active part in the other pixel driving circuit.

[0030] In one embodiment of this application, the first sub-part and the second sub-part both extend along the second direction, and the third sub-part extends along the first direction;

[0031] The two pixel driving circuits that share a first sub-part are arranged symmetrically with respect to the first sub-part.

[0032] In one embodiment of this application, the display panel further includes a data signal line extending along the second direction, and the data signal line is connected to a plurality of pixel driving circuits arranged along the second direction;

[0033] The second sub-part partially overlaps with the data signal line along the thickness direction of the display panel, and the first sub-part is located on the side of the data signal line away from the compensation active part.

[0034] In one embodiment of this application, the pixel driving circuit further includes a second light-emitting control transistor connected to the third node and the fourth node, and a light-emitting device connected to the fourth node;

[0035] The second semiconductor layer further includes a second light-emitting control active portion of the second light-emitting control transistor, the second light-emitting control active portion being located on the side of the switching active portion away from the driving active portion;

[0036] The first conductive layer further includes a fourth connecting line, which is connected between the driving active part and the second light-emitting control active part.

[0037] In one embodiment of this application, the pixel driving circuit further includes a reset transistor connected to the fourth node;

[0038] The first semiconductor layer further includes a reset active portion of the reset transistor, wherein the reset active portion is located on one side of the second light-emitting control active portion along the first direction;

[0039] The first conductive layer further includes a fifth connecting line, which is connected to the second light-emitting control active part and the reset active part, and is also electrically connected to the light-emitting device.

[0040] In one embodiment of this application, the first control signal line includes a first line segment and a second line segment connected together. The line width of the first line segment is greater than the line width of the second line segment. The first line segment overlaps with the compensation active portion along the thickness direction of the display panel. The first line segment overlaps with the first connecting line along the thickness direction of the display panel to form the voltage stabilizing capacitor.

[0041] In one embodiment of this application, the first control signal line includes a first sub-line and a second sub-line located on opposite sides of the compensated active portion along the thickness direction of the display panel. The first sub-line overlaps with the first connecting line along the thickness direction of the display panel, and the second sub-line overlaps with the first connecting line along the thickness direction of the display panel.

[0042] Wherein, the line width of the first sub-line corresponding to the first line segment is greater than the line width of the first sub-line corresponding to the second line segment, and / or the line width of the second sub-line corresponding to the first line segment is greater than the line width of the second sub-line corresponding to the second line segment.

[0043] In one embodiment of this application, the display panel further includes a plurality of repeating units arranged along the first direction and the second direction, and the repeating unit includes two pixel driving circuits arranged along the first direction, wherein the two pixel driving circuits in the repeating unit are arranged axially symmetrically.

[0044] In accordance with the above-mentioned objectives of this application, embodiments of this application also provide a display device, the display device including the display panel.

[0045] This application provides a display panel and a display device. By having a first connecting line and a first control signal line overlap along the thickness direction of the display panel, and the overlapping portion forming a voltage stabilizing capacitor, the leakage current generated at the first node of the compensation transistor in the off state can be reduced, thereby stabilizing the gate potential of the driving transistor, improving the phenomenon of leakage current generated by the compensation transistor, and improving the display uniformity of the display panel.

[0046] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0049] Figure 1 This is a film layer stacking diagram of a pixel circuit in one embodiment;

[0050] Figure 2 A film layer stacking pattern for a pixel driving circuit provided in an embodiment of this application;

[0051] Figure 3 This is a schematic diagram of a pixel driving circuit provided in an embodiment of this application;

[0052] Figure 4 This is a schematic diagram of a planar structure of a display panel provided in an embodiment of this application;

[0053] Figure 5 This is a schematic cross-sectional view of a display panel provided in an embodiment of this application;

[0054] Figure 6 Provided for the embodiments of this application Figure 2 Structural diagram of the middle shading layer;

[0055] Figure 7 Provided for the embodiments of this application Figure 2 Structure diagram of the second semiconductor layer;

[0056] Figure 8 Provided for the embodiments of this application Figure 2 Stack diagram of the middle light-shielding layer and the second semiconductor layer;

[0057] Figure 9 Provided for the embodiments of this application Figure 2 Structure diagram of the first gate layer;

[0058] Figure 10 Provided for the embodiments of this application Figure 2 Stack diagram of the middle light-shielding layer, the second semiconductor layer, and the first gate layer;

[0059] Figure 11 Provided for the embodiments of this application Figure 2 Structure diagram of the second gate layer;

[0060] Figure 12 Provided for the embodiments of this application Figure 2 Stack diagram of the light-shielding layer, the second semiconductor layer, the first gate layer, and the second gate layer;

[0061] Figure 13 Provided for the embodiments of this application Figure 2 Structure diagram of the first semiconductor layer;

[0062] Figure 14 Provided for the embodiments of this application Figure 2 Stack diagram of the light-shielding layer, the second semiconductor layer, the first gate layer, the second gate layer, and the first semiconductor layer;

[0063] Figure 15 Provided for the embodiments of this application Figure 2 Structure diagram of the third gate layer;

[0064] Figure 16 Provided for the embodiments of this application Figure 2 Stack diagram of the middle light-shielding layer, the second semiconductor layer, the first gate layer, the second gate layer, the first semiconductor layer, and the third gate layer;

[0065] Figure 17 Provided for the embodiments of this application Figure 2 Structure diagram of the fourth gate layer;

[0066] Figure 18 Provided for the embodiments of this application Figure 2Stack diagram of the middle light-shielding layer, the second semiconductor layer, the first gate layer, the second gate layer, the first semiconductor layer, the third gate layer, and the fourth gate layer;

[0067] Figure 19 Provided for the embodiments of this application Figure 2 Structure diagram of the first conductive layer;

[0068] Figure 20 Provided for the embodiments of this application Figure 2 Stack diagram of the middle light-shielding layer, the second semiconductor layer, the first gate layer, the second gate layer, the first semiconductor layer, the third gate layer, the fourth gate layer and the first conductive layer;

[0069] Figure 21 This is a schematic diagram of the structure of the first via and the second via in the display panel provided in the embodiments of this application;

[0070] Figure 22 Provided for the embodiments of this application Figure 2 Structure diagram of the second conductive layer;

[0071] Figure 23 Provided for the embodiments of this application Figure 2 Stack diagram of the light-shielding layer, the second semiconductor layer, the first gate layer, the second gate layer, the first semiconductor layer, the third gate layer, the fourth gate layer, the first conductive layer, and the second conductive layer;

[0072] Figure 24 This is a schematic diagram of the structure of the second semiconductor layer in the repeating unit provided in the embodiments of this application;

[0073] Figure 25 This is a stacked diagram of the light-shielding layer, second semiconductor layer, first gate layer, second gate layer, first semiconductor layer, third gate layer, fourth gate layer, first conductive layer, and second conductive layer in the repeating unit provided in the embodiments of this application;

[0074] Figure 26 Provided for the embodiments of this application Figure 2 Structure diagram of the third conductive layer;

[0075] Figure 27 This is a schematic diagram of the pixel driving circuit in Comparative Example 1 provided in the embodiments of this application;

[0076] Figure 28 This is a schematic diagram of the pixel driving circuit in Comparative Example 2 provided in the embodiments of this application;

[0077] Figure 29 Potential coupling curves of the compensation transistor and the first node in the embodiments provided in this application, Comparative Example 1 and Comparative Example 2.

[0078] Explanation of reference numerals in the attached figures:

[0079] T01, first transistor; T02, second transistor; T03, third transistor; T04, fourth transistor; T05, fifth transistor; T06, sixth transistor; Q, first point; A, second point;

[0080] AA, Display area; NA, Non-display area; PX, Subpixel;

[0081] T1, driving transistor; T2, switching transistor; T3, compensation transistor; T4, reset transistor; T5, first light-emitting control transistor; T6, second light-emitting control transistor; Cst, storage capacitor; Cst1, first plate; Cst2, second plate; Cw, voltage regulator capacitor; EL, light-emitting device; T1A, driving active section; T2A, switching active section; T3A, compensation active section; T4A, reset active section; T5A, first light-emitting control active section; T6A, second light-emitting control active section; N1, first node; N2, second node; N3, third node; N4 Fourth node; Scan1, first control signal line; Scan1a, first segment; Scan1b, second segment; Scan11, first sub-line; Scan12, second sub-line; Scan2, second control signal line; Data, data signal line; VDD, first power signal line; VDD1, protrusion; VSS, second power signal line; EM1, first light emission control signal line; EM2, second light emission control signal line; Scan3, third control signal line; Scan31, third sub-line; Scan32, fourth sub-line; VI, reset signal line;

[0082] 11. Substrate; 12. Barrier layer; 13. Buffer layer; 14. Light-shielding layer; 15. Gate drive circuit; 16. Bonding terminal; 21. First semiconductor layer; 22. Second semiconductor layer; 221. First sub-section; 222. Second sub-section; 223. Third sub-section; 31. First gate layer; 32. Second gate layer; 321. Bottom gate; 33. Third gate layer; 34. Fourth gate layer; 341. Third via; 41. First conductive layer; 4101. First via; 4102. Second via; 411. First connecting line; 412. Second connecting line; 413. Third connecting line; 414. Fourth connecting line; 415. Fifth connecting line Wiring; 416, Sixth connecting line; 417, Seventh connecting line; 42, Second conductive layer; 421, First adapter line; 422, Second adapter line; 423, Shielding part; 43, Third conductive layer; 431, Third adapter line; 51, Anode layer; 52, Light-emitting layer; 53, Cathode layer; 61, First gate insulating layer; 62, Second gate insulating layer; 63, First interlayer dielectric layer; 64, Third gate insulating layer; 65, Fourth gate insulating layer; 66, Second interlayer dielectric layer; 67, Spacer insulating layer; 68, First planarization layer; 69, Second planarization layer; 610, Third planarization layer; 611, Pixel definition layer; 612, Support pillar. Detailed Implementation

[0083] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0084] Please refer to Figure 1This diagram shows a film stacking diagram of a 6T1C pixel circuit. The pixel circuit includes a first transistor T01, a second transistor T02, a third transistor T03, a fourth transistor T04, a fifth transistor T05, and a sixth transistor T06. The first transistor T01 can be a driving transistor. The second transistor T02 can be a switching transistor. The third transistor T03 can be a compensation transistor. The fourth transistor T04 can be a reset transistor. The fifth transistor T05 can be a first light-emitting control transistor, and the sixth transistor T06 can be a second light-emitting control transistor. The gate of the first transistor T01 and the source of the third transistor T03 can be connected to a first point Q. The source of the first transistor T01 and the drain of the fifth transistor T05 are connected to a second point A. The third transistor T03 is prone to leakage current when off, which can lead to a decrease in the potential of the first point Q. This can cause threshold voltage drift in the first transistor T01, resulting in uneven color and brightness on the display panel and light leakage.

[0085] Please refer to Figure 2 as well as Figure 3 This application provides a display panel, which includes multiple pixel driving circuits PD. Each pixel driving circuit PD includes a driving transistor T1, a compensation transistor T3, and a first connection line 411. The gate of the driving transistor T1 and the source of the compensation transistor T3 are both connected to a first node N1. The compensation transistor T3 also includes a compensation active part T3A. The first connection line 411 is connected between the compensation active part T3A and the gate of the driving transistor T1A.

[0086] The display panel also includes a first control signal line Scan1 connected to the gate of the compensation transistor T3. The first connection line 411 and the first control signal line Scan1 overlap along the thickness direction of the display panel, and the overlapping part forms a voltage stabilizing capacitor Cw.

[0087] In the implementation process, the embodiments of this application make the first connection line 411 and the first control signal line Scan1 overlap along the thickness direction of the display panel, and the overlapping part forms a voltage stabilizing capacitor Cw; thereby reducing the leakage current generated at the first node N1 of the compensation transistor T3 in the off state, so as to stabilize the gate potential of the driving transistor T2, improve the phenomenon of leakage current generated by the compensation transistor T3, and improve the display uniformity of the display panel.

[0088] Specifically, please refer to Figure 3 and Figure 4 The display panel may include a display area AA and a non-display area NA adjacent to the display area AA. The non-display area NA may be set around the display area AA, and the non-display area NA may be the border area of ​​the display panel.

[0089] In some embodiments, the display panel further includes a plurality of sub-pixels PX disposed in the display area AA and used to implement the display function of the display panel, and a gate driving circuit 15 disposed in the non-display area NA, wherein the gate driving circuit 15 is used to input control signals to the sub-pixels PX in the display area AA.

[0090] In some embodiments, each sub-pixel PX is provided with a pixel driving circuit PD, and the gate driving circuit 15 is used to input a gate control signal to the transistor in the pixel driving circuit PD.

[0091] In some embodiments, a bonding terminal 16 is provided on the lower side of the display area AA, and the display panel also includes a data signal line Data extending into the display area AA and connected to the pixel driving circuit PD; the bonding terminal 16 can be connected to an external circuit, and the bonding terminal 16 transmits the signal input from the external circuit to the data signal line Data, thereby driving the display panel to display an image. For example, the bonding terminal 16 can be bonded to a chip or a flip-chip film, etc., to provide power and driving signals to the display panel.

[0092] In some embodiments, the gate driving circuit 15 is disposed in the non-display area NA, and the gate driving circuit 15 may be disposed on both sides of the display area AA; the gate driving circuit 15 may include a plurality of cascaded gate driving units, and the structure of the gate driving units is not specifically limited in this application.

[0093] In some embodiments, multiple pixel driving circuits PD can be arrayed within the display area AA. The pixel driving circuit PD can be 7T1C, 7T2C, 8T1C, 8T2C, 8T3C, 8T4C, 9T2C, 9T6C, etc. In the following embodiments, the 6T2C pixel driving circuit PD is used as an example for illustration.

[0094] Please refer to Figure 3 The pixel driving circuit PD includes a driving transistor T1, a switching transistor T2, a compensation transistor T3, a reset transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a storage capacitor Cst, and a voltage stabilizing capacitor Cw.

[0095] The gate of driving transistor T1 is connected to the first node N1, the drain of driving transistor T2 is connected to the second node N2, and the source of driving transistor T2 is connected to the third node N3.

[0096] The gate of the switching transistor T2 is connected to the second control signal line Scan2, the drain of the switching transistor T2 is connected to the data signal line Data, and the source of the switching transistor T2 is connected to the third node N3 to receive the data signal and transmit the data signal to the third node N3.

[0097] The gate of the compensation transistor T3 is connected to the first control signal line Scan1, the drain of the compensation transistor T3 is connected to the second node N2, and the source of the compensation transistor T3 is connected to the first node N1.

[0098] The gate of reset transistor T4 is connected to the third control signal line Scan3, the drain of reset transistor T4 is connected to the reset signal VI, and the source of reset transistor T4 is connected to the fourth node N4 to receive the reset signal and transmit the reset signal to the fourth node N4.

[0099] The gate of the first light-emitting control transistor T5 is connected to the first light-emitting control signal line EM1, the drain of the first light-emitting control transistor T5 is connected to the first power supply signal line VDD, and the source of the first light-emitting control transistor T5 is connected to the second node N2 to receive the first power supply signal and transmit the first power supply signal to the second node N2.

[0100] The gate of the second light-emitting control signal T6 is connected to the second light-emitting control signal line EM2, the drain of the second light-emitting control transistor T6 is connected to the third node N3, and the source of the second light-emitting control transistor T6 is connected to the fourth node N4.

[0101] The storage capacitor Cst is connected between the first node N1 and the fourth node N4. One plate of the storage capacitor Cst is connected to the first node N1, and the other plate of the storage capacitor Cst is connected to the fourth node N4.

[0102] The light-emitting device EL is connected between the fourth node and the second power signal line VSS; wherein, the light-emitting device EL may include an anode layer, a light-emitting layer and a cathode layer stacked together, wherein the anode layer may be electrically connected to the fourth node N4 and the cathode layer may be electrically connected to the second power signal line VSS.

[0103] In this embodiment, by adding a voltage-stabilizing capacitor Cw between the first control signal line Scan1 and the first node N1, the leakage current generated at the first node N1 of the compensation transistor T3 in the off state can be reduced, thereby stabilizing the gate potential of the driving transistor T2, improving the leakage current phenomenon of the compensation transistor T3, and improving the display uniformity of the display panel.

[0104] The switching transistor T2 in different sub-pixels PX is connected to different data signal lines Data. This application only uses one of them as an example for illustration.

[0105] In this embodiment, the first power signal line VDD is used to provide a constant high voltage level to the pixel driving circuit PD, and the second power signal line VSS is used to provide a constant low voltage level to the pixel driving circuit PD.

[0106] In the embodiments of this application, the driving transistor T1, the switching transistor T2, the compensation transistor T3, the reset transistor T4, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 are each independently selected from one of a P-type transistor or an N-type transistor; and in this application Figure 3 In the illustrated embodiment, the driving transistor T1, the switching transistor T2, the compensation transistor T3, and the reset transistor T4 are all N-type transistors, while the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both P-type transistors, for example.

[0107] Furthermore, in the embodiments of this application, the driving transistor T1, the switching transistor T2, the compensation transistor T3, the reset transistor T4, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 are each independently selected from a single-gate transistor or a dual-gate transistor.

[0108] In this embodiment, the source is only the output terminal of the thin-film transistor in this application, and the drain is only the input terminal of the thin-film transistor in this application. The only difference between the two is in their names.

[0109] The following is about Figure 5 The structure of the film layer of the pixel circuit in this application is described.

[0110] The display area AA and non-display area NA of the display panel may be provided with a substrate 11 and an array driving layer disposed on the substrate 11; within the display area AA, the display panel may further include a pixel definition layer 611 disposed on the array driving layer and support pillars 612 disposed on the pixel definition layer 611. The film layer structure within the display area AA is described below.

[0111] In some embodiments, the substrate 11 supports various layers disposed on the substrate 11. When the display panel is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent substrate can be used. When the display panel is a top-emitting light-emitting display device, a translucent or opaque substrate as well as a transparent substrate can be used.

[0112] In this embodiment, substrate 11 is used to support various film layers disposed on substrate 11. Substrate 11 may be made of an insulating material such as glass, quartz, or polymer resin. Substrate 11 may be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. Examples of flexible materials used for flexible substrates include, but are not limited to, polyimide (PI).

[0113] In this embodiment, the substrate 11 may include a first flexible substrate, a first barrier layer, a second flexible substrate, and a second barrier layer stacked together. The first flexible substrate and the second flexible substrate may be formed of the same material, such as polyimide, and the first barrier layer and the second barrier layer may be formed of an inorganic material, such as at least one of SiOx and SiNx.

[0114] Please refer to Figure 5 The array driving layer may include multiple thin-film transistors (TFTs). These TFTs can be etch-block type, back-channel etch type, or classified according to the position of the gate and active portion as bottom-gate TFTs, top-gate TFTs, etc., or according to their performance as N-type TFTs, P-type TFTs; among them, Figure 5 The thin-film transistor in the text does not represent Figure 3 The structural diagram of any transistor in this application is merely a schematic diagram of the various film layers of the display panel.

[0115] Please refer to Figure 5The array driving layer includes a barrier layer 12 disposed on a substrate 11, a light-shielding layer 14 disposed on the barrier layer 12, a buffer layer 13 disposed on the barrier layer 12 and covering the light-shielding layer 14, a second semiconductor layer 22 disposed on the buffer layer 13, a first gate insulating layer 61 disposed on the buffer layer 13 and covering the second semiconductor layer 22, a first gate layer 31 disposed on the first gate insulating layer 61, a second gate insulating layer 62 disposed on the first gate insulating layer 61 and covering the first gate layer 31, and a second gate insulating layer 62 disposed on the second gate insulating layer 11. The second gate layer 32 on layer 62, the first interlayer dielectric layer 63 disposed on and covering the second gate insulating layer 62, the first semiconductor layer 21 disposed on the first interlayer dielectric layer 63, the third gate insulating layer 64 disposed on the first interlayer dielectric layer 63 and covering the first semiconductor layer 21, the third gate layer 33 disposed on the third gate insulating layer 64, the fourth gate insulating layer 65 disposed on the third gate insulating layer 64 and covering the third gate layer 33, and the fourth gate insulating layer 65 disposed on the fourth gate insulating layer 65. Gate layer 34, second interlayer dielectric layer 66 disposed on and covering the fourth gate insulating layer 65, first conductive layer 41 disposed on the second interlayer dielectric layer 66, spacer insulating layer 67 disposed on the second interlayer dielectric layer 66 and covering the first conductive layer 41, first planarization layer 68 disposed on the spacer insulating layer 67, second conductive layer 42 disposed on the first planarization layer 68, second planarization layer 69 disposed on the first planarization layer 68 and covering the second conductive layer 42, and third conductive layer 69 disposed on the second planarization layer 69. The device comprises an electrical layer 43, a third planarization layer 610 disposed on the second planarization layer 69 and covering the third conductive layer 43, an anode layer 51 disposed on the third planarization layer 610, a light-emitting layer 52 disposed on the anode layer 51, a pixel definition layer 611 disposed on the third planarization layer 610, a support pillar 612 disposed on the pixel definition layer 611, and a cathode layer 53 disposed on the pixel definition layer 611, the support pillar 612, and the light-emitting layer 52; wherein the anode layer 51, the light-emitting layer 52, and the cathode layer 53 are stacked to form a light-emitting device EL.

[0116] In some embodiments, the material of the second semiconductor layer 22 may be silicon semiconductor, for example, the material of the second semiconductor layer 22 in this application may be low-temperature polycrystalline silicon.

[0117] In some embodiments, the material of the first semiconductor layer 21 can be a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO) in this application.

[0118] In some embodiments, the first gate insulating layer 61, the second gate insulating layer 62, the first interlayer dielectric layer 63, the third gate insulating layer 64, the fourth gate insulating layer 65, the second interlayer dielectric layer 66, and the spacer insulating layer 67 are respectively disposed on the corresponding gate layer, conductive layer, or semiconductor layer, with the gate layer, conductive layer, or semiconductor layer of different layers being separately disposed; and the materials of the first gate insulating layer 61, the second gate insulating layer 62, the first interlayer dielectric layer 63, the third gate insulating layer 64, the fourth gate insulating layer 65, the second interlayer dielectric layer 66, and the spacer insulating layer 67 can be composed of an inorganic material composed of silicon oxynitride or an organic material with planarity.

[0119] In some embodiments, the first gate layer 31, the second gate layer 32, the third gate layer 33, and the fourth gate layer 34 are respectively disposed on the corresponding insulating layer, and the materials of the first gate layer 31, the second gate layer 32, the third gate layer 33, and the fourth gate layer 34 can be copper, molybdenum, or molybdenum-titanium alloy, etc.

[0120] In some embodiments, the materials of the first conductive layer 41, the second conductive layer 42, and the third conductive layer 43 may be copper, molybdenum, molybdenum-titanium alloy, or titanium-aluminum-titanium trilayer metal, etc.

[0121] In some embodiments, the first planarization layer 68, the second planarization layer 69, and the third planarization layer 610 are laid in a continuous layer to ensure the flatness of the film layer of the array driving layer. The materials of the first planarization layer 68, the second planarization layer 69, and the third planarization layer 610 can be inorganic materials composed of silicon oxynitride or organic materials with flatness.

[0122] It should be noted that the pixel definition layer 611 is disposed on the planarization layer and has multiple pixel openings. The light-emitting device EL may include an anode layer 51, a light-emitting layer 52 and a cathode layer 53 stacked together. The anode layer 51 is located inside the pixel opening, the light-emitting layer 52 is disposed inside the pixel opening and located on the anode layer 51, and the cathode layer 53 is located on the light-emitting layer 52.

[0123] It is understood that each thin-film transistor and signal line in the pixel driving circuit PD can be located in the array driving layer. For example, the active part of each thin-film transistor can be located in the semiconductor layer, and the other electrodes of each thin-film transistor or the connected signal lines can be located in any one of the first gate layer 31, the second gate layer 32, the third gate layer 33, the fourth gate layer 34, the first conductive layer 41, the second conductive layer 42, and the third conductive layer 43.

[0124] Please refer to Figure 2 as well as Figure 4The display panel may include a plurality of pixel driving circuits PD arranged along a first direction X and a second direction Y, and the first direction X and the second direction Y intersect each other; in some embodiments, the first direction X and the second direction Y are perpendicular to each other.

[0125] Among them, two adjacent pixel driving circuits PD along the first direction X are arranged symmetrically, and two pixel driving circuits PD along the second direction Y have the same structural distribution.

[0126] Specifically, the display panel includes a plurality of repeating units arranged along a first direction X and a second direction Y, and each repeating unit includes two adjacent pixel driving circuits PD along the first direction X, and the two pixel driving circuits PD within the repeating unit are arranged axially symmetrically.

[0127] The following embodiments combine Figure 2 , Figure 3 , Figure 4 , Figure 5 as well as Figures 6 to 23 The technical solution of this application is described using the structure of each film layer in a pixel driving circuit PD as an example.

[0128] It is understood that the structural features and positional relationships described in the following embodiments can all be structural features and positional relationships in a top view.

[0129] like Figure 6 As shown, the light-shielding layer 14 is disposed on the substrate 11, and the light-shielding layer 14 can extend along the first direction X. Specifically, the light-shielding layer 14 can be located below a portion of the active portion in the second semiconductor layer 22 to serve to shield light and improve the stability of the active portion.

[0130] like Figure 7 As shown, the second semiconductor layer 22 includes a switching active portion T2A of a switching transistor T2, a first light-emitting active portion T5A of a first light-emitting control transistor T5, and a second light-emitting active portion T6A of a second light-emitting active portion T6.

[0131] The first light-emitting active part T5A and the second light-emitting active part T6A are located on opposite sides of the switch active part T2A along the second direction Y, and the first light-emitting active part T5A and the switch active part T2A are spaced apart, while the second light-emitting active part T6A is connected to the switch active part T2A away from the first light-emitting active part T5A.

[0132] In some embodiments, both the first light-emitting active control unit T5A and the second light-emitting active control unit T6A have a U-shaped structure, and the U-shaped opening of the first light-emitting active control unit T5A is arranged towards the direction of the switching active unit T2A, and the U-shaped opening of the second light-emitting active control unit T6A is also arranged towards the direction of the switching active unit T2A.

[0133] In some embodiments, the active switching portion T2A has an L-shaped structure, and a portion of the active switching portion T2A extends along a first direction X, while another portion of the active switching portion T2A extends along a second direction Y. The portion of the active switching portion T2A extending along the second direction Y is connected to the second light-emitting control active portion T6A.

[0134] like Figure 8 As shown, the light-shielding layer 14 can be located below the active switching part T2A, and the coverage area of ​​the light-shielding layer 14 at least blocks the channel portion of the active switching part T2A; so as to block light from shining onto the channel of the active switching part T2A and improve the electrical stability of the active switching part T2A.

[0135] like Figure 9 As shown, the first gate layer 31 includes a first control signal line Scan1, a second control signal line Scan2, a third control signal line Scan3, a first light emission control signal line EM1, and a second light emission control signal line EM2; further, the first control signal line Scan1 includes a first sub-line Scan11 located in the first gate layer 31, and the third control signal line Scan3 includes a third sub-line Scan31 located in the first gate layer 31.

[0136] Among them, the first sub-line Scan11, the second control signal line Scan2, the third sub-line Scan31, the first light emission control signal line EM1, and the second light emission control signal line EM2 all extend along the first direction X; and the above signal lines can overlap with the active part of the thin film transistor to be reused as the gate of the thin film transistor.

[0137] In some embodiments, the first sub-line Scan11 and the third sub-line Scan31 are located on opposite sides of the pixel driving circuit PD along the second direction Y, the first light emission control signal line EM1 is located between the first sub-line Scan11 and the third sub-line Scan31, the second control signal line Scan2 is located between the first light emission control signal line EM1 and the third sub-line Scan31, and the second light emission control signal line EM2 is located between the second control signal line Scan2 and the third sub-line Scan31.

[0138] like Figure 10As shown, the first light-emitting control signal line EM1 overlaps with the first light-emitting control active part T5A, and the overlapping portion of the first light-emitting control signal line EM1 and the first light-emitting control active part T5A is multiplexed as the gate of the first light-emitting control transistor T5.

[0139] The first light-emitting control active part T5A is U-shaped and has two parts extending along the second direction Y. The positions where the first light-emitting control signal line EM1 intersects with the two parts form the two gates of the first light-emitting control transistor T5.

[0140] Similarly, the second light-emitting control signal line EM2 overlaps with the second light-emitting control active part T6A, and the overlapping portion of the second light-emitting control signal line EM2 and the second light-emitting control active part T6A is multiplexed as the gate of the second light-emitting control transistor T6.

[0141] The second light-emitting control active part T6A is U-shaped and has two parts extending along the second direction Y. The two gates of the second light-emitting control transistor T6 are formed at the position where the second light-emitting control signal line EM2 intersects with the two parts.

[0142] Furthermore, the position where the second control signal line Scan2 intersects with the active switch portion T2A extending along the second direction Y is multiplexed as the gate of the active switch portion T2; and the second control signal line Scan2 can be located on the side of the light-shielding layer 14 away from the substrate 11.

[0143] like Figure 11 As shown, the second gate layer 32 includes a bottom gate 321, and the bottom gate 321 can be disposed below at least one thin-film transistor in the pixel driving circuit PD to stabilize the voltage.

[0144] like Figure 12 As shown, the bottom gate 321 is located between the switching active part T2A and the first light-emitting control active part T5A.

[0145] like Figure 13 and Figure 14 As shown, the first semiconductor layer 21 includes a driving active portion T1A of a driving transistor T1, a compensation active portion T3A of a compensation transistor T3, and a reset active portion T4A of a reset transistor T4.

[0146] The active driving part T1A extends along the second direction Y, the active compensation part T3A extends along the second direction Y, and the active reset part T4A extends along the second direction Y. The active compensation part T3A is located on one side of the active driving part T1A along the second direction Y and is connected to the active driving part T1A. The active reset part T4A is spaced apart from the active driving part T1A, and the active compensation part T3A and the active reset part T4A are located on opposite sides of the active driving part T1A along the second direction Y.

[0147] In addition, the second light-emitting control active part T6A is located on the side of the switching active part T2A away from the driving active part T1A, and the reset active part T4A is located on the side of the second light-emitting control active part T6A along the first direction X.

[0148] like Figure 14 As shown, the driving active part T1A is located above the bottom gate 321, that is, on the side of the bottom gate 321 away from the substrate 11.

[0149] The first sub-line Scan11 overlaps with the compensation active section T3A, and the overlapping portion of the first sub-line Scan11 and the compensation active section T3A is multiplexed as the gate of the compensation transistor T3.

[0150] The third sub-line Scan31 overlaps with the reset active section T4A, and the overlapping portion of the third sub-line Scan31 and the reset active section T4A is multiplexed as the gate of the reset transistor T4.

[0151] The compensating active part T3A is connected to the driving active part T1A, and the first light-emitting control active part T5A is disposed near the connection between the compensating active part T3A and the driving active part T1A; in some embodiments, the first light-emitting control active part T5A and the compensating active part T3A and / or the driving active part T1A partially overlap along the thickness direction of the display panel.

[0152] like Figure 15 As shown, the second gate layer 32 includes a first control signal line Scan1, a third control signal line Scan3, and a first electrode plate Cst1.

[0153] The first control signal line Scan1 includes a second sub-line Scan12 located in the second gate layer 32, and the third control signal line Scan3 includes a fourth sub-line Scan32 located in the second gate layer 32. Both the second sub-line Scan12 and the fourth sub-line Scan32 extend along the first direction X.

[0154] The first electrode plate Cst1 is located between the second sub-line Scan12 and the fourth sub-line Scan32.

[0155] like Figure 16As shown, the second sub-line Scan12 is located on the side of the first sub-line Scan11 away from the substrate 11, and the second sub-line Scan12 is located on the side of the compensation active part T3A away from the first sub-line Scan11. The second sub-line Scan12 overlaps with the compensation active part T3A, and the overlapping portion of the second sub-line Scan12 and the compensation active part T3A can also be reused as the gate of the compensation transistor T3. Specifically, the first sub-line Scan11 is reused as the bottom gate of the compensation transistor T3, and the second sub-line Scan12 is reused as the top gate of the compensation transistor T3, so that the compensation transistor T3 has a dual-gate structure, and the signal in the first sub-line Scan11 is the same as the signal in the second sub-line Scan12.

[0156] Furthermore, the fourth sub-line Scan32 is located on the side of the third sub-line Scan31 away from the substrate 11, and the fourth sub-line Scan32 is located on the side of the compensation active part T3A away from the third sub-line Scan31. The fourth sub-line Scan32 overlaps with the compensation active part T3A, and the overlapping portion of the fourth sub-line Scan32 and the compensation active part T3A can also be reused as the gate of the compensation transistor T3. Specifically, the third sub-line Scan31 is reused as the bottom gate of the compensation transistor T3, and the fourth sub-line Scan32 is reused as the top gate of the compensation transistor T3, so that the compensation transistor T3 has a dual-gate structure, and the signal in the third sub-line Scan31 is the same as the signal in the fourth sub-line Scan32.

[0157] Furthermore, the first portion of the first electrode plate Cst1 extends to the side of the driving active part T1A away from the substrate 11, and the second portion of the first electrode plate Cst1 is located on the side of the driving active part T1A along the first direction X; furthermore, the first portion of the first substrate Cst1 overlaps with the compensation active part T3A along the second direction Y, and the second portion of the first electrode plate Cst1 overlaps with the reset active part T4A along the second direction Y.

[0158] like Figure 17 As shown, the fourth gate layer 34 includes a second electrode plate Cst2, and the second electrode plate Cst2 is used together with the first electrode plate Cst1 to form a storage capacitor Cst.

[0159] In addition, a third via 341 is formed in the second electrode plate Cst2, and the third via 341 is used to provide an overlap path for subsequent wiring.

[0160] like Figure 18 As shown, the second electrode Cst2 is located on the side of the first electrode Cst1 away from the substrate 11, that is, the second electrode Cst2 and the first electrode Cst1 are arranged opposite to each other to form a storage capacitor Cst.

[0161] The third via 341 can expose the first electrode plate Cst1 below, so as to provide a path for subsequent wiring to connect to the first electrode plate Cst1.

[0162] In some embodiments, the orthographic projection of the second electrode plate Cst2 onto the substrate 11 is within the coverage area of ​​the orthographic projection of the first electrode plate Cst1 onto the substrate 11.

[0163] like Figure 19 As shown, the first conductive layer 41 includes a reset signal line VI, a first connection line 411, a second connection line 412, a third connection line 413, a fourth connection line 414, a fifth connection line 415, a sixth connection line 416, and a seventh connection line 417.

[0164] The reset signal line VI extends along the first direction X, and one end of the seventh connection line 417 is connected to the reset signal line VI. The other end of the seventh signal line 417 extends along the second direction Y to transmit the reset signal in the reset signal line VI to the reset transistor T4.

[0165] The first connecting line 411, the third connecting line 413, and the fourth connecting line 414 can all extend along the second direction Y. It should be noted that the first connecting line 411, the third connecting line 413, and the fourth connecting line 414 extending along the second direction Y means that the entire connecting line extends along the second direction Y, while a portion of the connecting line may be offset in a direction inclined to the second direction Y.

[0166] A portion of the fifth connecting line 415 extends along the second direction Y, and another portion of the fifth connecting line 415 extends along the first direction X.

[0167] Specifically, the second connecting line 412 is located between the first connecting line 411 and the third connecting line 413 along the first direction X; the sixth connecting line 416 is located between the fourth connecting line 414 and the fifth connecting line 415 along the first direction X; the fourth connecting line 414, the fifth connecting line 415, and the sixth connecting line 416 are all located between the reset signal line VI and the first connecting line 411 along the second direction Y, and / or the fourth connecting line 414, the fifth connecting line 415, and the sixth connecting line 416 are all located between the reset signal line VI and the second connecting line 412 along the second direction Y, and / or the fourth connecting line 414, the fifth connecting line 415, and the sixth connecting line 416 are all located between the reset signal line VI and the third connecting line 413 along the second direction Y; the seventh connecting line 417 is located on the side of the reset signal line VI away from the sixth connecting line 416.

[0168] like Figure 20 and Figure 21As shown, the first connection line 411 is located on one side of the compensation active part T3A along the first direction X and is connected to the compensation active part T3A; specifically, the first connection line 411 is connected to the side of the compensation active part T3A away from the driving active part T1A, wherein the portion of the first connection line 411 connected to the compensation active part T3A can be reused as the source of the compensation transistor T3.

[0169] Furthermore, one end of the first connection line 411 is connected to the compensation active part T3A, and the other end of the first connection line 411 extends along the second direction Y toward the direction close to the first electrode plate Cst1, and passes through the third via 341 to connect with the first electrode plate Cst1, so as to realize the connection between the source of the compensation transistor T3 and the gate of the driving transistor T1. That is, the first connection line 411 can be equivalent to the first node N1.

[0170] It is understandable that the third via 341 can pass through all the film layers between the first conductive layer 41 and the first electrode plate Cst1, so that the first connecting line 411 can be connected to the first electrode plate Cst1 through the third via 341.

[0171] It should be noted that during the extension of the first connecting line 411 along the second direction Y, it will overlap with the first control signal line Scan1, thereby forming a voltage stabilizing capacitor Cw between the first connecting line 411 and the first control signal line Scan1. This stabilizes the voltage on the first connecting line 411, which in turn stabilizes the voltage on the first node N1. This improves the leakage phenomenon of the compensation transistor T3 in the off state at the first node N1, enhances the signal transmission stability of the driving transistor T1, and improves the display uniformity of the display panel.

[0172] In some embodiments, the first light-emitting control active part T5A is located on the side of the compensation active part T3A away from the first connecting line 411.

[0173] In the embodiments of this application, such as Figure 20 and Figure 21 As shown, the second connecting line 412 can be connected to the driving active part T1A, the compensation active part T3A, and the first light-emitting control active part T5A. Specifically, a first via 4101 and a second via 4102 are formed in the display panel. The first via 4101 is correspondingly provided at the connection point between the compensation active part T2A and the driving active part T1A, and the second via 4102 is correspondingly provided at the connection point between the first light-emitting control active part T5A. That is, the first via 4101 can expose the compensation active part T2A and / or the driving active part T1A, and the second via 4102 can expose the second light-emitting control active part T5A.

[0174] The second connecting line 412 is connected to the compensation active part T3A and the driving active part T1A through the first via 4101, and the second connecting line 412 is connected to the first light-emitting control active part T5A through the second via 4102.

[0175] In this embodiment, both the compensation active part T3A and the driving active part T1A are disposed in the first semiconductor layer 21, and the compensation active part T3A and the driving active part T1A are directly connected, thereby relative to... Figure 1 As shown in the prior art, the second connection line 412 can be connected to both the compensation active part T3A and the driving active part T1A simultaneously through only one first via 4101, which can save the process and manufacturing process of one via, simplify the process, and reduce costs.

[0176] Understandably, the first via 4101 can pass through all the film layers between the first conductive layer 41 and the first semiconductor layer 21, so that the second connection line 412 can be connected to the compensation active part T3A and the driving active part T1A through the first via 4101; similarly, the second via 4102 can pass through all the film layers between the first conductive layer 41 and the second semiconductor layer 22, so that the second connection line 412 can be connected to the first light-emitting control active part T5A through the second via 4102.

[0177] Furthermore, the second connection line 412 can be regarded as the second node N2, and the portion of the second connection line 412 connected to the driving active part T1A can be reused as the drain of the driving transistor T1, the portion of the second connection line 412 connected to the compensation active part T3A can be reused as the drain of the compensation transistor T3, and the portion of the second connection line 412 connected to the first light-emitting control active part T5A can be reused as the source of the first light-emitting control transistor T5.

[0178] The second connecting line 412 and the first control signal line Scan1 do not overlap along the thickness direction of the display panel, thereby reducing the coupling capacitance between the second connecting line 412 and the first control signal line Scan1, reducing the coupling capacitance between the second node N2 and the first control signal line Scan1, and improving the signal stability at the second node N2.

[0179] One end of the third connecting line 413 is connected to the opposite end of the first light-emitting control active part T5A away from the driving active part T1A. The other end of the third connecting line 413 extends along the second direction Y. The third connecting line 413 overlaps with the first light-emitting control signal line EM1 along the thickness direction of the display panel. The third connecting line 413 also overlaps with the first control signal line Scan1 along the thickness direction of the display panel.

[0180] The portion of the third connecting line 413 that is connected to the first light-emitting control active part T5A is reused as the drain of the first light-emitting control active part T5A.

[0181] One end of the fourth connection line 414 is connected to the driving active part T1A and the bottom gate 321, and the other end of the fourth connection line 414 extends along the second direction Y and is connected to the second light-emitting control active part T6A and the switching active part T2A. On the one hand, the fourth connection line 414 is used to realize the connection between the driving active part T1A and the second light-emitting control active part T6A. The fourth connection line 414 is also used to realize the connection between the driving active part T1A and the bottom gate 321 to provide voltage to the bottom gate 321. That is to say, the fourth connection line 414 can be regarded as the third node N3.

[0182] The portion of the fourth connection line 414 connected to the driving active part T1A is multiplexed as the source of the driving transistor T1, the portion of the fourth connection line 414 connected to the second light-emitting control active part T6A is multiplexed as the drain of the second light-emitting control active part T6, and the portion of the fourth connection line 414 connected to the switching active part T2A is multiplexed as the source of the switching transistor T4.

[0183] In some embodiments, the fourth connection line 414 and the active switch T2A at least partially overlap along the thickness direction of the display panel, thereby saving wiring space in the pixel drive circuit PD.

[0184] One end of the fifth connecting line 415 is connected to the second light-emitting control active part T6A and the reset active part T4A. The other end of the fifth connecting line 415 extends along the second direction Y and is connected to the second electrode plate Cst2. The fifth connecting line 415 and the second control signal line Scan2 overlap along the thickness direction of the display panel. In addition, the other end of the fifth connecting line 415 is also electrically connected to the light-emitting device EL. That is to say, the fifth connecting line 415 can be regarded as the fourth node N4.

[0185] The portion of the fifth connection line 415 connected to the second light-emitting control active part T6A is multiplexed as the source of the second light-emitting control transistor T6, and the portion of the fifth connection line 415 connected to the reset active part T4A is multiplexed as the source of the reset transistor T4.

[0186] The sixth connection line 416 is connected to the active switch section T2A and can be used to connect the active switch section T2A to the data signal line Data; that is, the sixth connection line 416 can be multiplexed as the drain of the active switch section T2A.

[0187] One end of the seventh connection line 417 is connected to the reset signal line VI, and the other end of the seventh connection line 417 is connected to the end of the reset active part T4A away from the fifth connection line 415. The seventh connection line 417 and the third control signal line Scan3 overlap along the thickness direction of the display panel. The portion of the seventh connection line 417 connected to the reset active part T4A is multiplexed as the drain of the reset transistor T4.

[0188] like Figure 22 As shown, the second conductive layer 42 includes a first power signal line VDD, a first adapter line 421, a second adapter line 422, and a shielding portion 423.

[0189] The first power signal line VDD extends along the first direction X, and the first adapter 421 and the second adapter 422 are both located along the second direction Y between the first power signal line VDD and the shielding part 423.

[0190] The first power signal line VDD is connected to a protrusion VDD1, which extends along the second direction Y. The protrusion VDD1 is located on the side of the first power signal line VDD that is close to the first adapter cable 421, or the protrusion VDD1 is located on the side of the first power signal line VDD that is close to the second adapter cable 422.

[0191] like Figure 23 As shown, the third connection line 413 is connected to the first power signal line VDD to transmit the first power signal in the first power signal line VDD to the first light-emitting control transistor T5.

[0192] In some embodiments, the first power signal line VDD and the first light emission control signal line EM1 both extend along the first direction X, and the first power signal line VDD and the first light emission control signal line EM1 are located on opposite sides of the first control signal line Scan1 along the second direction Y; further, the first light emission control active part T5A is located on the side of the first control signal line Scan1 away from the first power signal line VDD.

[0193] The protrusion VDD1 is located on the side of the compensation active part T3A away from the substrate 11, so as to shield the side of the compensation active part T3A away from the substrate 11, reduce light exposure, and improve the stability of the compensation transistor T3. At the same time, the protrusion VDD1 is connected to the first power signal line VDD to provide a stable voltage to the protrusion VDD1 and avoid voltage fluctuations on the protrusion VDD1 from affecting the electrical properties of the compensation active part T3A.

[0194] In some embodiments, the protrusion VDD1 and the voltage regulator capacitor Cw at least partially overlap along the thickness direction of the display panel.

[0195] The first adapter cable 421 can be connected to the sixth connection cable 416 to connect the sixth connection cable 416 to the data signal line Data.

[0196] The second adapter cable 422 can be connected to the fifth connecting cable 415 to connect the fifth connecting cable 415 to the anode layer 51.

[0197] The shielding portion 423 is located on the side of the reset active portion T4A away from the substrate 11, so as to shield the side of the reset active portion T4A away from the substrate 11, reduce light exposure, and improve the stability of the reset transistor T4. In some embodiments, the shielding portion 423 is connected to the first power signal line VDD to provide a stable voltage for the shielding portion 423, so as to avoid voltage fluctuations on the shielding portion 423 from affecting the electrical properties of the reset active portion T4A.

[0198] In some embodiments, the first control signal line Scan1 includes a first line segment Scan1a and a second line segment Scan1b connected together. The line width of the first line segment Scan1a is greater than the line width of the second line segment Scan1b. The first line segment Scan1a overlaps with the compensation active part T3A along the thickness direction of the display panel, and the first line segment Scan1b overlaps with the first connecting line 411 along the thickness direction of the display panel to form a voltage regulator capacitor Cw. It can be understood that in this embodiment, the first line segment Scan1a of the first control signal line Scan1 located in the compensation active part T3A is widened. At the same time, the widened first line segment Scan1a overlaps with the first connecting line 411 to form a voltage regulator capacitor Cw. This increases the area of ​​the formed voltage regulator capacitor Cw, increases the capacitance, and improves the effect of the voltage regulator capacitor Cw on reducing leakage current at the first node N1.

[0199] In some embodiments, the first control signal line Scan1 includes a first sub-line Scan11 and a second sub-line Scan12 located on opposite sides of the compensation active portion T3A along the thickness direction of the display panel. The first sub-line Scan11 overlaps with the first connecting line 411 along the thickness direction of the display panel, and the second sub-line Scan12 overlaps with the first connecting line 411 along the thickness direction of the display panel. That is, in this application, a dual-gate structure is formed by forming the first control signal line Scan1 on both the upper and lower sides of the compensation active portion T3A. In addition, both layers of the first control signal line Scan1 can overlap with the first connecting line 411, which can further increase the capacitance of the formed voltage regulator capacitor Cw and improve the effect of the voltage regulator capacitor Cw on leakage current.

[0200] Furthermore, the line width of the first sub-line Scan11 at the first line segment Scan1a is greater than the line width of the first sub-line Scan11 at the second line segment Scan1b, and / or the line width of the second sub-line Scan12 at the first line segment Scan1a is greater than the line width of the second sub-line Scan12 at the second line segment Scan1b.

[0201] Please combine Figure 23 , Figure 24 as well as Figure 25 The first light-emitting active control unit T5A includes a first sub-unit 221 connected to the third connecting line 413, a second sub-unit 222 connected to the second connecting line 412, and a third sub-unit 223 connected between the first sub-unit 221 and the second sub-unit 222. Among two adjacent pixel driving circuits PD along the first direction X, the first light-emitting active control unit T5A in one pixel driving circuit PD shares a first sub-unit 211 with the first light-emitting active control unit T5A in the other pixel driving circuit PD. That is, based on the first light-emitting active control unit T5A being U-shaped to realize a dual-gate structure, the U-shapes of the first light-emitting active control units T5A of the two adjacent pixel driving circuits PD along the first direction X share a side to form a W-shape, which can reduce the spacing between the two adjacent pixel driving circuits PD along the first direction X, which is beneficial to improving the resolution of the display panel.

[0202] In some embodiments, the first sub-part 221 and the second sub-part 222 both extend along the second direction Y, and the third sub-part 223 extends along the first direction X; wherein, the two pixel driving circuits PD that share a first sub-part 211 are arranged symmetrically with respect to the first sub-part 221.

[0203] In other words, two pixel driving circuits PD that share a first sub-part 211 can form a repeating unit.

[0204] like Figure 26 As shown, the third conductive layer 43 includes a data signal line Data and a third adapter line 431, wherein the data signal line Data extends along the second direction Y, and the third adapter line 431 is located on one side of the data signal line Data along the first direction X.

[0205] like Figure 2 As shown, the data signal line Data is connected to the first adapter line 421 and then to the sixth connection line 416. In turn, the data signal line Data is connected to the active switch unit T2A through the first adapter line 421 and the sixth connection line 416 to transmit the data signal to the switch transistor T2.

[0206] In some embodiments, please combine Figure 2 , Figure 25 and Figure 26 The display panel also includes a data signal line Data extending along the second direction Y, and the data signal line Data is connected to a plurality of pixel driving circuits PD arranged along the second direction Y; wherein, the second sub-part 222 partially overlaps with the data signal line Data along the thickness direction of the display panel, and the first sub-part 221 is located on the side of the data signal line Data away from the compensation active part T3A.

[0207] Furthermore, the third adapter line 431 is connected to the second adapter line 422 to realize the connection between the third adapter line 431 and the fifth connecting line 415, which can then be used to realize the connection between the fifth connecting line 415 and the anode layer 51, so as to realize the connection between the second light-emitting control transistor T6, the reset transistor T4 and the anode layer 51.

[0208] Furthermore, the anode layer 51 is located on the side of the third conductive layer 43 away from the substrate 11, and the anode layer 51 is connected to the second light-emitting control transistor T6 and the reset transistor T4 through the third adapter line 431, the second adapter line 422 and the fifth connection line 415.

[0209] Continuing from the above, the embodiments of this application provide for example... Figure 3 The potential coupling of the first node N1 in the pixel driving circuit PD shown is verified.

[0210] In the embodiment, the structure of the pixel driving circuit PD is as follows: Figure 3 As shown.

[0211] In Comparative Example 1, the structure of the pixel driving circuit PD is as follows: Figure 27 As shown, and Figure 27 The pixel driving circuit PD film stacking diagram shown is as follows: Figure 1 As shown, Figure 27 The circuit structure shown is relative to Figure 3 In fact, no voltage stabilizing capacitor Cw was formed.

[0212] In Comparative Example 2, the structure of the pixel driving circuit is as follows: Figure 28 As shown, this is the 8T2C pixel driving circuit.

[0213] like Figure 28 As shown, the pixel driving circuit in Comparative Example 2 includes a driving thin-film transistor T001, a switching thin-film transistor T002, a compensation thin-film transistor T003, a first reset thin-film transistor T004, a first light-emitting control thin-film transistor T005, a second light-emitting control thin-film transistor T006, a second reset thin-film transistor T007, a third reset thin-film transistor T008, a first capacitor Cst0, a second capacitor Cboost, and a light-emitting element EL1.

[0214] Specifically, the gate of driving thin-film transistor T001 is connected to node Q, the drain of driving thin-film transistor T001 is connected to node A, and the source of driving thin-film transistor T001 is connected to node B; the gate of switching thin-film transistor T002 is connected to the first gate signal line Pscan, the drain of switching thin-film transistor T002 is connected to the data line Data, and the source of switching thin-film transistor T002 is connected to node A; the gate of compensation thin-film transistor T003 is connected to the second gate signal line Nscan1, the drain of compensation thin-film transistor T003 is connected to node B, and the source of compensation thin-film transistor T003 is connected to node Q; the gate of the first reset thin-film transistor T004 is connected to the third gate signal line Nscan2, the drain of the first reset thin-film transistor T004 is connected to the first reset signal Vi-G, and the source of the first reset thin-film transistor T004 is connected to node Q; the gate of the first light-emitting control thin-film transistor T005 is connected to the fourth gate signal line EM1, and the drain of the first light-emitting control thin-film transistor T005 is connected to the first power supply signal line VD. D, the source of the first light-emitting control thin-film transistor T005 is connected to node A; the gate of the second light-emitting control thin-film transistor T006 is connected to the fourth gate signal line EM1, the drain of the second light-emitting control thin-film transistor T006 is connected to node B, and the source of the second light-emitting control thin-film transistor T006 is connected to node B; the gate of the second reset thin-film transistor T007 is connected to the fifth gate signal line EM2, the drain of the second reset thin-film transistor T007 is connected to the second reset signal Vi-Ano, and the source of the second reset thin-film transistor T007 is connected to node C; the gate of the third reset thin-film transistor T008 is connected to the fifth gate signal line EM2, the drain of the third reset thin-film transistor T008 is connected to the third reset signal Vi, and the source of the third reset thin-film transistor T008 is connected to node A; the first capacitor Cst0 is connected between the first power supply signal line VDD and node Q, and the second capacitor Cboost is connected between the first gate signal line Pscan and node Q; the light-emitting element EL1 is connected between node C and the second power supply signal line VSS.

[0215] Next, the potential of the first node N1 (first point Q) and the threshold voltage of the compensation transistor T3 (third transistor T3A) in the embodiments, Comparative Example 1 and Comparative Example 2 are verified to obtain the following results: Figure 29 The curves shown are as follows: curve A1 is the potential of the first node N1 and the threshold voltage curve of the compensation transistor T3 in the embodiment; curve A2 is the potential of the first point Q and the threshold voltage curve of the third transistor T3 in Comparative Example 1; and curve A3 is the potential of the first point Q and the threshold voltage curve of the third transistor T3 in Comparative Example 2. The horizontal axis is the threshold voltage of the compensation transistor T3 (the third transistor T3A), and the vertical axis is the potential of the first node N1 (the first point Q).

[0216] As can be seen, Comparative Example 1 did not add a voltage-stabilizing capacitor Cw as in this application. Therefore, the potential change of the first point Q in Comparative Example 1 was large, resulting in severe leakage. However, in this embodiment, a voltage-stabilizing capacitor Cw was added, and the potential change of the first node N1 was small. The leakage situation was significantly improved compared to Comparative Example 1, and it was close to the level of the 8T2C pixel driving circuit in Comparative Example 2. That is, the embodiment of this application can achieve electrical stability close to that of the 8T2C pixel driving circuit with a smaller number of thin-film transistors, effectively improving the display uniformity of the display panel, without increasing the number of thin-film transistors, increasing the area of ​​the sub-pixels PX, or reducing the resolution of the display panel.

[0217] In summary, the embodiments of this application achieve this by having the first connection line 411 and the first control signal line Scan1 overlap along the thickness direction of the display panel, and the overlapping portion forming a voltage stabilizing capacitor Cw; thereby reducing the leakage current generated at the first node N1 of the compensation transistor T3 in the off state, so as to stabilize the gate potential of the driving transistor T2, improve the phenomenon of leakage current generated by the compensation transistor T3, and improve the display uniformity of the display panel.

[0218] In addition, this application embodiment also provides a display device, which includes the display panel described in the above embodiments.

[0219] It is understood that since the display device has the same display panel as the above embodiment, the display device has the same beneficial effects as the display panel in the above embodiment, which will not be repeated here.

[0220] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0221] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0222] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0223] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, The display panel includes multiple pixel driving circuits, each pixel driving circuit including a driving transistor, a compensation transistor, and a first connection line. The gate of the driving transistor and the source of the compensation transistor are both connected to a first node. The compensation transistor further includes a compensation active part, and the first connection line is connected between the compensation active part and the gate of the driving transistor. The display panel further includes a first control signal line connected to the gate of the compensation transistor. The first connection line and the first control signal line overlap along the thickness direction of the display panel, and the overlapping portion forms a voltage stabilizing capacitor.

2. The display panel according to claim 1, characterized in that, The plurality of pixel driving circuits are arranged along a first direction and a second direction, and the first direction and the second direction intersect each other; The display panel includes: substrate; A first semiconductor layer is disposed on the substrate, and the first semiconductor layer includes the compensation active portion and the driving active portion of the driving transistor. The first control signal line extends along the first direction, the compensation active part and the driving active part both extend along the second direction, and the compensation active part is located on one side of the driving active part along the second direction and is connected to the driving active part.

3. The display panel according to claim 2, characterized in that, The first connecting line extends along the second direction and is located on one side of the compensated active part along the first direction, and is connected to the compensated active part.

4. The display panel according to claim 2, characterized in that, The pixel driving circuit further includes a first light-emitting control transistor and a switching transistor. The source of the first light-emitting control transistor and the drain of the driving transistor are connected to a second node, and the source of the switching transistor and the source of the driving transistor are connected to a third node. The display panel also includes: A second semiconductor layer is disposed between the substrate and the first semiconductor layer. The second semiconductor layer includes a switching active portion of the switching transistor and a first light-emitting control active portion of the first light-emitting control transistor. The switching active portion and the first light-emitting control active portion are located on opposite sides of the driving active portion along the second direction. The first light-emitting control active part is located on the side of the compensation active part away from the first connecting line.

5. The display panel according to claim 4, characterized in that, The first light-emitting active control unit is disposed near the connection between the compensation active unit and the driving active unit. A first via and a second via are formed in the display panel. The first via is disposed corresponding to the connection between the compensation active unit and the driving active unit, and the second via is disposed corresponding to the first light-emitting active control unit. The display panel also includes: A first conductive layer is disposed on the side of the first semiconductor layer away from the substrate, and the first conductive layer includes the first connecting line and the second connecting line; The second connecting line is connected to the compensation active part and the driving active part through the first via, and the second connecting line is connected to the first light-emitting control active part through the second via.

6. The display panel according to claim 5, characterized in that, The second connecting line and the first control signal line do not overlap along the thickness direction of the display panel.

7. The display panel according to claim 5, characterized in that, The display panel further includes a first power signal line and a first light emission control signal line. The first conductive layer further includes a third connecting line, which is connected between the first power signal line and the first light emission control active part. The first light emission control signal line and the first light emission control active part overlap along the thickness direction of the display panel. The first power signal line and the first light emission control signal line both extend along the first direction, and the first power signal line and the first light emission control signal line are located on opposite sides of the first control signal line along the second direction.

8. The display panel according to claim 7, characterized in that, The first light-emitting control active part is located on the side of the first control signal line away from the first power signal line.

9. The display panel according to claim 7, characterized in that, A protrusion is connected to the first power signal line, the protrusion extends along the second direction and is located on the side of the compensated active part away from the substrate.

10. The display panel according to claim 9, characterized in that, The protrusion at least partially overlaps with the voltage regulator capacitor along the thickness direction of the display panel.

11. The display panel according to claim 7, characterized in that, The first light-emitting control active part includes a first sub-part connected to the third connecting line, a second sub-part connected to the second connecting line, and a third sub-part connected between the first sub-part and the second sub-part; In two adjacent pixel driving circuits along the first direction, the first light-emitting active part in one pixel driving circuit shares a first sub-part with the first light-emitting active part in the other pixel driving circuit.

12. The display panel according to claim 11, characterized in that, Both the first sub-part and the second sub-part extend along the second direction, and the third sub-part extends along the first direction; The two pixel driving circuits that share a first sub-part are arranged symmetrically with respect to the first sub-part.

13. The display panel according to claim 11, characterized in that, The display panel further includes a data signal line extending along the second direction, and the data signal line is connected to a plurality of pixel driving circuits arranged along the second direction; The second sub-part partially overlaps with the data signal line along the thickness direction of the display panel, and the first sub-part is located on the side of the data signal line away from the compensation active part.

14. The display panel according to claim 5, characterized in that, The pixel driving circuit also includes a second light-emitting control transistor connected to the third node and the fourth node, and a light-emitting device connected to the fourth node; The second semiconductor layer further includes a second light-emitting control active portion of the second light-emitting control transistor, the second light-emitting control active portion being located on the side of the switching active portion away from the driving active portion; The first conductive layer further includes a fourth connecting line, which is connected between the driving active part and the second light-emitting control active part.

15. The display panel according to claim 14, characterized in that, The pixel driving circuit also includes a reset transistor connected to the fourth node; The first semiconductor layer further includes a reset active portion of the reset transistor, wherein the reset active portion is located on one side of the second light-emitting control active portion along the first direction; The first conductive layer further includes a fifth connecting line, which is connected to the second light-emitting control active part and the reset active part, and is also electrically connected to the light-emitting device.

16. The display panel according to claim 1, characterized in that, The first control signal line includes a first line segment and a second line segment connected together. The line width of the first line segment is greater than that of the second line segment. The first line segment overlaps with the compensation active part along the thickness direction of the display panel. The first line segment overlaps with the first connecting line along the thickness direction of the display panel to form the voltage stabilizing capacitor.

17. The display panel according to claim 16, characterized in that, The first control signal line includes a first sub-line and a second sub-line located on opposite sides of the compensated active portion along the thickness direction of the display panel. The first sub-line intersects with the first connecting line along the thickness direction of the display panel, and the second sub-line intersects with the first connecting line along the thickness direction of the display panel. Wherein, the line width of the first sub-line corresponding to the first line segment is greater than the line width of the first sub-line corresponding to the second line segment, and / or the line width of the second sub-line corresponding to the first line segment is greater than the line width of the second sub-line corresponding to the second line segment.

18. The display panel according to any one of claims 2 to 15, characterized in that, The display panel further includes a plurality of repeating units arranged along the first direction and the second direction, and the repeating unit includes two pixel driving circuits arranged along the first direction, the two pixel driving circuits in the repeating unit being arranged axially symmetrically.

19. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1 to 18.

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