Anti-fuse memory and method of programming the same

Abstract

The present application relates to a kind of anti-fuse memory and its programming method, the anti-fuse memory includes anti-fuse storage array, the anti-fuse storage array includes a plurality of anti-fuse storage unit, each anti-fuse storage unit includes anti-fuse transistor, the anti-fuse storage array further includes: bit line;Feedback network is connected between the bit line and at least one anti-fuse storage unit, the feedback network is used to disconnect the connection of the bit line and anti-fuse storage unit when detecting the current size between the bit line and bit line connection anti-fuse storage unit meets preset condition.This application can program multiple bits simultaneously, and can eliminate unnecessary programming current, thereby reducing power consumption.

Description

Technical Field

[0001] This invention relates to memory, and more particularly to an antifuse memory, and also to a method for programming an antifuse memory. Background Technology

[0002] Antifuse memory uses gate oxide breakdown as its programming mechanism. The resulting connections are highly reliable and do not suffer from reverse growth issues, thus limiting the number of read cycles. Antifuse memory consists of an antifuse memory array, which comprises multiple antifuse memory cells. Generally, an antifuse memory cell consists of two transistors: a select transistor (NM1) and a memory cell transistor (NM2). See [link to relevant documentation]. Figure 1 Antifuse's advantages lie in its programming mechanism, security, and power consumption.

[0003] The programming mechanism of an antifuse is as follows: During programming, the antifuse creates a large potential difference across its thin gate oxide layer. This large potential difference causes avalanche breakdown in the oxide layer, short-circuiting the gate and source of the MOSFET, thus programming the antifuse bit cell. An antifuse can typically be programmed approximately 18 times. If the first programming attempt fails, the antifuse bit cell can be programmed multiple times, thereby improving the programming yield.

[0004] Antifuse offers superior security compared to other OTPs (One-Time Programmable Memory). Antifuse cannot distinguish between programmed and unprogrammed cells under a microscope, making it impossible to read programmed data. Not only is programming information undetectable under a microscope, but voltage hotspots are also undetectable by FIB (Focused Ion Beam) imaging, making it extremely difficult for unauthorized users to access data stored in Antifuse memory.

[0005] Antifuse has a higher resistance in the unprogrammed state and a lower resistance in the programmed state, thus its static power consumption is low.

[0006] Traditional antifuse memories are programmed one bit at a time, which results in low programming efficiency. Summary of the Invention

[0007] Therefore, it is necessary to provide an antifuse memory capable of programming multiple bits simultaneously and a programming method thereof.

[0008] An antifuse memory includes an antifuse memory array, the antifuse memory array including a plurality of antifuse memory cells, each antifuse memory cell including an antifuse transistor, the antifuse memory array further including: a bit line; a feedback network connected between the bit line and at least one of the antifuse memory cells, the feedback network being used to disconnect the connection between the bit line and the antifuse memory cell when the current between the bit line and the connected antifuse memory cell is detected to meet a preset condition.

[0009] The aforementioned antifuse memory utilizes the characteristic that the current between the antifuse memory cells connected to the bit lines becomes very large after programming data "1". A feedback network is set up to disconnect the connection between the bit lines and the antifuse memory cells when this large current is detected, so as to avoid the programming voltage supplied to the antifuse transistor from failing to reach the design value due to driving this large current. Therefore, it is possible to program multiple bits simultaneously.

[0010] In one embodiment, the preset condition is that when performing the operation of programming data "1", the current between the antifuse memory cells connected to the bit lines is greater than a preset threshold.

[0011] In one embodiment, the feedback network includes: a current mirror, wherein the reference current terminal of the current mirror is the current between the antifuse memory cells connected to the bit lines, and the reference current terminal is connected to the antifuse memory cells connected to the bit lines; a comparator, wherein the first input terminal of the comparator is connected to the copy current terminal of the current mirror, and the second input terminal of the comparator is used to input a reference signal; and a controlled switch unit, wherein the controlled terminal of the controlled switch unit is connected to the output terminal of the comparator, and is used to control the connection and disconnection between the antifuse memory cells connected to the bit lines.

[0012] In one embodiment, the controlled switch unit includes a transmission gate, which connects the bit lines to each of the antifuse memory cells when the output of the comparator outputs a first level, and disconnects the bit lines to each of the antifuse memory cells when the output of the comparator outputs a second level; one of the first level and the second level is a low level and the other is a high level.

[0013] In one embodiment, the controlled switch unit further includes: a D flip-flop, the first input of which is connected to the output of the comparator, and the first output of which is directly connected to the first control terminal of the transmission gate; and an inverter, the first output of which is connected to the second control terminal of the transmission gate.

[0014] In one embodiment, the current mirror includes: an NMOS transistor NM3, the drain of which is connected to its gate and each antifuse memory cell connected to the bit line, and the source of which is connected to the controlled switch unit; and an NMOS transistor NM4, the drain of which is connected to the first input terminal of the comparator, and the source of which is connected to the bit line.

[0015] In one embodiment, each of the antifuse memory cells further includes a select transistor, the controlled terminal of which is connected to a word line of the antifuse memory array, a first terminal of which is connected to the feedback network, and a second terminal of which is connected to the antifuse transistor; the controlled terminal of the antifuse transistor is used to receive a programming voltage.

[0016] In one embodiment, the antifuse memory further includes a programming signal generation unit, which is used to simultaneously output a third level to multiple bit lines when programming data is "1", the third level being the opposite of the level on the corresponding bit line when programming data is "0".

[0017] In one embodiment, the antifuse memory array further includes a sensitive amplifier, wherein the drain of the NMOS transistor NM3 is connected to the common terminal of the antifuse memory cell.

[0018] A programming method for an antifuse memory includes: in response to an operation of programming data "1" to an antifuse memory cell, detecting the magnitude of the current between a corresponding bit line of the antifuse memory array and the antifuse memory cell connected to the bit line; if the magnitude of the current meets a preset condition, disconnecting the connection between the bit line and the antifuse memory cell.

[0019] The above-mentioned antifuse memory programming method utilizes the characteristic that the current between the bit lines and the antifuse memory cells connected by the bit lines becomes very large after programming data "1". When this large current is detected, the connection between the bit line and the antifuse memory cell is disconnected, so as to avoid the situation where the programming voltage provided to the antifuse transistor cannot reach the design value due to driving this large current. Therefore, it is possible to program multiple bits at the same time.

[0020] In one embodiment, the operation of programming the antifuse memory cell with data "1" is performed simultaneously on antifuse memory cells connected to multiple bit lines. Attached Figure Description

[0021] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0022] Figure 1 This is a circuit diagram of an exemplary antifuse memory cell;

[0023] Figure 2 This is a circuit diagram of one row in an exemplary antifuse memory array;

[0024] Figure 3 This is a circuit diagram of an antifuse memory array according to an embodiment of this application;

[0025] Figure 4 This is a circuit diagram of the feedback network connecting the antifuse memory cell in one embodiment of this application;

[0026] Figure 5 This is a circuit diagram of the feedback network connecting the antifuse storage unit in another embodiment of this application;

[0027] Figure 6 This is a circuit diagram of the feedback network connecting the antifuse memory cell in another embodiment of this application;

[0028] Figure 7 This is a flowchart of a programming method for an antifuse memory according to an embodiment of this application. Detailed Implementation

[0029] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0032] Figure 2 In an exemplary antifuse memory array, if CELL0, CELL1, and CELL2 are to be programmed simultaneously, bit lines BL0, BL1, and BL2 should first be set to zero. The programming voltage VPPIN is then applied at a preset high voltage (e.g., 7.5V) after other programming control signals are ready. Taking CELL0 as an example, if CELL0 is successfully programmed, the gate oxide layer of the antifuse transistor is broken down, resulting in a very low resistance value for the programmed CELL0. This causes a large current to flow between the gate of the antifuse transistor and BL0 (hereinafter referred to as the programming current). The high voltage VPPIN is typically generated by the internal circuitry of the antifuse memory. If its driving capability is insufficient to maintain the original 7.5V voltage value while sustaining this current, programming CELL1 and CELL2 may fail. Taking an antifuse memory array with 8 I / Os as an example, if you want to program 8 I / Os simultaneously, the VPPIN needs to maintain a programming voltage of 7.5V even with 7 channels. This requires the VPPIN to have strong driving capability, which is difficult to achieve in actual products. In addition, a large programming current will lead to high power consumption.

[0033] This application provides an antifuse memory and its programming method, which can program multiple bits simultaneously to improve programming efficiency. The antifuse memory includes an antifuse memory array, which includes multiple antifuse memory cells, each antifuse memory cell including an antifuse transistor NM2. The antifuse memory array further includes:

[0034] Bit line;

[0035] A feedback network, connected between the bit line and at least one antifuse memory cell, is used to disconnect the bit line from the antifuse memory cell when the current between the bit line and the connected antifuse memory cell meets a preset condition. Figure 3Taking bit line BL0 as an example, a feedback network is connected between bit line BL0 and multiple antifuse memory cells. When programming data "1" (i.e. writing data "1"), if the feedback network connected to bit line BL0 detects that the current between bit line BL0 and the antifuse memory cell connected to bit line BL0 is greater than a preset threshold, then bit line BL0 is disconnected from the antifuse memory cell connected to it.

[0036] The aforementioned antifuse memory utilizes the characteristic that the current between the antifuse memory cells connected to the bit lines becomes very large after programming data "1". A feedback network is set up to disconnect the connection between the bit lines and the antifuse memory cells when this large current is detected, so as to avoid the situation where the programming voltage provided to the antifuse transistor cannot reach the design value due to driving this large current. Therefore, it is possible to program multiple bits at the same time.

[0037] exist Figure 4 In the illustrated embodiment, the feedback network includes:

[0038] The current mirror has a reference current terminal whose current is the current between the bit line BL and the anti-fuse memory cell connected to the bit line BL. The reference current terminal is connected to the anti-fuse memory cell.

[0039] The comparator has its first input terminal Ibl connected to the copy current terminal of the current mirror, and its second input terminal is used to input the reference signal Iref.

[0040] The controlled switch unit, whose controlled terminal is connected to the output terminal of the comparator, is used to control the connection and disconnection between the bit line BL and the antifuse memory cells connected to the bit line BL.

[0041] See Figure 5 In one embodiment of this application, the controlled switch unit includes a transmission gate. When the transmission gate outputs a first level at the output of the comparator, it connects the bit line BL to each antifuse memory cell connected to the bit line BL. When the transmission gate outputs a second level at the output of the comparator, it disconnects the bit line BL from each antifuse memory cell connected to the bit line BL. One of the first level and the second level is a low level, and the other is a high level.

[0042] In one embodiment of this application, the current mirror includes:

[0043] The drain of NMOS transistor NM3 is connected to its gate and the antifuse memory cells connected to the bit line BL. The source of NMOS transistor NM3 is connected to the controlled switch unit.

[0044] The drain of NMOS transistor NM4 is connected to the first input terminal of the comparator, and the source of NMOS transistor NM4 is connected to the bit line BL.

[0045] See Figure 6 In one embodiment of this application, the controlled switch unit further includes a D flip-flop and an inverter. The first input terminal C1 of the D flip-flop is connected to the output terminal of the comparator, the first output terminal of the D flip-flop is directly connected to the first control terminal of the transmission gate, and the first output terminal of the D flip-flop is also connected to the second control terminal of the transmission gate through the inverter.

[0046] In one embodiment of this application, each antifuse memory cell further includes a selection transistor NM1. The controlled terminal of the selection transistor NM1 is connected to the word line WL of the antifuse memory array, the first terminal of the selection transistor NM1 is connected to the feedback network, and the second terminal of the selection transistor NM1 is connected to the antifuse transistor NM2. Figure 4 In the illustrated embodiment, the drain of selection transistor NM1 is connected to the feedback network, the source of selection transistor NM1 is connected to the drain of antifuse transistor NM2, and the source of antifuse transistor NM2 is grounded. The controlled terminal of antifuse transistor NM2 is used to receive the programming voltage VPPIN.

[0047] In one embodiment of this application, the antifuse memory array further includes a sensitive amplifier SA. The drain of the NMOS transistor NM3 is connected to the common terminal of the antifuse memory cell via the sensitive amplifier SA.

[0048] In one embodiment of this application, the antifuse memory further includes a programming signal generation unit. The programming signal generation unit is used to simultaneously output a third level to multiple bit lines when programming data is "1". The third level is the opposite of the level on the corresponding bit line when programming data is "0" (i.e., writing data "0"). In one embodiment of this application, the programming signal generation unit is used to output a low level when programming data is "1".

[0049] The following combination Figure 6 The working principle of the antifuse memory in the embodiments of this application is introduced as follows:

[0050] NMOS transistors NM3 and NM4 form a current mirror. The drain of NMOS transistor NM3 is connected to the bl terminal of the antifuse memory cell, and the source is connected to the transmission gate and then to the bit line BL. The drain of NMOS transistor NM4 is connected to the positive input Ibl of the comparator, and the source is connected to the bit line BL. The reference current Iref is connected to the negative input of the comparator, and the output of the comparator is connected to the first input of a D flip-flop (rising edge triggered). The output of the D flip-flop is connected to the control terminal of the transmission gate through an inverter. This connection forms a feedback network.

[0051] When the antifuse memory is in the programming state, there are two possibilities: programming data "0" and programming data "1".

[0052] When programming data "0", the D flip-flop is first reset via its reset terminal Rst, thus turning on the transmission gate. The antifuse memory selects the address of the antifuse memory cell that needs to be programmed with data "0", i.e., setting the corresponding word line WL to "1" and the corresponding bit line BL to "1". The "1" signal (i.e., high level) of bit line BL is sent to the bl terminal of the corresponding antifuse memory cell through the transmission gate and then through the NMOS transistor NM3, and then to the drain of antifuse transistor NM2 through the conducting selection transistor NM1. At this time, the programming voltage VPPIN is high. Since the bit line BL provides a high level to the drain of antifuse transistor NM2, the voltage difference between the gate and drain of antifuse transistor NM2 is VPP-VDD (VDD is the power supply voltage of the antifuse memory, exemplarily 5V, and VPP is the voltage value of the programming voltage VPPIN). Because the voltage difference is small, it will not break down the thin gate oxide of antifuse transistor NM2, thus completing the programming data "0" operation of the antifuse memory cell. During this period, almost no current flows through NMOS transistor NM3, the comparator output remains "0", the D flip-flop will not trigger, and the transmission gate is in a normally on state.

[0053] When programming data "1" is input, the D flip-flop is first reset, thus turning on the transmission gate. The antifuse memory selects the address of the antifuse memory cell that needs programming data "1", i.e., setting the corresponding word line WL to "1" and the corresponding bit line BL to "0". The "0" signal (i.e., low level) of bit line BL is sent to the bl terminal of the corresponding antifuse memory cell through the transmission gate and then through the NMOS transistor NM3, and then to the drain of antifuse transistor NM2 through the conducting selection transistor NM1. At this time, the programming voltage VPPIN is high. Since the bit line BL is low at the drain of antifuse transistor NM2, the voltage difference between the gate and drain of antifuse transistor NM2 is VPP. The large voltage difference causes the thin gate oxide of antifuse transistor NM2 to break down, thus completing the programming data "1" operation of the antifuse memory cell. Before the thin gate oxide of antifuse transistor NM2 breaks down, almost no current flows through NMOS transistor NM3, the comparator output is "0", the D flip-flop is not triggered, and the transmission gate is normally on. However, after the thin gate oxide of antifuse transistor NM2 breaks down, a large programming current flows between the gate of antifuse transistor NM2 and the bit line BL (NMOS transistor NM3). At this time, the current at the positive input of the comparator suddenly increases, the comparator output becomes "1", the D flip-flop is triggered, and the transmission gate closes, thus shielding this large programming current. Therefore, the excess programming current is eliminated, reducing the power consumption of the antifuse memory. Understandably, the feedback network disconnects the corresponding bit line from the antifuse memory cell during the programming data "1" operation.

[0054] In the read (unprogrammed) operation state, the address of the antifuse memory cell to be read is first selected, that is, the corresponding word line WL is set to "1", the sensitive amplifier SA is turned on to the antifuse memory cell (the antifuse memory cell to be read), and the programming voltage VPPIN of the antifuse memory cell to be read is set to "0".

[0055] Based on the above embodiments, the antifuse memory of this application can achieve multi-bit programming, improving programming efficiency. It can also eliminate unnecessary programming current, thereby reducing the power consumption of the antifuse memory. Furthermore, traditional antifuse memories that program one bit at a time require numerous high-voltage decoding circuits, levelshift circuits, buffers, etc., while the antifuse memory of the embodiments of this application can omit these circuits, thus simplifying the antifuse memory circuitry.

[0056] This application provides a programming method for an antifuse memory. Figure 7 This is a flowchart of a programming method for an antifuse memory according to an embodiment of this application, including the following steps:

[0057] When the S710 is programmed to "1", it detects the current between the bit line and the connected antifuse memory cell.

[0058] When programming data "1" (i.e. writing data "1") to an antifuse memory cell, the current between the corresponding bit line of the antifuse memory cell to which data "1" needs to be written and the antifuse memory cell connected to the bit line is detected.

[0059] S720 determines whether the current magnitude meets preset conditions.

[0060] If the current magnitude meets a preset condition, proceed to step S730. In one embodiment of this application, the preset condition is that the current is greater than a preset threshold.

[0061] S730, disconnect the bit line from the antifuse memory cell.

[0062] Upon detecting a high current, the bit line experiencing the high current will be disconnected from the antifuse memory cell it is connected to. Note that the disconnection action occurs during the programming data "1" operation.

[0063] The above-mentioned antifuse memory programming method utilizes the characteristic that the current between the bit lines and the antifuse memory cells connected by the bit lines becomes very large after programming data "1". When this large current is detected, the connection between the bit line and the antifuse memory cell is disconnected, so as to avoid the situation where the programming voltage provided to the antifuse transistor cannot reach the design value due to driving this large current. Therefore, it is possible to program multiple bits at the same time.

[0064] In one embodiment of this application, the operation of programming data "1" to the antifuse memory cell is to operate on the antifuse memory cells connected to multiple bit lines simultaneously, thereby realizing the simultaneous programming of multiple bits.

[0065] In one embodiment of this application, the aforementioned steps S710 to S730 are achieved by setting a feedback network between the bit line and each antifuse memory cell connected to it.

[0066] In one embodiment of this application, the feedback network includes:

[0067] A current mirror, wherein the current at the reference current terminal of the current mirror is the current between the anti-fuse memory cells connected to the bit lines, and the reference current terminal is connected to the corresponding anti-fuse memory cell;

[0068] A comparator, wherein the first input terminal of the comparator is connected to the copy current terminal of the current mirror, and the second input terminal of the comparator is connected to the reference signal terminal;

[0069] A controlled switch unit, wherein the controlled terminal of the controlled switch unit is connected to the output terminal of the comparator, is used to control the connection and disconnection between the bit lines and the antifuse memory cells connected to the bit lines.

[0070] In one embodiment of this application, the controlled switch unit includes a transmission gate. When the output terminal of the comparator outputs a first level, the transmission gate connects the bit lines to each of the antifuse memory cells connected to the bit lines. When the output terminal of the comparator outputs a second level, the transmission gate disconnects the bit lines to each of the antifuse memory cells connected to the bit lines. One of the first level and the second level is a low level, and the other is a high level.

[0071] In one embodiment of this application, the controlled switch unit further includes:

[0072] A D flip-flop, wherein the first input of the D flip-flop is connected to the output of the comparator, and the first output of the D flip-flop is directly connected to the first control terminal of the transmission gate;

[0073] An inverter is used, and the first output of the D flip-flop is connected to the second control terminal of the transmission gate through the inverter.

[0074] In one embodiment of this application, the current mirror includes:

[0075] NMOS transistor NM3, the drain of NMOS transistor NM3 is connected to its gate and each antifuse memory cell connected by the bit line, and the source of NMOS transistor NM3 is connected to the controlled switch unit;

[0076] NMOS transistor NM4, the drain of which is connected to the first input terminal of the comparator, and the source of which is connected to the bit line.

[0077] It should be understood that although the steps in the flowchart of this application are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. Figures 2 to 6 A black dot at the intersection of conductors indicates that the intersecting conductors are connected; the absence of a black dot indicates that the conductors are not connected.

[0078] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0079] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0080] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An antifuse memory, comprising an antifuse memory array, the antifuse memory array comprising a plurality of antifuse memory cells, each antifuse memory cell comprising an antifuse transistor, characterized in that, The antifuse storage array also includes: Bit line; A feedback network is connected between the bit line and at least one of the antifuse memory cells. The feedback network is used to disconnect the bit line from the antifuse memory cell when the current between the bit line and the antifuse memory cell connected to the bit line is detected to meet a preset condition. The feedback network includes: A current mirror, wherein the current at the reference current terminal of the current mirror is the current between the anti-fuse memory cells connected to the bit lines, and the reference current terminal is connected to the anti-fuse memory cells connected to the bit lines. A comparator, wherein the first input terminal of the comparator is connected to the copy current terminal of the current mirror, and the second input terminal of the comparator is used to input a reference signal; A controlled switch unit, wherein the controlled terminal of the controlled switch unit is connected to the output terminal of the comparator, and is used to control the connection and disconnection between the bit lines and the antifuse memory cells connected to the bit lines; the controlled switch unit includes: A transmission gate, which connects each of the antifuse memory cells connected to the bit lines when the output of the comparator outputs a first level, and disconnects each of the antifuse memory cells connected to the bit lines when the output of the comparator outputs a second level; one of the first level and the second level is a low level, and the other is a high level; A D flip-flop, wherein the first input of the D flip-flop is connected to the output of the comparator, and the first output of the D flip-flop is directly connected to the first control terminal of the transmission gate; An inverter is used, and the first output of the D flip-flop is connected to the second control terminal of the transmission gate through the inverter.

2. The antifuse memory according to claim 1, characterized in that, The preset condition is that when performing the operation of programming data "1", the current between the antifuse memory cells connected to the bit lines is greater than a preset threshold.

3. The antifuse memory according to claim 1, characterized in that, The current mirror includes: NMOS transistor NM3, the drain of NMOS transistor NM3 is connected to its gate and each antifuse memory cell connected by the bit line, and the source of NMOS transistor NM3 is connected to the controlled switch unit; NMOS transistor NM4, the drain of which is connected to the first input terminal of the comparator, and the source of which is connected to the bit line.

4. The antifuse memory according to claim 1, characterized in that, Each of the antifuse memory cells further includes a selection transistor, the controlled terminal of which is connected to the word line of the antifuse memory array, the first terminal of which is connected to the feedback network, and the second terminal of which is connected to the antifuse transistor. The controlled terminal of the antifuse transistor is used to receive the programming voltage.

5. The antifuse memory according to claim 1, characterized in that, It also includes a programming signal generation unit, which is used to output a third level to multiple bit lines simultaneously when programming data is "1". The third level is the opposite of the level on the corresponding bit line when programming data is "0".

6. A programming method for the antifuse memory according to claim 1, characterized in that, include: In response to the operation of programming data "1" to the antifuse memory cell, the magnitude of the current between the corresponding bit line and the antifuse memory cell connected to the bit line of the antifuse memory array is detected; If the current magnitude meets the preset conditions, the connection between the bit line and the antifuse memory cell is disconnected.

7. The programming method for the antifuse memory according to claim 6, characterized in that, The operation of programming the antifuse memory cell with data "1" is performed simultaneously on antifuse memory cells connected by multiple bit lines.

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