Mode switching logic circuit and DC-DC conversion system

Abstract

The invention discloses a mode switching logic circuit and a DC-DC conversion system, and belongs to the technical field of power supplies. The circuit comprises a current sampling and scaling module, an average current comparison module and a sampling and holding module. The current sampling and scaling module is used for sampling sensing current input by an external current sensor, and outputting the sensing current to the average current comparison module after accurate current scaling; the average current comparison module is used for carrying out integral comparison on the current output by the current sampling and scaling module and outputting the current to the sampling and holding module; and the sampling and holding module is used for buffering and sampling and holding an integral comparison result of the average current comparison module and then outputting the integral comparison result to an external circuit to control mode switching. According to the invention, the high-precision average current comparison circuit compatible with the PFM / PWM is designed, so that the mode switching threshold value is stable and reliable under all working conditions, and due to the precise low-error design, the hysteresis window of the threshold value can be designed to be smaller, thereby maximizing the full-load range power supply efficiency of the system.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of power supply circuit, in particular to a mode switching logic circuit and a DC-DC conversion system. BACKGROUND

[0002] The PFM (pulse frequency modulation) and PWM (pulse width modulation) mode switching of the DC-DC converter is the core to realize high efficiency operation in a wide load range. PFM reduces the loss by reducing the switching frequency at light load, improving system efficiency; PWM ensures fast dynamic response and low ripple output by fixed frequency at heavy load. In complex working conditions, the mode switching is required to have high precision and strong robustness. Developing an accurate switching strategy can dynamically match the load demand, avoid misjudgment or frequent switching caused by traditional hysteresis threshold, thereby reducing voltage fluctuation, reducing EMI risk, and optimizing battery energy distribution. This is crucial to prolong battery life, ensure the stability of key systems (such as sensors, motor control), and is a key technical breakthrough direction that balances energy efficiency and reliability.

[0003] The traditional mode switching logic circuit includes the following three kinds: I. Switching from PWM to PFM when the inductor current is detected multiple times to zero (entering DCM mode), and the output voltage feedback signal Vfb is less than the output reference voltage Vref to reach the set threshold, then switching from PFM to PWM.

[0004] II. Automatic switching according to the PWM signal on time, if the PWM signal on time is too short, then automatically switch to the constant on time (COT) PFM mode, when the PWM signal on time recovers and exceeds the minimum on time, then switch back to the PWM mode.

[0005] III. Automatically skipping according to the error amplifier output signal VC amplitude of Vfb and Vref, if the VC amplitude is too low, then skip the next clock to trigger the inductor charging, until the VC amplitude recovers, thereby entering the PFM mode of PSM (pulse skipping modulation); if the load is large enough to keep the VC at a high level, then the inductor charging can be triggered normally every time, that is, enter the PWM mode.

[0006] These traditional mode switching logic circuits have the following two major drawbacks: First, threshold drift: due to input and output voltage changes, inductance parameter differences, temperature fluctuations, and process deviations, the threshold value drifts, causing the concave of the power efficiency curve, the uncertainty of the mode switching condition, etc. Second, misjudgment risk: the switching mechanism based on fixed threshold (such as Vfb-Vref difference or on time threshold) is prone to misjudgment during rapid load transients. In the heavy / light load scenario, small range load mutations exist the risk of mis-triggering PFM and PWM switching. SUMMARY

[0007] The application provides a mode switching logic circuit and a DC-DC conversion system. A high-precision average current comparison circuit compatible with PFM / PWM is designed, so that the mode switching threshold is stable and reliable under all working conditions. Due to the accurate low-error design, the hysteresis window of the threshold can be designed to be smaller, thereby maximizing the full-load range power efficiency of the system. Specifically as follows. A mode switching logic circuit includes a current sampling and scaling module, an average current comparison module, and a sample-and-hold module. The current sampling and scaling module is used to sample the externally input current and perform current scaling according to the configured threshold current and then output to the average current comparison module. The average current comparison module is used to integrate and compare the current output by the current sampling and scaling module and then output to the sample-and-hold module. The sample-and-hold module is used to buffer and sample and hold the integration and comparison result of the average current comparison module and then output to the external circuit to control the mode switching.

[0008] A DC-DC conversion system includes the above-mentioned mode switching logic circuit and further includes a DC-DC topology circuit for forming an output voltage by step-down or step-up of an input voltage, a current sensor connected with the DC-DC topology circuit for detecting the inductor current in the DC-DC topology circuit, a PWM controller having an input end connected with the current sensor and an output end connected to a first input end of a two-way multiplexer, a PFM controller having an input end connected with the current sensor and an output end connected to a second input end of the two-way multiplexer, an input end of the mode switching logic circuit connected with the current sensor and an output end connected to a selection control end of the two-way multiplexer, an output end of the two-way multiplexer connected to a drive logic circuit for selecting the output of the PWM controller or the output of the PFM controller according to the control signal of the mode switching logic circuit, the drive logic circuit generating a power tube control signal according to the signal selected and output by the two-way multiplexer in combination with a zero-crossing signal, and a driver driving the power tube in the DC-DC topology circuit according to the power tube control signal output by the drive logic circuit.

[0009] The mode switching logic circuit and the DC-DC conversion system have the following advantages: (1) dynamic threshold configuration: the threshold current can be programmed and adjusted by the resistance DAC unit to adapt to different working conditions; (2) direct average current comparison: the real load current is calculated based on the integral capacitor, without relying on multiple zero-crossing detection, and the switching threshold can be set at any load in the DCM mode; (3) noise resistance capability: the integral process filters out the disturbance of the sensing current to avoid false triggering; (4) no minimum time constraint: the integral comparison mechanism is naturally adapted to the discontinuous current (DCM), without the need for forced minimum conduction time; (5) smooth transition: a configurable narrow hysteresis window (such as ±1mA) can be used to eliminate oscillation under critical load; (6) no blind area problem: the current is directly compared instead of the VC amplitude, avoiding the clock skipping out of control of the jump pulse modulation PSM; (7) digital compatibility: the resistance DAC unit configuration interface can be linked with a digital controller (such as an MCU) to realize adaptive threshold adjustment. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 The circuit principle structure schematic diagram of the mode switching logic circuit according to an embodiment of the present application is shown in the figure. Figure 2 The circuit principle structure schematic diagram of the mode switching logic circuit according to another embodiment of the present application is shown in the figure. Figure 3 The circuit principle structure schematic diagram of the error amplifier according to an embodiment of the present application is shown in the figure. Figure 4 The circuit principle structure schematic diagram of the resistance DAC unit according to an embodiment of the present application is shown in the figure. Figure 5 The circuit principle structure schematic diagram of the Zux subunit according to an embodiment of the present application is shown in the figure. Figure 6 The circuit principle structure schematic diagram of the Zuy subunit according to an embodiment of the present application is shown in the figure. Figure 7 The Vint waveform diagram when the average current is greater / less than the threshold current is shown in the figure. Figure 8 The waveform diagram of the key signals in the mode switching logic circuit and the DC-DC conversion system is shown in the figure. Figure 9 The circuit principle structure schematic diagram of the DC-DC conversion system according to an embodiment of the present application is shown in the figure. Figure 10 The circuit principle structure schematic diagram of the first chopping unit according to an embodiment of the present application is shown in the figure. Figure 11 The circuit principle structure schematic diagram of the second chopping unit according to an embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0011] The embodiments of the present application will be described in detail below with reference to the drawings. It should be understood that the specific embodiments described below are only used to explain the present application and not to limit the present application. In the following description, specific details are given to provide a thorough understanding of the embodiments. However, one of ordinary skill in the art will understand that the relevant embodiments can be implemented without these specific details. For example, circuits can be shown in block diagrams so as not to obscure the embodiments in unnecessary details. In other cases, well-known circuits, structures and techniques can not be shown in detail in order not to obscure the embodiments.

[0012] As shown in the mode switching logic circuit shown in Figure 1 or Figure 2 , mainly used for PWM / PFM (pulse width modulation / pulse frequency modulation) mode switching control. The circuit includes current sampling and scaling module 10, average current comparison module 20 and sample and hold module 30. Among them, the current sampling and scaling module 10 is used to sample the sensing current Isen of the external current sensor, and the scaled current is output to the average current comparison module 20. The average current comparison module 20 is used to integrate and compare the current output by the current sampling and scaling module 10 with the reference current, and output to the sample and hold module 30. The sample and hold module 30 is used to buffer and sample and hold the integral comparison result of the average current comparison module 20 and output to the external circuit to control the mode switching.

[0013] The mode switching logic circuit belongs to a configurable threshold high-precision average current comparison circuit, which realizes the full working condition stability of the mode switching threshold of pulse width modulation PWM or pulse frequency modulation PFM through average current detection technology. The circuit effectively solves the threshold drift problem caused by input and output voltage changes, inductance parameter differences, temperature fluctuations and process deviations of traditional mode switching circuits, and provides accurate and reliable load state judgment basis for the entire power supply system. The core circuit is composed of a current sampling and scaling module 10 with a configurable peak current, an average current comparison module 20 that can realize average current comparison, and a sample and hold module 30 that can maintain stable output. Based on the sensing current of the external Sense-FET current sensor, through accurate sampling, scaling and integral comparison, the load current is finally matched with the configurable threshold with milliamperes level precision, so as to optimize the power efficiency curve.

[0014] As one of the implementation modes, as shown in Figure 1 , Figure 4 and Figure 5As shown, the current sampling and scaling module 10 comprises a resistance DAC unit RDAC, a sampling capacitor Cs, a sampling resistor Zs, a first switch S1, an error amplifier EA and a first MOS transistor M1. The resistance DAC unit RDAC has an equivalent resistance that can be dynamically adjusted, and has three terminals, i.e. an Up terminal, a Dn terminal and a Sel terminal. The Up terminal is a high-side terminal of the resistance DAC unit, used for connecting a power supply VDD; the Sel terminal is a control terminal of the resistance DAC unit, used for receiving a control signal Sel<6:0> input by an external controller to dynamically adjust the equivalent resistance between the Up terminal and the Dn terminal; and the Dn terminal is a low-side terminal of the resistance DAC unit, used for connecting a sensing current output terminal of an external current sensor, and according to the adjusted equivalent resistance between the Up terminal and the Dn terminal, the Dn terminal generates a corresponding sampling voltage Vs. One end of the sampling capacitor Cs is connected to the Up terminal of the resistance DAC unit RDAC, and the other end is connected to the external current input terminal and the Dn terminal of the resistance DAC unit RDAC through the first switch S1. One end of the sampling resistor Zs is connected to the Up terminal of the resistance DAC unit RDAC, and the other end is connected to the non-inverting input terminal of the error amplifier EA and the drain of the first MOS transistor M1. The Dn terminal of the resistance DAC unit RDAC is connected to the inverting input terminal of the error amplifier EA through the first switch S1. The output terminal of the error amplifier EA is connected to the gate of the first MOS transistor M1. The source of the first MOS transistor M1 is connected to ground Vss. The first MOS transistor M1 is an NMOS transistor. The high-side terminal and the low-side terminal are two opposite concepts, and the high and the low are relative. The high-side terminal means that in the circuit where the resistance DAC unit is located, the voltage of the Up terminal is higher than that of the Dn terminal; and the low-side terminal means that in the circuit where the resistance DAC unit is located, the voltage of the Dn terminal is lower than that of the Up terminal.

[0015] As one of the embodiments, the current sampling and scaling module 10 further comprises a first chopping unit Chop1a. The first chopping unit Chop1a is composed of four switches, one of which is connected in series between the first switch S1 and the inverting input terminal of the error amplifier EA, another of which is connected in series between the sampling resistor Zs and the non-inverting input terminal of the error amplifier EA, in addition, one of which is connected in series between the first switch S1 and the non-inverting input terminal of the error amplifier EA, and another of which is connected in series between the sampling resistor Zs and the inverting input terminal of the error amplifier EA, for switching the input signals of the error amplifier EA to achieve input chopping.

[0016] As another embodiment, as shown in FIG. 2, the current sampling and scaling module 10 further comprises a second chopping unit Chop1b. The second chopping unit Chop1b is composed of four switches, one of which is connected in series between the first switch S1 and the non-inverting input terminal of the error amplifier EA, another of which is connected in series between the sampling resistor Zs and the inverting input terminal of the error amplifier EA, in addition, one of which is connected in series between the first switch S1 and the inverting input terminal of the error amplifier EA, and another of which is connected in series between the sampling resistor Zs and the non-inverting input terminal of the error amplifier EA, for switching the input signals of the error amplifier EA to achieve input chopping. Figure 2As shown, the current sampling and scaling module 10 includes a resistor DAC unit RDAC, a sampling capacitor Cs, a sampling resistor Zs, a first switch S1, an error amplifier EA, and a first MOSFET M1. The equivalent resistance of the resistor DAC unit RDAC is dynamically adjustable, and it has three terminals: Up, Dn, and Sel. The Up terminal serves as the high-side terminal of the resistor DAC unit and is connected to the power supply VDD. The Sel terminal serves as the control terminal of the resistor DAC unit and receives the control signal Sel<6:0> input from an external controller to dynamically adjust the equivalent resistance between the Up and Dn terminals. The Dn terminal serves as the low-side terminal of the resistor DAC unit and is connected to the sensing current output terminal of an external current sensor. Based on the adjusted equivalent resistance between the Up and Dn terminals, the Dn terminal generates a corresponding sampling voltage Vs. One end of the sampling capacitor Cs is connected to one end of the sampling resistor Zs and the Up terminal of the resistor DAC unit RDAC, while the other end is connected to the inverting input terminal of the error amplifier EA. The other end of the sampling resistor Zux is connected to the externally input current Isen, and then connected to the inverting input of the error amplifier EA via the first switch S1. The Dn terminal of the resistor DAC unit RDAC is connected to the non-inverting input of the error amplifier EA and the drain of the first MOSFET M1. The output of the error amplifier EA is connected to the gate of the first MOSFET M1. The first MOSFET M1 is an NMOS transistor, with its source grounded to Vss. Here, "high-side" and "low-side" are relative concepts. "High-side" refers to the voltage at the Up terminal being higher than the voltage at the Dn terminal in the circuit containing the resistor DAC unit; "low-side" refers to the voltage at the Dn terminal being lower than the Up terminal in the circuit containing the resistor DAC unit.

[0017] In one implementation, the current sampling and scaling module 10 further includes a first chopper unit Chop1a. The first chopper unit Chop1a consists of four switches, such as... Figure 10 As shown, one of the switches is connected in series with the first switch S1 ( Figure 10 The inverting input of the error amplifier EA (represented by A in the diagram) is connected to the inverting input of the error amplifier EA. Figure 10 (represented by Y in the text), another switch is connected in series at the Dn terminal of the resistor DAC unit RDAC ( Figure 10 (represented by B in the text) and the non-inverting input terminal of the error amplifier EA ( Figure 10 In addition, a switch is connected in series between the first switch S1 and the non-inverting input terminal of the error amplifier EA, and another switch is connected in series between the Dn terminal of the resistor DAC unit RDAC and the inverting input terminal of the error amplifier EA, in order to exchange the input signal of the error amplifier EA to achieve input chopping.

[0018] The current sampling and scaling module, through the negative feedback loop composed of error amplifier EA, sampling resistor Zs and first MOS tube M1, makes the voltage VS=VS', so as to generate a current Is=IL / (K1K2) in the drain-source branch of the first MOS tube M1. Wherein K1=IL / Isen is the current sensing ratio of the current sensor, IL is the inductance current, K2=Rzs / RRDAC is the scaling ratio from Isen(Isen, Peak) to the current Is, wherein Rzs is the resistance value of the sampling resistor Zs, and RRDAC is the equivalent resistance value of the resistance DAC unit. Through the large scaling capability provided by the two-stage scaling, the amplitude of the current Is is greatly reduced, which guarantees the smaller capacitance requirement of the integral capacitor Cint in the subsequent circuit.

[0019] As one of the embodiments, the error amplifier EA includes eleventh MOS M11, twelfth MOS M12, thirteenth MOS M13, fourteenth MOS M14, fifteenth MOS M15, sixteenth MOS M16 and seventeenth MOS M17, all of which are NMOS; eighteenth MOS M18, nineteenth MOS M19, twentieth MOS M20 and twenty-first MOS M21, all of which are PMOS. The source of the eleventh MOS M11 is connected to ground Vss, the drain is connected to the source of the fourteenth MOS M14 and the fifteenth MOS M15, and the gate is connected to the VB1 terminal. The source of the twelfth MOS M12 is connected to ground Vss, the drain is connected to the source of the sixteenth MOS M16, and the gate is connected to the VB1 terminal. The source of the thirteenth MOS M13 is connected to ground Vss, the drain is connected to the source of the seventeenth MOS M17, and the gate is connected to the VB1 terminal. The drain of the fourteenth MOS M14 is connected to the source of the eighteenth MOS M18 and the drain of the twentieth MOS M20, respectively, and the gate is connected to the Vip terminal. The drain of the fifteenth MOS M15 is connected to the source of the nineteenth MOS M19 and the drain of the twenty-first MOS M21, respectively, and the gate is connected to the Vin terminal. The drain of the sixteenth MOS M16 is connected to the drain of the eighteenth MOS M18 and the first switching terminal of the fifth switch S5, respectively, and the gate is connected to the VB2 terminal. The drain of the seventeenth MOS M17 is connected to the second switching terminal of the fifth switch S5, and the gate is connected to the gate of the sixteenth MOS M16 and the VB2 terminal. The gate of the eighteenth MOS M18 is connected to the gate of the nineteenth MOS M19, and the source is connected to the drain of the twentieth MOS M20. The gate of the nineteenth MOS M19 is connected to the VB3 terminal, the source is connected to the drain of the twenty-first MOS M21, and the drain is connected to the drain of the seventeenth MOS M17 and is commonly used as the output terminal of the error amplifier EA. The gate of the twentieth MOS M20 is connected to the gate of the twenty-first MOS M21 and is commonly connected to the fixed terminal of the fifth switch S5, and the source is connected to the power supply VDD. The source of the twenty-first MOS M21 is connected to the power supply VDD.

[0020] The VB1 end, the VB2 end and the VB3 end are connected with an external bias circuit, and bias voltage provided by the external bias circuit can make the connected MOS transistor work normally. The main function of the bias circuit is to generate the gate voltage required for the MOS transistor to work normally, so as to determine the working current of the MOS transistor, for example, the bias voltage VB1 generated by the current mirror is provided to the twelfth MOS transistor M12, so that the drain-source current IDS12 of the MOS transistor is determined; in addition, the adjacent MOS transistor can also work in the saturation region, for example, the determined bias voltage VB3 and the determined gate-source voltage VGS18 of the eighteenth MOS transistor form the determined source voltage VS18 of the eighteenth MOS transistor, so that the drain-source voltage VDS20 of the twentieth MOS transistor M20 is sufficient to make the twentieth MOS transistor M20 work in the saturation region. Wherein D refers to the drain, S refers to the source, G refers to the gate, the bias voltage is generally denoted by VB or Vbias, and B is the abbreviation of bias. The bias circuit can use the existing circuit as long as the required voltages of the VB1 end, the VB2 end and the VB3 end can be outputted, which will not be described here.

[0021] The Vip end is used as the non-inverting input end of the error amplifier EA, the Vin end is used as the inverting input end of the error amplifier EA, and the Vout end is used as the output end of the error amplifier EA. The fifth switch S5 is a single-pole double-throw switch, Figure 3 The black point of the fifth switch S5 is a fixed end, and the two opposite hollow points are a first switching end and a second switching end, respectively. An external controller can control the first switching end to be in communication with the fixed end or control the second switching end to be in communication with the fixed end, so as to reduce the offset voltage of the input error amplifier through chopping. The fifth switch S5 and the switch of the first chopping unit are synchronously switched, so as to ensure that the input of the error amplifier EA is always Vip non-inverting and Vin inverting after switching.

[0022] In this embodiment, the chopping technology is introduced into the current sampling and scaling module to reduce the offset voltage of Vs and Vs', so as to realize high-precision current scaling.

[0023] As one of the implementation manners, the resistance DAC unit RDAC includes N levels of resistance sub-units connected in parallel between the Up end and the Dn end. The resistance sub-units are also connected to the Sel end of the resistance DAC unit RDAC, respectively. The number of resistance sub-units of each level is different, starting from 1 of the first level and multiplying sequentially, and the number of resistance sub-units of the last level is The N is the number of bits that the resistance DAC unit can handle, which can be 6 bits, 7 bits, 8 bits, 9 bits, or 10 bits, etc. The resistance sub-unit is a Zux sub-unit or a Zuy sub-unit, the resistance sub-units of the first and second levels adopt the Zux sub-unit, and the resistance sub-units of the third and subsequent levels adopt the Zuy sub-unit, thereby forming a resistance array composed of the Zux sub-unit and the Zuy sub-unit. Based on the resistance array composed of the Zux sub-unit and the Zuy sub-unit, the control signals Sel<0>, Sel<1>, Sel<2>, etc. input can accurately realize the dynamic adjustment of the equivalent resistance of the resistance array, and improve the accuracy of the subsequent circuit for current sampling and scaling.

[0024] Specifically, as shown in Figure 4 The control signals Sel<0> and Sel<1> control 2<0> and 2<1> parallel Zux sub-units, respectively, and the control signals Sel<2> to Sel<6> control 2<3>, 2<4>, 2<5>, and 2<6> parallel Zuy sub-units, respectively, wherein the resistance values of the Zux sub-units and the Zuy sub-units are equal, and are ZU. Through the Sel<6:0> control signal, the equivalent resistance unit of the 7-bit resistance DAC unit can change between ZU / 127 and ZU with a resolution of ZU / 127.

[0025] As one of the embodiments, the Zux sub-unit includes two parallel switch resistance branches, each of which includes two X switches Kx and two X resistors Rx connected in series. The first end of the switch resistance branch is connected to the Up end, the second end is connected to the Dn end, and the control end of the X switch Kx is connected to the Sel end. Among them, the first end of the switch resistance branch is one end of the X switch Kx, and the second end is one end of the X resistor Rx. The switch resistance branch passes through two X switches and two X resistors in sequence from the first end to the second end.

[0026] The Zuy sub-unit includes a Y switch Ky and a Y resistor Ry. One end of the Y switch Ky is connected to the Up end, and the other end is connected to the Dn end through the Y resistor Ry, and the control end of the Y switch is connected to the Sel end. Among them, the X resistor in the Zux sub-unit and the Y resistor in the Zuy sub-unit are resistors of the same type, size, and resistance value. Each Zux sub-unit and each Zuy sub-unit has the same equivalent resistance value.

[0027] Specifically, as shown in Figure 5 and Figure 6As shown, Zux subunit is composed of two parallel Kx-Kx-Rx-Rx element series circuit, where X switch is set near the Up end, and its on-resistance is much smaller than X resistance, so as to minimize the on-voltage drop on the substrate bias effect of switch resistance. This array structure of Zux subunit, while achieving the same equivalent resistance as Zuy subunit, increases the overall area, effectively reduces the layout mismatch, thereby reducing the mismatch error.

[0028] As one of the embodiments, the mode switching logic circuit samples 7bit structure, that is, N is 7. In this way, the resistance subunit of the first stage is 1 Zux subunit; the resistance subunit of the second stage is 2 parallel Zux subunits; the resistance subunit of the third stage is 4 parallel Zuy subunits; the resistance subunit of the fourth stage is 8 parallel Zuy subunits; the resistance subunit of the fifth stage is 16 parallel Zuy subunits; the resistance subunit of the sixth stage is 32 parallel Zuy subunits; and the resistance subunit of the seventh stage is 64 parallel Zuy subunits. Among them, the minimum adjustable resolution of the equivalent resistance of the resistance DAC unit RDAC is one hundred and twenty-seventh of the equivalent resistance of each Zux subunit, or one hundred and twenty-seventh of the equivalent resistance of each Zuy subunit.

[0029] The current sampling and scaling module can configure high-precision threshold current generation, dynamically adjust the equivalent resistance (Rth) through digital control signal (Sel<6:0>), realize the programmable range (resolution 1mA) of threshold current from 1mA to 127mA. , and can perform two-stage scaling technology, the first stage is current sensor proportional (such as 1000:1), and the second stage is resistance proportional . The final threshold formula supports wide range and high precision configuration.

[0030] ​As one of the embodiments, the average current comparison module 20 includes a first current source D1, a second switch S2, a second MOS tube M2 and an integration capacitor Cint. The first current source D1 is used to output a reference current, the input end of which is connected to a power supply VDD, the output end of which is connected to the sample and hold module 30, in addition, the output end of which is connected to the ground Vss through the integration capacitor Cint, and the output end of which is also connected to the second MOS tube M2 through the second switch S2. The second switch S2 is a single-pole double-throw switch, and the second MOS tube M2 is an NMOS tube. The first switching end of the second switch S2 is directly connected to the power supply VDD, the second switching end is directly connected to the output end of the first current source D1, and the fixed end is connected to the drain of the second MOS tube M2. The first switching end and the fixed end are in communication or the second switching end and the fixed end are in communication by switching the second switch S2. The gate of the second MOS tube M2 is connected to the gate of the first MOS tube M1 in the current sampling and scaling module 10, and the source of the second MOS tube M2 is connected to the ground Vss. Figure 1 and Figure 2 The black dot of the second switch S2 in the middle is the fixed end, and the opposite two hollow dots are the first switching end and the second switching end respectively. The first current source D1 can use an existing current source circuit as long as it can generate the required reference current, and the specific circuit structure is not described here.

[0031] As one of the embodiments, a second chopping unit Chop2 is arranged between the current sampling and scaling module 10 and the average current comparison module 20. The second chopping unit Chop2 is arranged between the sampling resistor Zs in the current sampling and scaling module 10 and the drain of the first MOS tube M1, and between the fixed end of the second switch S2 and the drain of the second MOS tube M2 in the average current comparison module 20, so that the second MOS tube M2 can accurately mirror the sampling current Is in the current sampling and scaling module 10. Specifically, as shown in Figure 11 The second chopping unit Chop2 is composed of four switches, one of which is arranged in series between the sampling resistor Zs in the current sampling and scaling module 10 and the drain of the first MOS tube M1, and the other is arranged in series between the fixed end of the second switch S2 and the drain of the second MOS tube M2. In addition, the drain of the first MOS tube M1 is also connected to the fixed end of the second switch S2 through a switch, and the drain of the second MOS tube M2 is also connected to the sampling resistor Zs through a switch. The external controller realizes the accurate mirroring of the sampling current in the current sampling and scaling module 10 by the second MOS tube M2 through chopping control.

[0032] Specifically, as shown in Figure 1 , Figure 7 and Figure 8As shown, due to the presence of the second chopping unit Chop2, the second MOS transistor M2 can accurately mirror the current Is, which is connected to the Vint node during the high level of the control signal CKint of the second switch S2 and to the power supply VDD during the low level of the control signal CKint of the second switch S2 to keep the second MOS transistor M2 in the saturation region, and can be quickly switched to the Vint node when the next CKint high level comes. The first current source D1 is always connected to the Vint node to output the reference current 2Iref. The condition for Vint to be maintained between VDD and Vss is that the charging and discharging charges of Cint are conserved every cycle, , that is where T is the switching period, is the high level time of CKint (the time when the inductor current is greater than zero), and Isen, peak is the peak current of Isen. The load current in the DCM mode, that is, the average inductor current, can be calculated by the following formula: Therefore, the above condition is equivalent to , that is If , the voltage curve of Vint will be pulled down to contact Vss, and if , the voltage curve of Vint will be pulled up to contact VDD. The curves of the two cases are shown in Figure 7 , and the Vint valley values Vint, Valley of the two cases are 0V and a higher potential, respectively.

[0033] The average current comparison module 20 can realize a dynamic integration mechanism, and the average current in the DCM mode can be calculated by the integration capacitor Cint. The integration process can naturally filter out short-time fluctuations of the load current to avoid false triggering.

[0034] As one of the embodiments, the sample-and-hold module 30 comprises a third MOS transistor M3, a second current source D2, a first sample-and-hold capacitor CT1, a second sample-and-hold capacitor CT2, a third switch S3, a fourth switch S4, a fourth MOS transistor and a third current source D3. The third MOS transistor M3 is an NMOS transistor, the drain of which is connected to the power supply VDD, and the gate of which is connected to the output of the first current source D1 in the average current comparison module 20. The input of the second current source D2 is connected to the source of the third MOS transistor M3, and the output is grounded Vss. One end of the first sample-and-hold capacitor CT1 is connected to the source of the third MOS transistor M3 through the third switch S3, and the other end is grounded Vss. One end of the second sample-and-hold capacitor CT2 is connected to the gate of the fourth MOS transistor, and is connected to the source of the third MOS transistor M3 in turn through the fourth switch S4 and the third switch S3, and the other end is grounded Vss. The fourth MOS transistor is an NMOS transistor, the source of which is grounded Vss, and the drain of which is an output of the mode switching logic circuit, outputting a selection signal SEL to an external circuit. The input of the third current source D3 is connected to the power supply VDD, and the output is connected to the drain of the fourth MOS transistor. The second current source D2 and the third current source D3 can adopt existing current source circuits, as long as the required bias current can be generated, and the specific circuit structure is not described here.

[0035] The sample-and-hold module 30 comprises a buffer composed of the bias current Ibn output by the third MOS transistor M3 and the second current source D2, a sample-and-hold circuit composed of the first sample-and-hold capacitor CT1, the second sample-and-hold capacitor CT2, the third switch S3 and the fourth switch S4, and a comparator composed of the fourth MOS transistor and the bias current Ibp output by the third current source D3. The sample-and-hold circuit works under CKint, and can collect the voltage Vint,Valley-VGS3 buffered by the buffer to obtain Vx. Wherein Vint,Valley is the valley value of Vint, and VGS3 is the gate-source voltage of the third MOS transistor M3. If Vx will be pulled down to Vss, and SEL outputs high level, otherwise Vx will be pulled up so that the drain-source current of the fourth MOS transistor is greater than Ibp, and thus SEL outputs low level. Thus, the average current comparison function is realized. The sample-and-hold module performs valley voltage detection, and the integral result can be accurately captured by the buffer and the sample-and-hold circuit. And combined with digital configuration, a narrower hysteresis window is supported, the hysteresis window is optimized, and the efficiency curve smoothness is improved.

[0036] As Figure 9The DC-DC conversion system shown includes the mode switching logic circuit described in any of the above embodiments, and further includes a DC-DC topology circuit, a current sensor, a PWM controller, a PFM controller, a mode switching logic circuit, a 2-to-1 multiplexer MUX2, a drive logic circuit, and a driver BUF. The DC-DC topology circuit is used to step down or boost the input voltage VI to form the output voltage VO. The current sensor is a Sense-FET current sensor, which is connected to the DC-DC topology circuit and is used to detect the inductor current IL in the DC-DC topology circuit. The input terminal of the PWM controller is connected to the current sensor, and the output terminal is connected to the first input terminal of the 2-to-1 multiplexer MUX2. The input terminal of the PFM controller is connected to the current sensor, and the output terminal is connected to the second input terminal of the 2-to-1 multiplexer MUX2. The input terminal of the mode switching logic circuit is connected to the current sensor, and the output terminal is connected to the selection control terminal of the 2-to-1 multiplexer MUX2, used to output a selection signal SEL to the 2-to-1 multiplexer MUX2 based on the circuit Isen output by the current sensor. The output of the 2-to-1 multiplexer MUX2 is connected to the driver logic circuit, which selects either the output of the PWM controller or the output of the PFM controller based on the selection signal SEL from the mode switching logic circuit. The driver logic circuit generates a power transistor control signal based on the selection signal CKH from the MUX2 multiplexer and the zero-crossing signal from the ZCD circuit. The driver BUF then drives the power transistor in the DC-DC topology circuit according to the power transistor control signal output from the driver logic circuit.

[0037] Combination Figures 1 to 8 The threshold current is determined by Configuration, minimum resolution is .by Take 1000, Taking 1μA as an example, then A 7-bit RDAC design allows the threshold current to be arbitrarily configured with 1mA resolution between 1mA and 127mA. By changing the RDAC's bit depth design and combining appropriate Zux and Cint values, the threshold current can be... It can be designed to operate within any DCM average current range. To reduce the charge injection effects caused by chopping, the chopper operates on a clock frequency divided by several orders of the switching frequency.

[0038] The mode switching logic circuits described in the above embodiments, through the integral averaging filtering characteristics in the average current comparison module, can filter out short-term disturbances in the load current or sensed current peak value, thus preventing mode switching errors. Furthermore, due to the overall high-precision, low-error design, the mode switching average current threshold can be configured within a precise and narrower hysteresis window via Sel<6:0>, thereby optimizing the power efficiency curve.

[0039] The switch in each of the above embodiments is controlled by a control signal output by an external controller.

[0040] The mode switching logic circuit and DC-DC conversion system described above have an average current comparison error within the order of mA, and the mode switching threshold hysteresis window is reduced from about 50 mA of the conventional technology to the order of several mA, which maximizes the full load range power efficiency of the system and effectively avoids the false triggering of mode switching. Compared with the prior art, at least the following advantages are achieved: (1) Dynamic threshold configuration: programmable adjustment (e.g. 1 mA to 127 mA) through 7-bit RDAC to adapt to different working conditions; (2) Direct average current comparison: based on integral capacitance to calculate the real load current, without relying on multiple zero-crossing detection, and the switching threshold can be set at any load in DCM mode; (3) Anti-noise capability: the integral process filters out the disturbance of the sensed current to avoid false triggering; (4) No minimum time constraint: the integral comparison mechanism is naturally adapted to discontinuous current (DCM) and does not require a forced minimum on-time; (5) Smooth transition: configurable narrow hysteresis window (e.g. ±1 mA) to eliminate oscillation at critical loads; (6) No blind area problem: direct comparison of current rather than VC amplitude to avoid clock skipping out of control in PSM; (7) Digital compatibility: RDAC configuration interface can be linked with a digital controller (e.g. MCU) to realize adaptive threshold adjustment.

[0041] These circuits have wide application prospects and can be applied to various electronic devices and systems, including: In the field of portable electronic devices, the circuit can significantly improve energy efficiency. For example, in smartphones and tablets, the system can intelligently switch between PFM and PWM modes according to the actual load: in low load state (e.g. standby or background task running), it automatically switches to PFM mode to minimize power consumption; when high load applications (e.g. games or 5G communication) are detected, it quickly switches back to PWM mode to ensure stable power supply. Compared with traditional circuits, this circuit can effectively prolong the battery life of the device.

[0042] In the field of wearable devices, TWS earphones and smartwatches are extremely sensitive to power consumption, especially in small current charging (less than 50 mA) or sleep mode. Through precise average current comparison, the system can achieve low static current while avoiding the "blind area effect" commonly seen in traditional PSM mode, effectively preventing system reset caused by output voltage drop.

[0043] For high-performance computing and communication devices, the circuit provides excellent dynamic response capability. In FPGA and ASIC power supply applications, in the face of dynamic voltage frequency adjustment (DVFS) scenarios, the system can complete mode switching according to real-time load current, ensure stable power supply of computing chips in different working states, and optimize overall energy efficiency performance.

[0044] In Internet of Things devices, the circuit solves the pain points of traditional solutions. Various sensor nodes and low-power MCU systems usually work in intermittent working mode, and the load current changes dramatically. Through configurable thresholds and intelligent switching algorithms, the system can accurately identify load state changes, maximize energy efficiency while maintaining stable power supply, which is particularly important for battery-powered Internet of Things terminals.

[0045] Automotive electronic systems can also benefit from the circuit. In vehicle infotainment systems and ADAS modules, the power management system needs to cope with complex load changes. The anti-interference characteristics and high-precision current comparison capability of this circuit enable it to effectively distinguish between real load changes and electrical noise, ensuring reliable power supply for critical systems while meeting the stringent requirements of automotive power management.

[0046] In industrial automation equipment, the circuit shows strong adaptability. PLC controllers and industrial sensors often work in harsh electrical environments, and traditional power supply solutions are prone to interference. The integral average comparison method and programmable threshold characteristics used by this circuit make it have excellent anti-interference ability and can work stably in complex electromagnetic environments in industrial sites.

[0047] Data center and server power management are also important application fields of the circuit. In the face of rapid changes in server load, the circuit can achieve accurate load current monitoring and fast mode switching, optimizing overall energy efficiency while ensuring power supply quality, providing an effective energy-saving solution for large-scale power consumption in data centers.

[0048] In medical electronic devices, the circuit meets special power supply requirements. For portable medical monitoring devices, both high accuracy of measurement and maximum battery life are required. The low-noise characteristics and precise current management capabilities of the circuit make it an ideal choice for such applications, ensuring system accuracy while achieving optimal energy efficiency.

[0049] In the fast charging scheme of consumer electronics products, the circuit accurately identifies the load current and adjusts the dynamic mode, allowing the charger to intelligently switch between different charging stages, ensuring fast charging performance and optimizing efficiency performance during light load, providing technical support for the development of the next generation of fast charging technology.

[0050] Obviously, the above embodiments are only some but not all of the embodiments of the present application, and the technical solutions of various embodiments can be combined with each other without conflict and contradiction. In addition, if the terms such as "first", "second", "third" and the like appear in the embodiments, they are used only for the convenience of distinguishing relevant features, and should not be understood as indicating or implying relative importance, order or number of technical features.

[0051] Although the embodiments of the present application have been shown and described, it should be understood by those skilled in the art that various changes, modifications, substitutions and variations can be made to the embodiments without departing from the principles and spirit of the present application, and the scope of the present application is defined by the appended claims and their equivalents. The above description is only for the preferred embodiments of the present application and is not intended to limit the present application, and the present application can have various modifications and changes for those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A mode switching logic circuit, comprising a current sampling and scaling module, an average current comparison module, and a sample-and-hold module, characterized in that: The current sampling and scaling module is used to sample the sensed current of the external current sensor, and output the current to the average current comparison module after scaling. The average current comparison module is used to integrate and compare the current output by the current sampling and scaling module with the reference current, and then output the result to the sample-and-hold module. The sample-and-hold module is used to buffer and sample-and hold the integral comparison result of the average current comparison module before outputting it to an external circuit to control mode switching.

2. The mode switching logic circuit according to claim 1, characterized in that, The current sampling and scaling module includes: The equivalent resistance of the resistor DAC unit can be dynamically adjusted. The sampling capacitor has one end connected to the Up terminal of the resistor DAC unit, and the other end connected to the external current input terminal and the Dn terminal of the resistor DAC unit through the first switch. The sampling resistor has one end connected to the Up terminal of the resistor DAC unit, and the other end connected to the non-inverting input terminal of the error amplifier and the drain of the first MOSFET. The error amplifier has its Dn terminal connected to the inverting input terminal of the error amplifier via a first switch, and its output terminal connected to the gate of the first MOS transistor. The first MOSFET is an NMOS transistor with its source grounded. The Up terminal serves as the high-side terminal of the resistor DAC unit and is used to connect to the power supply. The Sel terminal serves as the control terminal of the resistor DAC unit and is used to receive externally input control signals to dynamically adjust the equivalent resistance between the Up terminal and the Dn terminal. The Dn terminal serves as the low-side terminal of the resistor DAC unit and is used to connect to the sensing current output terminal of an external current sensor. Furthermore, the Dn terminal generates a corresponding sampling voltage based on the adjusted equivalent resistance between the Up terminal and the Dn terminal. The term "high-side" refers to the voltage at the Up terminal being higher than the voltage at the Dn terminal in the circuit containing the resistor DAC unit; the term "low-side" refers to the voltage at the Dn terminal being lower than the voltage at the Up terminal in the circuit containing the resistor DAC unit.

3. The mode switching logic circuit according to claim 2, characterized in that, The current sampling and scaling module is characterized in that it further includes: The first chopper unit is located between the first switch and the inverting input terminal of the error amplifier, and between the sampling resistor and the non-inverting input terminal of the error amplifier, and is used to exchange the input signal of the error amplifier to achieve input chopping.

4. The mode switching logic circuit according to claim 1, characterized in that, The current sampling and scaling module includes: The equivalent resistance of the resistor DAC unit can be dynamically adjusted. The sampling capacitor has one end connected to one end of the sampling resistor and the Up terminal of the resistor DAC unit, and the other end connected to the inverting input terminal of the error amplifier. The sampling resistor has one end connected to the externally input current and is connected to the inverting input of the error amplifier via the first switch. The resistor DAC unit has its Dn terminal connected to the non-inverting input of the error amplifier and the drain of the first MOS transistor, respectively. An error amplifier, the output of which is connected to the gate of the first MOS transistor; The first MOSFET is an NMOS transistor with its source grounded. The Up terminal serves as the high-side terminal of the resistor DAC unit and is used to connect to the power supply. The Sel terminal serves as the control terminal of the resistor DAC unit and is used to receive externally input control signals to dynamically adjust the equivalent resistance between the Up terminal and the Dn terminal. The Dn terminal serves as the low-side terminal of the resistor DAC unit and is used to connect to the sensing current output terminal of an external current sensor. Furthermore, the Dn terminal generates a corresponding sampling voltage based on the adjusted equivalent resistance between the Up terminal and the Dn terminal. The term "high-side" refers to the voltage at the Up terminal being higher than the voltage at the Dn terminal in the circuit containing the resistor DAC unit; the term "low-side" refers to the voltage at the Dn terminal being lower than the voltage at the Up terminal in the circuit containing the resistor DAC unit.

5. The mode switching logic circuit according to claim 4, characterized in that, Also includes: The first chopper unit is located between the first switch and the inverting input terminal of the error amplifier, and between the Dn terminal of the resistor DAC unit and the non-inverting input terminal of the error amplifier, and is used to exchange the input signal of the error amplifier to achieve input chopping.

6. The mode switching logic circuit according to any one of claims 2 to 5, characterized in that, The error amplifier includes: The eleventh MOSFET has its source grounded, its drain connected to the sources of the fourteenth and fifteenth MOSFETs, and its gate connected to the VB1 terminal. The twelfth MOSFET has its source grounded, its drain connected to the source of the sixteenth MOSFET, and its gate connected to the VB1 terminal. The thirteenth MOSFET has its source grounded, its drain connected to the source of the seventeenth MOSFET, and its gate connected to the VB1 terminal. The drain of the fourteenth MOSFET is connected to the source of the eighteenth MOSFET and the drain of the twentieth MOSFET, and its gate is connected to the Vip terminal. The drain of the fifteenth MOSFET is connected to the source of the nineteenth MOSFET and the drain of the twenty-first MOSFET, and its gate is connected to the Vin terminal. The drain of the sixteenth MOSFET is connected to the drain of the eighteenth MOSFET and the first switching terminal of the fifth switch, and its gate is connected to the VB2 terminal. The drain of the seventeenth MOSFET is connected to the second switching terminal of the fifth switch, and its gate is connected to the gate of the sixteenth MOSFET, which is connected to the VB2 terminal. The gate of the eighteenth MOSFET is connected to the gate of the nineteenth MOSFET, and its source is connected to the drain of the twentieth MOSFET. The gate of the nineteenth MOSFET is connected to the VB3 terminal, the source is connected to the drain of the twenty-first MOSFET, and the drain of the twenty-seventh MOSFET is connected to the drain of the seventeenth MOSFET, together serving as the output terminal of the error amplifier. The gate of the twentieth MOSFET is connected to the gate of the twentieth MOSFET and together they are connected to the fixed terminal of the fifth switch, while the source is connected to the power supply. The source of the twenty-first MOSFET is connected to the power supply. Among them, the eleventh, twelfth, thirteenth, fourteenth, fifteenth, sixteenth, and seventeenth MOSFETs are all NMOS transistors; the eighteenth, nineteenth, twentieth, and twenty-first MOSFETs are all PMOS transistors. The VB1, VB2, and VB3 terminals are all connected to an external bias circuit to ensure the normal operation of the connected MOS transistors. The Vip terminal serves as the non-inverting input of the error amplifier, the Vin terminal serves as the inverting input of the error amplifier, and the Vout terminal serves as the output of the error amplifier. The fifth switch is a single-pole double-throw switch. An external controller can control the first switching terminal to connect with the fixed terminal or control the second switching terminal to connect with the fixed terminal, so as to reduce the offset voltage of the input error amplifier by chopping.

7. The mode switching logic circuit according to claim 6, characterized in that, The resistor DAC unit includes: N-stage resistor sub-units are connected in parallel between the Up terminal and the Dn terminal, and the resistor sub-units are also connected to the Sel terminal of the resistor DAC unit. The number of resistor subunits varies in each stage, starting with one in the first stage and doubling each time, with the last stage having a maximum of [number missing]. N is the number of bits that the resistor DAC unit can process; The resistor sub-unit is a Zux sub-unit or a Zuy sub-unit. The first and second stage resistor sub-units use Zux sub-units, and the third stage and subsequent stage resistor sub-units use Zuy sub-units, thus forming a resistor array composed of Zux sub-units and Zuy sub-units.

8. The mode switching logic circuit according to claim 7, characterized in that: The Zux subunit includes two parallel switching resistor branches, each of which includes two X switches and two X resistors connected in series. The first end of the switch resistor branch is connected to the Up terminal, the second end is connected to the Dn terminal, and the control terminal of the X switch is connected to the Sel terminal. Wherein, the first end of the switch resistor branch is the end where the X switch is located, and the second end is the end where the X resistor is located. The switch resistor branch starts from the first end, passes through two X switches and two X resistors in sequence, and then reaches the second end. The Zuy subunit includes a Y switch and a Y resistor. One end of the Y switch is connected to the Up terminal, and the other end is connected to the Dn terminal through the Y resistor. The control terminal of the Y switch is connected to the Sel terminal. Among them, the X resistor in the Zux sub-unit and the Y resistor in the Zuy sub-unit are resistors of the same type, size and resistance value, and each Zux sub-unit and each Zuy sub-unit have the same equivalent resistance value.

9. The mode switching logic circuit according to claim 8, characterized in that: The value of N is 7; The first-stage resistor subunit is one Zux subunit; The second-stage resistor subunit consists of two parallel Zux subunits; The third-stage resistor subunit consists of four parallel Zuy subunits; The fourth stage resistor subunit consists of eight parallel Zuy subunits; The fifth stage resistor subunit consists of 16 parallel Zuy subunits; The sixth stage's resistor subunit consists of 32 parallel Zuy subunits; The seventh stage's resistor subunit consists of 64 parallel Zuy subunits; The minimum adjustable resolution of the equivalent resistance of the resistor DAC unit is one-one-one-twenty-seventh of the equivalent resistance of each Zux subunit, or one-one-one-twenty-seventh of the equivalent resistance of each Zuy subunit.

10. The mode switching logic circuit according to any one of claims 1 to 5, characterized in that, The average current comparison module includes: The first current source has its input terminal connected to the power supply, its output terminal connected to the sample and hold module, its output terminal also grounded through an integrating capacitor, and connected to the second MOSFET through a second switch; The second switch is a single-pole double-throw switch, the second MOSFET is an NMOS transistor, the first switching terminal of the second switch is directly connected to the power supply, the second switching terminal is directly connected to the output terminal of the first current source, and the fixed terminal is connected to the drain of the second MOSFET. By controlling the second switch to switch, the first switching terminal and the fixed terminal can be connected, or the second switching terminal and the fixed terminal can be connected. The gate of the second MOSFET is connected to the gate of the first MOSFET in the current sampling and scaling module, and the source of the second MOSFET is grounded.

11. The mode switching logic circuit according to claim 10, characterized in that: A second chopper unit is provided between the current sampling and scaling module and the average current comparison module. The second chopper unit is located between the sampling resistor in the current sampling and scaling module and the drain of the first MOS transistor, and between the fixed terminal of the second switch in the average current comparison module and the drain of the second MOS transistor, so that the second MOS transistor can mirror the sampling current in the current sampling and scaling module.

12. The mode switching logic circuit according to any one of claims 1 to 5, characterized in that, The sample-and-hold module includes: The third MOS transistor is an NMOS transistor, with its drain connected to the power supply and its gate connected to the output terminal of the first current source in the average current comparison module. The second current source has its input terminal connected to the source of the third MOSFET and its output terminal grounded. The first sample-and-hold capacitor has one end connected to the source of the third MOSFET via the third switch, and the other end grounded. The second sample-and-hold capacitor has one end connected to the gate of the fourth MOSFET and then connected to the source of the third MOSFET through the fourth and third switches in sequence, while the other end is grounded. The fourth MOS transistor is an NMOS transistor with its source grounded and its drain serving as the output of the mode switching logic circuit. The third current source has its input connected to the power supply and its output connected to the drain of the fourth MOSFET.

13. A DC-DC conversion system, comprising the mode switching logic circuit according to any one of claims 1 to 12, characterized in that, Also includes: DC-DC topology circuits are used to step down or step up the input voltage to form the output voltage; A current sensor, connected to a DC-DC topology circuit, is used to detect the inductor current in the DC-DC topology circuit; The PWM controller has its input connected to a current sensor and its output connected to the first input of a 2-to-1 multiplexer. The PFM controller has its input terminal connected to the current sensor and its output terminal connected to the second input terminal of a 2-to-1 multiplexer. The mode switching logic circuit has its input connected to a current sensor and its output connected to the selection control terminal of a 2-to-1 multiplexer. A 2-to-1 multiplexer whose output is connected to a drive logic circuit is used to select the output of the PWM controller or the output of the PFM controller according to the control signal of the mode switching logic circuit. The driving logic circuit generates a power transistor control signal based on the signal output from the 2-to-1 multiplexer and the zero-crossing signal. The driver drives the power transistors in the DC-DC topology circuit according to the power transistor control signals output by the driver logic circuit.

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