Data receiving method, data sending method and data exchange device

Abstract

This application provides a data receiving method, a data transmitting method, and a data exchanging apparatus. The data receiving method includes: in response to a reference clock changing from a first preset frequency to a second preset frequency, changing the frequency of a second clock signal, wherein the frequency of the second clock signal and the frequency of the reference clock satisfy a preset relationship; performing delay processing or advance processing on the second clock signal according to the second preset frequency to obtain a third clock signal; receiving a serial data stream according to the third clock signal, wherein the serial data stream has a data transmission delay of a first preset duration; wherein the frequency of the third clock signal is equal to the frequency of the first clock signal, and the phase difference between the third clock signal and the first clock signal is equal to the first preset duration. This application can ensure the accuracy of serial data stream transmission after changing the frequency of the reference clock.

Description

Technical Field

[0001] This application relates to the field of data transmission technology, specifically to a data receiving method, a data sending method, and a data exchange device. Background Technology

[0002] Currently, data exchange is the most fundamental advantage and development direction of modern digital devices. Being able to send data streams at higher frequencies and in more formats, or to receive data streams at higher frequencies and in more formats, means having stronger data interaction capabilities, better compatibility and scalability, and being able to more easily meet users' application needs.

[0003] However, in related technologies, once the data exchange device is designed, its circuit can only operate at a set operating frequency. If the actual operating frequency exceeds the upper limit of the set operating frequency, the expected function of the digital circuit cannot be guaranteed to be correctly realized. The reason is that data transmission has a fixed line delay. Simply changing the data transmission frequency will cause a misalignment between the effective signal captured by the data processing module interface and the clock, which limits the flexibility of the data exchange device's data exchange capability. Summary of the Invention

[0004] This application provides a data receiving method, a data sending method, and a data exchange apparatus, aiming to solve the above-mentioned technical problems.

[0005] In a first aspect, this application provides a data receiving method for receiving a serial data stream from a data sender, wherein the data sender transmits the serial data stream based on a first clock signal, and the serial data stream is transmitted based on a reference clock. The data receiving method includes:

[0006] In response to the reference clock changing from a first preset frequency to a second preset frequency, the frequency of the second clock signal is changed, and the frequency of the second clock signal satisfies a preset relationship with the frequency of the reference clock.

[0007] According to the second preset frequency, the second clock signal is delayed or advanced to obtain the third clock signal;

[0008] A serial data stream is received according to a third clock signal, and the serial data stream has a data transmission delay of a first preset duration.

[0009] The frequency of the third clock signal is the same as that of the first clock signal, and the phase difference between the third clock signal and the first clock signal is equal to the first preset duration.

[0010] In some embodiments, the phase difference between the second clock signal and the first clock signal is equal to the first delay duration corresponding to a first preset number of reference clock cycles, and the phase difference between the third clock signal and the first clock signal is equal to the second delay duration corresponding to a second preset number of reference clock cycles.

[0011] When the frequency of the reference clock is the first preset frequency, the first delay duration is equal to the first preset duration; when the frequency of the reference clock is the second preset frequency, the first delay duration is not equal to the first preset duration, but the second delay duration is equal to the first preset duration.

[0012] In some embodiments, the second preset frequency is N times the first preset frequency, and the second preset quantity is N times the first preset quantity; or

[0013] The first preset frequency is N times the second preset frequency, and the first preset quantity is N times the second preset quantity.

[0014] In some embodiments, the second preset frequency is N times the first preset frequency. The step of delaying or advancing the second clock signal according to the second preset frequency to obtain the third clock signal includes:

[0015] According to the second preset frequency, the second clock signal is delayed by a first preset duration to obtain the third clock signal; or

[0016] According to the second preset frequency, the second clock signal is advanced by a second preset time to obtain the third clock signal.

[0017] In some embodiments, N times the first set duration is equal to N-1 times the first preset duration.

[0018] In some embodiments, the first preset frequency is N times the second preset frequency, and the step of delaying or advancing the second clock signal according to the second preset frequency to obtain the third clock signal includes:

[0019] Based on the second preset frequency, the second clock signal is advanced by a third preset time to obtain the third clock signal; or

[0020] According to the second preset frequency, the second clock signal is delayed by a fourth preset duration to obtain the third clock signal.

[0021] In some embodiments, the third preset duration is equal to N-1 times the first preset duration.

[0022] Secondly, this application provides a data transmission method for transmitting a serial data stream to a data receiver, the data receiver receiving the serial data stream based on a second clock signal, the serial data stream being transmitted based on a reference clock, and the data transmission method comprising:

[0023] In response to the reference clock changing from a first preset frequency to a second preset frequency, the frequency of the first clock signal is changed, and the frequency of the first clock signal and the frequency of the reference clock satisfy a preset relationship.

[0024] According to the second preset frequency, the first clock signal is delayed or advanced to obtain the fourth clock signal;

[0025] A serial data stream is sent according to the fourth clock signal, and the serial data stream has a data transmission delay of a first preset duration.

[0026] The frequency of the fourth clock signal is the same as that of the second clock signal, and the phase difference between the fourth clock signal and the second clock signal is equal to the first preset duration.

[0027] In some embodiments, the phase difference between the first clock signal and the second clock signal is equal to the first lead time corresponding to a third preset number of reference clock cycles, and the phase difference between the fourth clock signal and the second clock signal is equal to the second lead time corresponding to a fourth preset number of reference clock cycles.

[0028] When the frequency of the reference clock is the first preset frequency, the first lead time is equal to the first preset time; when the frequency of the reference clock is the second preset frequency, the first lead time is not equal to the first preset time, but the second lead time is equal to the first preset time.

[0029] In some embodiments, the second preset frequency is N times the first preset frequency, and the fourth preset quantity is N times the third preset quantity; or

[0030] The first preset frequency is N times the second preset frequency, and the third preset quantity is N times the fourth preset quantity.

[0031] In some embodiments, the second preset frequency is N times the first preset frequency. The step of delaying or advancing the first clock signal according to the second preset frequency to obtain the fourth clock signal includes:

[0032] Based on the second preset frequency, the first clock signal is advanced by a fifth preset time to obtain the fourth clock signal; or

[0033] According to the second preset frequency, the first clock signal is delayed by a sixth preset time to obtain the fourth clock signal.

[0034] In some embodiments, N times the fifth preset duration is equal to N-1 times the first preset duration.

[0035] In some embodiments, the first preset frequency is N times the second preset frequency, and the step of delaying or advancing the first clock signal according to the second preset frequency to obtain the fourth clock signal includes:

[0036] According to the second preset frequency, the first clock signal is delayed by a seventh preset time to obtain the fourth clock signal; or

[0037] According to the second preset frequency, the first clock signal is advanced by an eighth preset time to obtain the fourth clock signal.

[0038] In some embodiments, the seventh preset duration is equal to N-1 times the first preset duration.

[0039] Thirdly, this application provides a data exchange device, which includes a data sending module and / or a data receiving module;

[0040] The data sending module is used to execute the data receiving method as described in the first aspect, and the data receiving module is used to execute the data sending method as described in the second aspect.

[0041] This application, when the reference clock changes from a first preset frequency to a second preset frequency, modifies the frequency of the second clock signal used by the data receiver to receive data and delays it to obtain a third clock signal, or modifies the frequency of the first clock signal used by the data sender to transmit data and advances it to obtain a fourth clock signal. This allows the use of the third clock signal to receive a serial data stream or the use of the fourth clock signal to transmit a serial data stream. Since the serial data stream has a data transmission delay of a first preset duration, and the phase difference between the third clock signal and the first clock signal is equal to the first preset duration, and the phase difference between the fourth clock signal and the second clock signal is also equal to the first preset duration, the relative relationship between the valid serial data stream signal and the capture clock (the third clock signal or the second clock signal) can be guaranteed during data exchange, thereby improving the flexibility of the data exchange capability of the data exchange device. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a schematic diagram of a data transmission scenario in related technologies;

[0044] Figure 2 This is a schematic diagram of a data transmission signal after increasing the operating frequency in related technologies;

[0045] Figure 3 This is a flowchart illustrating a data receiving method provided in an embodiment of this application;

[0046] Figure 4 This is a schematic diagram of the data transmission signals before and after frequency change provided in the embodiments of this application;

[0047] Figure 5 This is another schematic diagram of the data transmission signals before and after frequency change provided in the embodiments of this application;

[0048] Figure 6 This is a schematic diagram of a signal change process provided in the embodiments of this application for changing the frequency;

[0049] Figure 7 This is another schematic diagram of signal change during the frequency change process provided in the embodiments of this application;

[0050] Figure 8 This is another schematic diagram of signal change during the frequency change process provided in the embodiments of this application;

[0051] Figure 9 This is another schematic diagram of signal change during the frequency change process provided in the embodiments of this application;

[0052] Figure 10 This is a flowchart illustrating a data transmission method provided in an embodiment of this application;

[0053] Figure 11 This is another schematic diagram of the data transmission signals before and after frequency change provided in the embodiments of this application;

[0054] Figure 12 This is another schematic diagram of the data transmission signals before and after frequency change provided in the embodiments of this application;

[0055] Figure 13 This is another schematic diagram of signal change during the frequency change process provided in the embodiments of this application;

[0056] Figure 14 This is another schematic diagram of signal change during the frequency change process provided in the embodiments of this application;

[0057] Figure 15 This is another schematic diagram of signal change during the frequency change process provided in the embodiments of this application;

[0058] Figure 16 This is another schematic diagram of signal change in the frequency changing process provided in the embodiments of this application.

[0059] Among them, the reference clock is CLK0, the first clock signal is CLK1, the second clock signal is CLK2, the third clock signal is CLK3, and the fourth clock signal is CLK4. Detailed Implementation

[0060] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0061] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0062] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use the invention. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that the invention can be made without using these specific details. In other instances, well-known structures and processes will not be described in detail to avoid obscuring the description of the invention with unnecessary detail. Therefore, the invention is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0063] Currently, data exchange is the most fundamental advantage and development direction of modern digital devices. (See also...) Figure 1 , Figure 1The diagram illustrates a data transmission scenario in related technologies. In this scenario, a data transmission module sends a serial data stream based on a reference clock signal CLKL to a data receiving module according to a transmission clock signal CLKA. The data receiving module receives the serial data stream according to a reception clock signal CLKB. The reception clock signal CLKB has the same frequency as the transmission clock signal CLKA, and the frequency of the reference clock signal CLKL is a preset multiple of the transmission clock signal CLKA. For example, when the frequencies of the reception clock signal CLKB and the transmission clock signal CLKA are 48kHz, and each data segment corresponds to 32 bytes, the frequency of the reference clock signal CLKL is 1.546mHz. Alternatively, when the frequencies of the reception clock signal CLKB and the transmission clock signal CLKA are 24kHz, and each data segment corresponds to 32 bytes, the frequency of the reference clock signal CLKL is 768kHz. It can be seen that a higher frequency of the reference clock signal CLKL enhances the data exchange capability of the data switching device.

[0064] However, once the data exchange device is designed, its circuitry can only operate at a set operating frequency. If the actual operating frequency exceeds the set upper limit, a misalignment may occur between the valid signal captured by the data processing module interface and the clock signal. For example, see [reference needed]. Figure 2 , Figure 2 The diagram illustrates a data transmission signal after increasing the operating frequency in related technologies. Before the frequency of the reference clock signal CLKL is changed, the line delay time corresponding to the data transmission is one cycle of the reference clock signal CLKL. Therefore, by setting the phase difference between the received clock signal CLKB and the transmitted clock signal CLKA to one cycle of the reference clock signal CLKL, the synchronization of data transmission and data reception can be guaranteed.

[0065] When the frequency of the reference clock signal CLKL is doubled, the line delay for data transmission remains fixed. Therefore, the line delay is now two cycles of the doubled CLKL frequency. However, after the data exchange device is designed, the phase difference between the receiving clock signal CLKB and the transmitting clock signal CLKA is fixed at one cycle of the reference clock signal CLKL. This means that even after changing the frequency of the reference clock signal CLKL, the phase difference between the receiving clock signal CLKB and the transmitting clock signal CLKA remains one cycle. Consequently, the actual line delay for data transmission is twice the phase difference between the receiving clock signal CLKB and the transmitting clock signal CLKA, leading to transmission errors. For example, for the data B "B0B1...BN" output by the data transmitting module, the data receiving module actually captures "ANB0...BN-1", meaning the captured data includes the most significant / least significant bit of the previous data.

[0066] It can be seen that the fixed line delay in the data transmission process limits the flexibility of the data exchange capability of the data exchange device. Therefore, embodiments of this application provide a data receiving method, a data sending method, and a data exchange device, which will be described in detail below.

[0067] First, refer to Figure 3 , Figure 3 This illustration shows a flowchart of a data receiving method according to an embodiment of this application. The data receiving method is used to receive a serial data stream from a data sender. The data sender transmits the serial data stream based on a first clock signal CLK1, and the serial data stream is transmitted based on a reference clock CLK0. The data receiving method includes:

[0068] Step S301: In response to the reference clock CLK0 changing from a first preset frequency to a second preset frequency, the frequency of the second clock signal CLK2 is changed, and the frequency of the second clock signal CLK2 and the frequency of the reference clock CLK0 satisfy a preset relationship.

[0069] Specifically, the reference clock CLK0 is the base clock for the data sender to transmit the serial data stream. The data sender can be, but is not limited to, a host computer, memory, processor, or other device, chip, or circuit with data transmission capabilities. After the reference clock CLK0 is changed from a first preset frequency to a second preset frequency, the data receiver can change the frequency of the second clock signal CLK2 so that the frequency of the second clock signal CLK2 satisfies a preset relationship with the frequency of the reference clock CLK0. For example, taking a serial data stream where each data item is 32 bytes long, after the reference clock CLK0 frequency changes from 768kHz to 1.546mHz, the frequency of the second clock signal CLK2 changes from 24kHz to 48kHz. That is, the preset relationship is that the frequency of the reference clock CLK0 is 32 times the frequency of the second clock signal CLK2. As another example, taking a serial data stream where each data item is 16 bytes long, after the reference clock CLK0 frequency changes from 768kHz to 384kHz, the frequency of the second clock signal CLK2 changes from 48kHz to 24kHz. That is, the preset relationship is that the frequency of the reference clock CLK0 is 16 times the frequency of the second clock signal CLK2.

[0070] In some embodiments of this application, the second clock signal CLK2 and the reference clock CLK0 can be clock signals from the same source, that is, the second clock signal CLK2 and the reference clock CLK0 are generated based on the clock signal output from the same clock source (e.g., a crystal oscillator). Therefore, changing the frequency of the clock signal output from the clock source will synchronously change the frequency of the reference clock CLK0 and the frequency of the second clock signal CLK2. In some embodiments of this application, the second clock signal CLK2 and the reference clock CLK0 can also be clock signals from different sources, that is, the reference clock CLK0 is generated based on one clock source, while the second clock signal CLK2 is generated based on another clock source. By controlling the oscillation frequencies of these two clock sources, the frequencies of the reference clock CLK0 and the second clock signal CLK2 can be changed.

[0071] Step S302: According to the second preset frequency, the second clock signal CLK2 is delayed or advanced to obtain the third clock signal CLK3;

[0072] After changing the frequency of the second clock signal CLK2, it can be delayed or advanced according to the second preset frequency to obtain the third clock signal CLK3. In some embodiments of this application, when the frequency of the reference clock CLK0 increases, the frequency of the second clock signal CLK2 increases accordingly. In this case, the second clock signal CLK2 can be delayed to obtain the third clock signal CLK3. In other embodiments of this application, when the frequency of the reference clock CLK0 decreases, the frequency of the second clock signal CLK2 decreases accordingly. In this case, the second clock signal CLK2 can be advanced to obtain the third clock signal CLK3.

[0073] For example, the second clock signal CLK2 can be processed by a delay circuit such as an offset register to obtain the third clock signal CLK3.

[0074] It should be noted that the delay processing referred to in this application refers to delaying the rising edge and falling edge of the clock signal by a corresponding period of time. For example, the second clock signal CLK2 triggers the Nth rising edge at time t1. After delay processing of the second clock signal CLK2, the third clock signal CLK3 triggers the Nth rising edge at time t2, and time t2 is after time t1. Similarly, the advance processing referred to in this application refers to advancing the rising edge and falling edge of the clock signal by a corresponding period of time. For example, the second clock signal CLK2 triggers the Mth rising edge at time t3. After advance processing of the second clock signal CLK2, the third clock signal CLK3 triggers the Mth rising edge at time t4, and time t4 is before time t3.

[0075] Step S303: Receive a serial data stream according to the third clock signal CLK3. The serial data stream has a data transmission delay of a first preset duration.

[0076] After obtaining the third clock signal CLK3, the serial data stream can be received according to the third clock signal CLK3. Since the first clock signal CLK1 for transmitting data has the same frequency as the third clock signal CLK3 for receiving data, and the third clock signal CLK3 is processed by delay or advance processing, the phase difference between the third clock signal CLK3 and the first clock signal CLK1 can be made equal to the first preset duration corresponding to the data transmission delay of the serial data stream, thus ensuring the relative relationship between the effective signal of the serial data stream and the third clock signal CLK3.

[0077] As an example, see Figure 4 , Figure 4 The illustration shows a schematic diagram of the data transmission signal before and after changing the frequency in an embodiment of this application. When the frequency of the reference clock CLK0 is the first set frequency, the first preset duration corresponding to the serial data stream data transmission delay is the duration corresponding to one cycle of the reference clock CLK0 at the first set frequency. The phase difference between the second clock signal CLK2 and the first clock signal CLK1 is also the duration corresponding to one cycle of the reference clock CLK0. Therefore, the phase difference between the second clock signal CLK2 and the first clock signal CLK1 is equal to the first preset duration, thereby ensuring the accuracy of data transmission. After doubling the frequency of the reference clock CLK0 to a second preset frequency, the first preset duration corresponding to the serial data stream data transmission delay is the duration corresponding to two cycles of the reference clock CLK0 at the second preset frequency. The phase difference between the second clock signal CLK2 and the first clock signal CLK1 is the duration corresponding to one cycle of the reference clock CLK0 at the second preset frequency. After delaying the second clock signal CLK2 to obtain the third clock signal CLK3, the phase difference between the third clock signal CLK3 and the first clock signal CLK1 is the duration corresponding to two cycles of the reference clock CLK0 at the second preset frequency. That is, when the frequency of the reference clock CLK0 is the second preset frequency, the phase difference between the third clock signal CLK3 and the first clock signal CLK1 is equal to the first preset duration, thereby ensuring the accuracy of data transmission even after doubling the frequency of the reference clock CLK0.

[0078] As another example, see Figure 5 , Figure 5This illustration shows another schematic diagram of the data transmission signal before and after changing the frequency in an embodiment of this application. When the frequency of the reference clock CLK0 is the first set frequency, the first preset duration corresponding to the serial data stream data transmission delay is the duration corresponding to one cycle of the reference clock CLK0 at the first set frequency. The phase difference between the second clock signal CLK2 and the first clock signal CLK1 is also the duration corresponding to one cycle of the reference clock CLK0 at the first set frequency. Therefore, the phase difference between the second clock signal CLK2 and the first clock signal CLK1 is equal to the first preset duration, thereby ensuring the accuracy of data transmission. After doubling the frequency of the reference clock CLK0 to a second preset frequency, the first preset duration corresponding to the serial data stream data transmission delay is the duration corresponding to two cycles of the reference clock CLK0 at the second preset frequency. The phase difference between the second clock signal CLK2 and the first clock signal CLK1 is also the duration corresponding to one cycle of the reference clock CLK0 at the second preset frequency. After processing the second clock signal CLK2 in advance to obtain the third clock signal CLK3, the phase difference between the third clock signal CLK3 and the first clock signal CLK1 is also the duration corresponding to two cycles of the reference clock CLK0 at the second preset frequency. That is, when the frequency of the reference clock CLK0 is the second preset frequency, the phase difference between the third clock signal CLK3 and the first clock signal CLK1 is equal to the first preset duration, thereby achieving the goal of ensuring data transmission accuracy after doubling the frequency of the reference clock CLK0.

[0079] This application, when the reference clock CLK0 changes from a first preset frequency to a second preset frequency, modifies the frequency of the second clock signal CLK2 used by the data receiver to receive data and performs a delay processing to obtain a third clock signal CLK3, thereby enabling the reception of the serial data stream using the third clock signal CLK3. Since the serial data stream has a data transmission delay of a first preset duration, and the phase difference between the third clock signal CLK3 and the first clock signal CLK1 is equal to the first preset duration, the relative relationship between the valid serial data stream signal and the third clock signal CLK3 can be guaranteed during data exchange. In other words, even if the frequency of the reference clock CLK0 is changed, the accuracy of data transmission can be guaranteed, thus improving the flexibility of the data exchange capability of the data exchange device.

[0080] In some embodiments of this application, the phase difference between the second clock signal CLK2 and the first clock signal CLK1 is equal to the first delay duration corresponding to a first preset number of reference clock CLK0 cycles, and the phase difference between the third clock signal CLK3 and the first clock signal CLK1 is equal to the second delay duration corresponding to a second preset number of reference clock CLK0 cycles. The first delay duration and the second delay duration change with the frequency of the reference clock CLK0. For example, see [reference]. Figure 4 or Figure 5The first delay duration is the duration corresponding to one reference clock CLK0 cycle, and the second delay duration is the duration corresponding to two reference clock CLK0 cycles. When the frequency of the reference clock CLK0 changes, the period of the reference clock CLK0 changes accordingly, thereby causing the first delay duration and the second delay duration to change accordingly.

[0081] Therefore, when the frequency of the reference clock CLK0 is the first preset frequency, the first delay duration is equal to the first preset duration. This means that the phase difference between the second clock signal CLK2 and the first clock signal CLK1 before the frequency change is equal to the first preset duration, ensuring accuracy when receiving data when the reference clock CLK0's frequency is the first preset frequency. However, when the frequency of the reference clock CLK0 is the second preset frequency, the period of the reference clock CLK0 changes accordingly. The first delay duration is no longer equal to the first preset duration, but the second delay duration is equal to the first preset duration. This means that the phase difference between the third clock signal CLK3 and the first clock signal CLK1 after the frequency change is also equal to the first preset duration, thus ensuring accuracy when receiving data when the reference clock CLK0's frequency is the second preset frequency.

[0082] In some embodiments of this application, the second preset frequency is N times the first preset frequency, and the second preset quantity is N times the first preset quantity. For example, see [reference needed]. Figure 4 or Figure 5 The second preset frequency is twice the first preset frequency. The phase difference between the third clock signal CLK3 and the first clock signal CLK1 is the duration corresponding to two cycles of the reference clock CLK0 at the second preset frequency. The phase difference between the second clock signal CLK2 and the first clock signal CLK1 is the duration corresponding to one cycle of the reference clock CLK0. That is, the second preset quantity is twice the first preset quantity.

[0083] In some embodiments of this application, such as an embodiment where the second preset frequency is N times the first preset frequency, the step of delaying or advancing the second clock signal CLK2 to obtain the third clock signal CLK3 according to the second preset frequency includes: delaying the second clock signal CLK2 for a first set duration according to the second preset frequency to obtain the third clock signal CLK3.

[0084] As an example, see Figure 6 , Figure 6This illustration shows a signal change diagram of a frequency change process in an embodiment of this application. Before the reference clock CLK0 changes frequency, the first preset duration corresponding to the serial data stream data transmission delay is the duration corresponding to one cycle of the reference clock CLK0 at the first set frequency, and the phase difference between the second clock signal CLK2 and the first clock signal CLK1 is the duration corresponding to one cycle of the reference clock CLK0. After the frequency of the reference clock CLK0 is doubled, the phase difference between the second clock signal CLK2 and the first clock signal CLK1 is still the duration corresponding to one cycle of the reference clock CLK0. After delaying the second clock signal CLK2 by the duration corresponding to one cycle of the reference clock CLK0 at the second set frequency (i.e., the first preset duration), the phase difference between the obtained third clock signal CLK3 and the first clock signal CLK1 is the duration corresponding to two cycles of the reference clock CLK0 at the second set frequency, ultimately making the phase difference between the third clock signal CLK3 and the first clock signal CLK1 equal to the first preset duration.

[0085] In other embodiments of this application, for example, for an embodiment where the second preset frequency is N times the first preset frequency, the step of delaying or advancing the second clock signal CLK2 to obtain the third clock signal CLK3 according to the second preset frequency includes: advancing the second clock signal CLK2 by a second preset duration according to the second preset frequency to obtain the third clock signal CLK3, wherein the sum of the first preset duration and the second preset duration is equal to an integer multiple of the period of the third clock signal CLK3.

[0086] As an example, see Figure 7 , Figure 7 This illustration shows another signal change diagram of the frequency changing process in an embodiment of this application. Before the reference clock CLK0 changes frequency, the first preset duration corresponding to the serial data stream data transmission delay is the duration corresponding to one cycle of the reference clock CLK0 at the first set frequency. The phase difference between the second clock signal CLK2 and the first clock signal CLK1 is the duration corresponding to one cycle of the reference clock CLK0. After the frequency of the reference clock CLK0 is doubled, the phase difference between the second clock signal CLK2 and the first clock signal CLK1 is still the duration corresponding to one cycle of the reference clock CLK0. After the second clock signal CLK2 is preprocessed for a second preset duration, since the sum of the first preset duration and the second preset duration is equal to one cycle of the third clock signal CLK3, the phase difference between the obtained third clock signal CLK3 and the first clock signal CLK1 is the duration corresponding to two cycles of the reference clock CLK0 at the second set frequency. Finally, the phase difference between the third clock signal CLK3 and the first clock signal CLK1 is equal to the first preset duration.

[0087] In some embodiments of this application, such as an embodiment where the second preset frequency is N times the first preset frequency, N times the first preset duration is equal to N-1 times the first preset duration. For example, see [reference needed]. Figure 6 The second preset frequency is twice the first preset frequency, the first preset duration is the duration of one cycle of the reference clock CLK0 at the second preset frequency, and the first preset duration is the duration of two cycles of the reference clock CLK0 at the second preset frequency, that is, 2 times the first preset duration is equal to 1 times the first preset duration.

[0088] Understandably, when the second preset frequency is three times the first preset frequency, then three times the first preset duration is equal to two times the first preset duration; when the second preset frequency is four times the first preset frequency, then four times the first preset duration is equal to three times the first preset duration, and so on. This will not be elaborated further here.

[0089] It should be noted that the above embodiments are merely illustrative; in this application, N can be an integer or a non-integer, and this application does not impose any specific limitations. Meanwhile, Figure 6 The first set duration is less than one cycle of the third clock signal CLK3, but it is not limited to this. For example, the first set duration can also be set to the duration corresponding to the sum of one cycle of the third clock signal CLK3 and one cycle of the reference clock CLK0; or, for another example, the first set duration can also be set to the duration corresponding to the sum of two cycles of the third clock signal CLK3 and one cycle of the reference clock CLK0.

[0090] In some embodiments of this application, the first preset frequency is N times the second preset frequency, and the first preset quantity is N times the second preset quantity. That is, the frequency of the reference clock CLK0 can also be reduced, and the phase difference between the third clock signal CLK3 and the first clock signal CLK1 can be reduced according to the reduction factor, which can ultimately ensure the accuracy of data transmission when changing the frequency.

[0091] In some embodiments of this application, such as an embodiment where the first preset frequency is N times the second preset frequency, the step of delaying or advancing the second clock signal CLK2 to obtain the third clock signal CLK3 according to the second preset frequency includes: advancing the second clock signal CLK2 by a third preset time according to the second preset frequency to obtain the third clock signal CLK3.

[0092] As an example, see Figure 8 , Figure 8This illustration shows another signal change diagram of the frequency changing process in an embodiment of this application. Before the reference clock CLK0 changes frequency, the first preset duration corresponding to the serial data stream data transmission delay is the duration corresponding to two cycles of the reference clock CLK0 at the first set frequency. The phase difference between the second clock signal CLK2 and the first clock signal CLK1 is the duration corresponding to two cycles of the reference clock CLK0. After the reference clock CLK0 frequency is halved, the phase difference between the second clock signal CLK2 and the first clock signal CLK1 is still the duration corresponding to two cycles of the reference clock CLK0. After the second clock signal CLK2 is preprocessed for a third preset duration, since the third preset duration is equal to the duration corresponding to one cycle of the reference clock CLK0 at the second set frequency, the phase difference between the third clock signal CLK3 and the first clock signal CLK1 can be made equal to the first preset duration, thus ensuring the accuracy of the serial data stream transmission.

[0093] In some embodiments of this application, such as an embodiment where the first preset frequency is N times the second preset frequency, the step of delaying or advancing the second clock signal CLK2 to obtain the third clock signal CLK3 according to the second preset frequency includes: delaying the second clock signal CLK2 for a fourth preset duration according to the second preset frequency to obtain the third clock signal CLK3; wherein the sum of the third preset duration and the fourth preset duration is equal to an integer multiple of the period of the third clock signal CLK3.

[0094] As an example, see Figure 9 , Figure 9 This illustration shows another signal change diagram of the frequency changing process in an embodiment of this application. Before the reference clock CLK0 changes frequency, the first preset duration corresponding to the serial data stream data transmission delay is the duration corresponding to two cycles of the reference clock CLK0 at the first set frequency. The phase difference between the second clock signal CLK2 and the first clock signal CLK1 is the duration corresponding to two cycles of the reference clock CLK0. After the reference clock CLK0 frequency is halved, the phase difference between the second clock signal CLK2 and the first clock signal CLK1 is still the duration corresponding to two cycles of the reference clock CLK0. After the second clock signal CLK2 is delayed for a fourth preset duration, since the sum of the third preset duration and the fourth preset duration is equal to one cycle of the third clock signal CLK3, the phase difference between the obtained third clock signal CLK3 and the first clock signal CLK1 is the duration corresponding to one cycle of the reference clock CLK0 at the second set frequency. This makes the phase difference between the third clock signal CLK3 and the first clock signal CLK1 equal to the first preset duration, and ultimately ensures the accuracy of the serial data stream transmission.

[0095] In some embodiments of this application, such as an embodiment where the first preset frequency is N times the second preset frequency, the third preset duration is equal to N-1 times the first preset duration. For example, see [reference needed]. Figure 8 The first preset frequency is twice the second preset frequency, and the third preset duration is the duration of one cycle of the reference clock CLK0 at the second preset frequency. The first preset duration is the duration of one cycle of the reference clock CLK0 at the second preset frequency, which means that the third preset duration is equal to 1 times the first preset duration.

[0096] Understandably, when the second preset frequency is 3 times the first preset frequency, the third preset duration is equal to 2 times the first preset duration; when the second preset frequency is 4 times the first preset frequency, the third preset duration is equal to 3 times the first preset duration, and so on. This will not be elaborated further here.

[0097] It should be noted that the aforementioned first, second, third, and fourth time settings can be pre-tested and then burned into the data receiver. As an example of the first set duration test process, the data sending module sends reference data to the data receiving module without delay. The receiving module compares the difference between the two sets of data by parsing and processing the result data without correction, and thus determines how many reference clock CLK0 cycles are misaligned. For example, if the serial data stream is sent with the most significant bit first, and the sent data are 32'h1111, 32'h22222, and 32'h333333, and the received data are 32'h444, 32'h8888, and 32'hccccc, then the first set duration can be determined to be the duration corresponding to two cycles of the reference clock CLK0 at that frequency. If the received data are 32'h484, 32'h8908, and 32'hccd8c, that is, the corresponding data are offset by 2 bits in some cases and 1 bit (or 3 bits) in others, then the first set duration can be determined to be the duration corresponding to 1.5 cycles of the reference clock CLK0 at that frequency. Meanwhile, it is understandable that when the data transmission delay between the data receiver and the data sender is uncertain, and the phase difference between the second clock signal CLK2 and the first clock signal CLK1 is not equal to the first preset duration, the above method can also be used to determine the first preset duration of the data transmission delay, and then the second clock signal CLK2 can be delayed or advanced so that the phase difference between the second clock signal CLK2 and the first clock signal CLK1 is equal to the first preset duration before the reference clock CLK0 changes from the first preset frequency to the second preset frequency.

[0098] Further, see Figure 10 , Figure 10This illustration shows a flowchart of a data transmission method according to an embodiment of this application. The data transmission method is used to send a serial data stream to a data receiver. The data receiver receives the serial data stream based on a second clock signal CLK2. The serial data stream is transmitted based on a reference clock CLK0. The data transmission method includes:

[0099] Step S1001: In response to the reference clock CLK0 changing from a first preset frequency to a second preset frequency, the frequency of the first clock signal CLK1 is changed, and the frequency of the first clock signal CLK1 and the frequency of the reference clock CLK0 satisfy a preset relationship.

[0100] Specifically, the data receiver can be, but is not limited to, a host computer, memory, processor, or other device, chip, or circuit with data receiving capabilities. After the reference clock CLK0 changes from a first preset frequency to a second preset frequency, the data sender can change the frequency of the first clock signal CLK1 so that the frequency of the first clock signal CLK1 satisfies a preset relationship with the frequency of the reference clock CLK0. For example, taking a serial data stream where each data item is 32 bytes long, after the reference clock CLK0 frequency changes from 768kHz to 1.546mHz, the frequency of the first clock signal CLK1 changes from 24kHz to 48kHz, meaning the preset relationship is that the frequency of the reference clock CLK0 is 32 times the frequency of the first clock signal CLK1. As another example, taking a serial data stream where each data item is 16 bytes long, after the reference clock CLK0 frequency changes from 768kHz to 384kHz, the frequency of the first clock signal CLK1 changes from 48kHz to 24kHz, meaning the preset relationship is that the frequency of the reference clock CLK0 is 16 times the frequency of the first clock signal CLK1.

[0101] In some embodiments of this application, the first clock signal CLK1 and the reference clock CLK0 can be clock signals from the same source, that is, the first clock signal CLK1 and the reference clock CLK0 are generated based on the clock signal output from the same clock source (e.g., a crystal oscillator). Therefore, changing the frequency of the clock signal output from the clock source will synchronously change the frequency of the reference clock CLK0 and the frequency of the first clock signal CLK1. In some embodiments of this application, the first clock signal CLK1 and the reference clock CLK0 can also be clock signals from different sources, that is, the reference clock CLK0 is generated based on one clock source, while the first clock signal CLK1 is generated based on another clock source. By controlling the oscillation frequencies of these two clock sources, the frequencies of the reference clock CLK0 and the first clock signal CLK1 can be changed.

[0102] Step S1002: According to the second preset frequency, the first clock signal CLK1 is delayed or advanced to obtain the fourth clock signal CLK4.

[0103] After changing the frequency of the first clock signal CLK1, it can be delayed or advanced according to the second preset frequency to obtain the fourth clock signal CLK4. In some embodiments of this application, when the frequency of the reference clock CLK0 increases, the frequency of the first clock signal CLK1 increases accordingly. In this case, the first clock signal CLK1 can be advanced to obtain the fourth clock signal CLK4. In other embodiments of this application, when the frequency of the reference clock CLK0 decreases, the frequency of the first clock signal CLK1 decreases accordingly. In this case, the first clock signal CLK1 can be delayed to obtain the fourth clock signal CLK4.

[0104] For example, the first clock signal CLK1 can be processed by a delay circuit such as an offset register to obtain the fourth clock signal CLK4.

[0105] Step S1003: A serial data stream is sent according to the fourth clock signal CLK4, and the serial data stream has a data transmission delay of a first preset duration;

[0106] After obtaining the fourth clock signal CLK4, a serial data stream can be sent according to the fourth clock signal CLK4. Since the frequency of the fourth clock signal CLK4 for sending data is equal to that of the second clock signal CLK2 for receiving data, and the fourth clock signal CLK4 is processed by delay or advance processing, the phase difference between the fourth clock signal CLK4 and the second clock signal CLK2 can be made equal to the first preset duration corresponding to the data transmission delay of the serial data stream, thus ensuring the relative relationship between the effective signal of the serial data stream and the second clock signal CLK2.

[0107] As an example, see Figure 11 , Figure 11This illustration shows another schematic diagram of the data transmission signal before and after changing the frequency in an embodiment of this application. When the frequency of the reference clock CLK0 is the first set frequency, the first preset duration corresponding to the serial data stream data transmission delay is the duration corresponding to one cycle of the reference clock CLK0 at the first set frequency. The phase difference between the second clock signal CLK2 and the first clock signal CLK1 is also the duration corresponding to one cycle of the reference clock CLK0. Therefore, the phase difference between the second clock signal CLK2 and the first clock signal CLK1 is equal to the first preset duration, thereby ensuring the accuracy of data transmission. After doubling the frequency of the reference clock CLK0 to a second preset frequency, the first preset duration corresponding to the serial data stream data transmission delay is the duration corresponding to two cycles of the reference clock CLK0 at the second preset frequency. The phase difference between the second clock signal CLK2 and the first clock signal CLK1 is still the duration corresponding to one cycle of the reference clock CLK0 at the second preset frequency. After preprocessing the first clock signal CLK1 to obtain the fourth clock signal CLK4, the phase difference between the fourth clock signal CLK4 and the second clock signal CLK2 is the duration corresponding to two cycles of the reference clock CLK0 at the second preset frequency. That is, when the frequency of the reference clock CLK0 is the second preset frequency, the phase difference between the fourth clock signal CLK4 and the second clock signal CLK2 is equal to the first preset duration, thereby ensuring the accuracy of data transmission even after doubling the frequency of the reference clock CLK0.

[0108] As another example, see Figure 12 , Figure 12This illustration shows another schematic diagram of the data transmission signal before and after changing the frequency in an embodiment of this application. When the frequency of the reference clock CLK0 is the first set frequency, the first preset duration corresponding to the serial data stream data transmission delay is the duration corresponding to one cycle of the reference clock CLK0 at the first set frequency. The phase difference between the second clock signal CLK2 and the first clock signal CLK1 is also the duration corresponding to one cycle of the reference clock CLK0 at the first set frequency. Therefore, the phase difference between the second clock signal CLK2 and the first clock signal CLK1 is equal to the first preset duration, thereby ensuring the accuracy of data transmission. After doubling the frequency of the reference clock CLK0 to a second preset frequency, the first preset duration corresponding to the serial data stream data transmission delay is the duration corresponding to two cycles of the reference clock CLK0 at the second preset frequency. The phase difference between the second clock signal CLK2 and the first clock signal CLK1 is also the duration corresponding to one cycle of the reference clock CLK0 at the second preset frequency. After delaying the second clock signal CLK2 to obtain the fourth clock signal CLK4, the phase difference between the fourth clock signal CLK4 and the first clock signal CLK1 is also the duration corresponding to two cycles of the reference clock CLK0 at the second preset frequency. That is, when the frequency of the reference clock CLK0 is the second preset frequency, the phase difference between the fourth clock signal CLK4 and the second clock signal CLK2 is equal to the first preset duration, thereby achieving the goal of ensuring data transmission accuracy after doubling the frequency of the reference clock CLK0.

[0109] This application, when the reference clock CLK0 changes from a first preset frequency to a second preset frequency, modifies the frequency of the first clock signal CLK1 used by the data sender to transmit data and preprocesses it to obtain a fourth clock signal CLK4, thereby enabling the transmission of a serial data stream using the fourth clock signal CLK4. Since the serial data stream has a data transmission delay of a first preset duration, the phase difference between the fourth clock signal CLK4 and the second clock signal CLK2 is equal to the first preset duration. Therefore, during data exchange, the relative relationship between the valid serial data stream signal and the second clock signal CLK2 can be guaranteed. In other words, even if the frequency of the reference clock CLK0 is changed, the accuracy of data transmission can be ensured, thus improving the flexibility of the data exchange capability of the data exchange device.

[0110] In some embodiments of this application, the phase difference between the first clock signal CLK1 and the second clock signal CLK2 is equal to a first lead time corresponding to a third preset number of reference clock CLK0 cycles, and the phase difference between the fourth clock signal CLK4 and the second clock signal CLK2 is equal to a second lead time corresponding to a fourth preset number of reference clock CLK0 cycles. The first lead time and the second lead time change with the frequency of the reference clock CLK0. For example, see [reference]. Figure 11 or Figure 12The first lead time is the duration corresponding to one reference clock CLK0 cycle, and the second lead time is the duration corresponding to two reference clock CLK0 cycles. When the frequency of the reference clock CLK0 changes, the period of the reference clock CLK0 changes accordingly, thereby causing the first lead time and the second lead time to change as well.

[0111] Therefore, when the frequency of the reference clock CLK0 is the first preset frequency, the first lead time is equal to the first preset time. This means that the phase difference between the second clock signal CLK2 and the first clock signal CLK1 before the frequency change is equal to the first preset time, ensuring accuracy when receiving data when the reference clock CLK0's frequency is the first preset frequency. However, when the frequency of the reference clock CLK0 is the second preset frequency, the period of the reference clock CLK0 changes accordingly. The first lead time is no longer equal to the first preset time, but the second lead time is equal to the first preset time. This means that the phase difference between the fourth clock signal CLK4 and the second clock signal CLK2 after the frequency change is also equal to the first preset time, thus ensuring accuracy when receiving data when the reference clock CLK0's frequency is the second preset frequency.

[0112] In some embodiments of this application, the second preset frequency is N times the first preset frequency, and the fourth preset quantity is N times the third preset quantity. For example, see [reference needed]. Figure 11 or Figure 12 The second preset frequency is twice the first preset frequency. The phase difference between the fourth clock signal CLK4 and the second clock signal CLK2 is the duration corresponding to two cycles of the reference clock CLK0 at the second preset frequency. The phase difference between the first clock signal CLK1 and the second clock signal CLK2 is the duration corresponding to one cycle of the reference clock CLK0. That is, the second preset quantity is twice the first preset quantity.

[0113] In some embodiments of this application, such as an embodiment where the second preset frequency is N times the first preset frequency, the step of delaying or advancing the first clock signal CLK1 to obtain the fourth clock signal CLK4 according to the second preset frequency includes: advancing the first clock signal CLK1 by a fifth preset time according to the second preset frequency to obtain the fourth clock signal CLK4.

[0114] As an example, see Figure 13 , Figure 13This illustration shows a signal change diagram of a frequency change process in an embodiment of this application. Before the reference clock CLK0 changes frequency, the first preset duration corresponding to the serial data stream data transmission delay is the duration corresponding to one cycle of the reference clock CLK0 at the first set frequency, and the phase difference between the second clock signal CLK2 and the first clock signal CLK1 is the duration corresponding to one cycle of the reference clock CLK0. After the frequency of the reference clock CLK0 is doubled, the phase difference between the second clock signal CLK2 and the first clock signal CLK1 is still the duration corresponding to one cycle of the reference clock CLK0. After the first clock signal CLK1 is preprocessed to the duration corresponding to one cycle of the reference clock CLK0 at the second set frequency (i.e., the fifth preset duration), the phase difference between the fourth clock signal CLK4 and the second clock signal CLK2 is the duration corresponding to two cycles of the reference clock CLK0 at the second set frequency, ultimately making the phase difference between the fourth clock signal CLK4 and the second clock signal CLK2 equal to the first preset duration.

[0115] In other embodiments of this application, such as an embodiment where the second preset frequency is N times the first preset frequency, the step of delaying or advancing the second clock signal CLK2 to obtain the fourth clock signal CLK4 according to the second preset frequency includes: delaying the first clock signal CLK1 by a sixth preset duration according to the second preset frequency to obtain the fourth clock signal CLK4; wherein the sum of the fifth preset duration and the sixth preset duration is equal to an integer multiple of the period of the fourth clock signal CLK4.

[0116] As an example, see Figure 14 , Figure 14 This illustration shows another signal change diagram of the frequency changing process in an embodiment of this application. Before the reference clock CLK0 changes frequency, the first preset duration corresponding to the serial data stream data transmission delay is the duration corresponding to one cycle of the reference clock CLK0 at the first set frequency. The phase difference between the second clock signal CLK2 and the first clock signal CLK1 is the duration corresponding to one cycle of the reference clock CLK0. After the frequency of the reference clock CLK0 is doubled, the phase difference between the second clock signal CLK2 and the first clock signal CLK1 is still the duration corresponding to one cycle of the reference clock CLK0. After the second clock signal CLK2 is delayed for a fifth preset duration, since the sum of the fifth preset duration and the sixth preset duration is equal to one cycle of the fourth clock signal CLK4, the phase difference between the fourth clock signal CLK4 and the second clock signal CLK2 is the duration corresponding to two cycles of the reference clock CLK0 at the second set frequency. Finally, the phase difference between the fourth clock signal CLK4 and the second clock signal CLK2 is equal to the first preset duration.

[0117] In some embodiments of this application, such as an embodiment where the second preset frequency is N times the first preset frequency, the N times fifth preset duration is equal to N-1 times the first preset duration. For example, see [reference needed]. Figure 13 The second preset frequency is twice the first preset frequency, the fifth preset duration is the duration corresponding to one cycle of the reference clock CLK0 at the second preset frequency, and the first preset duration is the duration corresponding to two cycles of the reference clock CLK0 at the second preset frequency, that is, 2 times the first preset duration is equal to 1 times the first preset duration.

[0118] Understandably, when the second preset frequency is three times the first preset frequency, then three times the fifth preset duration is equal to two times the first preset duration; when the second preset frequency is four times the first preset frequency, then four times the fifth preset duration is equal to three times the first preset duration, and so on. This will not be elaborated further here.

[0119] It should be noted that the above embodiments are merely illustrative; in this application, N can be an integer or a non-integer, and this application does not impose any specific limitations. Meanwhile, Figure 13 The fifth set duration is less than one cycle of the fourth clock signal CLK4, but it is not limited to this. For example, the fifth set duration can also be set to the duration corresponding to the sum of one cycle of the fourth clock signal CLK4 and one cycle of the reference clock CLK0; or, for another example, the fifth set duration can also be set to the duration corresponding to the sum of two cycles of the fourth clock signal CLK4 and one cycle of the reference clock CLK0.

[0120] In some embodiments of this application, the first preset frequency is N times the second preset frequency, and the third preset quantity is N times the fourth preset quantity. That is, the frequency of the reference clock CLK0 can also be reduced, and the phase difference between the fourth clock signal CLK4 and the second clock signal CLK2 can be increased according to the reduction factor, which can ultimately ensure the accuracy of data transmission when changing the frequency.

[0121] In some embodiments of this application, such as an embodiment where the first preset frequency is N times the second preset frequency, the step of delaying or advancing the first clock signal CLK1 to obtain the fourth clock signal CLK4 according to the second preset frequency includes: delaying the first clock signal CLK1 for a seventh set duration according to the second preset frequency to obtain the fourth clock signal CLK4.

[0122] As an example, see Figure 15 , Figure 15This illustration shows another signal change diagram of the frequency changing process in an embodiment of this application. Before the reference clock CLK0 changes frequency, the first preset duration corresponding to the serial data stream data transmission delay is the duration corresponding to two cycles of the reference clock CLK0 at the first set frequency. The phase difference between the second clock signal CLK2 and the first clock signal CLK1 is the duration corresponding to two cycles of the reference clock CLK0. After the frequency of the reference clock CLK0 is halved, the phase difference between the second clock signal CLK2 and the first clock signal CLK1 is still the duration corresponding to two cycles of the reference clock CLK0. After the delay processing of the first clock signal CLK1 for the seventh preset duration, since the seventh preset duration is equal to the duration corresponding to one cycle of the reference clock CLK0 at the second set frequency, the phase difference between the fourth clock signal CLK4 and the second clock signal CLK2 can be made equal to the first preset duration, thus ensuring the accuracy of the serial data stream transmission.

[0123] In some embodiments of this application, such as an embodiment where the first preset frequency is N times the second preset frequency, the step of delaying or advancing the second clock signal CLK2 to obtain the fourth clock signal CLK4 according to the second preset frequency includes: advancing the first clock signal CLK1 by an eighth preset duration according to the second preset frequency to obtain the fourth clock signal CLK4; wherein the sum of the seventh preset duration and the eighth preset duration is equal to an integer multiple of the period of the fourth clock signal CLK4.

[0124] As an example, see Figure 16 , Figure 16 This illustration shows another signal change diagram of the frequency changing process in an embodiment of this application. Before the reference clock CLK0 changes frequency, the first preset duration corresponding to the serial data stream data transmission delay is the duration corresponding to two cycles of the reference clock CLK0 at the first set frequency. The phase difference between the second clock signal CLK2 and the first clock signal CLK1 is the duration corresponding to two cycles of the reference clock CLK0. After the frequency of the reference clock CLK0 is halved, the phase difference between the second clock signal CLK2 and the first clock signal CLK1 is still the duration corresponding to two cycles of the reference clock CLK0. After the second clock signal CLK2 is preprocessed for a fourth preset duration, since the sum of the seventh preset duration and the eighth preset duration is equal to an integer multiple of the cycle of the fourth clock signal CLK4, the phase difference between the obtained fourth clock signal CLK4 and the first clock signal CLK1 is the duration corresponding to one cycle of the reference clock CLK0 at the second set frequency. This makes the phase difference between the fourth clock signal CLK4 and the second clock signal CLK2 equal to the first preset duration, and ultimately ensures the accuracy of the serial data stream transmission.

[0125] In some embodiments of this application, such as an embodiment where the first preset frequency is N times the second preset frequency, the seventh preset duration is equal to N-1 times the first preset duration. For example, see [reference needed]. Figure 15 The first preset frequency is twice the second preset frequency, and the seventh preset duration is the duration corresponding to one cycle of the reference clock CLK0 at the second preset frequency. The first preset duration is the duration corresponding to one cycle of the reference clock CLK0 at the second preset frequency, which satisfies the condition that the third preset duration is equal to 1 times the first preset duration.

[0126] Understandably, when the second preset frequency is 3 times the first preset frequency, the seventh preset duration is equal to 2 times the first preset duration; when the second preset frequency is 4 times the first preset frequency, the seventh preset duration is equal to 3 times the first preset duration, and so on. This will not be elaborated further here.

[0127] It should be noted that the aforementioned fifth, sixth, seventh, and eighth set durations can be pre-tested and then burned into the data sender receiving the data. As an example of the fifth set duration testing process, the data sending module sends reference data to the data receiving module without delay. The receiving module compares the difference between the processed data and the reference data to determine the number of reference clock cycles (CLK0) that are misaligned. For example, if the serial data stream is sent with the most significant bit first, and the sent data are 32'h1111, 32'h22222, and 32'h333333, and the resulting data are 32'h4444, 32'h88888, and 32'hcccccc, then the fifth set duration can be determined as the duration corresponding to two cycles of the reference clock (CLK0) at that frequency. If the obtained data are 32'h4844, 32'h89088, and 32'hccd8cc, respectively, meaning some data are offset by 2 bits and others by 1 bit (or 3 bits), then the fifth preset duration can be determined as the duration corresponding to 1.5 cycles of the reference clock CLK0 at that frequency. Simultaneously, it can be understood that when the data transmission delay between the data receiver and the data sender is uncertain, and the phase difference between the second clock signal CLK2 and the first clock signal CLK1 is not equal to the first preset duration, the above method can also be used to determine the first preset duration of the data transmission delay. Then, the first clock signal CLK1 can be delayed or advanced so that before the reference clock CLK0 changes from the first preset frequency to the second preset frequency, the phase difference between the second clock signal CLK2 and the first clock signal CLK1 is equal to the first preset duration.

[0128] Furthermore, to better implement the data receiving and data sending methods in the embodiments of this application, based on the data receiving and data sending methods, this application also provides a data exchange apparatus, which includes a data sending module and / or a data receiving module; wherein, the data sending module is used to execute the data receiving method as described in any of the above embodiments, and the data receiving module is used to execute the data sending method as described in any of the above embodiments. Since the data exchange apparatus in the embodiments of this application executes the data receiving and / or data sending methods of the above embodiments, it has all the beneficial effects of the above data receiving and / or data sending methods, which will not be repeated here.

[0129] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the detailed descriptions of other embodiments above, which will not be repeated here.

[0130] The basic concepts have been described above. Obviously, for those skilled in the art, the detailed disclosure above is merely illustrative and does not constitute a limitation of this application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this application, and therefore remain within the spirit and scope of the exemplary embodiments of this application.

[0131] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic associated with at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0132] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments of the invention, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the application requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0133] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used in the description of embodiments are modified in some examples with the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may be changed depending on the characteristics required by individual embodiments. In some embodiments, numerical parameters should take into account specified significant digits and employ a general method of digit reservation. Although the numerical ranges and parameters used to confirm their breadth of scope in some embodiments of this application are approximate values, in specific embodiments, such values ​​are set as precisely as feasible.

[0134] For each patent, patent application, patent application publication, and other material such as articles, books, specifications, publications, and documents referenced in this application, the entire contents of that patent application are incorporated herein by reference, except for historical application documents that are inconsistent with or conflict with the content of this application, and documents that limit the broadest scope of the claims of this application (currently or subsequently appended to this application). It should be noted that if there are any inconsistencies or conflicts between the descriptions, definitions, and / or terminology used in the supplementary materials of this application and the content of this application, the descriptions, definitions, and / or terminology used in this application shall prevail.

[0135] The data receiving method, data sending method, and data exchange device provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A data receiving method characterized by comprising: The data receiving method is used to receive a serial data stream from a data sender based on a second clock signal. The data sender transmits the serial data stream based on a first clock signal. The serial data stream is transmitted based on a reference clock. The serial data stream has a data transmission delay of a first preset duration. When the frequency of the reference clock is the first preset frequency, the phase difference between the second clock signal and the first clock signal is equal to the first preset duration. The data receiving method includes: In response to the reference clock changing from a first preset frequency to a second preset frequency, the frequencies of the first clock signal and the second clock signal are changed, and the frequencies of the first clock signal and the second clock signal satisfy a preset relationship with the frequency of the reference clock. According to the second preset frequency, the modified second clock signal is delayed or advanced to obtain the third clock signal; The serial data stream is received according to the third clock signal; Wherein, the frequency of the third clock signal is equal to the frequency of the modified first clock signal, and the phase difference between the third clock signal and the modified first clock signal is equal to the first preset duration.

2. The data receiving method as described in claim 1, characterized in that, The phase difference between the second clock signal and the first clock signal is equal to the first delay duration corresponding to the first preset number of reference clock cycles, and the phase difference between the third clock signal and the modified first clock signal is equal to the second delay duration corresponding to the second preset number of reference clock cycles. When the frequency of the reference clock is a first preset frequency, the first delay duration is equal to the first preset duration; When the frequency of the reference clock is the second preset frequency, the first delay duration is not equal to the first preset duration, and the second delay duration is equal to the first preset duration.

3. The data receiving method as described in claim 2, characterized in that, The second preset frequency is N times the first preset frequency, and the second preset quantity is N times the first preset quantity; or The first preset frequency is N times the second preset frequency, and the first preset quantity is N times the second preset quantity.

4. The data receiving method as described in claim 1, characterized in that, The second preset frequency is N times the first preset frequency. The step of delaying or advancing the modified second clock signal according to the second preset frequency to obtain the third clock signal includes: According to the second preset frequency, the modified second clock signal is delayed by a first preset duration to obtain the third clock signal; or According to the second preset frequency, the modified second clock signal is advanced by a second preset time to obtain the third clock signal.

5. The data receiving method as described in claim 4, characterized in that, N times the first set duration is equal to N-1 times the first preset duration.

6. The data receiving method as described in claim 1, characterized in that, The first preset frequency is N times the second preset frequency, and the step of delaying or advancing the modified second clock signal according to the second preset frequency to obtain the third clock signal includes: According to the second preset frequency, the modified second clock signal is advanced by a third preset time to obtain the third clock signal; or According to the second preset frequency, the modified second clock signal is delayed by a fourth preset time to obtain the third clock signal.

7. The data receiving method as described in claim 6, characterized in that, The third preset duration is equal to N-1 times the first preset duration.

8. A data transmission method, characterized in that, The data transmission method is used to send a serial data stream to a data receiver based on a first clock signal, and the data receiver receives the serial data stream based on a second clock signal. The serial data stream has a data transmission delay of a first preset duration. When the frequency of the reference clock is the first preset frequency, the phase difference between the second clock signal and the first clock signal is equal to the first preset duration. The serial data stream is transmitted based on the reference clock. The data transmission method includes: In response to the reference clock changing from a first preset frequency to a second preset frequency, the frequencies of the first clock signal and the second clock signal are changed, and the frequencies of the first clock signal and the second clock signal satisfy a preset relationship with the frequency of the reference clock. According to the second preset frequency, the modified first clock signal is delayed or advanced to obtain a fourth clock signal. The serial data stream is transmitted according to the fourth clock signal; Wherein, the frequency of the fourth clock signal is equal to the frequency of the modified second clock signal, and the phase difference between the fourth clock signal and the modified second clock signal is equal to the first preset duration.

9. The data transmission method as described in claim 8, characterized in that, The phase difference between the first clock signal and the second clock signal is equal to the first lead time corresponding to a third preset number of reference clock cycles, and the phase difference between the fourth clock signal and the changed second clock signal is equal to the second lead time corresponding to a fourth preset number of reference clock cycles. When the frequency of the reference clock is a first preset frequency, the first lead time is equal to the first preset time. When the frequency of the reference clock is the second preset frequency, the first lead time is not equal to the first preset time, and the second lead time is equal to the first preset time.

10. The data transmission method as described in claim 9, characterized in that, The second preset frequency is N times the first preset frequency, and the fourth preset quantity is N times the third preset quantity; or The first preset frequency is N times the second preset frequency, and the third preset quantity is N times the fourth preset quantity.

11. The data transmission method as described in claim 8, characterized in that, The second preset frequency is N times the first preset frequency. The step of delaying or advancing the modified first clock signal according to the second preset frequency to obtain the fourth clock signal includes: Based on the second preset frequency, the modified first clock signal is advanced by a fifth preset time to obtain the fourth clock signal; or According to the second preset frequency, the modified first clock signal is delayed by a sixth preset time to obtain the fourth clock signal.

12. The data transmission method as described in claim 11, characterized in that, The fifth preset duration, N times the original duration, is equal to N-1 times the first preset duration.

13. The data transmission method as described in claim 8, characterized in that, The first preset frequency is N times the second preset frequency, and the step of delaying or advancing the modified first clock signal according to the second preset frequency to obtain the fourth clock signal includes: Based on the second preset frequency, the modified first clock signal is delayed by a seventh set time to obtain the fourth clock signal; or According to the second preset frequency, the modified first clock signal is advanced by an eighth preset time to obtain the fourth clock signal.

14. The data transmission method as described in claim 13, characterized in that, The seventh preset duration is equal to N-1 times the first preset duration.

15. A data exchange device, characterized in that, The data exchange device includes a data sending module and / or a data receiving module; The data sending module is used to perform the data receiving method as described in any one of claims 1 to 7, and the data receiving module is used to perform the data sending method as described in any one of claims 8 to 14.

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