A normally-off GaN HEMT device and its fabrication method

Abstract

The application provides a normally-off GaN HEMT device and a preparation method, and relates to the technical field of semiconductors. The normally-off GaN HEMT device and the preparation method introduce BaTiO3 / SiN x The composite dielectric layer regulates the threshold voltage, the three-dimensional charge coupling structure is arranged on the drain metal side to optimize the electric field distribution, and the BaTiO3 / SiN x The composite dielectric layer forms a synergistic effect. Not only does the application solve the technical bottlenecks of current HEMT devices in normally-off operation, dynamic on-resistance and breakdown voltage, but also has good threshold voltage stability and dynamic performance compared with the prior art.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a normally-off GaN HEMT device and its fabrication method. Background Technology

[0002] High electron mobility transistors (HEMTs), as representatives of third-generation wide-bandgap semiconductor devices, utilize a two-dimensional electron gas (2DEG) at the heterojunction interface as a conductive channel, and have advantages such as high electron mobility (>2000cm² / V·s), high breakdown field strength (3.3MV / cm) and low on-resistance.

[0003] While HEMT technology has made significant progress, it still faces technical bottlenecks such as the traditional HEMT being normally open, requiring additional negative bias voltage for circuit applications, a significant increase in dynamic on-resistance during high-voltage switching, and limited breakdown voltage due to high electric field concentration. Existing technologies, through techniques such as recessed gate structures, fluorine ion implantation, and p-GaN gates, have partially addressed these issues, but their threshold voltage stability and dynamic performance remain unsatisfactory. Summary of the Invention

[0004] To address the aforementioned issues, this application provides a normally-off GaN HEMT device and its fabrication method, which not only solves the technical bottlenecks of current HEMT devices in terms of normally-off operation, dynamic on-resistance, and breakdown voltage, but also exhibits good threshold voltage stability and dynamic performance compared to existing technologies.

[0005] The technical solution adopted by this invention to solve its technical problem is: A normally-off GaN HEMT device includes a device body, which comprises a substrate and a GaN buffer layer from bottom to top. A source metal and a drain metal are respectively disposed on both sides of the GaN buffer layer. A GaN channel layer and an AlGaN barrier layer are disposed from bottom to top between the source metal and the drain metal. A composite dielectric layer and a three-dimensional charge coupling structure are disposed between the source metal and the drain metal on the upper side of the AlGaN barrier layer, and the three-dimensional charge coupling structure is attached to the drain metal. A gate metal is disposed above the composite dielectric layer; A SiN cap layer is disposed on the upper side of the AlGaN barrier layer between the source metal and the composite dielectric layer, and a SiN cap layer is disposed on the upper side of the AlGaN barrier layer between the composite dielectric layer and the three-dimensional charge-coupled structure. The composite dielectric layer, from bottom to top, comprises a BaTiO3 layer and a SiN layer. x layer; The three-dimensional charge-coupled structure is formed by overlapping a p-type first GaN layer and an n-type first AlGaN layer. The first GaN layer is implanted with Mg ions, and the first AlGaN layer is doped with Si. A passivation layer is provided on the upper surface of the device body; The upper surface of the passivation layer is provided with a Ti / Cu stacked wiring layer, and a number of pad areas are provided on the Ti / Cu stacked wiring layer.

[0006] Furthermore, the GaN buffer layer comprises, from bottom to top, an AlN nucleation layer and a superlattice buffer layer. The superlattice buffer layer is formed by overlapping a second AlGaN layer and a second GaN layer, and the aluminum content of the second AlGaN layer in the superlattice buffer layer gradually decreases from bottom to top.

[0007] Furthermore, the aluminum content of the second AlGaN layer decreases linearly from 30% to 5% along the direction away from the AlN nucleation layer.

[0008] Furthermore, the dislocation density of the superlattice layer is <5×10⁻⁶. 8 cm -2 .

[0009] Furthermore, the aluminum content in the AlGaN barrier layer decreases linearly away from the GaN channel layer, and the Si doping concentration in the AlGaN barrier layer decreases linearly away from the GaN channel layer.

[0010] Furthermore, the aluminum content in the AlGaN barrier layer decreases linearly from 25% to 15% along the direction away from the GaN channel layer, and the Si doping concentration in the AlGaN barrier layer decreases from 1×10⁻⁶ along the direction away from the GaN channel layer. 18 cm -3 Linear gradient to 5×10 17 cm -3 .

[0011] Furthermore, the passivation layer comprises, from bottom to top, a SiO2 layer and a polymer layer.

[0012] Furthermore, the hole concentration of the first GaN layer after Mg ion implantation is 5 × 10⁻⁶. 17 cm -3 .

[0013] A method for fabricating a normally-off GaN HEMT device includes the following steps: S1, After cleaning, the substrate is placed in the MOCVD reaction chamber; S2, a GaN buffer layer is grown on the substrate; 2.1 Growth of an AlN nucleation layer on a substrate; 2.2 AlGaN and GaN layers are alternately grown on the AlN nucleation layer; S3, grow GaN channel layer; S4, grow an AlGaN barrier layer; S5, grow a SiN cap layer; S6, etching is performed on both sides of the upper surface of the epitaxial wafer to form isolation trenches, and the isolation trenches extend downward to the upper surface of the GaN buffer layer or the interior of the GaN buffer layer. S7, deposits multiple layers of metal in two isolation tanks, with one multilayer metal serving as the source metal and the other as the drain metal; S8, growth composite medium layer; 8.1 An etching is performed between two multilayer metals on the upper surface of the epitaxial wafer to form a first growth trench, and the first growth trench extends downward to the upper surface of the AlGaN barrier layer. 8.2 Preparation of BaTiO3 layer in the first growth tank; 8.3 Deposition of SiN on the surface of BaTiO3 layer x layer; S9, growing a three-dimensional charge-coupled structure; 9.1 An etching is performed between the drain metal and the composite dielectric layer on the upper surface of the epitaxial wafer to form a second growth trench, and the second growth trench extends downward to the upper surface of the AlGaN barrier layer. 9.2 The first GaN layer is grown in the second growth tank, and then Mg ions are implanted by tilting ions; 9.3 A Si-doped first AlGaN layer is grown on the upper surface of the first GaN layer; 9.4 Repeat steps 9.2-9.3 to obtain the three-dimensional charge-coupled structure; S10, after photolithography windowing, gate metal is deposited on the upper surface of the composite dielectric layer; S11, a passivation layer is prepared on the upper surface of the epitaxial wafer; 11.1 Deposit a SiO2 layer on the upper surface of the epitaxial wafer; 11.2 Spin-coat a polymer layer onto the upper surface of the SiO2 layer.

[0014] S12, a titanium adhesion layer and a copper conductive layer are sequentially sputtered on the surface of the passivation layer to form a Ti / Cu stacked wiring layer, and then a number of pad areas are defined in the Ti / Cu stacked wiring layer by photolithography patterning process.

[0015] Furthermore, the background electron concentration during GaN channel layer growth is <5×10⁻⁶. 15 cm-3 Furthermore, the background electron mobility at room temperature is >2000 cm² / V·s.

[0016] The beneficial effects of this invention are: 1. This application provides a normally-off GaN HEMT device and its fabrication method, which introduces BaTiO3 / SiN into the gate dielectric layer. x Composite structure, ferroelectric polarization field of composite dielectric layer and SiN x The synergistic effect of interface passivation effectively improves the stability of the threshold voltage and high-temperature stability, enabling HEMT devices to have stable normally-off characteristics. Specifically, the normally-off GaN HEMT device provided in this application has a threshold voltage of +1.2V and a high-temperature drift of <0.3V (175°C).

[0017] 2. The normally-off GaN HEMT device and its fabrication method provided in this application reduce the peak electric field from 3.5MV / cm to 2.1MV / cm through a three-dimensional charge-coupled structure. The dynamic on-resistance increases by only 20% under 600V stress (while the dynamic on-resistance of traditional structures typically increases by 200% under 600V stress), exhibiting excellent dynamic performance.

[0018] 3. This application provides a normally-off GaN HEMT device and its fabrication method, which effectively improves the breakdown voltage through synergistic optimization of the gradient barrier layer design and the three-dimensional charge-coupled structure. Specifically, the normally-off GaN HEMT device provided in this application achieves a breakdown voltage exceeding 2100V, a specific on-resistance of 2.3mΩcm², and a figure of merit (FOM = BV² / R). on It reached 1917MW / cm².

[0019] 4. The normally-off GaN HEMT device and fabrication method provided in this application have good process compatibility and are compatible with 6-inch GaN-on-Si production lines. Only three photomasks are added (composite dielectric layer, ion implantation, and three-dimensional charge-coupled structure etching), and the chip yield can reach over 85%. Mass production can be achieved with existing photomask and etching equipment, and the yield is controllable.

[0020] 5. The normally-off GaN HEMT device provided in this application embodiment is applicable to a wide voltage range from 650V to 2000V, and in particular solves the reliability problem of HEMT in electric vehicle on-board chargers (OBCs), with an expected lifespan of more than 10 years under 100kHz hard switching conditions. Attached Figure Description

[0021] Figure 1 The process engineering of a normally-off GaN HEMT device fabrication method provided in this application embodiment Figure 1 ; Figure 2 The process engineering of a normally-off GaN HEMT device fabrication method provided in this application embodiment Figure 2 ; Figure 3 The process engineering of a normally-off GaN HEMT device fabrication method provided in this application embodiment Figure 3 ; Figure 4 The process engineering of a normally-off GaN HEMT device fabrication method provided in this application embodiment Figure 4 ; Figure 5 The process engineering of a normally-off GaN HEMT device fabrication method provided in this application embodiment Figure 5 ; Figure 6 The process engineering of a normally-off GaN HEMT device fabrication method provided in this application embodiment Figure 6 ; Figure 7 The process engineering of a normally-off GaN HEMT device fabrication method provided in this application embodiment Figure 7 ; Figure 8 The process engineering of a normally-off GaN HEMT device fabrication method provided in this application embodiment Figure 8 ; Figure 9 The process engineering of a normally-off GaN HEMT device fabrication method provided in this application embodiment Figure 9 ; Figure 10 The process engineering of a normally-off GaN HEMT device fabrication method provided in this application embodiment Figure 10 .

[0022] In the figure: 11, substrate; 12, GaN buffer layer; 131, source metal; 132, drain metal; 14, GaN channel layer; 15, AlGaN barrier layer; 16, composite dielectric layer; 17, three-dimensional charge-coupled structure; 18, gate metal; 19, SiN cap layer; 2. Passivation layer; 21. SiO2 layer; 22. Polymer layer; 3. Ti / Cu stacked wiring layer; 41. Isolation tank; 42. First growth tank; 43. Second growth tank. Detailed Implementation

[0023] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be described in detail below with reference to the accompanying drawings. The described embodiments are merely a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort should fall within the protection scope of this application.

[0024] like Figure 10 As shown, a normally-off GaN HEMT device includes a device body. From bottom to top, the device body includes a substrate 11 and a GaN buffer layer 12. A source metal 131 and a drain metal 132 are respectively disposed on both sides of the upper side of the GaN buffer layer 12. Between the source metal 131 and drain metal 132, a GaN channel layer 14 and an AlGaN barrier layer 15 are disposed sequentially from bottom to top on the upper side of the GaN buffer layer 12. Above the AlGaN barrier layer 15, between the source metal 131 and drain metal 132, a composite dielectric layer 16 and a three-dimensional charge-coupled structure 17 are disposed sequentially along the direction close to the drain metal 132, and the three-dimensional charge-coupled structure 17 is attached to the drain metal 132. A gate metal 18 is disposed above the composite dielectric layer 16. A SiN cap layer 19 is disposed on the upper side of the AlGaN barrier layer 15 between the source metal 131 and the composite dielectric layer 16, and a SiN cap layer 19 is disposed on the upper side of the AlGaN barrier layer 15 between the composite dielectric layer 16 and the three-dimensional charge-coupled structure 17.

[0025] The composite dielectric layer 16 comprises, from bottom to top, a BaTiO3 layer and a SiN layer. x The composite dielectric layer 16 has a thickness of 80-120 nm.

[0026] In one specific embodiment, the thickness of the composite dielectric layer 16 in this example is 80 nm, wherein the thickness of the BaTiO3 layer is 50 nm, and the thickness of the SiN layer is... x The thickness of the layer is 30nm.

[0027] The composite dielectric layer 16 enhances the controllability of the gate metal 18 through a ferroelectric polarization field (>1MV / cm), while SiN x The interface layer reduces the density of states to <5×10 11 cm -2 ·eV -1 Experiments show that this design stabilizes the threshold voltage at +1.2V ± 0.05V and the gate leakage current is <1nA / mm.

[0028] The three-dimensional charge-coupled structure 17 is formed by overlapping a p-type first GaN layer and an n-type first AlGaN layer. The first GaN layer is implanted with Mg ions at a dose of 5 × 10⁻⁶. 14 cm -2 The Mg ion implantation energy was 100 keV, and the hole concentration of the first GaN layer after Mg ion implantation was 5 × 10⁻⁶. 17 cm -3 The first AlGaN layer is doped with Si, and the Si doping concentration is 1×10⁻⁶. 18 cm -3 .

[0029] In one specific implementation, the overlap period of the first GaN layer and the first AlGaN layer in this embodiment is 3, the thickness of the first GaN layer is 300nm, and the thickness of the first AlGaN layer is 50nm.

[0030] This structure can reduce the peak value of the transverse electric field by 40% and increase the breakdown voltage to 2100V.

[0031] Furthermore, the GaN buffer layer 12 comprises, from bottom to top, an AlN nucleation layer and a superlattice buffer layer. The superlattice buffer layer is formed by overlapping a second AlGaN layer and a second GaN layer, and the aluminum content of the second AlGaN layer in the superlattice buffer layer gradually decreases from bottom to top.

[0032] In one specific implementation, the aluminum content of the second AlGaN layer in this embodiment decreases linearly from 30% to 5% along the direction away from the AlN nucleation layer.

[0033] In one specific implementation, the thickness of the superlattice buffer layer in this embodiment is 2 μm, and the overlap period of the second AlGaN layer and the second GaN layer is 50, so the thickness of each overlap period is 40 nm.

[0034] Furthermore, the dislocation density of the superlattice layer is <5×10⁻⁶. 8 cm -2 .

[0035] Furthermore, the AlGaN barrier layer 15 has a thickness of 30 nm, and the aluminum content in the AlGaN barrier layer 15 decreases linearly from 25% to 15% along the direction away from the GaN channel layer 14. The Si doping concentration in the AlGaN barrier layer 15 decreases from 1×10⁻⁶ along the direction away from the GaN channel layer 14. 18 cm -3 Linear gradient to 5×10 17 cm -3 .

[0036] The aluminum content in the AlGaN barrier layer 15 is varied by a gradient to mitigate the sudden change in polarization electric field, so that the dynamic resistance increases by only 8% after 1000 switching cycles.

[0037] Furthermore, a passivation layer 2 is disposed on the upper surface of the device body. The passivation layer 2 comprises, from bottom to top, a SiO2 layer 21 and a polymer layer 22. A Ti / Cu stacked wiring layer 3 is disposed on the upper surface of the passivation layer 2, and a plurality of pad areas are disposed on the Ti / Cu stacked wiring layer 3.

[0038] In one specific embodiment, the polymer layer 22 described in this example is made of polytetrafluoroethylene (PTFE). This structure allows the surface trap density to be reduced to 3 × 10⁻⁶. 10 cm -2 At a frequency of 100kHz, C ext / C lx It decreased from 0.25 to 0.08.

[0039] In one specific implementation, the GaN channel layer 14 in this embodiment has a thickness of 300 nm and is not intentionally doped. The SiN cap layer 19 has a thickness of 5 nm.

[0040] A method for fabricating a normally-off GaN HEMT device includes the following steps: S1, after being cleaned by RCA (wet chemical cleaning method), the substrate 11 is placed in the MOCVD reaction chamber, heated to 1050°C in a hydrogen atmosphere, and then annealed for 10 minutes.

[0041] As one specific implementation, the substrate 11 described in this embodiment is a high-resistivity Si substrate 11 with a resistivity >1000Ω·cm.

[0042] S2, a GaN buffer layer 12 is grown on substrate 11.

[0043] 2.1 An AlN nucleation layer is grown on substrate 11 to alleviate the lattice mismatch between Si and GaN.

[0044] In one specific implementation, the AlN nucleation layer in this embodiment has a thickness of 200 nm, a growth temperature of 550 °C, a growth pressure of 50 Torr, and a V / III ratio of 200.

[0045] 2.2 A second AlGaN layer and a second GaN layer are alternately grown on the AlN nucleation layer obtained in step 2.1 to obtain a superlattice buffer layer.

[0046] S3, a GaN channel layer 14 is grown on the GaN buffer layer 12 grown in step S2.

[0047] In one specific embodiment, the growth temperature of the GaN channel layer 14 in this example is 1050℃, and the background electron concentration during the growth of the GaN channel layer 14 is <5×10⁻⁶. 15 cm -3 Furthermore, the background electron mobility at room temperature is >2000 cm² / V·s.

[0048] S4, An AlGaN barrier layer 15 is grown on the GaN channel layer 14 grown in step S3.

[0049] S5, a SiN cap layer 19 is grown on the AlGaN barrier layer 15 grown in step S4, thereby obtaining the following... Figure 1 The epitaxial wafer shown.

[0050] During growth, the flow ratio of NH3 to SiH4 was 3:1, the growth temperature was 750℃, the growth pressure was 100 Torr, and the surface state density was reduced to <1×10⁻⁶. 11 cm -2 ·eV -1 .

[0051] S6, such as Figure 2 As shown, etching is performed on both sides of the upper surface of the epitaxial wafer obtained in step S5 to form isolation trenches 41, and the isolation trenches 41 extend downward to the upper surface of the GaN buffer layer 12 or the interior of the GaN buffer layer 12 to define the active region.

[0052] In one specific implementation, the isolation trench 41 described in this embodiment is etched using a Cl2 / Ar plasma etching process, with an ICP power of 300W and a DC bias voltage of 100V during the etching process.

[0053] S7, such as Figure 3 As shown, multilayer metals are deposited in the two isolation tanks 41 obtained in step S6 by electron beam evaporation, and the multilayer metals in one isolation tank 41 are used as source metals 131 and the multilayer metals in the other isolation tank 41 are used as drain metals 132.

[0054] As one specific implementation, the multilayer metal in this embodiment includes, from bottom to top, a Ti layer, an Al layer, a Ni layer, and an Au layer, with thicknesses of 20 nm, 100 nm, 40 nm, and 50 nm, respectively.

[0055] Furthermore, after the deposition of the overlayer metal is completed, it is heated to 850°C in a nitrogen atmosphere and then rapidly annealed for 30 seconds.

[0056] Preferably, the contact resistance of the resulting multilayer metal is <0.5Ω·mm.

[0057] S8, growth composite medium layer 16.

[0058] 8.1 Etching is performed between the two multilayer metals on the upper surface of the epitaxial wafer obtained in step S7 to form a layer as shown in the figure. Figure 4 The first growth trench 42 shown extends downward to the upper surface of the AlGaN barrier layer 15.

[0059] 8.2 In the first growth tank 42 obtained in step 8.1, a BaTiO3 layer is prepared by magnetron sputtering. During the magnetron sputtering process, the target purity is 99.9%, the argon flow rate is 25 cm³ / s, the RF power is 80 W, and the substrate temperature is 400 °C.

[0060] 8.3 SiN deposition on the surface of the BaTiO3 layer obtained in step 8.1 using PECVD (plasma-enhanced chemical vapor deposition) technology x Layers, to obtain as Figure 5 The composite dielectric layer 16 is shown. During the deposition process, the flow ratio of SiH4 to NH3 was 1:3, the pressure was 0.5 Torr, and the RF power was 50W.

[0061] S9, grow a three-dimensional charge-coupled structure 17.

[0062] 9.1 Etching is performed between the drain metal 132 and the composite dielectric layer 16 on the upper surface of the epitaxial wafer obtained in step S8, thereby forming a layer as shown in step S8. Figure 6 The second growth groove 43 is shown, and the second growth groove 43 extends downward to the upper surface of the AlGaN barrier layer 15.

[0063] 9.2 The first GaN layer is grown in the second growth tank 43, and then Mg ions are implanted by tilting ions.

[0064] In one specific implementation, the tilt angle during Mg ion injection in this embodiment is 30°.

[0065] 9.3 A Si-doped first AlGaN layer is grown on the upper surface of the first GaN layer.

[0066] 9.4 Repeat steps 9.2-9.3 until the first GaN layer and the first AlGaN layer reach a preset overlap period, to obtain the following... Figure 7 The three-dimensional charge-coupled structure 17 is shown.

[0067] S10, such as Figure 8 As shown, after photolithography to open the window, gate metal 18 is deposited on the upper surface of composite dielectric layer 16 by electron beam evaporation.

[0068] In one specific implementation, the gate metal 18 in this embodiment includes a Ti layer and an Au layer from bottom to top, with thicknesses of 30nm and 200nm respectively.

[0069] S11, such as Figure 9 As shown, a passivation layer 2 is prepared on the upper surface of the epitaxial wafer obtained in step S10.

[0070] 11.1 A SiO2 layer 21 is deposited on the upper surface of the epitaxial wafer obtained in step S10 using PECVD (plasma-enhanced chemical vapor deposition) technology; 11.2 A polymer layer 22 is spin-coated onto the upper surface of the SiO2 layer 21 obtained in step 11.1 and cured at 200°C for 1 hour.

[0071] S12, as Figure 10 As shown, a titanium adhesion layer and a copper conductive layer are sequentially sputtered onto the surface of the passivation layer 2 to form a Ti / Cu stacked wiring layer 3. Then, a number of pad areas are defined in the Ti / Cu stacked wiring layer 3 by photolithography patterning. When the pad areas are connected to external package terminals through wires, electrical interconnection from the chip electrodes to the external package terminals is achieved.

[0072] In one specific embodiment, the thickness of the titanium adhesive layer is 50 nm and the thickness of the copper conductive layer is 3 μm.

[0073] Other embodiments obtained by those skilled in the art based on the embodiments provided in this application by combining, splitting, or reorganizing the embodiments of this application do not exceed the protection scope of this application.

[0074] The above detailed embodiments have provided a detailed explanation of the purpose, technical solutions, and beneficial effects of the embodiments of this application. The above are merely specific embodiments of the embodiments of this application and are not intended to limit the protection scope of the embodiments of this application. That is, any modifications, equivalent substitutions, improvements, etc., made on the basis of the embodiments of this application should be included within the protection scope of the embodiments of this application.

Claims

1. A normally-off GaN HEMT device, comprising a device body, wherein the device body comprises, from bottom to top, a substrate (11) and a GaN buffer layer (12), wherein a source metal (131) and a drain metal (132) are respectively disposed on both sides of the GaN buffer layer (12), and a GaN channel layer (14) and an AlGaN barrier layer (15) are respectively disposed from bottom to top between the source metal (131) and the drain metal (132), characterized in that: A composite dielectric layer (16) and a three-dimensional charge coupling structure (17) are disposed between the source metal (131) and the drain metal (132) on the upper side of the AlGaN barrier layer (15), and the three-dimensional charge coupling structure (17) is attached to the drain metal (132). A gate metal (18) is disposed above the composite dielectric layer (16). A SiN cap layer (19) is disposed on the upper side of the AlGaN barrier layer (15) between the source metal (131) and the composite dielectric layer (16), and a SiN cap layer (19) is disposed on the upper side of the AlGaN barrier layer (15) between the composite dielectric layer (16) and the three-dimensional charge-coupled structure (17). The composite dielectric layer (16) comprises, from bottom to top, a BaTiO3 layer and a SiN layer. x layer; The three-dimensional charge-coupled structure (17) is formed by overlapping a p-type first GaN layer and an n-type first AlGaN layer. The first GaN layer is implanted with Mg ions, and the first AlGaN layer is doped with Si. A passivation layer (2) is provided on the upper surface of the device body; The passivation layer (2) has a Ti / Cu stacked wiring layer (3) on its upper surface, and the Ti / Cu stacked wiring layer (3) has several pad areas.

2. A normally-off GaN HEMT device according to claim 1, characterized in that: The GaN buffer layer (12) includes an AlN nucleation layer and a superlattice buffer layer from bottom to top. The superlattice buffer layer is formed by overlapping a second AlGaN layer and a second GaN layer, and the aluminum content of the second AlGaN layer in the superlattice buffer layer gradually decreases from bottom to top.

3. A normally-off GaN HEMT device according to claim 2, characterized in that: The aluminum content of the second AlGaN layer decreases linearly from 30% to 5% along the direction away from the AlN nucleation layer.

4. A normally-off GaN HEMT device according to claim 2, characterized in that: The dislocation density of the superlattice layer is <5×10⁻⁶. 8 cm -2 .

5. A normally-off GaN HEMT device according to claim 1, characterized in that: The aluminum content in the AlGaN barrier layer (15) decreases linearly in the direction away from the GaN channel layer (14), and the Si doping concentration in the AlGaN barrier layer (15) decreases linearly in the direction away from the GaN channel layer (14).

6. A normally-off GaN HEMT device according to claim 5, characterized in that: The aluminum content in the AlGaN barrier layer (15) decreases linearly from 25% to 15% along the direction away from the GaN channel layer (14), and the Si doping concentration in the AlGaN barrier layer (15) decreases from 1×10⁻⁶ along the direction away from the GaN channel layer (14). 18 cm -3 Linear gradient to 5×10 17 cm -3 .

7. A normally-off GaN HEMT device according to claim 1, characterized in that: The passivation layer (2) consists of a SiO2 layer (21) and a polymer layer (22) from bottom to top.

8. A normally-off GaN HEMT device according to claim 1, characterized in that: The hole concentration of the first GaN layer after Mg ion implantation is 5 × 10⁻⁶. 17 cm -3 .

9. A method for fabricating a normally-off GaN HEMT device as described in any one of claims 1-8, characterized in that: Includes the following steps, S1, after cleaning the substrate (11), it is placed into the MOCVD reaction chamber; S2, a GaN buffer layer (12) is grown on the substrate (11). 2.1 An AlN nucleation layer is grown on the substrate (11); 2.2 AlGaN and GaN layers are alternately grown on the AlN nucleation layer; S3, grow GaN channel layer (14). S4, grow AlGaN barrier layer (15). S5, grow SiN cap layer (19); S6, etching is performed on both sides of the upper surface of the epitaxial wafer to form an isolation trench (41), and the isolation trench (41) extends downward to the upper surface of the GaN buffer layer (12) or the interior of the GaN buffer layer (12). S7, deposit multilayer metals in two isolation tanks (41), with one multilayer metal as the source metal (131) and the other multilayer metal as the drain metal (132). S8, growth composite medium layer (16). 8.1 Etching is performed between two multilayer metals on the upper surface of the epitaxial wafer to form a first growth groove (42), and the first growth groove (42) extends downward to the upper surface of the AlGaN barrier layer (15); 8.2 Prepare a BaTiO3 layer in the first growth tank (42); 8.3 Deposition of SiN on the surface of BaTiO3 layer x layer; S9, grow a three-dimensional charge-coupled structure (17); 9.1 An etching is performed between the drain metal (132) and the composite dielectric layer (16) on the upper surface of the epitaxial wafer to form a second growth trench (43), and the second growth trench (43) extends downward to the upper surface of the AlGaN barrier layer (15). 9.2 The first GaN layer is grown in the second growth tank (43), and then Mg ions are implanted by tilting ions; 9.3 A Si-doped first AlGaN layer is grown on the upper surface of the first GaN layer; 9.4 Repeat steps 9.2-9.3 to obtain the three-dimensional charge-coupled structure (17). S10, after photolithography windowing, gate metal (18) is deposited on the upper surface of the composite dielectric layer (16). S11, a passivation layer is prepared on the upper surface of the epitaxial wafer (2). 11.1 A SiO2 layer is deposited on the upper surface of the epitaxial wafer (21). 11.2 A polymer layer (22) is spin-coated onto the upper surface of the SiO2 layer (21). S12, a titanium adhesion layer and a copper conductive layer are sputtered sequentially on the surface of the passivation layer (2) to form a Ti / Cu stacked wiring layer (3), and then a number of pad areas are defined in the Ti / Cu stacked wiring layer (3) by photolithography patterning process.

10. A method for fabricating a normally-off GaN HEMT device according to claim 9, characterized in that: Background electron concentration <5×10⁻⁶ during GaN channel layer (14) growth 15 cm -3 Furthermore, the background electron mobility at room temperature is >2000 cm⁻¹ 2 / V·s.

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