LDMOSFET device and method of manufacture, chip
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING SMARTCHIP MICROELECTRONICS TECHNOLOGY CO LTD
- Filing Date
- 2025-07-10
- Publication Date
- 2026-07-21
AI Technical Summary
The breakdown voltage of LDMOSFET devices in the existing BCD process is insufficient, making it difficult to withstand higher voltages, and the device reliability is low.
A gate structure with an ONO dielectric layer is adopted, with the drift region embedded and the sharp corners of the shallow trench isolation region covered to form a field plate structure, which captures charge to reduce charge accumulation and lower the surface electric field.
This improves the breakdown voltage and reliability of LDMOSFET devices, avoids breakdown at sharp corners, and enhances the device's withstand voltage capability.
Smart Images
Figure CN121001380B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more specifically to an LDMOSFET device, a method for manufacturing an LDMOSFET device, and a chip. Background Technology
[0002] BCD (Bipolar-CMOS-DMOS) technology is a series of process technologies that integrate bipolar transistors (Bipolar), complementary metal-oxide-semiconductor (CMOS), and double-diffused metal-oxide-semiconductor (DMOS) processes. With technological advancements, various device functions are integrated onto the BCD process platform. BCD technology is widely used in the manufacture of power management chips, where LDMOSFETs (Lateral Double-diffused MOSFETs), as high-voltage devices, play a crucial role, with withstand voltages reaching 800V or even higher. Therefore, it is necessary to research LDMOSFET devices based on BCD technology that can withstand even higher breakdown voltages. Summary of the Invention
[0003] This invention provides an LDMOSFET device and its manufacturing method. The LDMOSFET device adopts an ONO dielectric layer gate structure, which can improve the breakdown voltage and reliability of the device.
[0004] The LDMOSFET device provided by the present invention includes: a substrate, a body region, a drift region, a first shallow trench isolation region, a source region, a drain region, and a gate structure. The body region and the drift region are formed in the substrate, the first shallow trench isolation region is formed in the drift region, the source region is formed on the surface of the body region, and the drain region is formed on the surface of the drift region. The gate structure includes: a first polysilicon layer, a second polysilicon layer, and an ONO dielectric layer.
[0005] The first polysilicon layer is located on the body region, the second polysilicon layer is located on the drift region, the ONO dielectric layer is located at the bottom of the second polysilicon layer and embedded in the drift region, the ONO dielectric layer is connected to the side of the first shallow trench isolation region near the source region and covers the sharp corner of the first shallow trench isolation region near the source region.
[0006] The second polysilicon layer, the ONO dielectric layer, and the first shallow trench isolation region constitute a field plate structure. The ONO dielectric layer can store charge to reduce charge accumulation at the sharp corner of the first shallow trench isolation region near the source region.
[0007] In this embodiment of the invention, one end of the ONO dielectric layer near the first shallow trench isolation region is vertical and covers the upper sharp corner of the first shallow trench isolation region; the other end of the ONO dielectric layer extends obliquely to the surface of the body region and covers the sharp corner of the surface of the body region.
[0008] In this embodiment of the invention, the ONO dielectric layer includes: a first oxide layer, a second oxide layer, and a nitride layer located between the first oxide layer and the second oxide layer.
[0009] In this embodiment of the invention, the first oxide layer is formed on the surface of the groove in the drift region, the nitride layer is formed on the surface of the first oxide layer, and the second oxide layer is formed on the surface of the nitride layer.
[0010] In this embodiment of the invention, the second polysilicon layer is formed on the surface of the second oxide layer and on the surface of the shallow trench isolation region.
[0011] In this embodiment of the invention, the LDMOSFET device further includes a well region, a second shallow trench isolation region, and a third shallow trench isolation region. The well region is located below the body region and the drift region. The second shallow trench isolation region is located at the boundary between the drift region and the well region. The third shallow trench isolation region is located at the boundary between the well region and the substrate.
[0012] In this embodiment of the invention, the LDMOSFET device further includes: a first contact terminal, a second contact terminal, and a third contact terminal;
[0013] The first contact end is formed on the surface of the body region and is adjacent to the source region;
[0014] The second contact end is formed on the surface of the well region and is located between the second shallow trench isolation region and the third shallow trench isolation region;
[0015] The third contact terminal is formed on the surface of the substrate.
[0016] In this embodiment of the invention, the LDMOSFET device further includes: a plurality of mutually isolated metal electrodes, wherein the plurality of metal electrodes are respectively connected to a first polysilicon layer, a source region and a drain region; or, the plurality of metal electrodes are respectively connected to a first polysilicon layer, a second polysilicon layer, a source region and a drain region.
[0017] The present invention also provides a method for manufacturing the above-described LDMOSFET device, the method comprising:
[0018] Well regions, bulk regions, and drift regions are formed in the substrate;
[0019] A shallow trench isolation zone is formed within the drift zone;
[0020] The shallow groove isolation area within the drift zone is etched to form a groove.
[0021] An ONO dielectric layer is formed on the surface and sidewalls of the groove;
[0022] Polysilicon is deposited on the surfaces of the bulk region, the ONO dielectric layer and the shallow trench isolation region, and etched to form the first polysilicon layer and the second polysilicon layer.
[0023] The source region is formed on the surface of the solid region, and the drain region is formed on the surface of the drift region.
[0024] In this embodiment of the invention, forming a shallow trench isolation region within the drift region includes: using a shallow trench isolation process to form a first shallow trench isolation region within the drift region, a second shallow trench isolation region at the boundary between the drift region and the well region, and a third shallow trench isolation region at the boundary between the well region and the substrate.
[0025] In this embodiment of the invention, an ONO dielectric layer is formed on the surface and sidewalls of the groove, including:
[0026] A first oxide layer is formed by depositing silicon dioxide (SiO2) on the surface and sidewalls of the groove;
[0027] A silicon nitride (Si3N4) nitride layer is formed by depositing silicon nitride (Si3N4) on the surface of the first oxide layer;
[0028] A second oxide layer is formed by depositing silicon dioxide (SiO2) on the surface of the nitride layer.
[0029] In this embodiment of the invention, polysilicon is deposited on the surfaces of the body region, the ONO dielectric layer, and the shallow trench isolation region, and etched to form a first polysilicon layer and a second polysilicon layer, including:
[0030] N-type doped polysilicon is deposited on the surfaces of the bulk region, the ONO dielectric layer, and the shallow trench isolation region, and then etched to form a gap between the polysilicon on the surface of the bulk region and the polysilicon on the surface of the ONO dielectric layer. The polysilicon on the surface of the bulk region serves as the first polysilicon layer, and the polysilicon on the surface of the ONO dielectric layer and the polysilicon on the surface of the shallow trench isolation region serve as the second polysilicon layer.
[0031] In this embodiment of the invention, a source region is formed on the surface of the body region, and a drain region is formed on the surface of the drift region, including:
[0032] Photolithography is performed on the surfaces of the solid region and the drift region to form regional patterns;
[0033] N-type ions are injected into the regional patterns of the body region and the drift region, respectively, to form the source region and the drain region.
[0034] In this embodiment of the invention, the method further includes:
[0035] P-type ions are implanted into the region adjacent to the source region on the surface of the bulk region to form the first contact end;
[0036] N-type ions are implanted into the surface of the trap region to form a second contact end;
[0037] P-type ions are implanted into the surface of the substrate to form a third contact terminal.
[0038] The present invention also provides a chip comprising the above-described LDMOSFET device.
[0039] The LDMOSFET device of the present invention includes an ONO dielectric layer embedded in a drift region in its gate structure. The ONO dielectric layer is connected to the source region side of a first shallow trench isolation region and covers the sharp corner of the first shallow trench isolation region near the source region. A second polysilicon layer, the ONO dielectric layer, and the first shallow trench isolation region constitute a field plate structure. Since the ONO dielectric layer can trap charge, and the ONO dielectric layer and the second polysilicon layer can trap electrons, the interface states between Si in the substrate and SiO2 in the shallow trench isolation region can be fixed, reducing the surface electric field of the drift region and improving the breakdown voltage and reliability of the device. Moreover, the ONO dielectric layer embedded in the drift region covers one sharp corner of the shallow trench isolation region. Since the ONO dielectric layer can trap charge, it can reduce charge accumulation at the sharp corner of the first shallow trench isolation region near the source region, preventing breakdown at the sharp corner of the first shallow trench isolation region and further improving the breakdown voltage of the device.
[0040] Other features and advantages of the technical solution of the present invention will be described in detail in the following detailed embodiments section. Attached Figure Description
[0041] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:
[0042] Figure 1 This is a schematic diagram of the structure of an LDMOSFET device provided in an embodiment of the present invention;
[0043] Figure 2 This is a schematic diagram of the structure of an LDMOSFET device provided in another embodiment of the present invention;
[0044] Figure 3 This is a flowchart of a method for manufacturing an LDMOSFET device provided in an embodiment of the present invention;
[0045] Figure 4 This is a schematic diagram of the structure of the well region, body region and drift region formed in the manufacturing method provided in the embodiments of the present invention;
[0046] Figure 5This is a schematic diagram of the shallow trench isolation zone formed in the manufacturing method provided in this embodiment of the invention;
[0047] Figure 6 This is a schematic diagram of the groove formed in the shallow trench isolation area in the manufacturing method provided in the embodiment of the present invention;
[0048] Figure 7 This is a schematic diagram of the structure of the ONO dielectric layer formed in the manufacturing method provided in the embodiment of the present invention;
[0049] Figure 8 This is a schematic diagram of the gate structure formed in the manufacturing method provided in the embodiments of the present invention;
[0050] Figure 9 This is a schematic diagram of the source region, drain region, and contact end formed in the manufacturing method provided in the embodiments of the present invention;
[0051] Figure 10 This is a schematic diagram of the structure of the metal electrode formed in the manufacturing method provided in the embodiment of the present invention.
[0052] Explanation of reference numerals in the attached figures
[0053] 1-Substrate, 2-Trap region, 3-Bulk region, 4-Drift region, 5-First shallow trench isolation region
[0054] 6-Second shallow trench isolation region, 7-Third shallow trench isolation region, 8-First polysilicon layer
[0055] 9a - First oxide layer, 9b - Nitride layer, 9c - Second oxide layer
[0056] 10-Second polysilicon layer, 11-Source region, 12-Drain region, 13-First contact terminal, 14-Second contact terminal
[0057] 15-Third contact end, 16-Isolation dielectric layer, 17-Metal electrode, 18-Groove. Detailed Implementation
[0058] To make the technical solutions and advantages of the embodiments of the present invention clearer, the exemplary embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present invention can be combined with each other.
[0059] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "surface," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0060] In this invention, unless otherwise explicitly specified and limited, the terms "connected," "interlocked," and "linked" should be interpreted broadly. For example, they can refer to mechanical connections, electrical connections, or connections that allow for mutual communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal connection of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0061] Figure 1 This is a schematic diagram of the structure of an LDMOSFET device provided in an embodiment of the present invention. Figure 1As shown, the LDMOSFET device provided in this embodiment includes: a substrate 1, a well region 2, a body region 3, a drift region 4, a first shallow trench isolation region 5, a source region 11, a drain region 12, and a gate structure. The body region 3 and the drift region 4 are formed in the substrate 1, the source region 11 is formed on the surface of the body region 3, the first shallow trench isolation region 5 is formed within the drift region, and the drain region 12 is formed on the surface of the drift region 4. The gate structure includes: a first polysilicon layer 8, a second polysilicon layer 10, and an ONO dielectric layer (9a, 9b, 9c). The first polysilicon layer 8 is located on the body region 3, the second polysilicon layer 10 is located on the drift region 4, the ONO dielectric layer is located at the bottom of the second polysilicon layer 10 and embedded in the drift region 4, and the ONO dielectric layer is connected to the side of the first shallow trench isolation region 5 near the source region 11 and covers the sharp corner of the first shallow trench isolation region 5 near the source region 5. The second polysilicon layer 10, the ONO dielectric layer, and the first shallow trench isolation region 5 constitute a field plate structure. Since the ONO dielectric layer can trap charge, and the second polysilicon layer and the ONO dielectric layer can trap electrons, they can fix the interface states between Si in the substrate and SiO2 in the shallow trench isolation region, reduce the surface electric field in the drift region, and improve the breakdown voltage and reliability of the device. Furthermore, the ONO dielectric layer embedded in the drift region covers one of the sharp corners of the shallow trench isolation region. Because the ONO dielectric layer can trap charge, it can reduce charge accumulation at the sharp corners of the first shallow trench isolation region near the source region, preventing breakdown at the sharp corners of the first shallow trench isolation region and further improving the breakdown voltage of the device.
[0062] In this embodiment, one end of the ONO dielectric layer near the first shallow trench isolation region 5 is vertical and covers the upper sharp corner of the first shallow trench isolation region 5. The other end of the ONO dielectric layer extends obliquely to the surface of the body region 3 and covers the sharp corner of the surface of the body region 3. The ONO dielectric layer includes a first oxide layer 9a, a second oxide layer 9c, and a nitride layer 9b located between the first oxide layer 9a and the second oxide layer 9c. The first oxide layer 9a is formed on the surface of the first polysilicon layer 8, the nitride layer 9b is formed on the surface of the first oxide layer 9a, and the second oxide layer 9c is formed on the surface of the nitride layer 9b. The materials of the first oxide layer 9a and the second oxide layer 9c can be silicon dioxide, and the material of the nitride layer 9b can be silicon nitride.
[0063] In this embodiment, the LDMOSFET device further includes a second shallow trench isolation region 6 and a third shallow trench isolation region 7. The second shallow trench isolation region 6 is located at the junction of the drift region 4 and the well region 2, and the third shallow trench isolation region 7 is located at the junction of the well region 2 and the substrate 1.
[0064] In this embodiment, the LDMOSFET device further includes a first contact terminal 13, a second contact terminal 14, and a third contact terminal 15. The first contact terminal 13 is formed on the surface of the body region 3 and is adjacent to the source region 11; the second contact terminal 14 is formed on the surface of the well region 2 and is located between the second shallow trench isolation region 6 and the third shallow trench isolation region 7; the third contact terminal 15 is formed on the surface of the substrate 1. The conductivity type (P-type) of the first contact terminal 13 is different from the conductivity type (N-type) of the second contact terminal 14, while the conductivity type (P-type) of the first contact terminal 13 is the same as the conductivity type (P-type) of the third contact terminal 15.
[0065] In this embodiment, the LDMOSFET device further includes multiple isolated metal electrodes 17, which are respectively connected to a first polysilicon layer 8, a second polysilicon layer 10, a source region 11, a drain region 12, a first contact terminal 13, a second contact terminal 14, and a third contact terminal 15. The source region 11 and the first contact terminal 13 are connected to the same metal electrode 17, while the first polysilicon layer 8, the second polysilicon layer 10, the source region 11, the drain region 12, the second contact terminal 14, and the third contact terminal 15 are connected to different metal electrodes 17. An isolation dielectric layer 16 separates adjacent metal electrodes 17, and different metal electrodes 17 are isolated from each other by the isolation dielectric layer 16. Both the first polysilicon layer 8 and the second polysilicon layer 10 are connected to metal electrodes, and electrical signals are input through these metal electrodes to control the activation of the device.
[0066] Figure 2 This is a schematic diagram of the structure of an LDMOSFET device provided in another embodiment of the present invention. Figure 2As shown, the LDMOSFET device provided in this embodiment includes: a substrate 1, a well region 2, a body region 3, a drift region 4, a first shallow trench isolation region 5, a second shallow trench isolation region 6, a third shallow trench isolation region 7, a source region 11, a drain region 12, and a gate structure. The body region 3 and the drift region 4 are formed on the substrate 1, the source region 11 is formed on the surface of the body region 3, the first shallow trench isolation region 5 is formed within the drift region, and the drain region 12 is formed on the surface of the drift region 4. The gate structure includes: a first polysilicon layer 8, a second polysilicon layer 10, and an ONO dielectric layer. The first polysilicon layer 8 is located on the body region 3, and the second polysilicon layer 10 is located on the drift region 4. The ONO dielectric layer includes a first oxide layer 9a, a second oxide layer 9c, and a nitride layer 9b located between the first oxide layer 9a and the second oxide layer 9c. The ONO dielectric layer is located at the bottom of the second polysilicon layer 10 and embedded in the drift region 4. The ONO dielectric layer is connected to the side of the first shallow trench isolation region 5 near the source region 11 and covers the sharp corner of the first shallow trench isolation region 5 near the source region 5. The second shallow trench isolation region 6 is located at the junction of the drift region 4 and the well region 2, and the third shallow trench isolation region 7 is located at the junction of the well region 2 and the substrate 1. The second polysilicon layer 10, the ONO dielectric layer, and the first shallow trench isolation region 5 constitute a field plate structure. The second polysilicon layer and the ONO dielectric layer can trap electrons, which can fix the interface state between Si in the substrate and SiO2 in the shallow trench isolation region, reduce the surface electric field of the drift region, and improve the breakdown voltage and reliability of the device. Moreover, the ONO dielectric layer embedded in the drift region covers one of the sharp corners of the shallow trench isolation region. The ONO dielectric layer can store charge, which can reduce the charge accumulation at the sharp corner of the first shallow trench isolation region near the source region, avoid the sharp corner of the first shallow trench isolation region being broken down, and further improve the breakdown voltage of the device.
[0067] In this embodiment, the first oxide layer 9a of the ONO dielectric layer is formed on the surface of the first polysilicon layer 8, the nitride layer 9b is formed on the surface of the first oxide layer 9a, and the second oxide layer 9c is formed on the surface of the nitride layer 9b. The materials of the first oxide layer 9a and the second oxide layer 9c can be silicon dioxide, and the material of the nitride layer 9b can be silicon nitride.
[0068] In this embodiment, the LDMOSFET device further includes a first contact terminal 13, a second contact terminal 14, a third contact terminal 15, and a plurality of metal electrodes 17. The first contact terminal 13 is formed on the surface of the body region 3 and is adjacent to the source region 11; the second contact terminal 14 is formed on the surface of the well region 2 and is located between the second shallow trench isolation region 6 and the third shallow trench isolation region 7; the third contact terminal 15 is formed on the surface of the substrate 1. The conductivity type (P-type) of the first contact terminal 13 is different from that of the second contact terminal 14 (N-type), while the conductivity type (P-type) of the first contact terminal 13 is the same as that of the third contact terminal 15 (P-type). The plurality of metal electrodes 17 are respectively connected to the first polysilicon layer 8, the source region 11, the drain region 12, the first contact terminal 13, the second contact terminal 14, and the third contact terminal 15. In this configuration, the source region 11 and the first contact terminal 13 are connected to the same metal electrode 17. The first polysilicon layer 8, the source region 11, the drain region 12, the second contact terminal 14, and the third contact terminal 15 are each connected to different metal electrodes 17. An isolation dielectric layer 16 separates adjacent metal electrodes 17, and the multiple metal electrodes 17 are isolated from each other by the isolation dielectric layer 16. The second polysilicon layer 10 serves as a floating gate, and its surface is covered with the isolation dielectric layer 16. The first polysilicon layer 8 receives an electrical signal through a metal electrode to control the activation of the device.
[0069] The LDMOSFET device of the above embodiment has a gate structure including an ONO dielectric layer embedded in the drift region. The ONO dielectric layer is connected to the side of the first shallow trench isolation region 5 near the source region 11 and covers the sharp corner of the first shallow trench isolation region 5 near the source region 5. The second polysilicon layer 10, the ONO dielectric layer, and the first shallow trench isolation region 5 constitute a field plate structure. Since the ONO dielectric layer (the middle silicon nitride layer) can trap charge, and the second polysilicon layer and the ONO dielectric layer can trap electrons, the interface state between Si in the substrate and SiO2 in the shallow trench isolation region can be fixed, reducing the surface electric field of the drift region and improving the breakdown voltage and reliability of the device. Moreover, the ONO dielectric layer embedded in the drift region covers one sharp corner of the shallow trench isolation region. Since the ONO dielectric layer can trap charge, it can reduce the charge accumulation at the sharp corner of the first shallow trench isolation region near the source region, preventing the sharp corner of the first shallow trench isolation region from being broken down, and further improving the breakdown voltage of the device.
[0070] This invention also provides a method for manufacturing the above-described LDMOSFET device. For example... Figure 3 As shown, the manufacturing method of the LDMOSFET device provided in this embodiment includes the following steps:
[0071] S310 forms a well region, a bulk region, and a drift region in the substrate;
[0072] S320 forms a shallow trench isolation zone within the drift zone;
[0073] S330, etching is performed on the shallow groove isolation area in the drift zone to form a groove;
[0074] S340, an ONO dielectric layer is formed on the surface and sidewalls of the groove;
[0075] S350, polysilicon is deposited on the surface of the bulk region, the ONO dielectric layer and the shallow trench isolation region, and etched to form the first polysilicon layer and the second polysilicon layer.
[0076] S360 forms a source region on the surface of the in-body region and a drain region on the surface of the drift region.
[0077] The LDMOSFET device provided in this embodiment of the invention can be either an N-type LDMOSFET or a P-type LDMOSFET. When the LDMOSFET device is an N-type LDMOSFET, the first doping type is P-type and the second doping type is N-type; when the LDMOSFET device is a P-type LDMOSFET, the first doping type is N-type and the second doping type is P-type. The following describes the manufacturing method steps of the above-mentioned LDMOSFET device in detail, using an N-type LDMOSFET as an example.
[0078] In step S310 above, a substrate 1 is first provided, which is one of a silicon substrate, a silicon-germanium substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate. In this embodiment, substrate 1 is a P-type silicon substrate. Then, a thin oxide layer is grown on the surface of substrate 1 to form a photoresist layer. The photoresist is exposed and developed to form an ion implantation window. N-type ion implantation is performed on the substrate 1 through the ion implantation window to remove the photoresist. Another layer of photoresist is formed on the surface of substrate 1, and the photoresist is exposed and developed to form an ion implantation window. N-type ion implantation is performed on the substrate 1 through the ion implantation window to remove the photoresist. Another layer of photoresist is formed on the surface of substrate 1, and the photoresist is exposed and developed to form an ion implantation window. P-type ion implantation is performed on the substrate 1 through the ion implantation window to remove the photoresist. High-temperature propulsion and wet removal of the oxide layer on the surface of substrate 1 are then performed to form the substrate 1 as shown in the image. Figure 4 The trap region 2, body region 3, and drift region 4 are shown.
[0079] In step S320 above, a shallow trench isolation (STI) process is used to form a first shallow trench isolation region 5 within the drift region 4, a second shallow trench isolation region 6 at the boundary between the drift region 4 and the well region 2, and a third shallow trench isolation region 7 at the boundary between the well region 2 and the substrate 1. Specifically, in Figure 4A thin layer of silicon dioxide (SiO2) is oxidized again on the structure shown, followed by vapor deposition of silicon nitride (Si3N4). Photolithography is then performed, and the silicon nitride and silicon dioxide are dry-etched. The substrate 1 is dry-etched to form trenches for a first shallow trench isolation region within the drift region 4. A second shallow trench isolation region is formed at the boundary between the drift region 4 and the well region 2, and a third shallow trench isolation region is formed at the boundary between the well region 2 and the substrate 1. Silicon dioxide is deposited within the trenches, followed by high-temperature annealing and chemical mechanical polishing to remove the surface silicon dioxide dielectric. Wet etching is then used to remove the silicon nitride and silicon dioxide from the surface of the substrate 1, forming a structure as shown. Figure 5 The first shallow trench isolation zone 5, the second shallow trench isolation zone 6, and the third shallow trench isolation zone 7 are shown.
[0080] In step S330 above, a dry etching method is used to etch the first shallow trench isolation region 5, forming a groove 18 at one end of the first shallow trench isolation region 5 near the body region 3. For example... Figure 6 As shown, the sidewall of the groove 18 near the body region 3 is inclined, and the sidewall of the groove 18 near the first shallow groove isolation region 5 is vertical.
[0081] In step S340 above, silicon dioxide (SiO2) is deposited on the surface and sidewalls of the groove 18 using chemical vapor deposition (CVD) or atomic layer deposition (ALD) to form a first oxide layer 9a. Silicon nitride (Si3N4) is then deposited on the surface of the first oxide layer to form a nitride layer 9b. Finally, silicon dioxide (SiO2) is deposited on the surface of the nitride layer to form a second oxide layer 9c. Specifically, in... Figure 6 The surface of the structure shown is subjected to thermal oxidation to form a thin layer of silicon dioxide (SiO2), followed by annealing for surface treatment, and then wet etching to remove the thin silicon dioxide layer. Next, another thin layer of silicon dioxide is formed through thermal oxidation. Atomic layer deposition (ALD) is then used to form a thin layer of silicon nitride on the surface of the thin silicon dioxide, followed by another thin layer of silicon dioxide on the surface of the thin silicon nitride. Finally, dry etching is used to etch both the thin silicon dioxide and silicon nitride layers to form the structure shown. Figure 7 The structure shown is as follows. Since the ONO dielectric layer needs to be thin enough to obtain better capacitive coupling effect, atomic layer deposition (ALD) is used to deposit silicon dioxide and silicon nitride, which can obtain a thin ONO dielectric layer with better uniformity.
[0082] In step S350 above, N-type doped polysilicon is deposited on the surfaces of the body region, the ONO dielectric layer, and the shallow trench isolation region, and etched to form a gap between the polysilicon on the surface of the body region and the polysilicon on the surface of the ONO dielectric layer. The polysilicon on the surface of the body region serves as the first polysilicon layer 8, and the polysilicon on the surface of the ONO dielectric layer and the polysilicon on the surface of the shallow trench isolation region serve as the second polysilicon layer 10. Specifically, in... Figure 7The surface of the structure shown was deposited with a layer of heavily N-type doped polysilicon using low-pressure chemical vapor deposition (LPCVD), followed by chemical mechanical polishing (CMP), and then dry etching of the heavily N-type doped polysilicon to form the structure shown. Figure 8 The diagram shows a first polysilicon layer 8 and a second polysilicon layer 10. The first polysilicon layer 8 is located on the body region 3, the second polysilicon layer 10 is located on the drift region 4, the ONO dielectric layer is located at the bottom of the second polysilicon layer 10 and embedded in the drift region 4, the ONO dielectric layer is connected to the side of the first shallow trench isolation region 5 near the source region 11, and covers the sharp corner of the first shallow trench isolation region 5 near the source region 5.
[0083] In step S360 above, photolithography is performed on the surfaces of the body region 3 and the drift region 4 to form region patterns. N-type ions are then implanted into the region patterns of the body region 3 and the drift region 4 to form the source region 11 and the drain region 12, respectively. During this process, P-type ions can also be implanted simultaneously in the region of the body region 3 adjacent to the source region 11 to form a first contact terminal 13, N-type ions can be implanted on the surface of the well region 2 to form a second contact terminal 14, and P-type ions can be implanted on the surface of the substrate 1 to form a third contact terminal 15, forming a... Figure 9 The structure shown.
[0084] Finally, on the surface of the substrate 1 where the gate structure, source region 11, and drain region 12 are formed ( Figure 9 Silicon dioxide is deposited on the surface of the structure shown to form an isolation dielectric layer 16. The isolation dielectric layer 16 is then dry-etched to form contact holes. Next, physical vapor deposition (PVD) is used to deposit metal inside and on the surface of the contact holes. The metal is then dry-etched and alloyed to form a structure as shown. Figure 10 The metal electrode 17 is shown. The source region 11 and the first contact terminal 13 are connected to the same metal electrode 17. The first polysilicon layer 8, the second polysilicon layer 10, the source region 11, the drain region 12, the first contact terminal 13, the second contact terminal 14, and the third contact terminal 15 are each connected to a different metal electrode 17. An isolation dielectric layer 16 separates adjacent metal electrodes 17, thus isolating different metal electrodes 17 from each other. Both the first polysilicon layer 8 and the second polysilicon layer 10 are connected to the metal electrode, through which an electrical signal is input to control the activation of the device.
[0085] In other embodiments, Figure 9 Based on the structure shown, it is also possible to form something like... Figure 2The diagram shows an isolation dielectric layer 16 and metal electrodes 17. The first polysilicon layer 8, source region 11, drain region 12, second contact terminal 14, and third contact terminal 15 are each connected to different metal electrodes 17, and adjacent metal electrodes 17 are isolated from each other by the isolation dielectric layer 16. A second polysilicon layer 10 serves as a floating gate, and its surface is covered by the isolation dielectric layer 16. Electrical signals are input to the first polysilicon layer 8 through the metal electrodes to control the activation of the device.
[0086] The present invention also provides a chip comprising the above-described LDMOSFET device.
[0087] The optional embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the scope of the technical concept of the embodiments of the present invention, various simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all fall within the protection scope of the embodiments of the present invention. Furthermore, it should be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. As long as such combination does not violate the spirit of the embodiments of the present invention, it should also be considered as the content disclosed in the embodiments of the present invention.
Claims
1. An LDMOSFET device, comprising: The present invention comprises a substrate, a body region, a drift region, a first shallow trench isolation region, a source region, a drain region, and a gate structure, wherein the body region and the drift region are formed in the substrate, the first shallow trench isolation region is formed in the drift region, the source region is formed on the surface of the body region, and the drain region is formed on the surface of the drift region. The gate structure comprises a first polysilicon layer, a second polysilicon layer, and an ONO dielectric layer. The first polysilicon layer is located on the body region, the second polysilicon layer is located on the drift region, the ONO dielectric layer is located at the bottom of the second polysilicon layer and embedded in the drift region, the ONO dielectric layer is connected to the side of the first shallow trench isolation region near the source region and covers the sharp corner of the first shallow trench isolation region near the source region. The second polysilicon layer, the ONO dielectric layer, and the first shallow trench isolation region constitute a field plate structure, and the ONO dielectric layer is capable of storing charge.
2. The LDMOSFET device according to claim 1, characterized in that, The end of the ONO dielectric layer near the first shallow trench isolation region is vertical and covers the upper sharp corner of the first shallow trench isolation region. The other end of the ONO dielectric layer extends obliquely to the surface of the body region and covers the sharp corners of the body region surface.
3. The LDMOSFET device according to claim 1, characterized in that, The ONO dielectric layer includes: a first oxide layer, a second oxide layer, and a nitride layer located between the first oxide layer and the second oxide layer.
4. The LDMOSFET device according to claim 3, characterized in that, The first oxide layer is formed on the surface of the groove in the drift region, the nitride layer is formed on the surface of the first oxide layer, and the second oxide layer is formed on the surface of the nitride layer.
5. The LDMOSFET device according to claim 4, characterized in that, The second polysilicon layer is formed on the surface of the second oxide layer and on the surface of the shallow trench isolation region.
6. The LDMOSFET device according to claim 1, characterized in that, Also includes: The system comprises a well region, a second shallow trench isolation region, and a third shallow trench isolation region. The well region is located below the body region and the drift region. The second shallow trench isolation region is located at the boundary between the drift region and the well region. The third shallow trench isolation region is located at the boundary between the well region and the substrate.
7. The LDMOSFET device according to claim 6, characterized in that, Also includes: First contact end, second contact end, and third contact end; The first contact end is formed on the surface of the body region and is adjacent to the source region; The second contact end is formed on the surface of the well region and is located between the second shallow trench isolation region and the third shallow trench isolation region; The third contact terminal is formed on the surface of the substrate.
8. The LDMOSFET device according to claim 1, characterized in that, Also includes: Multiple isolated metal electrodes are connected to a first polysilicon layer, a source region, and a drain region, respectively; or, multiple metal electrodes are connected to a first polysilicon layer, a second polysilicon layer, a source region, and a drain region, respectively.
9. A method for manufacturing an LDMOSFET device, characterized in that, The LDMOSFET device is the LDMOSFET device according to claim 1, and the method includes: Well regions, bulk regions, and drift regions are formed in the substrate; A shallow trench isolation zone is formed within the drift zone; The shallow groove isolation area within the drift zone is etched to form a groove. An ONO dielectric layer is formed on the surface and sidewalls of the groove; Polysilicon is deposited on the surfaces of the bulk region, the ONO dielectric layer and the shallow trench isolation region, and etched to form the first polysilicon layer and the second polysilicon layer. The source region is formed on the surface of the solid region, and the drain region is formed on the surface of the drift region.
10. The method for manufacturing an LDMOSFET device according to claim 9, characterized in that, A shallow trench isolation zone is formed within the drift zone, including: A shallow trench isolation process is used to form a first shallow trench isolation region in the drift region, a second shallow trench isolation region at the boundary between the drift region and the well region, and a third shallow trench isolation region at the boundary between the well region and the substrate.
11. The method for manufacturing an LDMOSFET device according to claim 9, characterized in that, An ONO dielectric layer is formed on the surface and sidewalls of the groove, including: A first oxide layer is formed by depositing silica on the surface and sidewalls of the groove; A silicon nitride layer is formed by depositing silicon nitride on the surface of the first oxide layer; A second oxide layer is formed by depositing silicon dioxide on the surface of the nitride layer.
12. The method for manufacturing an LDMOSFET device according to claim 9, characterized in that, Polysilicon is deposited on the surfaces of the bulk region, the ONO dielectric layer, and the shallow trench isolation region, and etched to form a first polysilicon layer and a second polysilicon layer, including: N-type doped polysilicon is deposited on the surfaces of the bulk region, the ONO dielectric layer, and the shallow trench isolation region, and then etched to form a gap between the polysilicon on the surface of the bulk region and the polysilicon on the surface of the ONO dielectric layer. The polysilicon on the surface of the bulk region serves as the first polysilicon layer, and the polysilicon on the surface of the ONO dielectric layer and the polysilicon on the surface of the shallow trench isolation region serve as the second polysilicon layer.
13. The method for manufacturing an LDMOSFET device according to claim 9, characterized in that, A source region is formed on the surface of the bulk region, and a drain region is formed on the surface of the drift region, including: Photolithography is performed on the surfaces of the solid region and the drift region to form regional patterns; N-type ions are injected into the regional patterns of the body region and the drift region, respectively, to form the source region and the drain region.
14. The method for manufacturing an LDMOSFET device according to claim 13, characterized in that, The method further includes: P-type ions are implanted into the region adjacent to the source region on the surface of the bulk region to form the first contact end; N-type ions are implanted into the surface of the trap region to form a second contact end; P-type ions are implanted into the surface of the substrate to form a third contact terminal.
15. A chip, characterized in that, The chip includes the LDMOSFET device according to any one of claims 1-8.