LDMOSFET device and method of manufacture, chip

Abstract

This invention relates to the field of semiconductor technology, providing an LDMOSFET device, its manufacturing method, and a chip. The device includes a substrate, a body region, a drift region, a source region, a drain region, a field oxide layer, and a gate structure. The gate structure includes a first polysilicon layer, a second polysilicon layer, and an ONO dielectric layer. The first polysilicon layer is embedded in the body region, the second polysilicon layer is embedded in the drift region, and the ONO dielectric layer is located in a groove between the first and second polysilicon layers. The first polysilicon layer and the ONO dielectric layer constitute a floating gate, the second polysilicon layer and the ONO dielectric layer constitute a control gate, and the second polysilicon layer, the ONO dielectric layer, and the field oxide layer constitute a field plate structure. This invention integrates the functions of an LDMOS and a memory, employing an embedded gate structure containing an ONO dielectric layer, which reduces the surface electric field of the device, increases the breakdown voltage of the device, and allows for device turn-on control without an external gate control signal.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to an LDMOSFET device, a method for manufacturing an LDMOSFET device, and a chip. Background Technology

[0002] BCD (Bipolar-CMOS-DMOS) technology is a series of process technologies that integrate bipolar transistors (Bipolar), complementary metal-oxide-semiconductor (CMOS), and double-diffused metal-oxide-semiconductor (DMOS) processes. With technological advancements, various device functions are integrated into the BCD process platform. BCD technology is widely used in the manufacture of power management chips, where LDMOSFETs (Lateral Double-diffused MOSFETs), as high-voltage devices with withstand voltages reaching 800V or even higher, play a crucial role. Existing LDMOSFET devices require an external gate control signal to control their turn-on. Furthermore, a higher breakdown voltage of the LDMOSFET indicates better withstand voltage. Currently, there is a need to research the structure and manufacturing method of LDMOSFET devices based on BCD technology, which can control the device's turn-on without an external gate control signal and improve the device's breakdown voltage. Summary of the Invention

[0003] This invention provides an LDMOSFET device and its manufacturing method, which can control the turn-on of the LDMOSFET without the need for an external gate control signal, while improving the breakdown voltage of the LDMOSFET. Moreover, the manufacturing method of this device is compatible with BCD process.

[0004] The LDMOSFET device provided by the present invention includes: a substrate, a body region, a drift region, a source region, a drain region, a field oxide layer, and a gate structure. The body region and the drift region are formed in the substrate, the source region is embedded in the body region, and the drain region is embedded in the drift region. The gate structure includes: a first polysilicon layer, a second polysilicon layer, and an ONO dielectric layer. The first polysilicon layer is embedded in the body region, the second polysilicon layer is embedded in the drift region, the ONO dielectric layer is located in a groove between the first polysilicon layer and the second polysilicon layer, and the field oxide layer is located at the bottom of the second polysilicon layer. The ONO dielectric layer can capture charge. The first polysilicon layer and the ONO dielectric layer form a floating gate. The second polysilicon layer and the ONO dielectric layer form a control gate. The second polysilicon layer, the ONO dielectric layer, and the field oxide layer form a field plate structure.

[0005] In this embodiment of the invention, there are three ONO dielectric layers: the first ONO dielectric layer is located in the groove between the first polysilicon layer and the second polysilicon layer; the second ONO dielectric layer is located in the groove between the first polysilicon layer and the source region; and the third ONO dielectric layer is located in the groove between the second polysilicon layer and the drain region.

[0006] In this embodiment of the invention, the ONO dielectric layer includes: a first oxide layer, a second oxide layer, and a nitride layer located between the first oxide layer and the second oxide layer; The first oxide layer is in contact with the sidewall of the first polysilicon layer, and the second oxide layer is in contact with the sidewall of the second polysilicon layer.

[0007] In this embodiment of the invention, the first oxide layer and the second oxide layer are made of silicon dioxide, and the nitride layer is made of silicon nitride.

[0008] In this embodiment of the invention, the LDMOSFET device further includes a shallow trench isolation region, which is located at the junction of the drift region and the substrate.

[0009] In this embodiment of the invention, the LDMOSFET device further includes: a first contact terminal and a second contact terminal; The first contact end is located on the surface of the body region and is adjacent to the source region; The second contact end is located on the surface of the substrate.

[0010] In this embodiment of the invention, the LDMOSFET device further includes: a plurality of metal electrodes, which are respectively connected to the second polysilicon layer, the source region and the drain region.

[0011] The present invention also provides a method for manufacturing the above-mentioned LDMOSFET device, comprising: Forming bulk and drift regions in the substrate; An embedded source region is formed within the body region, and an embedded drain region is formed within the drift region; The body region and drift region are etched to form deep trenches; A field oxide layer is formed on the bottom surface of the deep trench near the drift zone; Polysilicon is deposited in a deep trench with a field oxide layer, and grooves are etched in the polysilicon to form a first polysilicon layer and a second polysilicon layer. An ONO dielectric layer is formed in the groove.

[0012] In this embodiment of the invention, the method for manufacturing an LDMOSFET device further includes: Before forming the source and drain regions, a shallow trench isolation region is formed at the junction of the drift region and the substrate.

[0013] In this embodiment of the invention, an embedded source region is formed within the body region, and an embedded drain region is formed within the drift region, including: Photolithography is performed on the surfaces of the bulk region and the drift region to form source region and drain region patterns; High-concentration, high-energy N-type ions are injected into the source and drain regions respectively, and then annealed to advance them, forming embedded source and drain regions.

[0014] In this embodiment of the invention, the body region and the drift region are etched to form deep trenches, including: The volume region and drift region between the source region and the drain region are etched, and a portion of the source region is etched away to form a deep trench connecting the source region and the drain region.

[0015] In this embodiment of the invention, polysilicon is deposited in a deep trench with a field oxide layer, and the polysilicon is etched to form grooves, forming a first polysilicon layer and a second polysilicon layer, including: A gate oxide layer is formed on the bottom surface of the deep trench near the body region; N-type doped polycrystalline silicon is deposited in deep trenches and then surface planarized. The polysilicon is etched to form three grooves, which separate the first polysilicon layer and the second polysilicon layer.

[0016] In this embodiment of the invention, forming an ONO dielectric layer in the groove includes: The groove is subjected to thermal oxidation treatment to form an oxide layer on both sides of the groove. The oxide layer on one side of the groove is used as the first oxide layer, and the oxide layer on the other side of the groove is used as the second oxide layer. Silicon nitride is deposited within the groove to form a nitride layer.

[0017] In this embodiment of the invention, the method for manufacturing an LDMOSFET device further includes: Silicon dioxide is deposited on a substrate having a first polysilicon layer, a second polysilicon layer and an ONO dielectric layer to form an isolation dielectric layer; The isolation dielectric layer is etched to form contact holes; Metal is deposited within the contact holes to form multiple metal electrodes that are respectively connected to the second polysilicon layer, the source region, and the drain region.

[0018] The present invention also provides a chip comprising the above-described LDMOSFET device.

[0019] The LDMOSFET device of this invention employs an embedded structure with an ONO dielectric layer in its gate structure. A first polysilicon layer and the ONO dielectric layer constitute a floating gate, and a second polysilicon layer and the ONO dielectric layer constitute a control gate. Since the ONO dielectric layer can trap charge, the trapped charge is easily attracted into and stored in the floating gate. Therefore, the floating gate can store more charge, making it easier to control the turn-on of the LDMOSFET device. Furthermore, the second polysilicon layer, the ONO dielectric layer, and the field oxide layer constitute a field plate structure. Because the source, drain, and gate structures are all embedded in the substrate, and the field plate structure formed by the gate structure and the ONO dielectric layer extends deep into the drift region, the ONO dielectric layer's ability to trap charge significantly reduces the surface electric field of the device, thereby increasing its breakdown voltage.

[0020] This invention integrates the functions of LDMOS and memory. The first polysilicon layer serves as a floating gate, and the second polysilicon layer serves as a control gate. The first polysilicon layer, the second polysilicon layer, and the ONO dielectric layer constitute a capacitor structure. The first polysilicon layer and the ONO dielectric layer can store charge and control the turn-on state of the LDMOSFET device. The LDMOSFET can be turned on without an external gate control signal, which can be applied to scenarios without power supply.

[0021] Other features and advantages of the technical solution of the present invention will be described in detail in the following detailed embodiments section. Attached Figure Description

[0022] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic diagram of the structure of the LDMOSFET device provided in an embodiment of the present invention; Figure 2 This is a flowchart of a method for manufacturing an LDMOSFET device provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of the body region and the drift region formed in the manufacturing method provided in the embodiment of the present invention; Figure 4 This is a schematic diagram of the shallow trench isolation zone formed in the manufacturing method provided in this embodiment of the invention; Figure 5 This is a schematic diagram of the source region, drain region, and contact end formed in the manufacturing method provided in the embodiments of the present invention; Figure 6 This is a schematic diagram of the deep trench formed in the manufacturing method provided in the embodiment of the present invention; Figure 7This is a schematic diagram of the structure of the field oxide layer formed in the manufacturing method provided in the embodiments of the present invention; Figure 8 This is a schematic diagram of the structure of polycrystalline silicon formed in the manufacturing method provided in the embodiments of the present invention; Figure 9 This is a schematic diagram of the structure of the first polycrystalline silicon layer and the second polycrystalline silicon layer formed in the manufacturing method provided in the embodiments of the present invention; Figure 10 This is a schematic diagram of the structure of the first oxide layer and the second oxide layer formed in the manufacturing method provided in the embodiment of the present invention; Figure 11 This is a schematic diagram of the structure of the ONO dielectric layer formed in the manufacturing method provided in the embodiment of the present invention; Figure 12 This is a schematic diagram of the structure of the metal electrode formed in the manufacturing method provided in the embodiment of the present invention.

[0023] Explanation of reference numerals in the attached figures 1-Substrate, 2-Bulk region, 3-Drift region, 4-Shallow trench isolation region, 5-Source region, 6-Drain region 7-Field oxide layer, 8-First polysilicon layer, 9-Second polysilicon layer, 10-ONO dielectric layer, 10a - First oxide layer, 10b - Nitride layer, 10c - Second oxide layer 11-First contact terminal, 12-Second contact terminal, 13-Isolation dielectric layer, 14-Metal electrode, 15 - Deep groove, 16 - Groove. Detailed Implementation

[0024] To make the technical solutions and advantages of the embodiments of the present invention clearer, the exemplary embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0025] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "surface," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0026] In this invention, unless otherwise explicitly specified and limited, the terms "connected," "interlocked," and "linked" should be interpreted broadly. For example, they can refer to mechanical connections, electrical connections, or connections that allow for mutual communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal connection of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0027] Figure 1 This is a schematic diagram of the LDMOSFET device provided in an embodiment of the present invention. Figure 1As shown, the LDMOSFET device provided in this embodiment includes: a substrate 1, a body region 2, a drift region 3, a source region 5, a drain region 6, a field oxide layer 7, and a gate structure. The body region 2 and the drift region 3 are formed in the substrate 1. The source region 5 is embedded in the body region 2, and the drain region 6 is embedded in the drift region 3. The gate structure includes: a first polysilicon layer 8, a second polysilicon layer 9, and an ONO dielectric layer 10. The first polysilicon layer 8 is embedded in the body region 2, the second polysilicon layer 9 is embedded in the drift region 3, the ONO dielectric layer 10 is located in a groove 16 between the first polysilicon layer 8 and the second polysilicon layer 9, and the field oxide layer 7 is located at the bottom of the second polysilicon layer 9. The ONO dielectric layer 10 can store charge. The first polysilicon layer 8 and the ONO dielectric layer 10 constitute a floating gate, the second polysilicon layer 9 and the ONO dielectric layer 10 constitute a control gate, and the second polysilicon layer 9, the ONO dielectric layer 10, and the field oxide layer 7 constitute a field plate structure. Since the source region 5, drain region 6, and gate structure are all embedded in the substrate 1, and the field plate structure formed by the gate structure and the ONO dielectric layer 10 also extends deep into the drift region 3, and the ONO dielectric layer 10 can store charge, the surface electric field of the device can be greatly reduced, thereby increasing the breakdown voltage of the device. The first polysilicon layer 8 also serves as a floating gate, and the second polysilicon layer 9 serves as a control gate. The first polysilicon layer 8, the second polysilicon layer 9, and the ONO dielectric layer 10 constitute a capacitor structure. The first polysilicon layer 8 and the ONO dielectric layer 10 can store charge and control the turn-on state of the LDMOSFET device.

[0028] Reference Figure 1 , Figure 9 and Figure 11 There are three ONO dielectric layers 10. The first ONO dielectric layer 10 is located in the groove 16 between the first polysilicon layer 8 and the second polysilicon layer 9. The second ONO dielectric layer 10 is located in the groove 16 between the first polysilicon layer 8 and the source region 5. The third ONO dielectric layer 10 is located in the groove 16 between the second polysilicon layer 9 and the drain region 6. The ONO dielectric layers include: a first oxide layer 10a, a second oxide layer 10c, and a nitride layer 10b located between the first oxide layer 10a and the second oxide layer 10c. The first oxide layer 10a is in contact with the sidewall of the first polysilicon layer 8, and the second oxide layer 10c is in contact with the sidewall of the second polysilicon layer 9. The first oxide layer 10a and the second oxide layer 10c can be made of silicon dioxide, and the nitride layer 10b can be made of silicon nitride.

[0029] In this embodiment, the LDMOSFET device further includes a shallow trench isolation region 4, a first contact terminal 11, and a second contact terminal 12. The shallow trench isolation region 4 is located at the junction of the drift region 3 and the substrate 1. The first contact terminal 11 is located on the surface of the body region 2 and is adjacent to the source region 5. The second contact terminal 12 is located on the surface of the substrate 1.

[0030] In this embodiment, the LDMOSFET device further includes multiple metal electrodes 14, which are respectively connected to the second polysilicon layer 9, the source region 5, the drain region 6, the first contact terminal 11, and the second contact terminal 12. The source region 5 and the first contact terminal 11 are connected to the same metal electrode 14, while the second polysilicon layer 9, the source region 5, the drain region 6, and the second contact terminal 12 are respectively connected to different metal electrodes 14. An isolation dielectric layer 13 separates adjacent metal electrodes 14, and different metal electrodes 14 are isolated from each other through the isolation dielectric layer 13.

[0031] In the LDMOSFET device described in the above embodiment, when a high voltage is applied to the control gate relative to the substrate, electrons in the drift region are attracted and tunnel into the floating gate. Since the silicon nitride layer in the middle of the ONO dielectric layer can capture electrons, more electrons are attracted into the floating gate and stored therein. After the applied voltage is stopped, because the floating gate layer is wrapped by an insulating layer, the electrons in the floating gate layer remain stored there. The charge stored in the floating gate layer enables the LDMOSFET device to turn on. For example, when a high voltage is applied to the substrate relative to the gate, the electrons stored in the floating gate layer tunnel back to the substrate (drift region) under the influence of the electric field, at which point the LDMOSFET device is in the turned-on state.

[0032] The LDMOSFET device of this invention employs an embedded structure containing an ONO dielectric layer in its gate structure. The first polysilicon layer 8 and the ONO dielectric layer 10 form a floating gate, and the second polysilicon layer 9 and the ONO dielectric layer 10 form a control gate. Since the ONO dielectric layer can capture charge, the captured charge is easily attracted into and stored in the floating gate. Therefore, the floating gate can store more charge, making it easier to control the turn-on of the LDMOSFET device. Furthermore, the second polysilicon layer 9, the ONO dielectric layer 10, and the field oxide layer 7 form a field plate structure. Because the source region 5, the drain region 6, and the gate structure are all embedded in the substrate 1, and the field plate structure formed by the gate structure and the ONO dielectric layer 10 extends deep into the drift region 3, and the ONO dielectric layer 10 can capture charge, the surface electric field of the device can be greatly reduced, thereby increasing the breakdown voltage of the device.

[0033] This invention integrates the functions of LDMOS and memory. The first polysilicon layer 8 serves as a floating gate, and the second polysilicon layer 9 serves as a control gate. The first polysilicon layer 8, the second polysilicon layer 9, and the ONO dielectric layer 10 constitute a capacitor structure. The first polysilicon layer 8 and the ONO dielectric layer 10 can store charge and control the turn-on state of the LDMOSFET device. The LDMOSFET can be turned on without an external gate control signal, which can be applied to scenarios without power supply.

[0034] This invention also provides a method for manufacturing the above-described LDMOSFET device. For example... Figure 2 As shown, the manufacturing method of the LDMOSFET device provided in this embodiment includes the following steps: S210, forming a bulk region and a drift region in the substrate; S220 forms an embedded source region within the body region and an embedded drain region within the drift region; S230 is used to etch the bulk region and drift region to form deep trenches; S240 forms a field oxide layer on the bottom surface of the deep trench near the drift zone; S250, polysilicon is deposited in a deep trench with a field oxide layer, and grooves are etched in the polysilicon to form a first polysilicon layer and a second polysilicon layer. S260, an ONO dielectric layer is formed in the groove.

[0035] The LDMOSFET device provided in this embodiment of the invention can be either an N-type LDMOSFET or a P-type LDMOSFET. When the LDMOSFET device is an N-type LDMOSFET, the first doping type is P-type and the second doping type is N-type; when the LDMOSFET device is a P-type LDMOSFET, the first doping type is N-type and the second doping type is P-type. The following describes the manufacturing method steps of the above-mentioned LDMOSFET device in detail, using an N-type LDMOSFET as an example.

[0036] In step S210 above, a substrate 1 is first provided. Substrate 1 is one of a silicon substrate, a silicon-germanium substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate. In this embodiment, substrate 1 is a P-type silicon substrate. Then, a thin oxide layer is grown on the surface of substrate 1 to form a photoresist layer. The photoresist is exposed and developed to form an ion implantation window. N-type ion implantation is performed on the drift region of substrate 1 through the ion implantation window to remove the photoresist. Another layer of photoresist is formed on the surface of substrate 1. The photoresist is exposed and developed to form an ion implantation window. P-type ion implantation is performed on the bulk region of substrate 1 through the ion implantation window to remove the photoresist. High-temperature propulsion and wet removal of the oxide layer on the surface of substrate 1 are then performed to form a substrate 1 with the substrate surface as described above. Figure 3 The body region 2 and drift region 3 are shown.

[0037] Prior to step S220 above, a shallow trench isolation process is used to form a shallow trench isolation region 4 at the interface between the drift region 3 and the substrate 1. Specifically, in Figure 3The structure shown is further oxidized with a thin layer of silicon dioxide (SiO2), followed by vapor deposition of silicon nitride (Si3N4), photolithography, dry etching of silicon nitride and silicon dioxide, dry etching of the substrate, forming shallow trenches at the interface between the drift region and the substrate, depositing silicon dioxide in the trenches, high-temperature annealing, chemical mechanical polishing to remove the surface silicon dioxide dielectric, and wet removal of silicon nitride and silicon dioxide from the substrate surface, forming a structure as shown. Figure 4 Shallow trench isolation zone 4 is shown.

[0038] In step S220 above, photolithography is performed on the surfaces of the body region 2 and the drift region 3 to form source and drain patterns. High-concentration, high-energy N-type ions are implanted into the source and drain patterns, respectively, and then annealed to advance the process, forming embedded source and drain regions 5 and 6, as shown below. Figure 5 As shown. In this step, the pattern of the contact end can also be formed simultaneously. P-type ions are injected into the patterned region adjacent to the source region 5 on the surface of the body region 2 to form the first contact end 11, and P-type ions are injected into the region adjacent to the shallow trench isolation region 4 on the surface of the substrate 1 to form the second contact end 12.

[0039] In step S230 above, the body region and drift region between the source region 5 and the drain region 6 are etched, and a portion of the source region 5 is etched away to form a deep trench 15 connecting the source region 5 and the drain region 6, as shown below. Figure 6 As shown, a portion of the right end of the source region 5 is etched away, and the left end of the drain region 6 is connected to the deep trench 15. The portion of the source region 5 that has been etched away is subsequently used to form an ONO dielectric layer 10. The source region 5 is connected to the first polysilicon layer 8 through the ONO dielectric layer 10, which can form a conductive channel in the body region 2 (below the first polysilicon layer 8), enabling the device to be turned on.

[0040] In step S240 above, a relatively thick layer of silicon dioxide (SiO2) is deposited in the deep trench 15, and the silicon dioxide is dry etched to form a field oxide layer 7 on the bottom surface of the deep trench 15 near the drift region 3. Then, a gate oxide layer (not shown in the figure) is formed on the bottom surface of the deep trench 15 near the body region 2, forming a layer as shown in the figure. Figure 7 The structure shown.

[0041] In step S250 above, a gate oxide layer (not shown in the attached figure) is formed at the bottom of the deep trench 15. Then, N-type heavily doped polysilicon is deposited in the deep trench 15, and surface planarization is performed to form a layer as shown in the attached figure. Figure 8 The structure shown is illustrated. Next, a dry etching method is used to etch the polysilicon, forming a structure as shown. Figure 9The three grooves 16 shown divide the first polysilicon layer 8 and the second polysilicon layer 9. The first groove 16 is located between the first polysilicon layer 8 and the second polysilicon layer 9, the second groove 16 is located between the first polysilicon layer 8 and the source region 5, and the third groove 16 is located between the second polysilicon layer 9 and the drain region 6.

[0042] In step S260 above, the groove 16 is subjected to thermal oxidation treatment to form an oxide layer (i.e., silicon dioxide SiO2) on both side walls of the groove 16. The oxide layer on one side wall of the groove serves as the first oxide layer 10a, and the oxide layer on the other side wall of the groove serves as the second oxide layer 10c. Figure 10 As shown. Next, silicon nitride (Si3N4) is deposited in the groove 16 using low-pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD) to form a nitride layer 10b. Then, chemical mechanical polishing (CMP) is performed to remove excess silicon nitride and silicon dioxide from the surface, achieving planarization and forming a layer as shown. Figure 11 The structure shown is as follows. Due to the relatively small size of the grooves, atomic layer deposition (ALD) is used to deposit silicon nitride (Si3N4) within the grooves containing the oxide layer to achieve better filling effect, as the film deposited by atomic layer deposition (ALD) has better uniformity and coverage.

[0043] Finally, in such Figure 11 Silicon dioxide (SiO2) is deposited on the structure shown (a substrate with a first polysilicon layer 8, a second polysilicon layer 9, and an ONO dielectric layer 10) to form an isolation dielectric layer 13. The isolation dielectric layer 13 is then dry-etched to form contact holes. Next, a physical vapor deposition (PVD) process is used to deposit metal inside and on the surface of the contact holes. The metal is then dry-etched and alloyed to form a structure as shown. Figure 12 The metal electrode 14 is shown. The source region 5 and the first contact terminal 11 are connected to the same metal electrode 14, while the second polysilicon layer 9, the drain region 6, and the second contact terminal 12 are connected to different metal electrodes 14. Adjacent metal electrodes are isolated by an isolation dielectric layer 13.

[0044] The present invention also provides a chip comprising the above-described LDMOSFET device.

[0045] The optional embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the scope of the technical concept of the embodiments of the present invention, various simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all fall within the protection scope of the embodiments of the present invention. Furthermore, it should be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. As long as such combination does not violate the spirit of the embodiments of the present invention, it should also be considered as the content disclosed in the embodiments of the present invention.

Claims

1. An LDMOSFET device, comprising: The present invention comprises a substrate, a body region, a drift region, a source region, a drain region, a field oxide layer, and a gate structure, wherein the body region and the drift region are formed in the substrate, and the source region is embedded in the body region, the drain region is embedded in the drift region, and the gate structure comprises a first polysilicon layer, a second polysilicon layer, and an ONO dielectric layer, wherein the first polysilicon layer is embedded in the body region, the second polysilicon layer is embedded in the drift region, and the ONO dielectric layer comprises a first ONO dielectric layer located in a groove between the first polysilicon layer and the second polysilicon layer, and the field oxide layer is located at the bottom of the second polysilicon layer. The ONO dielectric layer can capture charge. The first polysilicon layer and the first ONO dielectric layer form a floating gate. The second polysilicon layer and the first ONO dielectric layer form a control gate. The second polysilicon layer, the first ONO dielectric layer, and the field oxide layer form a field plate structure.

2. The LDMOSFET device according to claim 1, characterized in that, The ONO dielectric layer has three layers, including a second ONO dielectric layer and a third ONO dielectric layer. The second ONO dielectric layer is located in the groove between the first polysilicon layer and the source region, and the third ONO dielectric layer is located in the groove between the second polysilicon layer and the drain region.

3. The LDMOSFET device according to claim 1, characterized in that, The first ONO dielectric layer includes: a first oxide layer, a second oxide layer, and a nitride layer located between the first oxide layer and the second oxide layer; The first oxide layer is in contact with the sidewall of the first polysilicon layer, and the second oxide layer is in contact with the sidewall of the second polysilicon layer.

4. The LDMOSFET device according to claim 3, characterized in that, The first oxide layer and the second oxide layer are made of silicon dioxide, and the nitride layer is made of silicon nitride.

5. The LDMOSFET device according to claim 1, characterized in that, Also includes: A shallow trench isolation region is located at the boundary between the drift region and the substrate.

6. The LDMOSFET device according to claim 5, characterized in that, Also includes: First contact end and second contact end; The first contact end is located on the surface of the body region and is adjacent to the source region; The second contact end is located on the surface of the substrate.

7. The LDMOSFET device according to claim 1, characterized in that, Also includes: Multiple metal electrodes are connected to the second polysilicon layer, the source region, and the drain region, respectively.

8. A method for manufacturing an LDMOSFET device, wherein the LDMOSFET device is the LDMOSFET device according to claim 1, characterized in that, The method includes: Forming bulk and drift regions in the substrate; An embedded source region is formed within the body region, and an embedded drain region is formed within the drift region; The body region and drift region are etched to form deep trenches; A field oxide layer is formed on the bottom surface of the deep trench near the drift zone; Polysilicon is deposited in a deep trench with a field oxide layer, and grooves are etched in the polysilicon to form a first polysilicon layer and a second polysilicon layer. An ONO dielectric layer is formed in the groove.

9. The method for manufacturing an LDMOSFET device according to claim 8, characterized in that, The method further includes: Before forming the source and drain regions, a shallow trench isolation region is formed at the junction of the drift region and the substrate.

10. The method for manufacturing an LDMOSFET device according to claim 8, characterized in that, An embedded source region is formed within the body region, and an embedded drain region is formed within the drift region, including: Photolithography is performed on the surfaces of the bulk region and the drift region to form source region and drain region patterns; High-concentration, high-energy N-type ions are injected into the source and drain regions respectively, and then annealed to advance the process, forming embedded source and drain regions.

11. The method for manufacturing an LDMOSFET device according to claim 8, characterized in that, The body region and drift region are etched to form deep trenches, including: The volume region and drift region between the source region and the drain region are etched, and a portion of the source region is etched away to form a deep trench connecting the source region and the drain region.

12. The method for manufacturing an LDMOSFET device according to claim 8, characterized in that, Polysilicon is deposited in a deep trench with a field oxide layer, and the polysilicon is etched to form grooves, forming a first polysilicon layer and a second polysilicon layer, including: A gate oxide layer is formed on the bottom surface of the deep trench near the body region; N-type doped polycrystalline silicon is deposited in deep trenches and then surface planarized. The polysilicon is etched to form three grooves, which separate the first polysilicon layer and the second polysilicon layer.

13. The method for manufacturing an LDMOSFET device according to claim 8, characterized in that, Forming an ONO dielectric layer in the groove includes: The groove is subjected to thermal oxidation treatment to form an oxide layer on both sides of the groove. The oxide layer on one side of the groove is used as the first oxide layer, and the oxide layer on the other side of the groove is used as the second oxide layer. Silicon nitride is deposited within the groove to form a nitride layer.

14. The method for manufacturing an LDMOSFET device according to claim 8, characterized in that, The method further includes: Silicon dioxide is deposited on a substrate having a first polysilicon layer, a second polysilicon layer and an ONO dielectric layer to form an isolation dielectric layer; The isolation dielectric layer is etched to form contact holes; Metal is deposited within the contact holes to form multiple metal electrodes that are respectively connected to the second polysilicon layer, the source region, and the drain region.

15. A chip, characterized in that, The chip includes the LDMOSFET device according to any one of claims 1-7.

Images