A power supply control circuit, a power supply control method, and a controller

Abstract

The application provides a power supply control circuit, a power supply control method and a controller, relates to the technical field of power supply, and the power supply control circuit comprises a power management module and a control module. In the case that a sleep signal sent by a digital domain circuit is acquired, the control module is used to stop the power management module from supplying power to the digital domain circuit, so that the digital domain circuit is in a sleep state. Then, the control module is used to supply power to the digital domain circuit after a preset time length, so that the digital domain circuit is switched from the sleep state to a wake-up state. In the case that the digital domain circuit is in the sleep state, the digital domain circuit is powered off, and compared with the power consumption of the digital domain circuit in the sleep state in the related art, the power consumption of the digital domain circuit is reduced.

Description

Technical Field

[0001] This application belongs to the field of power supply technology, specifically relating to a power supply control circuit, a power supply control method, and a controller. Background Technology

[0002] In the controller, when the first low dropout linear regulator (LDO) in the power management module supplies power to the digital domain circuit, the digital domain circuit is in a wake-up state; when the first low dropout linear regulator is turned off and stops supplying power to the digital domain circuit, the digital domain circuit is in a sleep state and can be switched to a wake-up state.

[0003] When the digital domain circuit is in sleep mode, the second low-dropout linear regulator in the power management module needs to supply power to the digital domain circuit in order to maintain the sleep signal sent by the digital domain circuit to the power management module. The sleep signal is used to keep the first low-dropout linear regulator off and keep the second low-dropout linear regulator on. The power supply power of the second low-dropout linear regulator is lower than that of the first low-dropout linear regulator.

[0004] However, the power consumption of digital domain circuits in sleep mode is high. Summary of the Invention

[0005] This application aims to provide a power supply control circuit, a power supply control method, and a controller, which at least solves the problem of high power consumption in digital domain circuits due to power consumption in the sleep state in related technologies.

[0006] To solve the above-mentioned technical problems, this application is implemented as follows:

[0007] In a first aspect, embodiments of this application provide a power supply control circuit, including: a power management module and a control module;

[0008] The power management module is connected to the control module, and the power management module is used to connect to the digital domain circuits in the power supply and controller;

[0009] The control module is used to connect to the digital domain circuit, and when a sleep signal is received from the digital domain circuit, to cause the power management module to stop supplying power to the digital domain circuit, and after a preset time, to cause the power management module to supply power to the digital domain circuit.

[0010] Secondly, embodiments of this application also provide a power supply control method, applied to the power supply control circuit as described in the first aspect, the method comprising:

[0011] Upon receiving the sleep signal and the timing signal, the digital domain circuit is powered off, and the preset duration represented by the timing signal is obtained.

[0012] After the preset time period, the digital domain circuit is energized.

[0013] Thirdly, embodiments of this application also provide a controller, including the power supply control circuit as described in the first aspect, or the steps of implementing the power supply control method as described in the second aspect.

[0014] In this embodiment, when the control module receives a sleep signal from the digital domain circuit, it causes the power management module to stop supplying power to the digital domain circuit, thereby putting the digital domain circuit into a sleep state. Then, after a preset time, the control module causes the power management module to supply power to the digital domain circuit, so as to switch the digital domain circuit from the sleep state to the wake-up state. When the digital domain circuit is in the sleep state, the power is cut off, which reduces the power consumption of the digital domain circuit compared with the power consumption of the digital domain circuit in the sleep state in related technologies. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a power supply control circuit provided in an embodiment of this application;

[0017] Figure 2 This is a schematic diagram of a power supply control circuit provided in an embodiment of this application;

[0018] Figure 3 This is a schematic diagram of a wake-up unit provided in an embodiment of this application;

[0019] Figure 4 This is a flowchart of the steps of a power supply control method provided in an embodiment of this application.

[0020] Figure label:

[0021] 10-Power Management Module; 11-First Bandgap Reference Chip; 12-Low Dropout Linear Regulator; 13-Second Bandgap Reference Chip; 20-Control Module; 21-Power-On Reset Chip; 22-First Voltage Converter; 23-Control Submodule; 231-Second Voltage Converter; 232-Wake-up Unit; 2321-Counting Accumulator Subunit; 24-First AND Gate Device; 25-Clock Oscillator; 30-Digital Domain Circuit; U1-Register; U2-Comparator; U3-Counter; U4-Accumulator. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0024] Reference Figure 1 This application provides a power supply control circuit, including a power management module 10 and a control module 20. The power management module 10 is connected to the control module 20, and the power management module 10 is used to connect to a digital domain circuit 30 in a power supply and controller. The control module 20 is used to connect to the digital domain circuit 30, and when a sleep signal is received from the digital domain circuit 30, to stop the power management module 10 from supplying power to the digital domain circuit 30, and after a preset time, to supply power to the digital domain circuit 30.

[0025] In some embodiments, the digital domain circuit 30 generates a sleep signal in response to an external command and sends it to the control module 20.

[0026] In some embodiments, the controller type includes a microcontroller unit (MCU), a single-chip microcomputer, or other types of chips.

[0027] In some embodiments, the controller includes analog domain circuitry and digital domain circuitry 30. The analog domain circuitry includes multiple analog devices (e.g., analog-to-digital converters) that process analog signals. The digital domain circuitry 30 includes multiple digital devices (e.g., logic gates) that process digital signals.

[0028] In some embodiments, the control module 20 is also connected to a power source that supplies power to the devices in the power management module 10 and the devices in the control module 20.

[0029] In this embodiment, when the control module 20 receives a sleep signal from the digital domain circuit 30, it causes the power management module 10 to stop supplying power to the digital domain circuit 30, thereby putting the digital domain circuit 30 into a sleep state. Then, after a preset time, the control module 20 causes the power management module 10 to supply power to the digital domain circuit 30, so as to switch the digital domain circuit 30 from a sleep state to a wake-up state. When the digital domain circuit 30 is in a sleep state, the power is cut off. Compared with the power consumption of the digital domain circuit 30 in a sleep state in related technologies, the power consumption of the digital domain circuit 30 is reduced.

[0030] Optionally, in some embodiments, the control module 20 includes a power-on reset chip 21, a first voltage converter 22, a control submodule 23, and a first AND gate device 24; the first input terminal of the power-on reset chip 21 is connected to the output terminal of the power management module 10, and the first output terminal of the power-on reset chip 21 is connected to the enable terminal of the first voltage converter 22; the input terminal of the first voltage converter 22 is connected to the sleep signal terminal of the digital domain circuit 30, and the output terminal of the first voltage converter 22 is connected to the first input terminal of the first AND gate device 24; the input terminal of the control submodule 23 is connected to the timing signal terminal of the digital domain circuit 30, and the output terminal of the control submodule 23 is connected to the second input terminal of the first AND gate device 24; the output terminal of the first AND gate device 24 is connected to the enable terminal of the power management module 10.

[0031] In this embodiment, since the first input terminal of the power-on reset chip 21 is connected to the output terminal of the power management module 10, the first input terminal of the power-on reset chip 21 is used to detect the power supply signal. When the power management module 10 outputs the power supply signal, the power management module 10 supplies power to the digital domain circuit 30, the digital domain circuit 30 is in a wake-up state, and the first input terminal of the power-on reset chip 21 is at a high level. When the power management module 10 stops outputting the power supply signal, the power management module 10 stops supplying power to the digital domain circuit 30, the digital domain circuit 30 is in a sleep state, and the first input terminal of the power-on reset chip 21 is at a low level.

[0032] When the first input terminal of the power-on reset chip 21 is at a high level, the first output terminal of the power-on reset chip 21 is at a high level; when the first input terminal of the power-on reset chip 21 is at a low level, the first output terminal of the power-on reset chip 21 is at a low level.

[0033] Since the first output terminal of the power-on reset chip 21 is connected to the enable terminal of the first voltage converter 22, the state of the first voltage converter 22 can be controlled through the first output terminal of the power-on reset chip 21. Since the input terminal of the first voltage converter 22 is connected to the sleep signal terminal of the digital domain circuit 30, the sleep signal sent by the digital domain circuit 30 can be received through the input terminal of the first voltage converter 22. Since the output terminal of the first voltage converter 22 is connected to the first input terminal of the first AND gate device 24, the output signal of the first AND gate device 24 can be adjusted through the output terminal of the first voltage converter 22. Therefore, when the enable terminal of the first voltage converter 22 is high, the voltage conversion function of the first voltage converter 22 is enabled, that is, the voltage of the sleep signal received by the input terminal of the first voltage converter 22 can be boosted and output by the output terminal of the first voltage converter 22. When the enable terminal of the first voltage converter 22 is low, the voltage conversion function of the first voltage converter 22 is disabled, and the output terminal of the first voltage converter 22 is locked at a high level.

[0034] Since the input terminal of the control submodule 23 is connected to the timing signal terminal of the digital domain circuit 30, the timing signal representing the preset duration sent by the digital domain circuit 30 can be received through the input terminal of the control submodule 23.

[0035] Since the output of the control submodule 23 is connected to the second input of the first AND gate device 24, the output signal of the first AND gate device 24 can be adjusted through the output of the control submodule 23.

[0036] Optionally, in some embodiments, when the power management module 10 supplies power to the digital domain circuit 30, the first output terminal of the power-on reset chip 21 is at a high level, causing the output terminal of the first voltage converter 22 to output the sleep signal; the sleep signal is at a high level; when the power management module 10 stops supplying power to the digital domain circuit 30, the first output terminal of the power-on reset chip 21 is at a low level, causing the output terminal of the first voltage converter 22 to be at a high level; the control submodule 23 is used to acquire a preset duration represented by the timing signal when it receives a timing signal sent by the timing signal terminal of the digital domain circuit 30, and within the preset duration, make the output terminal of the control submodule 23 at a high level, and after the preset duration, make the output terminal of the control submodule 23 at a low level; when the output terminal of the first AND gate device 24 is at a high level, the power management module 10 supplies power to the digital domain circuit 30; when the output terminal of the first AND gate device 24 is at a low level, the power management module 10 stops supplying power to the digital domain circuit 30.

[0037] In some embodiments, the digital domain circuit 30 responds to an external command, generates a timing signal, and sends it to the control submodule 23.

[0038] In this embodiment, when the power management module 10 supplies power to the digital domain circuit 30, the first output of the power-on reset chip 21 is at a high level, causing the output of the first voltage converter 22 to output a sleep signal. Since the sleep signal is at a high level, the first input of the first AND gate device 24 is at a high level. When the power management module 10 stops supplying power to the digital domain circuit 30, the first output of the power-on reset chip 21 is at a low level, causing the output of the first voltage converter 22 to be at a high level. Thus, the first input of the first AND gate device 24 is at a high level.

[0039] Since the control submodule 23 acquires the preset duration represented by the timing signal sent by the timing signal terminal of the digital domain circuit 30, and makes the output terminal of the control submodule 23 high level within the preset duration, the second input terminal of the first AND gate device 24 is high level; since the control submodule 23 makes the output terminal of the control submodule 23 low level after the preset duration, the second input terminal of the first AND gate device 24 is low level.

[0040] Since the power management module 10 supplies power to the digital domain circuit 30 when the output of the first AND gate 24 is high and stops supplying power to the digital domain circuit 30 when the output of the first AND gate 24 is low, within a preset time period after the control module 20 obtains the sleep signal and the timing signal, the first input of the first AND gate 24 is high and the second input of the first AND gate 24 is high, so the output of the first AND gate 24 is high and the power management module 10 supplies power to the digital domain circuit 30; after the preset time period, the first input of the first AND gate 24 is high and the second input of the first AND gate 24 is low, so the output of the first AND gate 24 is low and the power management module 10 stops supplying power to the digital domain circuit 30.

[0041] Optionally, in some embodiments, the control submodule 23 includes a second voltage converter 231 and a wake-up unit 232; the enable terminal of the second voltage converter 231 is connected to the first output terminal of the power-on reset chip 21, the input terminal of the second voltage converter 231 is connected to the timing signal terminal of the digital domain circuit 30, and the output terminal of the second voltage converter 231 is connected to the first input terminal of the wake-up unit 232. The second voltage converter 231 is used to output the timing signal when the first output terminal of the power-on reset chip 21 is at a high level; the output terminal of the wake-up unit 232 is connected to the second input terminal of the first AND gate device 24. The wake-up unit 232 is used to acquire a preset duration represented by the timing signal when the timing signal is acquired, and within the preset duration, make the output terminal of the wake-up unit 232 at a high level, and after the preset duration, make the output terminal of the wake-up unit 232 at a low level.

[0042] In this embodiment, since the enable terminal of the second voltage converter 231 is connected to the first output terminal of the power-on reset chip 21, the state of the second voltage converter 231 can be controlled through the first output terminal of the power-on reset chip 21. Since the input terminal of the second voltage converter 231 is connected to the timing signal terminal of the digital domain circuit 30, the timing signal can be received through the input terminal of the second voltage converter 231. When the enable terminal of the second voltage converter 231 is high, the voltage conversion function of the second voltage converter 231 is enabled, that is, the second voltage converter 231 can boost the voltage of the timing signal received at the input terminal of the second voltage converter 231 and output it through the output terminal of the second voltage converter 231. When the enable terminal of the second voltage converter 231 is low, the voltage conversion function of the second voltage converter 231 is disabled, and the output terminal of the second voltage converter 231 is locked at a low level. The locked level of the output terminal of the second voltage converter 231 is opposite to the locked level of the output terminal of the first voltage converter 22.

[0043] Therefore, when the power management module 10 supplies power to the digital domain circuit 30, the first output terminal of the power-on reset chip 21 is at a high level, causing the first voltage converter 22 to boost the voltage of the sleep signal and output it when it receives the sleep signal, and causing the second voltage converter 231 to boost the voltage of the timing signal and output it when it receives the timing signal; when the power management module 10 stops supplying power to the digital domain circuit 30, the first output terminal of the power-on reset chip 21 is at a low level, causing the output terminal of the first voltage converter 22 to be at a high level, and causing the output terminal of the second voltage converter 231 to be at a low level.

[0044] Since the output terminal of the second voltage converter 231 is connected to the first input terminal of the wake-up unit 232, the first input terminal of the wake-up unit 232 can receive the timing signal output by the output terminal of the second voltage converter 231. Since the output terminal of the wake-up unit 232 is connected to the second input terminal of the first AND gate device 24, and the wake-up unit 232 obtains the preset duration represented by the timing signal when it obtains the timing signal, and within the preset duration, makes the output terminal of the wake-up unit 232 high, so that the second input terminal of the first AND gate device 24 is high. After the preset duration, the output terminal of the wake-up unit 232 is low, so that the second input terminal of the first AND gate device 24 is low.

[0045] Optionally, in some embodiments, the wake-up unit 232 includes a counting and accumulating subunit 2321, a register U1, and a comparator U2; the output of the counting and accumulating subunit 2321 is connected to the first input of the comparator U2, and the counting and accumulating subunit 2321 is used to output an accumulated value and receive a clock signal, and increment the accumulated value by one in each clock cycle of the clock signal; the input of the register U1 is connected to the output of the second voltage converter 231, and the output of the register U1 is connected to the second input of the comparator U2, and the register U1 is used to output the value of the preset duration; the output of the comparator U2 is connected to the second input of the first AND gate device 24, and the comparator U2 is used to output a high level when the value of the preset duration is greater than the accumulated value, and to output a low level when the value of the preset duration is equal to or less than the accumulated value.

[0046] In some embodiments, the accumulated value is initialized to zero.

[0047] In some embodiments, register U1 is also used to store a value of a preset duration, for example, a value of the preset duration representing 180 seconds.

[0048] In this embodiment, the counting and accumulating subunit 2321 outputs the accumulated value and receives a clock signal. In each clock cycle of the clock signal, the accumulated value is incremented by one, and a value of a preset duration is output through register U1. If the value of the preset duration is greater than the accumulated value, the comparator U2 outputs a high level, making the second input terminal of the first AND gate device 24 high. Then, if the value of the preset duration is equal to or less than the accumulated value, the comparator U2 outputs a low level, making the second input terminal of the first AND gate device 24 low.

[0049] Optionally, in some embodiments, the counting and accumulating subunit 2321 includes a counter U3 and an accumulator U4; the output terminal of the counter U3 is connected to the input terminal of the accumulator U4, the counter U3 is used to receive the clock signal, and output a counting signal in each clock cycle; the output terminal of the accumulator U4 is connected to the first input terminal of the comparator U2, the accumulator U4 is used to output the accumulated value, and increment the accumulated value by one each time the counting signal is obtained.

[0050] In some embodiments, the reset signal terminal of the digital domain circuit 30 is connected to the first input terminal of the second AND gate device, the second output terminal of the power-on reset chip 21 is connected to the second input terminal of the second AND gate device, the output terminal of the second AND gate device is connected to the reset terminal of the wake-up unit 232, the reset terminal of the wake-up unit 232 is connected to the reset terminal of the counting and accumulating subunit 2321 and the reset terminal of the register U1, and the reset terminal of the counting and accumulating subunit 2321 is connected to the reset terminal of the counter U3 and the reset terminal of the accumulator U4, respectively.

[0051] When the digital domain circuit 30 is powered on, that is, when the power management module 10 supplies power to the digital domain circuit 30, the reset signal terminal of the digital domain circuit 30 outputs a reset signal, which is low level; when the digital domain circuit 30 is powered off, that is, when the power management module 10 stops supplying power to the digital domain circuit 30, the reset signal terminal of the digital domain circuit 30 is high level.

[0052] When the power supply is on the power-on reset chip 21, the second output terminal of the power-on reset chip 21 is at a high level; when the power supply is off, the second output terminal of the power-on reset chip 21 is at a low level.

[0053] In some embodiments, when the reset terminal of the wake-up unit 232 is at a low level, the data in the counter U3 is reset to zero, the data in the accumulator U4 is reset to zero (i.e., the accumulated value is initialized to zero), and the data in the register U1 is reset to zero; when the reset terminal of the wake-up unit 232 is at a high level, the counter U3, the accumulator U4, and the register U1 are not reset.

[0054] In some embodiments, the enable signal terminal of the digital domain circuit 30 is connected to the input terminal of the third voltage converter, the output terminal of the third voltage converter is connected to the clock enable terminal of the counter U3, and the enable terminal of the third voltage converter is connected to the first output terminal of the power-on reset chip 21.

[0055] When the power management module 10 supplies power to the digital domain circuit 30, the enable signal terminal of the digital domain circuit 30 outputs an enable signal, which is at a high level. The enable terminal of the third voltage converter is also at a high level, and the voltage conversion function of the third voltage converter is enabled. This means the third voltage converter can boost the voltage of the enable signal received at its input terminal and output it from its output terminal. When the power management module 10 stops supplying power to the digital domain circuit 30, the enable terminal of the third voltage converter is at a low level, and the voltage conversion function of the third voltage converter is disabled. At this time, the output terminal of the third voltage converter is locked at a high level.

[0056] When the clock enable pin of counter U3 is high, the counting function of counter U3 is enabled, and counter U3 outputs a counting signal in each clock cycle. When the clock enable pin of counter U3 is low, the counting function of counter U3 is disabled, and counter U3 stops counting.

[0057] In this embodiment of the application, a clock signal is received by a counter U3, and a counting signal is output in each clock cycle. The accumulated value is then output by an accumulator U4. The accumulated value is incremented by one each time a counting signal is received. The comparator U2 outputs a high level when the value for a preset duration is greater than the accumulated value, and outputs a low level when the value for a preset duration is equal to or less than the accumulated value.

[0058] Optionally, in some embodiments, the control module 20 further includes a clock oscillator 25; the output of the clock oscillator 25 is connected to the input of the counting and accumulating subunit 2321, and the clock oscillator 25 is used to generate the clock signal.

[0059] In some embodiments, the clock signal is a low-frequency clock signal.

[0060] In some embodiments, the input terminal of the clock oscillator 25 is connected to the second output terminal of the second bandgap reference chip 13, and the second output terminal of the second bandgap reference chip 13 is used to output a bias current so that the clock oscillator 25 can generate a clock signal.

[0061] In this embodiment of the application, a clock signal is generated and output by a clock oscillator 25 so that the counter U3 can receive the clock signal and output a counting signal in each clock cycle.

[0062] Optionally, in some embodiments, the power management module 10 includes a first bandgap reference chip 11 and a low dropout linear regulator 12; the power supply terminal of the first bandgap reference chip 11 is connected to the power supply, the output terminal of the first bandgap reference chip 11 is connected to the input terminal of the low dropout linear regulator 12, and the enable terminal of the first bandgap reference chip 11 is connected to the output terminal of the control module 20.

[0063] The power supply terminal of the low dropout linear regulator 12 is used to connect to the power supply, the output terminal of the low dropout linear regulator 12 is connected to the first input terminal of the control module 20 and the power supply terminal of the digital domain circuit 30 respectively, and the enable terminal of the low dropout linear regulator 12 is connected to the output terminal of the control module 20.

[0064] When the output of the control module 20 is at a high level, the first bandgap reference chip 11 outputs a first reference signal, and the low dropout linear regulator 12 outputs a power supply signal according to the first reference signal; when the output of the control module 20 is at a low level, the first bandgap reference chip 11 stops outputting the first reference signal, and the low dropout linear regulator 12 stops outputting the power supply signal.

[0065] In some embodiments, the first bandgap reference chip 11 is used to output a first reference signal with a stable voltage.

[0066] In this embodiment, when the output of the control module 20 is at a high level, the first bandgap reference chip 11 outputs a first reference signal, and then the low dropout linear regulator 12 outputs a power supply signal according to the first reference signal, so that the power management module 10 supplies power to the digital domain circuit 30; when the output of the control module 20 is at a low level, the first bandgap reference chip 11 stops outputting the first reference signal, and the low dropout linear regulator 12 stops outputting the power supply signal, so that the power management module 10 stops supplying power to the digital domain circuit 30.

[0067] Optionally, in some embodiments, the output terminal of the first bandgap reference chip 11 is also connected to the second input terminal of the control module 20; the control module 20 is specifically used to cause the power management module 10 to stop supplying power to the digital domain circuit 30 when the voltage of the power supply signal is greater than the voltage of the first reference signal and the sleep signal is obtained, and to cause the power management module 10 to supply power to the digital domain circuit 30 after the preset time.

[0068] In some embodiments, the output terminal of the first bandgap reference chip 11 is also connected to the second input terminal of the power-on reset chip 21. Specifically, the power-on reset chip 21 is used to make the second output terminal of the power-on reset chip 21 high level when the voltage of the power supply is greater than the voltage of the first reference signal, and to make the second output terminal of the power-on reset chip 21 low level when the voltage of the power supply is less than or equal to the voltage of the first reference signal.

[0069] In this embodiment, when the voltage of the power supply signal is greater than the voltage of the first reference signal and a sleep signal is obtained, the control module 20 causes the power management module 10 to stop supplying power to the digital domain circuit 30, thereby putting the digital domain circuit 30 into a sleep state. After a preset time, the control module 20 causes the power management module 10 to supply power to the digital domain circuit 30, so as to realize the switching of the digital domain circuit 30 from the sleep state to the wake-up state.

[0070] Optionally, in some embodiments, the power management module 10 further includes a second bandgap reference chip 13; the power supply terminal of the second bandgap reference chip 13 is connected to the power supply, the first output terminal of the second bandgap reference chip 13 is connected to the third input terminal of the control module 20, and the first output terminal of the second bandgap reference chip 13 is used to output a second reference signal; the control module 20 is further configured to, when the voltage of the power supply signal is greater than the voltage of the second reference signal and the sleep signal is obtained, cause the power management module 10 to stop supplying power to the digital domain circuit 30, and after the preset time, cause the power management module 10 to supply power to the digital domain circuit 30.

[0071] In some embodiments, the first output terminal of the second bandgap reference chip 13 is also connected to the third input terminal of the power-on reset chip 21. Specifically, the power-on reset chip 21 is used to make the second output terminal of the power-on reset chip 21 high level when the voltage of the power supply is greater than the voltage of the second reference signal, and to make the second output terminal of the power-on reset chip 21 low level when the voltage of the power supply is less than or equal to the voltage of the second reference signal.

[0072] In this embodiment, a second reference signal is output from the first output terminal of the second bandgap reference chip 13. Then, when the voltage of the power supply signal is greater than the voltage of the second reference signal and a sleep signal is obtained, the control module 20 causes the power management module 10 to stop supplying power to the digital domain circuit 30, thereby putting the digital domain circuit 30 into a sleep state. After a preset time, the control module 20 causes the power management module 10 to supply power to the digital domain circuit 30, so as to realize the switching of the digital domain circuit 30 from the sleep state to the wake-up state.

[0073] In some embodiments, the power-on reset chip 21 is specifically used to make the first output terminal of the power-on reset chip 21 high level when the voltage of the power supply signal is greater than the voltage of the first reference signal, and to make the first output terminal of the power-on reset chip 21 low level when the voltage of the power supply signal is less than or equal to the voltage of the first reference signal.

[0074] In some embodiments, the power-on reset chip 21 is specifically used to make the first output terminal of the power-on reset chip 21 high level when the voltage of the power supply signal is greater than the voltage of the second reference signal, and to make the first output terminal of the power-on reset chip 21 low level when the voltage of the power supply signal is less than or equal to the voltage of the second reference signal.

[0075] In some embodiments, after the power supply is powered on, the voltage of the power supply gradually increases, the second bandgap reference chip 13 provides bias current to the clock oscillator 25, the clock oscillator 25 starts to work and outputs a clock signal, and at the same time the second bandgap reference chip 13 provides a second reference signal to the power-on reset chip 21. When the voltage of the power supply is less than or equal to the voltage of the second reference signal, the second output terminal of the power-on reset chip 21 is at a low level, and the wake-up unit 232 is in a reset state. When the voltage of the power supply is greater than the voltage of the second reference signal, the second output terminal of the power-on reset chip 21 is at a high level, the wake-up unit 232 is released and is in a normal working state.

[0076] At this time, the output of the wake-up unit 232 is low. Regardless of whether the sleep signal is high or low, after the wake-up signal and the sleep signal pass through the first AND gate device 24, the first AND gate device 24 outputs a low level, and the first bandgap reference chip 11 and the low dropout linear regulator 12 start normally. The first bandgap reference chip 11 provides a stable first reference signal for the main low dropout linear regulator 12 and the power-on reset chip 21. The low dropout linear regulator 12 outputs a stable voltage signal (i.e., power supply signal) with a certain load-carrying capacity to power the digital domain circuit 30.

[0077] After the low-dropout linear regulator 12 outputs a stable power supply signal, the first output of the power-on reset chip 21 is at a low level. This is the power-on reset trigger stage of the digital domain circuit 30, ensuring its correct initialization. After a certain period, the first output of the power-on reset chip 21 goes high, and the digital domain circuit 30 returns to normal operation. The digital domain circuit 30 then sends a default low-level signal through the first voltage converter 22. At this time, both the first and second inputs of the first AND gate device 24 are at low levels, so the output of the first AND gate device 24 is low, and the digital domain circuit 30 operates normally. Specifically, when the first output of the power-on reset chip 21 is low, the first voltage converter 22 locks its output to a high level, and the second voltage converter 231 locks its output to a low level.

[0078] In some embodiments, after power-on, the second output of the power-on reset chip 21 is low, at which time the wake-up unit 232 is in a reset state, and the data in counter U3, accumulator U4, and register U1 are all zero. Comparator U2 compares the data in accumulator U4 with the data in register U1. Since the data in accumulator U4 is equal to the data in register U1, the output of comparator U2 is low. The enable signal terminal of the digital domain circuit 30 outputs an enable signal. When the first output of the power-on reset chip 21 is low, the output of the third voltage converter is locked at a high level.

[0079] After the second output of the power-on reset chip 21 goes high, the power-on reset of the wake-up unit 232 ends, and the counter U3 starts counting. Until the rising edge of the first counting pulse of the counter U3 output counting signal, i.e., within the first counting pulse cycle, the data in the accumulator U4 is equal to the data in the register U1 and is still zero. At this time, the output of the wake-up unit 232 is still low. Then, the first output of the power-on reset chip 21 changes from low to high, and the digital domain circuit 30 completes the power-on reset. After the digital domain circuit 30 starts, it resets the wake-up unit 232, resetting the data in the counter U3, accumulator U4, and register U1 to zero, and making the clock enable terminal of the counter U3 low, further reducing power consumption. At this time, the wake-up unit 232 does not work and its output remains low.

[0080] In some embodiments, when the digital domain circuit 30 needs to enter sleep mode from normal operation, the digital domain circuit 30 first writes the timing data for the next wake-up (i.e., data of a preset duration) to register U1 in the wake-up unit 232 through the second voltage converter 231. At this time, since the data in the accumulator U4 is different from the data in the register U1, the output of the comparator U2 is high. At this time, the first input of the first AND gate device 24 is low and the second input of the first AND gate device 24 is high. Therefore, the output of the first AND gate device 24 is low, and the digital domain circuit 30 sends an enable signal to the wake-up unit 232 through the third voltage converter. Counter U3 starts counting. The wake-up unit 232 consumes only tens of nanoamps of current during normal counting. Then, the digital domain circuit 30 sends a high-level sleep signal through the first voltage converter 22. At this time, the first input terminal of the first AND gate device 24 is at a high level and the second input terminal of the first AND gate device 24 is at a high level. Therefore, the output terminal of the first AND gate device 24 is at a high level. The first bandgap reference chip 11 and the low dropout linear regulator 12 are turned off. The first output terminal of the power-on reset chip 21 becomes low level. The supply voltage of the digital domain power supply slowly drops to zero. At the same time, the output terminal of the first voltage converter 22 is locked at a high level, maintaining the sleep state of the digital domain circuit 30.

[0081] At this time, due to the power-on, the second output of the power-on reset chip 21 remains at a high level, and the wake-up unit 232 is not reset and works normally until the data in the accumulator U4 in the wake-up unit 232 is equal to the timing data pre-written in the register U1. At this time, the output of the wake-up unit 232 becomes low level, the first input of the first AND gate device 24 is high level and the second input of the first AND gate device 24 is low level, so the output of the first AND gate device 24 is low level, the first bandgap reference chip 11 and the low dropout linear regulator 12 are restarted, the voltage of the power supply signal gradually rises to a stable level, and the first output of the power-on reset chip 21 also becomes high level, releasing the digital domain circuit 30. The digital domain circuit 30 enters the normal working state, and at the same time, the sleep signal terminal of the digital domain circuit 30 returns to the default low level.

[0082] The embodiments of this application enable complete power-off when the digital domain circuit 30 enters sleep mode, reducing the use of at least one LDO and thus reducing the circuit board area and power consumption of the controller. The embodiments of this application can also reuse the wake-up circuit in the controller; therefore, the wake-up circuit used does not increase the circuit board area of ​​the controller, and the wake-up circuit consumes only tens of nanoamperes of current during normal counting operation, resulting in extremely low power consumption.

[0083] In summary, in this embodiment, when the control module 20 receives a sleep signal from the digital domain circuit 30, it causes the power management module 10 to stop supplying power to the digital domain circuit 30, thereby putting the digital domain circuit 30 into a sleep state. Then, after a preset time, the control module 20 causes the power management module 10 to supply power to the digital domain circuit 30, thereby switching the digital domain circuit 30 from a sleep state to a wake-up state. Furthermore, when the digital domain circuit 30 is in a sleep state, the power is cut off. Compared with the power consumption of the digital domain circuit 30 in a sleep state in related technologies, this reduces the power consumption of the digital domain circuit 30.

[0084] Figure 4 This application provides a power supply control method, applied to the aforementioned power supply control circuit, such as... Figure 4 As shown, the method may include:

[0085] Step 101: Upon receiving the sleep signal and the timing signal, power off the digital domain circuit 30 and obtain the preset duration represented by the timing signal.

[0086] The implementation method for this step is similar to the aforementioned process, and will not be repeated here.

[0087] Step 102: After the preset time, the digital domain circuit 30 is energized.

[0088] The implementation method for this step is similar to the aforementioned process, and will not be repeated here.

[0089] In this embodiment, the digital domain circuit 30 is powered off when a sleep signal and a timing signal are received, thereby putting the digital domain circuit 30 into a sleep state. The timing signal represents a preset duration, and then after the preset duration, the digital domain circuit 30 is powered on to switch from a sleep state to a wake-up state. Furthermore, the digital domain circuit 30 is powered off while in a sleep state. Compared with the power consumption of the digital domain circuit 30 in a sleep state in related technologies, this reduces the power consumption of the digital domain circuit 30.

[0090] This application also provides a controller, including the power supply control circuit as described above, or the steps of implementing the power supply control method as described above.

[0091] The specific implementation process of the power supply control circuit in the controller is similar to that described above, and will not be repeated here.

[0092] In related technologies, the power management module includes multiple low-dropout linear regulators, which power the digital domain circuits. The controller has a large circuit board area and high power consumption.

[0093] In this embodiment, the power management module 10 includes a low-dropout linear regulator 12, which powers the digital domain circuit 30, reducing the number of low-dropout linear regulators 12 and thus reducing the circuit board area and power consumption of the controller.

[0094] In summary, when the control module 20 receives the sleep signal sent by the digital domain circuit 30, it causes the power management module 10 to stop supplying power to the digital domain circuit 30, thereby putting the digital domain circuit 30 into a sleep state. Then, after a preset time, the control module 20 causes the power management module 10 to supply power to the digital domain circuit 30, thereby switching the digital domain circuit 30 from a sleep state to a wake-up state. Furthermore, when the digital domain circuit 30 is in a sleep state, it is powered off. Compared with the power consumption of the digital domain circuit 30 in a sleep state in related technologies, this reduces the power consumption of the digital domain circuit 30.

[0095] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0096] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A power supply control circuit, characterized in that, include: Power management module (10) and control module (20); The power management module (10) is connected to the control module (20), and the power management module (10) is used to connect to the digital domain circuit (30) in the power supply and controller; The control module (20) is used to connect to the digital domain circuit (30), and when a sleep signal is received from the digital domain circuit (30), the power management module (10) stops supplying power to the digital domain circuit (30), and after a preset time, the power management module (10) supplies power to the digital domain circuit (30). The control module (20) includes a power-on reset chip (21), a first voltage converter (22), a control submodule (23), and a first AND gate device (24). The first input terminal of the power-on reset chip (21) is connected to the output terminal of the power management module (10), and the first output terminal of the power-on reset chip (21) is connected to the enable terminal of the first voltage converter (22). The input terminal of the first voltage converter (22) is connected to the sleep signal terminal of the digital domain circuit (30), and the output terminal of the first voltage converter (22) is connected to the first input terminal of the first AND gate device (24). The input terminal of the control submodule (23) is connected to the timing signal terminal of the digital domain circuit (30), and the output terminal of the control submodule (23) is connected to the second input terminal of the first AND gate device (24); the control submodule (23) includes a second voltage converter (231) and a wake-up unit (232). The output terminal of the first AND gate device (24) is connected to the enable terminal of the power management module (10); The enable terminal of the second voltage converter (231) is connected to the first output terminal of the power-on reset chip (21), the input terminal of the second voltage converter (231) is connected to the timing signal terminal of the digital domain circuit (30), and the output terminal of the second voltage converter (231) is connected to the first input terminal of the wake-up unit (232). The second voltage converter (231) is used to output the timing signal when the first output terminal of the power-on reset chip (21) is high. The output terminal of the wake-up unit (232) is connected to the second input terminal of the first AND gate device (24). The wake-up unit (232) is used to acquire the preset duration represented by the timing signal when the timing signal is acquired, and to make the output terminal of the wake-up unit (232) high level within the preset duration, and to make the output terminal of the wake-up unit (232) low level after the preset duration.

2. The power supply control circuit according to claim 1, characterized in that, When the power management module (10) supplies power to the digital domain circuit (30), the first output terminal of the power-on reset chip (21) is at a high level, causing the output terminal of the first voltage converter (22) to output the sleep signal; the sleep signal is at a high level; when the power management module (10) stops supplying power to the digital domain circuit (30), the first output terminal of the power-on reset chip (21) is at a low level, causing the output terminal of the first voltage converter (22) to be at a high level; The control submodule (23) is used to acquire a preset duration represented by the timing signal when the timing signal sent by the timing signal terminal of the digital domain circuit (30) is acquired, and to make the output terminal of the control submodule (23) high level within the preset duration, and to make the output terminal of the control submodule (23) low level after the preset duration. When the output of the first AND gate (24) is high, the power management module (10) supplies power to the digital domain circuit (30); when the output of the first AND gate (24) is low, the power management module (10) stops supplying power to the digital domain circuit (30).

3. The power supply control circuit according to claim 1, characterized in that, The wake-up unit (232) includes a counting and accumulating subunit (2321), a register (U1), and a comparator (U2); The output of the counting and accumulating subunit (2321) is connected to the first input of the comparator (U2). The counting and accumulating subunit (2321) is used to output the accumulated value and receive a clock signal, and increment the accumulated value by one in each clock cycle of the clock signal. The input terminal of the register (U1) is connected to the output terminal of the second voltage converter (231), and the output terminal of the register (U1) is connected to the second input terminal of the comparator (U2). The register (U1) is used to output the value of the preset duration. The output of the comparator (U2) is connected to the second input of the first AND gate device (24). The comparator (U2) is used to output a high level when the value of the preset duration is greater than the accumulated value, and to output a low level when the value of the preset duration is equal to or less than the accumulated value.

4. The power supply control circuit according to claim 3, characterized in that, The counting and accumulating subunit (2321) includes a counter (U3) and an accumulator (U4); The output of the counter (U3) is connected to the input of the accumulator (U4). The counter (U3) is used to receive the clock signal and output a count signal in each clock cycle. The output of the accumulator (U4) is connected to the first input of the comparator (U2). The accumulator (U4) is used to output the accumulated value and increment the accumulated value by one each time the counting signal is acquired.

5. The power supply control circuit according to claim 4, characterized in that, The control module (20) also includes a clock oscillator (25); The output of the clock oscillator (25) is connected to the input of the counting and accumulating subunit (2321), and the clock oscillator (25) is used to generate the clock signal.

6. The power supply control circuit according to claim 1, characterized in that, The power management module (10) includes a first bandgap reference chip (11) and a low dropout linear regulator (12). The power supply terminal of the first bandgap reference chip (11) is used to connect to the power supply, the output terminal of the first bandgap reference chip (11) is connected to the input terminal of the low dropout linear regulator (12), and the enable terminal of the first bandgap reference chip (11) is connected to the output terminal of the control module (20). The power supply terminal of the low dropout linear regulator (12) is used to connect to the power supply. The output terminal of the low dropout linear regulator (12) is connected to the first input terminal of the control module (20) and the power supply terminal of the digital domain circuit (30) respectively. The enable terminal of the low dropout linear regulator (12) is connected to the output terminal of the control module (20). When the output of the control module (20) is at a high level, the first bandgap reference chip (11) outputs a first reference signal, and the low-dropout linear regulator (12) outputs a power supply signal according to the first reference signal; when the output of the control module (20) is at a low level, the first bandgap reference chip (11) stops outputting the first reference signal, and the low-dropout linear regulator (12) stops outputting the power supply signal.

7. The power supply control circuit according to claim 6, characterized in that, The output terminal of the first bandgap reference chip (11) is also connected to the second input terminal of the control module (20); The control module (20) is specifically used to cause the power management module (10) to stop supplying power to the digital domain circuit (30) when the voltage of the power supply signal is greater than the voltage of the first reference signal and the sleep signal is obtained, and to cause the power management module (10) to supply power to the digital domain circuit (30) after the preset time.

8. The power supply control circuit according to claim 7, characterized in that, The power management module (10) also includes a second bandgap reference chip (13). The power supply terminal of the second bandgap reference chip (13) is used to connect to the power supply, the first output terminal of the second bandgap reference chip (13) is connected to the third input terminal of the control module (20), and the first output terminal of the second bandgap reference chip (13) is used to output a second reference signal. The control module (20) is further configured to, when the voltage of the power supply signal is greater than the voltage of the second reference signal and the sleep signal is obtained, cause the power management module (10) to stop supplying power to the digital domain circuit (30), and after the preset time, cause the power management module (10) to supply power to the digital domain circuit (30).

9. A power supply control method, characterized in that, The method, applied to a power supply control circuit as described in any one of claims 1 to 8, comprises: Upon receiving the sleep signal and the timing signal, the digital domain circuit (30) is powered off, and the preset duration represented by the timing signal is obtained; After the preset time period, the digital domain circuit (30) is energized.

10. A controller, characterized in that, Includes the power supply control circuit as described in any one of claims 1 to 8, or implements the power supply control method as described in claim 9.

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