NVMe-based SSD ultra-high data rate large-capacity acquisition and storage system

Abstract

This invention relates to an NVMe-based SSD-based high-data-rate, high-capacity data acquisition and storage system. The system includes a transmission module, a storage module, and a control module. The transmission module has USB and optical interfaces for data transmission and reception. The storage module includes RAM and at least two SSDs configured with an NVMe storage architecture, capable of splitting data packets into multiple parallel writes to multiple SSDs, utilizing RAM buffering to handle SSD latency. The control module's processor can switch system function modes and control the transmission and storage modules based on these modes. The processor employs an FPGA architecture with PCIe hard core resources, utilizing it to configure multiple independent PCIe Gen4x4 interfaces. The FPGA acts as the root complex, directly enumerating and managing the SSDs. The system also employs specific data fragmentation algorithms, striping strategies, and read path technologies, offering multiple function modes to adapt to different business needs. This system solves the problems of limited transmission bandwidth, insufficient storage capacity, and single operating modes in traditional data acquisition systems.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and more specifically, to an NVMe-based SSD-based high-data-rate, high-capacity acquisition and storage system. Background Technology

[0002] In an era of rapid development in information technology, the performance requirements for data acquisition and storage systems in fields such as aerospace, industrial IoT, 5G communications, and scientific observation are growing exponentially. Traditional data acquisition systems face numerous challenges and struggle to meet the demands of modern applications for high data rates and large-capacity storage.

[0003] Traditional data acquisition systems typically struggle to achieve acquisition rates exceeding 10GB / s per board. When multi-channel expansion is required, system performance is often limited by bus protocols and architecture design. For example, systems using PCIe buses are prone to data congestion and transmission delays during multi-channel data acquisition due to bandwidth limitations. Storage units often employ fixed redundancy, making it difficult to balance the dual requirements of flexible capacity expansion and data security. Traditional systems typically use SATA or SAS interface hard drives for data storage; these interfaces have limited bandwidth, failing to fully utilize the potential of high-performance solid-state drives (SSDs). Furthermore, expanding capacity in fixed-redundancy storage systems requires downtime for hardware upgrades or replacements, which is impractical in many application scenarios.

[0004] Existing systems typically only support single real-time processing or offline batch processing modes, failing to dynamically adapt to the multi-tasking requirements of complex scenarios. For example, in the aerospace field, data acquisition systems need to simultaneously support multiple functions such as real-time data transmission, data storage, and data playback. Traditional systems, due to their fixed operating modes, cannot flexibly switch functions, severely restricting the effective utilization of high-value data.

[0005] To address the limitations of traditional data acquisition and storage systems, this invention aims to design an ultra-high data rate, high-capacity acquisition and storage system based on NVMe SSDs. By employing an advanced NVMe storage architecture, high-performance FPGA control, and multi-mode functional design, this system effectively solves problems such as limited transmission bandwidth, insufficient storage capacity, and single operating mode, meeting the demands of modern high data rate and high-capacity storage applications. Summary of the Invention

[0006] The present invention aims to solve at least one of the aforementioned technical problems existing in the prior art.

[0007] Therefore, this invention provides an NVMe-based SSD-based high-data-rate, high-capacity acquisition and storage system.

[0008] This invention provides an NVMe-based SSD-based ultra-high data rate, large-capacity acquisition and storage system, comprising:

[0009] The transmission module has a USB interface and an optical interface, used to receive external data and transmit data to the host computer.

[0010] The storage module includes a RAM memory and at least two SSD hard drives configured in an NVMe storage architecture. In the NVMe storage architecture, data packets are split into N paths and written in parallel to N SSD hard drives, with the RAM memory serving as a write buffer to handle the instantaneous latency of the SSD hard drives.

[0011] The control module includes a processor, which is used to switch the functional modes of the storage system and control the transmission module and the storage module based on the functional modes; wherein the functional modes are the data flow direction, storage method and transmission method configured under different business requirements.

[0012] The NVMe-based SSD-based high data rate, large-capacity acquisition and storage system according to the above-described technical solution of the present invention may also have the following additional technical features:

[0013] In the above technical solution, the processor adopts an FPGA architecture configured with PCIe hard core resources;

[0014] By utilizing the PCIe hard core resources of the FPGA, N independent PCIe Gen4x4 interfaces are configured, with each SSD hard drive connected to one corresponding PCIe Gen4x4 interface, achieving independent control of the entire bandwidth;

[0015] The FPGA acts as the root complex, directly enumerating and managing SSDs via the PCIe protocol.

[0016] In the above technical solution, the FPGA-based GTY transceiver supports the PCIe Gen4x4 interface;

[0017] Each PCIe Gen4x4 interface requires individual impedance matching, with a differential impedance of 85Ω.

[0018] The insertion loss of each PCIe Gen4x4 interface is less than 28dB@8GHz;

[0019] Striped writing is implemented using the FPGA's built-in RAID controller, where data is distributed and stored across multiple SSDs via striped writing.

[0020] In the above technical solution, the write path of the NVMe storage architecture includes:

[0021] By using data fragmentation, the input data stream is split into 64KB blocks.

[0022] Determine the SSD hard disk index, allocate the SSD hard disk index once every 16 LBAs, and determine the SSD hard disk to be written for each 64KB data block;

[0023] The calculation method for the target logical block address on the target SSD includes:

[0024] target_lba=(lba / 64)*16+(lba%16)

[0025] Write buffering is implemented using RAM memory cache, which temporarily stores data blocks in RAM memory cache;

[0026] A dual-bank ping-pong operation method is used to control concurrency in the cache, thereby improving write efficiency;

[0027] Each SSD controller independently handles DMA transfers, transferring data from the cache to the corresponding SSD.

[0028] Use the AXI4-Stream interface to achieve cross-clock domain synchronization and ensure correct data transmission.

[0029] In the above technical solution, the read path of the NVMe storage architecture includes:

[0030] Initiate a read request, using a multi-path aggregation method to initiate N read requests in parallel;

[0031] Data reading and recombination: The read data is timestamped, which is used to reassemble the data and ensure the correct data order.

[0032] Each data block is appended with a CRC32 checksum to detect whether the data is corrupted;

[0033] If a data error is detected, a single disk reread operation is triggered to reread the data block.

[0034] The read data is sent out via USB or optical interface.

[0035] In the above technical solution, the value of N is 4.

[0036] In the above technical solution, the processor is also configured with an additional PCIe Gen4x4 interface as an expansion interface;

[0037] The expansion interface is used to cascade another identical storage system to improve storage speed.

[0038] In the above technical solution, the optical interface is provided by a 100G optical module QSFP, and the USB interface is provided by a 10GUSB chip FX10.

[0039] In the above technical solution, the functional modes include:

[0040] The first functional mode is used for low-bandwidth real-time transmission with a data bandwidth of less than 1GB / s, transmitting the real-time data received by the optical interface to the host computer via the USB interface; the data flow of the first functional mode is: QSFP→FPGA→FX10→USB→host computer.

[0041] The second functional mode is used for low-bandwidth offline reading with a data bandwidth of less than 1GB / s, transferring data from the SSD to the host computer via the USB interface; the data flow in the second functional mode is: SSD → FPGA → FX10 → USB → host computer;

[0042] The third functional mode is used for low-bandwidth real-time transmission and storage of data with a bandwidth of less than 1GB / s. The real-time data received by the optical interface is transmitted to the host computer via the USB interface and stored in the SSD hard drive. The data flow of the third functional mode is: QSFP→FPGA→FX10→USB→host computer and QSFP→FPGA→memory.

[0043] The fourth functional mode is used for high-bandwidth storage with a data bandwidth greater than 1GB / s, storing the real-time data received by the optical interface in the SSD hard disk; the data flow of the fourth functional mode is: QSFP→FPGA→memory;

[0044] The fifth functional mode is used for high-bandwidth real-time storage and sampling transmission of data with a bandwidth greater than 1GB / s. The real-time data received by the optical interface is stored in the SSD hard drive and then sampled and transmitted to the host computer in real time through the USB chip path. The data flow of the fifth functional mode is: QSFP→FPGA→Memory and QSFP→FPGA→FX10→USB→Host computer. Among them, the bandwidth of the data transmitted to the host computer after sampling is less than 1GB / s.

[0045] The sixth function mode is used for data playback, where the FPGA reads data from the SSD and outputs it through the optical interface.

[0046] In the above technical solution, the method of switching the function mode includes adjustment via onboard DIP switch or real-time control via USB interface.

[0047] In summary, due to the adoption of the above-mentioned technical features, the beneficial effects of the present invention are:

[0048] The NVMe-based SSD ultra-high data rate large-capacity acquisition and storage system of the present invention has significant advantages in terms of data transmission speed, storage capacity, functional flexibility, data reliability and cost-effectiveness, and can effectively meet the urgent needs of modern information technology for high-performance data acquisition and storage systems.

[0049] Based on this invention, for applications with data volumes smaller than 1GB / s, data can be transmitted to a host computer in real time for online preview, or stored in real time for long-term storage. For applications with data volumes greater than 1GB / s, data can be stored in real time in a large-capacity NVMe SSD on the board, achieving a maximum storage speed of 13GB / s, or extracted and transmitted to a host computer. By cascading another identical device through an expansion interface, a data recording speed of 25GB / s can be achieved.

[0050] Specifically, this invention adopts NVMe standard SSD hard drives and configures N independent PCIe Gen4x4 interfaces. It uses FPGA as the root complex to directly enumerate and manage SSD devices, giving full play to the high-speed transmission advantage of PCIe Gen4. This greatly improves the data writing and reading speed, and can meet the needs of ultra-high data rate acquisition and storage. For example, in the massive data transmission scenario in the 5G communication field, it can achieve rapid data landing.

[0051] By employing a RAID 0 striping write strategy, data is distributed across multiple SSDs, which not only improves the parallelism of data writing and reading but also enables flexible expansion of storage capacity. The number of SSDs can be increased according to actual needs without requiring large-scale modifications to the existing storage architecture, reducing the cost and complexity of storage capacity upgrades. This makes it suitable for long-duration, high-volume data acquisition tasks in fields such as aerospace.

[0052] Additional aspects and advantages of the invention will become apparent in the following description or may be learned by practice of the invention. Attached Figure Description

[0053] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0054] Figure 1 This is a schematic diagram of a module of an NVMe-based SSD ultra-high data rate large-capacity acquisition and storage system according to an embodiment of the present invention;

[0055] Figure 2 This is a schematic diagram of the hardware architecture of an NVMe-based SSD-based ultra-high data rate, large-capacity acquisition and storage system according to an embodiment of the present invention. Detailed Implementation

[0056] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0057] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0058] The following reference Figure 1 and Figure 2 This describes an NVMe-based SSD-based high-data-rate, high-capacity acquisition and storage system provided according to some embodiments of the present invention.

[0059] Some embodiments of this application provide an NVMe-based SSD-based ultra-high data rate, large-capacity acquisition and storage system.

[0060] like Figure 1 As shown, the first embodiment of the present invention proposes an NVMe-based SSD ultra-high data rate large-capacity acquisition and storage system, including: a transmission module, a storage module and a control module.

[0061] The transmission module has a USB interface and an optical interface for receiving external data and transmitting data to the host computer; Figure 1 In the illustrated embodiment, the transmission module is schematically represented as a receiving unit and a sending unit. The receiving unit selects to receive USB data, fiber optic data, or not receive data under the control of the control module according to the functional mode. The sending unit communicates with the host computer or other devices to perform data interaction.

[0062] The storage module includes a RAM memory and at least two SSD hard drives configured in an NVMe storage architecture. In the NVMe storage architecture, data packets are split into N paths and written in parallel to N SSD hard drives. The RAM memory is used as a write buffer to cope with the instantaneous latency of the SSD hard drives. In this disclosure, an example of N being 4 is used for illustration. It can be understood that for a conventional SSD hard drive with a single capacity of 8TB, a basic storage unit of 32TB can be built based on the settings of this disclosure, and it can be seamlessly expanded to a capacity of 64TB, while being compatible with RAID0 / RAID1 disk array storage modes.

[0063] The control module includes a processor, which switches the functional modes of the storage system and controls the transmission and storage modules based on these modes. The functional modes are configured to control data flow, storage methods, and transmission methods under different business requirements. Specifically, the control module can perform interface control, functional mode switching, and storage control. The processor-running system can also establish a data record netlist to manage the writing and reading of data streams.

[0064] Specifically, the processor adopts an FPGA architecture with PCIe hard core resources; utilizing the FPGA's PCIe hard core resources, four independent PCIe Gen4x4 interfaces (a total of 16 lanes) are configured, with each SSD hard drive connected to one corresponding PCIe Gen4x4 interface to achieve independent control of the entire bandwidth (theoretical bandwidth of 7.8GB / s per disk); the FPGA acts as the root complex (RC) and directly enumerates and manages the SSD hard drives through the PCIe protocol.

[0065] like Figure 2 As shown, the system hardware includes a USB chip, an optical module, a processor, an SSD hard drive, and RAM. In one specific embodiment, the USB chip can be an EZ-USB. TM The FX10 uses a 100GBASE-LR4QSFP28 optical module, an Intel Agilex 5SOC series FPGA chip A5ED051A processor, an 8TB SSD from a certain brand, and 16GB of DDR4 RAM. It is understood that the above hardware configuration is for illustrative purposes only, and those skilled in the art can choose other models / brands of hardware with similar performance as needed.

[0066] In some embodiments, the physical layer of the NVMe storage architecture is designed as follows: the FPGA's GTY transceiver supports the PCIe Gen4x4 interface; each PCIe Gen4x4 interface is individually impedance matched, requiring a differential impedance of 85Ω; the insertion loss of each PCIe Gen4x4 interface is less than 28dB@8GHz; and striped writing is implemented using the FPGA's built-in RAID controller, wherein data is distributed and stored across multiple SSDs through striped writing.

[0067] In some embodiments, the write path of the NVMe storage architecture includes:

[0068] By using data fragmentation, the input data stream is split into 64KB blocks.

[0069] Determine the SSD disk index, allocating the SSD disk index every 16 LBAs, and determine the SSD disk to be written to for each 64KB data block. This can be represented as:

[0070] ssd_index=(LBA / 16)%4

[0071] ssd_index represents the index of the SSD disk corresponding to the current data block; LBA represents the logical block address;

[0072] The calculation method for the target logical block address on the target SSD includes:

[0073] target_lba=(LBA / 64)*16+(LBA%16)

[0074] target_lba represents the target logical block address of the current data block on the target SSD hard disk;

[0075] Write buffering is implemented using RAM memory cache, which temporarily stores data blocks in RAM memory cache;

[0076] A dual-bank ping-pong operation method is used to control concurrency in the cache, thereby improving write efficiency;

[0077] Each SSD controller independently handles DMA transfers, transferring data from the cache to the corresponding SSD.

[0078] Use the AXI4-Stream interface to achieve cross-clock domain synchronization and ensure correct data transmission.

[0079] In some embodiments, the read path of the NVMe storage architecture includes:

[0080] Initiate a read request, using a multi-path aggregation method to initiate 4 read requests in parallel;

[0081] Data reading and recombination: The read data is timestamped, which is used to reassemble the data and ensure the correct data order.

[0082] Each data block is appended with a CRC32 checksum to detect whether the data is corrupted;

[0083] If a data error is detected, a single disk reread operation is triggered to reread the data block.

[0084] The read data is sent out via USB or optical interface.

[0085] Continue reading Figure 2 In some embodiments, the processor is also configured with an additional PCIe Gen4x4 interface as an expansion interface;

[0086] The expansion interface is used to cascade another identical storage system to improve storage speed. In this embodiment, it can achieve a data recording scenario of 25GB / s.

[0087] Specifically, two 100Gbps QSFP28 modules (4×25G channels) are used, with the FPGA integrating a 100Gbps Ethernet IP core to achieve data distribution. The local storage is 13GB / s (4×NVMe), and the cascaded output is 12GB / s to the next level device.

[0088] In some embodiments, the functional modes include:

[0089] The first functional mode is used for low-bandwidth real-time transmission with a data bandwidth of less than 1GB / s, transmitting the real-time data received by the optical interface to the host computer via the USB interface; the data flow of the first functional mode is: QSFP→FPGA→FX10→USB→host computer.

[0090] The second functional mode is used for low-bandwidth offline reading with a data bandwidth of less than 1GB / s, transferring data from the SSD to the host computer via the USB interface; the data flow in the second functional mode is: SSD → FPGA → FX10 → USB → host computer;

[0091] The third functional mode is used for low-bandwidth real-time transmission and storage of data with a bandwidth of less than 1GB / s. The real-time data received by the optical interface is transmitted to the host computer via the USB interface and stored in the SSD hard drive. The data flow of the third functional mode is: QSFP→FPGA→FX10→USB→host computer and QSFP→FPGA→memory.

[0092] The fourth functional mode is used for high-bandwidth storage with a data bandwidth greater than 1GB / s, storing the real-time data received by the optical interface in the SSD hard disk; the data flow of the fourth functional mode is: QSFP→FPGA→memory;

[0093] The fifth functional mode is used for high-bandwidth real-time storage and sampling transmission of data with a bandwidth greater than 1GB / s. The real-time data received by the optical interface is stored in the SSD hard drive and then sampled and transmitted to the host computer in real time through the USB chip path. The data flow of the fifth functional mode is: QSFP→FPGA→Memory and QSFP→FPGA→FX10→USB→Host computer. Among them, the bandwidth of the data transmitted to the host computer after sampling is less than 1GB / s.

[0094] The sixth function mode is used for data playback. The FPGA reads data from the SSD and outputs it via the optical interface. It supports rate control (1GB / s~10GB / s) and loop playback mode. Protocol compatibility: encapsulated as UDP / IP or a custom high-speed protocol.

[0095] The USB interface mentioned above can be a USB 3.2 interface, with a peak data bandwidth of 13GB / s in high-bandwidth mode.

[0096] In some embodiments, the method for switching the function mode can be to adjust it via an onboard DIP switch; in other embodiments, the method for switching the function mode can also be to control it in real time via a USB interface.

[0097] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0098] Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this invention shall be included within the scope of protection of this invention.

Claims

1. A high-data-rate, high-capacity acquisition and storage system based on NVMe SSDs, characterized in that, include: The transmission module has a USB interface and an optical interface, used to receive external data and transmit data to the host computer. A storage module includes RAM memory and at least two SSD hard drives configured as NVMe storage architecture; In the NVMe storage architecture, data packets are split into N paths and written in parallel to N SSDs, with RAM as a write buffer to handle the instantaneous latency of the SSDs. The control module includes a processor, which is used to switch the functional modes of the storage system and control the transmission module and the storage module based on the functional modes; wherein, the functional modes are the data flow direction, storage method and transmission method configured under different business requirements; The functional modes include: The first functional mode is used for low-bandwidth real-time transmission with a data bandwidth of less than 1GB / s, transmitting the real-time data received by the optical interface to the host computer via the USB interface; the data flow of the first functional mode is: QSFP→FPGA→FX10→USB→host computer. The second functional mode is used for low-bandwidth offline reading with a data bandwidth of less than 1GB / s, transferring data from the SSD to the host computer via the USB interface; the data flow in the second functional mode is: SSD → FPGA → FX10 → USB → host computer; The third functional mode is used for low-bandwidth real-time transmission and storage of data with a bandwidth of less than 1GB / s. The real-time data received by the optical interface is transmitted to the host computer via the USB interface and stored in the SSD hard drive. The data flow of the third functional mode is: QSFP→FPGA→FX10→USB→host computer and QSFP→FPGA→memory. The fourth functional mode is used for high-bandwidth storage with a data bandwidth greater than 1GB / s, storing the real-time data received by the optical interface in the SSD hard disk; the data flow of the fourth functional mode is: QSFP→FPGA→memory; The fifth functional mode is used for high-bandwidth real-time storage and sampling transmission of data with a bandwidth greater than 1GB / s. The real-time data received by the optical interface is stored in the SSD hard drive and then sampled and transmitted to the host computer in real time through the USB chip path. The data flow of the fifth functional mode is: QSFP→FPGA→Memory and QSFP→FPGA→FX10→USB→Host computer. Among them, the bandwidth of the data transmitted to the host computer after sampling is less than 1GB / s. The sixth function mode is used for data playback, where the FPGA reads data from the SSD and outputs it through the optical interface.

2. The NVMe-based SSD ultra-high data rate large-capacity acquisition and storage system according to claim 1, characterized in that, The processor adopts an FPGA architecture with PCIe hard core resources; By utilizing the PCIe hard core resources of the FPGA, N independent PCIe Gen4x4 interfaces are configured, with each SSD hard drive connected to a corresponding PCIe Gen4x4 interface, achieving independent control of the entire bandwidth. The FPGA acts as the root complex, directly enumerating and managing SSDs via the PCIe protocol.

3. The NVMe-based SSD ultra-high data rate large-capacity acquisition and storage system according to claim 2, characterized in that, The GTY transceiver using an FPGA supports the PCIe Gen4x4 interface; Each PCIe Gen4x4 interface requires individual impedance matching, with a differential impedance of 85Ω. The insertion loss of each PCIe Gen4x4 interface is less than 28dB@8GHz; Striped writing is implemented using the FPGA's built-in RAID controller, where data is distributed and stored across multiple SSDs via striped writing.

4. The NVMe-based SSD ultra-high data rate large-capacity acquisition and storage system according to claim 3, characterized in that, The write path of the NVMe storage architecture includes: By using data fragmentation, the input data stream is split into 64KB blocks. Determine the SSD hard disk index, allocate the SSD hard disk index once every 16 LBAs, and determine the SSD hard disk to be written for each 64KB data block; The calculation method for the target logical block address on the target SSD includes: target_lba=(lba / 64)*16+(lba%16) Write buffering is implemented using RAM memory cache, which temporarily stores data blocks in RAM memory cache; A dual-bank ping-pong operation method is used to control concurrency in the cache, thereby improving write efficiency; Each SSD controller independently handles DMA transfers, transferring data from the cache to the corresponding SSD. Use the AXI4-Stream interface to achieve cross-clock domain synchronization and ensure correct data transmission.

5. The NVMe-based SSD ultra-high data rate large-capacity acquisition and storage system according to claim 4, characterized in that, The read path of the NVMe storage architecture includes: Initiate a read request, using a multi-path aggregation method to initiate N read requests in parallel; Data reading and recombination: The read data is timestamped, which is used to reassemble the data and ensure the correct data order. Each data block is appended with a CRC32 checksum to detect whether the data is corrupted; If a data error is detected, a single disk reread operation is triggered to reread the data block. The read data is sent out via USB or optical interface.

6. The NVMe-based SSD ultra-high data rate large-capacity acquisition and storage system according to claim 1, characterized in that, The value of N is 4.

7. The NVMe-based SSD ultra-high data rate large-capacity acquisition and storage system according to claim 2, characterized in that, The processor is also configured with an additional PCIe Gen4x4 interface as an expansion interface; The expansion interface is used to cascade another identical storage system to improve storage speed.

8. The NVMe-based SSD ultra-high data rate large-capacity acquisition and storage system according to claim 2, characterized in that, The optical interface is provided by a 100G optical module QSFP, and the USB interface is provided by a 10GUSB chip FX10.

9. The NVMe-based SSD ultra-high data rate large-capacity acquisition and storage system according to claim 8, characterized in that, The method for switching the function mode includes adjusting via an onboard DIP switch or controlling in real time via a USB interface.

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