Driving circuit and display panel

Abstract

The application provides a driving circuit and a display panel, a gate driving circuit of the driving circuit comprises a stage transmission circuit, an output circuit and an output frequency division circuit, the output circuit is electrically connected with the stage transmission circuit, the output frequency division circuit is connected between the stage transmission circuit and the output circuit, the output circuit is electrically connected with at least one clock signal line, the clock signal lines connected by adjacent two-stage gate driving circuits are different, and in each clock signal line, the width between the starting moments of adjacent two active levels is greater than or equal to the product of the width of the active level and 8; the application increases the width between adjacent two active levels in each clock signal line, increases the width between the ripples caused by the jump of the clock signal, avoids the non-overlapping of the data writing stage of the pixel driving circuit in the display panel and the ripple, eliminates the influence of the ripple on the sub-pixel, avoids the abnormal phenomenon of the frequency division boundary in the frequency switching area, and improves the display effect of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to driving circuits and display panels. Background Technology

[0002] OLED (Organic Light-Emitting Diode) display panels are widely used due to their flexibility and other characteristics.

[0003] In current OLED display panels, different refresh rates are typically used to drive different display areas in order to reduce the power consumption of the display panel. However, when different display areas of the display panel are displayed at different display frequencies at the same time, the frequency switching area will have abnormal frequency division boundary, which will lead to display abnormalities of the display panel. Summary of the Invention

[0004] This invention provides a driving circuit and a display panel to address the technical problem of display abnormalities in existing frequency-division display panels.

[0005] This invention provides a driving circuit, including a frequency division signal line and a plurality of cascaded gate driving circuits. The frequency division signal line is used to transmit a frequency division control signal to the plurality of gate driving circuits. The gate driving circuit includes:

[0006] The stage transmission circuit includes a stage transmission receiving circuit and a stage transmission output circuit. The stage transmission receiving circuit is used to receive the stage transmission signal generated by the gate driving circuit of the previous stage. The stage transmission output circuit is electrically connected to the stage transmission receiving circuit through a first node and a second node, and is used to output the stage transmission signal of this stage to the gate driving circuit of the next stage according to the signal of the first node and the signal of the second node.

[0007] An output circuit, electrically connected to the stage output circuit via one of the first node, the second node, and the third node, is used to output a gate control signal based on the signal from one of the first node, the second node, and the signal from the third node; and

[0008] The stage transmission frequency division circuit is electrically connected to the stage transmission receiving circuit through the first node or the second node, and electrically connected to the stage transmission output circuit through the fourth node. It is used to control the signal of one of the first node and the second node according to the frequency division control signal, so as to control the stage transmission output circuit to output the stage transmission signal of this stage.

[0009] An output frequency divider circuit is connected between the first node, the second node, and the third node, and is used to control the signal of the third node according to the frequency divider control signal, so as to control the output circuit to output the gate control signal of this stage.

[0010] This application increases the width between two adjacent active levels in each clock signal line, thereby increasing the width between ripples caused by clock signal transitions. This prevents the data writing stage of the pixel driving circuit in the display panel from not overlapping with the ripple, eliminates the influence of ripple on sub-pixels, avoids abnormal frequency division boundaries in the frequency switching area, and improves the display effect of the display panel. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the display panel structure of this application.

[0013] Figure 2 This is a structural diagram of the pixel driving circuit in the display panel of this application.

[0014] Figure 3 for Figure 2 Timing diagram of the mid-pixel driving circuit.

[0015] Figure 4 This is a structural diagram of the gate driving group in the display panel of this application.

[0016] Figure 5 for Figure 4 The first structural diagram of the third gate drive circuit.

[0017] Figure 6 for Figure 4 The second structural diagram of the third gate drive circuit.

[0018] Figure 7 for Figure 5 The first timing diagram of the third gate drive circuit.

[0019] Figure 8 This is a structural diagram of the gate drive group in the prior art.

[0020] Figure 9 for Figure 8 Timing diagram of the gate drive circuit within the middle gate drive group.

[0021] Figure 10 for Figure 5 The second timing diagram of the third gate drive circuit.

[0022] Figure 11 for Figure 4 The third structure diagram of the third gate drive circuit. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0024] Please see Figure 1 The display panel 100 includes a display area AA and a non-display area NA adjacent to the display area AA. A display unit 200 is provided within the display area AA. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is enclosed by the non-display area NA. The display area AA is the area within the display panel 100 used for display functions, and it contains multiple sub-pixels Pi that perform their display functions. The non-display area NA may be a border area of ​​the display panel 100, and it may contain functional components that assist the sub-pixels Pi within the display area AA in displaying information.

[0025] Please see Figure 1 A bonding terminal 400 is provided on the lower side of the display area AA. The bonding terminal 400 can be connected to an external circuit and transmits the signal input from the external circuit to the data trace, thereby driving the display panel 100 to display the image. For example, the bonding terminal 400 can be bonded to a chip or a flip-chip film to provide power and drive signals to the display panel 100.

[0026] In this embodiment, multiple light-emitting devices (LEDs) and pixel driving circuits 302 for driving the LEDs can be arrayed within the display area AA. The pixel driving circuits 302 can be 7T1C, 7T2C, 8T2C, etc. (The following section will use...) Figure 2 The pixel driving circuit 302 in the example will be used for illustration.

[0027] exist Figure 1 In the structure, a driving circuit 30 is provided in the non-display area NA. The driving circuit 30 includes multiple cascaded gate driving circuits 20. The gate control signal output by the gate driving circuit 20 is transmitted to the gate of multiple transistors in the corresponding multiple pixel driving circuits 302 via the corresponding scan lines, such as the first scan line EML1, the second scan line NDL1, the third scan line PSL, the fourth scan line NSL2, and the fifth scan line EML2.

[0028] Please see Figure 2The pixel driving circuit 302 may include a data transistor M2, the source of which is loaded with a data signal Vdata, the drain of which is electrically connected to the source of the driving transistor M1, and the gate of the data transistor M2 (e.g., a P-type transistor) may be electrically connected to the third scan line PSL to load the PScan signal.

[0029] The pixel driving circuit 302 may further include a reset transistor M4 and a compensation transistor M3. The gate of the reset transistor M4 (e.g., an N-type transistor) may be electrically connected to the scan line NSL1 to load the NScan1 signal. The reset transistor M4 is configured to transmit the reset signal VI1 to the gate of the driving transistor M1 for reset. The gate of the compensation transistor M3 (e.g., an N-type transistor) may be electrically connected to the fourth scan line NSL2 to load the NScan2 signal. The source and drain of the compensation transistor M3 are electrically connected to the drain and gate of the driving transistor M1, respectively.

[0030] The pixel driving circuit 302 may further include an initialization transistor M7. The gate of the initialization transistor M7 (e.g., a P-type transistor) is electrically connected to the fifth scan line EML2 to load the EM2 signal. The drain of the initialization transistor M7 is electrically connected to one end of the light-emitting device 301 (the other end of the light-emitting device 301 may be loaded with a low-voltage signal VSS). The initialization transistor M7 is configured to transmit the initialization signal VI2 to one end of the light-emitting device 301 for initialization.

[0031] The pixel driving circuit 302 also includes a reset transistor M8. The gate of the reset transistor M8 (e.g., a P-type transistor) can be electrically connected to the fifth scan line EML2 to load the EM2 signal. The drain of the reset transistor M8 is electrically connected to the source of the driving transistor M1. The reset transistor M8 is configured to transmit the reset signal VI3 to the source of the driving transistor M1 to reset its voltage.

[0032] The pixel driving circuit 302 may further include a first light-emitting control transistor M5 and a second light-emitting control transistor M6. The source of the first light-emitting control transistor M5 is loaded with a first high voltage VDD, and the drain of the first light-emitting control transistor M5 is electrically connected to the source of the driving transistor M1. The source and drain of the second light-emitting control transistor M6 are electrically connected to the drain of the driving transistor M1 and one end of the light-emitting device 301, respectively. The gates of both the first light-emitting control transistor M5 and the second light-emitting control transistor M6 (e.g., both are P-type transistors) are electrically connected to the first scan line EML1 to load the EM1 signal. Both are configured to control the light-emitting time of the light-emitting device 301 according to the EM1 signal.

[0033] The pixel driving circuit 302 also includes a storage capacitor Cst, which is connected in series between the source of the first light-emitting control transistor M5 and the gate of the driving transistor M1.

[0034] The pixel driving circuit 302 also includes a boost capacitor Cboost, which is connected in series between the gate of the driving transistor M1 and the gate of the data transistor M2.

[0035] exist Figure 1 In the structure, the non-display area includes a first sub-area NA1 and a second sub-area NA2 located on both sides of the display unit. The first sub-area NA1 is equipped with a Pscan driving circuit 110, a first Nscan driving circuit 121, and an EM signal source 130. The second sub-area NA2 is equipped with a Pscan driving circuit 110, a second Nscan driving circuit 122, and an EM signal source 130. The Pscan driving circuit 110 is a dual-drive circuit, and its output terminal is connected to the third scan line PSL. The Nscan driving circuit is a single-drive circuit. The output terminal of the first Nscan driving circuit 121 can be connected to the fourth scan line NSL2, and the output terminal of the second Nscan driving circuit 122 can be connected to the second scan line NSL1. The EM signal source 130 can be connected to the first scan line EML1 and the fifth scan line EML2.

[0036] Please see Figure 3 , Figure 3 for Figure 2 Timing diagram of the pixel driving circuit 302. In the gate driving circuit 20, due to the transition of the clock signal, ripple appears in the scan signal output by the gate driving circuit 20. For example, the fourth scan line NSL2 will have ripple during the transition of the clock signal. The fourth scan line NSL2 is electrically connected to the gate of the compensation transistor M3. Figure 3 In the structure, the ripple stage of the fourth scan line NSL2 coincides with the writing stage of the third scan line PSL, which causes the gate potential of the driving transistor M1 to fluctuate. When the signal output by the fourth scan line NSL2 is too high, the gate potential of the driving transistor M1 is too high, and the brightness of the light-emitting device LED is too dim. When the signal output by the fourth scan line NSL2 is too low, the gate potential of the driving transistor M1 is too low, and the brightness of the light-emitting device LED is too bright, thus causing the technical problem of uneven display.

[0037] Please see Figure 4 , Figure 4This is a structural diagram of the driving circuit 30 of this application. The driving circuit 30 includes a frequency divider signal line FDL, multiple clock signal lines, and multiple gate drive groups 500. Each gate drive group 500 includes multiple cascaded gate drive circuits 20. The frequency divider signal line FDL is used to transmit the frequency divider control signal FD to the multiple gate drive circuits 20, such as... Figure 5 and Figure 6 As shown, the gate drive circuit 20 may include:

[0038] The stage transmission circuit 201 includes a stage transmission receiving circuit 2011 and a stage transmission output circuit 2012. The stage transmission receiving circuit 2011 is used to receive the stage transmission signal generated by the upper-level gate driving circuit 20. The stage transmission output circuit 2012 is electrically connected to the stage transmission receiving circuit 2011 through a first node P and a second node Q, and is used to output the stage transmission signal of this stage to the lower-level gate driving circuit 20 according to the signal of the first node P and the signal of the second node Q.

[0039] Output circuit 202 is electrically connected to the first node P and the second node Q in the cascade circuit 201. Output circuit 202 outputs gate control signal according to the frequency division control signal FD, the signals of the first node P and the second node Q. Output circuit 202 is electrically connected to the clock signal line. The clock signal lines connected to the adjacent two gate drive circuits 20 are different.

[0040] The output frequency divider circuit 204 has one end connected to the output circuit 202 at the third node S, and the other end connected to the cascade circuit 201 at either the first node P or the second node Q. The output frequency divider circuit 204 controls the signal transmission between the first node P, the second node Q and the output circuit 202 according to the signal from the first node P or the second node Q and the frequency division control signal FD.

[0041] In this embodiment, the width of the active level in each clock signal line is H, and the width between the start times of two adjacent active levels is greater than or equal to 8H.

[0042] It should be noted that this application's Figures 4 to 6 The gate drive circuit 20 in the middle can be Figure 1 The Pscan and Nscan driving circuits in the following embodiments are used as examples. Figures 4 to 6 The gate driving circuit 20 is described using either the first Nscan driving circuit 121 or the second Nscan driving circuit 122 as an example, and multiple first Nscan driving circuits 121 or multiple second Nscan driving circuits 122 constitute a gate driving group 500.

[0043] This application increases the width between two adjacent effective levels in each clock signal line, thereby increasing the width between ripples caused by clock signal transitions. This prevents the data writing stage of the pixel driving circuit 302 in the display panel 100 from not overlapping with the ripple, eliminates the influence of ripple on sub-pixels Pi, avoids abnormal frequency division boundaries in the frequency switching area, and improves the display effect of the display panel 100.

[0044] It should be noted that each stage transmission circuit 201 connects to two different clock signal lines, and the four clock signal lines connected to adjacent stage transmission circuits 201 are all different. For example, the number of clock signal lines in this application can be equal to the number of gate drive circuits 20 in the gate drive group 500; in Figure 4 In the structure, each gate drive group 500 includes a first gate drive circuit 21, a second gate drive circuit 22, a third gate drive circuit 23, and a fourth gate drive circuit 24. The multiple clock signal lines include at least a first clock signal line CKL1, a second clock signal line CKL2, a third clock signal line CKL3, and a fourth clock signal line CKL4. Each gate drive circuit 20 can connect two clock signal lines. The first gate drive circuit 21 connects the first clock signal line CKL1 and the third clock signal line CKL3. The second gate drive circuit 22 connects the second clock signal line CKL2 and the fourth clock signal line CKL4. The third gate drive circuit 23 connects the first clock signal line CKL1 and the third clock signal line CKL3. The fourth gate drive circuit 24 connects the second clock signal line CKL2 and the fourth clock signal line CKL4.

[0045] exist Figure 4 In the structure, the width between the start times of two adjacent effective levels of the first clock signal line CKL1 and the start time of the effective level of the second clock signal line CKL2, the width between the start time of the effective level of the second clock signal line CKL2 and the start time of the effective level of the third clock signal line CKL3, and the width between the start time of the effective level of the third clock signal line CKL3 and the start time of the effective level of the fourth clock signal line CKL4 are all the product of the width of the effective level and 2.

[0046] For example, please see Figure 7With the effective level width of the clock signal line as H, the width between the start times of two adjacent effective levels of each clock signal line is 8H. The width between the start time of the effective level of the first clock signal line CKL1 and the start time of the effective level of the second clock signal line CKL2 is 2H. The width between the start time of the effective level of the second clock signal line CKL2 and the start time of the effective level of the third clock signal line CKL3 is 2H. The width between the start time of the effective level of the third clock signal line CKL3 and the start time of the effective level of the fourth clock signal line CKL4 is 2H. The width between the start time of the effective level of the fourth clock signal line CKL4 and the start time of the next effective level in the first clock signal line CKL1 is 2H.

[0047] It should be noted that each gate drive group 500 includes six cascaded gate drive circuits 20, and the multiple clock signal lines include six clock signal lines; or, for example, each gate drive group 500 includes eight cascaded gate drive circuits 20, and the multiple clock signal lines include eight clock signal lines. The more clock signal lines there are, the larger the width of two adjacent ripples on the fourth scan line NSL2; in the following embodiments, Figure 4 Let's take the structure of [example] as an example for explanation.

[0048] exist Figures 4 to 6 In the structure, each gate driving circuit 20 includes a first transistor T6 and a second transistor T4 connected in series; the gate of the first transistor T6 of the first gate driving circuit 21 is electrically connected to the first clock signal line CKL1, and the drain of the second transistor T4 of the first gate driving circuit 21 is electrically connected to the third clock signal line CKL3; the gate of the first transistor T6 of the second gate driving circuit 22 is electrically connected to the second clock signal line CKL2, and the drain of the second transistor T4 of the second gate driving circuit 22 is electrically connected to the fourth clock signal line CKL4; the gate of the first transistor T6 of the third gate driving circuit 23 is electrically connected to the third clock signal line CKL3, and the drain of the second transistor T4 of the third gate driving circuit 23 is electrically connected to the first clock signal line CKL1; the gate of the first transistor T6 of the fourth gate driving circuit 24 is electrically connected to the fourth clock signal line CKL4, and the drain of the second transistor T4 of the fourth gate driving circuit 24 is electrically connected to the second clock signal line CKL2.

[0049] exist Figures 4 to 6 In the structure, the driving circuit 30 also includes multiple high-potential lines spaced apart. The number of high-potential lines is the same as the number of gate driving circuits 20 in the gate driving group 500. The output circuit of one gate driving circuit 20 is connected to one high-potential line. In the gate driving group 500, the high-potential lines connected to any two gate driving circuits 20 are different.

[0050] exist Figures 4 to 6 In the structure, the output circuit 202 includes a first coupling capacitor C4, one end of which is connected to a high-potential line and the other end of which is connected to a third node S; meanwhile, in the gate drive group 500, the high-potential lines connected to any of the first coupling capacitors C4 are different.

[0051] It should be noted that since the ripple is generated following the transition of the clock signal, in addition to increasing the number of clock signal lines, it is also necessary to increase the number of high-potential lines so that the high-potential lines connected to any gate drive circuit 20 in the gate drive group 500 are different.

[0052] For example Figure 4 In the structure, the output circuit 202 also includes a first output transistor T22, and multiple high-potential lines including a first high-potential line Vgh1, a second high-potential line Vgh2, a third high-potential line Vgh3, and a fourth high-potential line Vgh4 arranged at intervals. The first coupling capacitor C4 of the first gate driving circuit 21 and the source of the first output transistor T22 are both electrically connected to the first high-potential line Vgh1. The first coupling capacitor C4 of the second gate driving circuit 22 and the source of the first output transistor T22 are both electrically connected to the second high-potential line Vgh2. The first coupling capacitor C4 of the third gate driving circuit 23 and the source of the first output transistor T22 are both electrically connected to the third high-potential line Vgh3. The first coupling capacitor C4 of the fourth gate driving circuit 24 and the source of the first output transistor T22 are both electrically connected to the fourth high-potential line Vgh4.

[0053] In this embodiment, the voltages of the first high-potential line Vgh1, the second high-potential line Vgh2, the third high-potential line Vgh3, and the fourth high-potential line Vgh4 can be equal.

[0054] Down Figure 5 and Figure 6 The structure of the gate drive circuit 20 of this application will be described using two circuit structure diagrams of the third gate drive circuit 23 as examples.

[0055] Specifically, Figure 4 A structural diagram of a gate drive group 500 is shown, namely the cascaded gate drive circuits 20 from the (i-2)th to the (i+1)th stage. Figure 5 and Figure 6 The i-th stage gate driving circuit 20 is used as an example for explanation. The i-th stage gate driving circuit 20 can generate and output the gate control signal Scan(i) of the current stage (i-th stage) according to the gate control signal Scan(i-1) of the (i-1)-th stage.

[0056] exist Figure 5 and Figure 6In the structure, the gate drive circuit 20 may further include a stage transmission frequency divider circuit 203. The stage transmission frequency divider circuit 203 is electrically connected to the stage transmission receiver circuit 2011 through a first node P or a second node Q, and is electrically connected to the stage transmission output circuit 2012 through a fourth node R. It is used to control the signal of one of the first node P and the second node Q according to the frequency division control signal FD, so as to control the stage transmission output circuit 2012 to output the stage transmission signal of this stage.

[0057] Understandably, while the signal of one of the first node P and the second node Q electrically connected to the stage output circuit 2012 remains unchanged, this embodiment provides a stage transmission frequency divider circuit 203 connected between the stage transmission receiving circuit 2011 and the stage transmission output circuit 2012. According to the frequency division control signal FD, the signal of the other of the first node P and the second node Q can be controlled (whether it can be acted upon by the fourth node R). This allows control over the signal transmitted to the stage output circuit 2012, thereby determining the specific situation of the stage transmission signal output by the stage output circuit 2012 (whether it has a valid stage transmission pulse). This determines whether it drives the next stage gate drive circuit 20. If the stage transmission signal has a valid stage transmission pulse, it can be considered that the stage transmission receiving circuit 2011 in the next stage gate drive circuit 20 can work normally. Similarly, the stage transmission frequency divider circuit 203 is used to determine the specific situation of the stage transmission signal output by the stage output circuit 2012.

[0058] On the other hand, this embodiment also includes an output frequency divider circuit 204 connected between one of the first node P, the second node Q and the third node S, so as to control the signal of the third node S according to the frequency divider control signal FD, thereby controlling the specific situation of the output circuit 202 outputting the gate control signal of this stage.

[0059] It is important to understand that for multiple gate driving circuits 20 cascaded in sequence, if the gate control signals output by the first part of the multiple gate driving circuits 20 all output a gate effective pulse once in one frame of every n1 frames, the gate control signals output by the second part of the multiple gate driving circuits 20 all output a gate effective pulse once in one frame of every n2 frames, and the gate control signals output by the third part of the multiple gate driving circuits 20 all output a gate effective pulse once in one frame of every n3 frames, then it can be considered that the three display areas formed by the three sub-pixels Pi corresponding to these three parts of the gate driving circuits 20 have three corresponding refresh rates of (1 / n1)*m, (1 / n2)*m, and (1 / n3)*m, respectively, where m is the least common multiple of n1, n2, and n3.

[0060] In summary, in this embodiment, the gate control signal used to determine the refresh rate of any display area of ​​the display panel 100 is directly determined by the corresponding output frequency divider circuit 204 and the frequency divider control signal FD at this time. One input terminal of the output frequency divider circuit 204 is connected to one of the first node P and the second node Q, and the other input terminal is connected to the third node S. The third node S is connected to the first node P or the second node Q through the cascade frequency divider circuit 203. That is, it can be considered that the signal of the third node S is jointly determined by the cascade frequency divider circuit 203 and the frequency divider control signal FD loaded onto the cascade frequency divider circuit 203. Therefore, the gate control signal is jointly determined by the cascade frequency divider circuit 203, the output frequency divider circuit 204, and the frequency divider control signal FD loaded onto the cascade frequency divider circuit 203 and the output frequency divider circuit 204. By reasonably setting these three elements, the refresh rate of the corresponding display area can be determined. Furthermore, the above three elements in the different gate drive circuits 20 corresponding to different display areas of the display panel 100 can be reasonably set to achieve different refresh rates respectively.

[0061] Please see Figures 4 to 6 The frequency division control signal FD includes a first frequency division signal FD1 and a second frequency division signal FD2. The frequency division signal line FDL includes a first frequency division signal line FDL1 for transmitting the first frequency division signal FD1 and a second frequency division signal line FDL2 for transmitting the second frequency division signal FD2. The first frequency division signal line FDL is electrically connected to the output frequency division circuit 204 to control the signal of the third node S. The second frequency division signal line FDL is electrically connected to the cascade frequency division circuit 203 to control the signal of one of the first node P and the second node Q.

[0062] Understandably, in this embodiment, by specifically setting the frequency division signal line FDL as an independent first frequency division signal line FDL and the first frequency division signal line FDL, independent first frequency division signal FD1 and second frequency division signal FD2 can be transmitted respectively, so as to independently control the working state of the output frequency division circuit 204 and the stage transmission frequency division circuit 203, thereby controlling the specific situation of the stage transmission signal and the gate signal generated by the gate drive circuit 20 of this stage respectively.

[0063] Please see Figures 4 to 6 The output frequency divider circuit 204 includes a first frequency divider transistor T18. The gate of the first frequency divider transistor T18 is connected to the first frequency divider signal line FDL. The source of the first frequency divider transistor T18 is electrically connected to the first node P or the second node Q. The drain of the control transistor is electrically connected to the third node S. The first frequency divider signal FD1 is used to control the electrical connection or disconnection between the third node S and the first node P or the second node Q. For example... Figure 5 The source of the first frequency divider transistor T18 is electrically connected to the first node P. Figure 6The source of the first frequency divider transistor T18 is electrically connected to the second node Q.

[0064] As discussed above, the first frequency division signal FD1 can be applied to the output frequency division circuit 204 to control whether the third node S is affected by the first node P or the second node Q. Furthermore, in this embodiment, it is explained that the first frequency division signal FD1 can be applied to the gate of the first frequency division transistor T18 in the output frequency division circuit 204 to control the electrical connection or disconnection between the third node S and the first node P or the second node Q.

[0065] Specifically, if electrically connected, the third node S can be considered to be acted upon by the first node P or the second node Q, which means that the signal of the first node P or the signal of the second node Q can control whether the gate control signal generated and output by the output circuit 202 has a gate effective pulse; if disconnected, the third node S cannot be acted upon by the first node P or the second node Q. Since neither the first node P nor the second node Q, which is used to control the generation of the stage transmission signal, can act on the output circuit 202, the gate control signal generated and output by the output circuit 202 can be considered to have no gate effective pulse.

[0066] Please see Figures 4 to 6 The output frequency divider circuit 204 also includes a second frequency divider transistor T20. The gate of the second frequency divider transistor T20 is electrically connected to the fifth node Z of the stage transmission circuit 201, the source of the second frequency divider transistor T20 is electrically connected to the first frequency divider signal line FDL, and the drain of the second frequency divider transistor T20 is electrically connected to the gate of the first frequency divider transistor T18. The first frequency divider signal FD1 and the signal of the fifth node Z are used to control the third node S to be electrically connected or disconnected from the first node P or the second node Q. The signal of the fifth node Z is also used to control the stage transmission signal and the gate control signal output by the gate drive circuit 20 of this stage.

[0067] Understandably, in this embodiment, a second frequency divider transistor T20 is further provided electrically connected to the gate of the first frequency divider transistor T18, and the turn-on state of the second frequency divider transistor T20 is determined by the signal of the fifth node Z. The signal of the fifth node Z is also used to control the stage transmission signal and the gate control signal output by this stage. That is, it can be considered that the state of the signal of the fifth node Z can reflect the state of both the stage transmission signal and the gate control signal of this stage. This ensures that the second frequency divider transistor T20 is turned on only when the state of both the stage transmission signal and the gate control signal generated by this stage is appropriate. This allows the first frequency divider signal FD1 to be transmitted to the gate of the first frequency divider transistor T18 of this stage to control the turn-on state of the first frequency divider transistor T18. This can achieve differentiated refresh rate settings for different display areas while ensuring that the output of the stage transmission signal and the gate control signal of each stage is the correct waveform.

[0068] Please see Figures 4 to 6 The cascade frequency divider circuit 203 includes a third frequency divider transistor T17, the gate of which is electrically connected to the second frequency divider signal line FDL. The source of the first frequency divider transistor T18 is electrically connected to the cascade receiver circuit 2011 through the fourth node R. The drain of the third frequency divider transistor T17 is electrically connected to the first node P or the second node Q. The second frequency divider signal FD2 is used to control the electrical connection or disconnection of the fourth node R with the first node P or the second node Q. For example... Figure 5 The drain of the third frequency divider transistor T17 is electrically connected to the first node P. Figure 6 The drain of the third frequency divider transistor T17 is electrically connected to the second node Q.

[0069] Please see Figures 4 to 6 The stage transmission output circuit 2012 includes a first stage transmission transistor T10, the gate of which is electrically connected to the first node P, the source of which is electrically connected to the high-level source VGH, and the drain of which is electrically connected to the stage transmission output terminal OUT in the gate drive circuit 20 for outputting the stage transmission signal; and a second stage transmission transistor T9, the gate of which is electrically connected to the second node Q, the source of which is electrically connected to the low-level source VGL, and the drain of which is electrically connected to the stage transmission output terminal OUT.

[0070] Please see Figures 4 to 6The output circuit 202 includes a first output transistor T22 and a second output transistor T21. The gate of the first output transistor T22 is electrically connected to the third node S, the source of the first output transistor T22 is electrically connected to the third high-potential line Vgh3, and the drain of the first output transistor T22 is electrically connected to the gate output terminal OUTA in the gate drive circuit 20 for outputting the gate control signal. The gate of the second output transistor T21 is electrically connected to the first node P or the second node Q, the source of the second output transistor T21 is electrically connected to the low-level source VGL, and the drain of the second output transistor T21 is electrically connected to the gate output terminal OUTA.

[0071] It should be noted that, if Figure 5 and Figure 6 If the structure is a second gate drive circuit 22, then the source of the first output transistor T22 is electrically connected to the second high-potential line Vgh2. Figure 5 and Figure 6 If the structure is a first gate drive circuit 21, then the source of the first output transistor T22 is electrically connected to the first high-potential line Vgh1. Figure 5 and Figure 6 If the structure is the fourth gate drive circuit 24, then the source of the first output transistor T22 is electrically connected to the fourth high potential line Vgh4.

[0072] Similarly, as discussed above, the third node S can control the on / off state of the first output transistor T22 to control whether a high voltage can be transmitted to the gate output terminal OUTA. The first node P or the second node Q can control the on / off state of the second output transistor T21 to control whether a low voltage can be transmitted to the gate output terminal OUTA. Combining the above discussion, it can be seen that in this invention, by setting a first frequency divider transistor T18 connected between the third node S and the first node P or the second node Q, the third node S can control whether it can receive signals from the first node P or the second node Q, thereby controlling the on / off state of the first output transistor T22 or the second output transistor T21, and thus controlling the specific situation of the gate control signal generated and output at the gate output terminal OUTA.

[0073] Please see Figures 4 to 6 The transmission receiving circuit 2011 includes an input circuit 2011c, a first control circuit 2011a, and a second control circuit 2011b.

[0074] In this embodiment, the input circuit 2011c includes an input transistor T3, the gate of the input transistor T3 is loaded with a first type of clock signal, the source of the input transistor T3 is configured as the input terminal of the input circuit 2011c, and the drain of the input transistor T3 is configured as the output terminal of the input circuit 2011c.

[0075] In this embodiment, the first control circuit 2011a includes a first transistor T4, a seventh transistor T5, a second transistor T6 and a third transistor T7 connected in series. The gate of the seventh transistor T5 is electrically connected to the drain of the input transistor T3. The source of the seventh transistor T5 is loaded with a first type of clock signal. The gate of the first transistor T4 is loaded with a first type of clock signal. The source of the first transistor T4 is loaded with a low-level source VGL. The drain of the first transistor T4 is electrically connected to the gate of the second transistor T6 and the drain of the seventh transistor T5. The drain of the second transistor T6 is electrically connected to the source of the third transistor T7. The source of the second transistor T6 and the gate of the third transistor T7 are both loaded with a second type of clock signal. The drain of the third transistor T7 is electrically connected to the fourth node R.

[0076] In this embodiment, the second control circuit 2011b includes a fourth transistor T13, a first capacitor C1, a fifth transistor T1 and a sixth transistor T2 connected in series. The gate of the fourth transistor T13 (electrically connected to the control line CL) is loaded with a control signal, the source of the fourth transistor T13 is loaded with a high-level source VGH, and the drain of the fourth transistor T13 is electrically connected to the second node Q. The gate of the fifth transistor T1 is electrically connected to the drain of the first transistor T4, the source of the fifth transistor T1 is loaded with a high-level source VGH, the drain of the fifth transistor T1 is electrically connected to the source of the sixth transistor T2, the drain of the sixth transistor T2 is loaded with a second type of clock signal, and the gate of the sixth transistor T2 is also loaded with a stage transmission signal generated by the upper-level gate drive circuit 20. The first capacitor C1 is electrically connected between the gate and drain of the sixth transistor T2.

[0077] In this invention, taking the gate drive circuit 20 as an example where all transistors are P-type transistors, the operation of some signals in some states is explained as follows: At power-on, the control signal transmitted by CL can control the fourth transistor T13 to turn on, transmitting the high-level source VGH to the second node Q; later, when the voltage in the first clock signal is low and the voltage in the (i-1)th stage gate control signal NScano(i-1) is low, the gate control signal NScano(i-1) controls both the seventh transistor T5 and the second output transistor T21 to turn on, and the low-level source VGL passes through the second output transistor T21. The signal is transmitted to the stage output terminal OUT, and the first clock signal controls the first transistor T4 to turn on. The low-level source VGL is transmitted to the gate of the second transistor T6 to control it to turn on. At this time, the high voltage in the second type of clock signal controls the third transistor T7 to turn off. Later, when the first type of clock signal is high, the input transistor T3, the second transistor T6 and the first transistor T4 are turned off. At this time, it can be considered that the second output transistor T21 remains on. The low voltage in the second type of clock signal controls the third transistor T7 to turn on. The fourth node R is still not loaded with voltage, and the stage output terminal OUT still outputs a low level.

[0078] It should be noted that the present invention does not limit the type of each transistor in the gate drive circuit 20. For example, they can all be P-type transistors, or some can be N-type transistors and the other part can be P-type transistors. The corresponding signals can also be matched and set according to the type of transistor. For details, please refer to the full text of the principle explanation that "the transistors in the gate drive circuit 20 are all P-type transistors".

[0079] Please see Figures 4 to 6 The first control circuit 2011a may further include an eighth transistor T11 and a second capacitor C2, and the second control circuit 2011b may further include a ninth transistor T12. The stage output circuit 2012 may further include a third capacitor C3 electrically connected between the gate and source of the first stage output transistor T10. The gate of the eighth transistor T11 and the gate of the ninth transistor T12 can both be loaded with a low-level source VGL to maintain their on state. The source and drain of the eighth transistor T11 are electrically connected to the drain of the first transistor T4 and the gate of the second transistor T6, respectively. The second capacitor C2 is electrically connected between the gate and drain of the second transistor T6. The source and drain of the ninth transistor T12 are electrically connected to the drain of the input transistor T3 and the second node Q, respectively.

[0080] In this embodiment, the first capacitor C1, the second capacitor C2, and the third capacitor C3 can be used to maintain the voltage of the corresponding nodes and to act as coupling. The eighth transistor T11 and the ninth transistor T12 can be turned on only when their source voltages are low enough, so as to maintain their drain voltages at a low level, which is beneficial to the turn-on of the first output transistor T22 and the second output transistor T21, respectively.

[0081] Please see Figures 4 to 6 The second control circuit 2011b also includes a tenth transistor T14 and an eleventh transistor T16.

[0082] In this embodiment, the source of the tenth transistor T14 is loaded with the stage transmission signal generated by the upper gate drive circuit 20, the gate of the tenth transistor T14 is loaded with the first type of clock signal, and the drain of the tenth transistor T14 is electrically connected to the gate of the sixth transistor T2.

[0083] In this embodiment, the gate and source of the eleventh transistor T16 are electrically connected to the gate of the sixth transistor T2, and the drain of the eleventh transistor T16 is electrically connected to the second node Q.

[0084] Please see Figures 4 to 6The second control circuit 2011b can also be configured with a twelfth transistor T15 to maintain a low voltage at the gate of the sixth transistor T2. The gate of the twelfth transistor T15 can be loaded with a low-level source VGL. The source and drain of the twelfth transistor T15 can be electrically connected to the drain of the tenth transistor T14 and the gate of the sixth transistor T2, respectively.

[0085] Understandably, in this embodiment, the second control circuit 2011b is also provided with the aforementioned tenth transistor T14 and eleventh transistor T16. The tenth transistor T14 can be used to control the voltage of the gate of the sixth transistor T2. Furthermore, by setting the eleventh transistor T16 connected between the second node Q and the gate of the sixth transistor T2, the second node Q is not directly electrically connected to the first capacitor C1, so as to avoid being coupled by the first capacitor C1 and to maintain the second node Q with a lower voltage.

[0086] Please see Figures 5 to 6 The gate drive circuit 20 also includes a first coupling capacitor C4 and a second coupling capacitor C5. One end of the first coupling capacitor C4 is connected to the third high potential line Vgh3, and the other end of the first coupling capacitor C4 is connected to the gate of the first output transistor T22. One end of the second coupling capacitor C5 is connected to the third high potential line Vgh3, and the other end of the second coupling capacitor C5 is connected to the gate of the first frequency divider transistor T18.

[0087] It should be noted that, Figure 5 and Figure 6 The difference is: Figure 5 The second frequency divider transistor T20 is a P-type transistor. Figure 6 The second frequency divider transistor T20 is an N-type transistor.

[0088] It should be noted that, due to Figure 5 and Figure 6 The gate drive circuit 20 in Figure 4 The third gate drive circuit 23 in the example illustrates that the first type of clock signal comes from the first clock signal line CKL1, and the second type of clock signal comes from the third clock signal line CKL3.

[0089] Please see Figure 8 and Figure 9 , Figure 8 This is a structural diagram of the gate drive circuit 20 in the prior art. Figure 9 for Figure 8 Timing diagram of the gate drive circuit 20.

[0090] Figure 8The driving circuit 30 in the middle is provided with two cascaded gate driving circuits 20. Each gate driving circuit 20 is connected to two identical clock signal lines. The effective level is periodically output through the two clock signal lines to realize the frequency division display of the display panel. Figure 9 The timing diagrams for the existing third scan line PSL and fourth scan line NSL2 are listed, based on... Figure 9 As can be seen from the timing data, the start time of ripples in the fourth scan line NSL2 is the same as the start time of the effective level of the clock signal line. When the fourth scan line NSL2 is outputting an effective level, the interval between two adjacent ripples is 4H. During the effective level phase of the fourth scan line NSL2, it can have 4 ripples, for example, as shown in the attached image. Figure 9 The effective level output by Nscano(i) has 4 ripples, and Pscan(n+1) and Pscan(n+2) corresponding to Nscano(i) both fall within the ripples of Nscano1, where i can be 1 and n can be 0; Pscan(n+3) and Pscan(n+4) corresponding to Nscano(i+1) both fall within the ripples of Nscano(i+1); Pscan(n+5) and Pscan(n+6) corresponding to Nscano(i+2) both fall within the ripples of Nscano(i+2).

[0091] Appendix to this application Figure 4 In the structure, the driving circuit 30 has four cascaded gate driving circuits 20. Each gate driving circuit 20 is connected to two clock signal lines. The arrangement of the four clock signal lines ensures that the first transistor T6 and the second transistor T4 in each gate driving circuit 20 are connected to different clock signal lines, and the interval between the start times of two adjacent effective levels in each clock signal line is 8H. Please refer to [link to relevant documentation]. Figure 7 Since the start time of ripple in the fourth scan line NSL2 is the same as the start time of the effective level of the clock signal line, the interval between two adjacent ripples is 8H when the fourth scan line NSL2 outputs an effective level. Simultaneously, each gate drive group 500 in this application has four spaced high-potential lines. The output terminal of each gate drive circuit 20 in the gate drive group 500 is connected to different high-potential lines. The arrangement of multiple high-potential lines reduces the load on the high-potential lines and avoids the generation of ripple; for example, see attached... Figure 7During the effective level phase of the fourth scan line NSL2, it can have 2 ripples. The effective level output by Nscano(i) has 2 ripples, and Pscan(n+1) and Pscan(n+2) corresponding to Nscano(i) do not fall within the ripple of Nscano(i). i can be 1 and n can be 0. Pscan(n+3) and Pscan(n+4) corresponding to Nscano(i+1) do not fall within the ripple of Nscano(i+1). Pscan(n+4) and Pscan(n+6) corresponding to Nscano(i+2) do not fall within the ripple of Nscano(i+1).

[0092] It should be noted that, in Figure 7 and Figure 9 In the process, when the first frequency divider signal line jumps from low level to high level, the load on the high potential line will decrease due to the change in frequency, and therefore the amplitude of the ripple generated in the fourth scan line NSL2 will decrease.

[0093] This application can also control the timing of the active level in the third scan line PSL, for example, advancing or delaying the output time of the active level by H or 2H to avoid ripple in the fourth scan line NSL2.

[0094] exist Figure 5 and Figure 6 In this structure, since one end of the second coupling capacitor C5 is connected to the third high-potential line Vgh3, and the other end of the second coupling capacitor C5 is connected to the gate of the first frequency divider transistor T18, when the first frequency divider signal line transitions, due to the coupling effect of the second coupling capacitor C5, the output waveform of the third high-potential line Vgh3 will have a transition ripple, for example... Figure 10 The effective level of Nscano(i) in the display panel will cause bright lines to appear on the display panel due to this sudden change.

[0095] Please see Figure 11 In the gate drive group 500, the high-potential lines connected to any of the first coupling capacitors C4 are the same. For example, in Figure 5 and Figure 6 Based on this, the driving circuit 30 also includes a fifth high potential line Vgh5, which is spaced apart from the first high potential line Vgh1, the second high potential line Vgh2, the third high potential line Vgh3 and the fourth high potential line Vgh4.

[0096] In this embodiment, the source of the first output transistor T22 of the first gate driving circuit 21 is electrically connected to the first high potential line Vgh1, the source of the first output transistor T22 of the second gate driving circuit 22 is electrically connected to the second high potential line Vgh2, the source of the first output transistor T22 of the third gate driving circuit 23 is electrically connected to the third high potential line Vgh3, the source of the first output transistor T22 of the fourth gate driving circuit 24 is electrically connected to the fourth high potential line Vgh4, and the first coupling capacitor C4 of the first gate driving circuit 21, the second gate driving circuit 22, the third gate driving circuit 23, and the fourth gate driving circuit 24 are all electrically connected to the fifth high potential line Vgh5.

[0097] Taking the third gate drive circuit 23 as an example, in Figure 11 In this structure, one end of the first coupling capacitor C4 is connected to the fifth high-potential line Vgh5, and the other end of the first coupling capacitor C4 is connected to the gate of the first output transistor T22. One end of the second coupling capacitor C5 is connected to the fifth high-potential line Vgh5, and the other end of the second coupling capacitor C5 is connected to the gate of the first frequency divider transistor T18. Because the fifth and third high potentials are spaced apart, they do not interfere with each other. When the first frequency divider signal line changes, due to the coupling effect of the second coupling capacitor C5, the waveform of the output of the fifth high-potential line Vgh5 will have a ripple. However, the third high potential, which is responsible for the output load, is not affected by the change in the first frequency divider signal line. This eliminates the technical problem of ripple in the waveform of the output of the third high-potential line Vgh3 when the first frequency divider signal line changes, thus improving the display effect of the display panel.

[0098] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A driving circuit, characterized in that, It includes a frequency divider signal line, multiple gate drive groups, and multiple clock signal lines. Each gate drive group includes multiple cascaded gate drive circuits. The frequency divider signal line is used to transmit a frequency divider control signal to the multiple gate drive circuits. The gate drive circuit includes: The stage transmission circuit is used to output the stage transmission signal of this stage to the gate drive circuit of the next stage; The output circuit is electrically connected to the first node and the second node in the cascade circuit. The output circuit outputs a gate control signal according to the frequency division control signal, the signals of the first node and the second node. The output circuit is electrically connected to the clock signal line. The clock signal lines connected to the gate drive circuits of adjacent stages are different. An output frequency divider circuit is provided, one end of which is connected to the output circuit at a third node, and the other end of which is connected to the cascade circuit at either the first node or the second node. The output frequency divider circuit controls the signal transmission between the first node, the second node, and the output circuit based on the signal from the first node or the second node and the frequency division control signal. Multiple high-potential lines are spaced apart, the number of which is the same as the number of gate driving circuits in the gate driving group; the output circuit of one of the gate driving circuits is connected to one of the high-potential lines, and in the gate driving group, the high-potential lines connected to any of the gate driving circuits are different. In each of the clock signal lines, the width of the active level is H, and the width between the start times of two adjacent active levels is greater than or equal to 8H.

2. The driving circuit according to claim 1, characterized in that, Each of the aforementioned transmission circuits is connected to two different clock signal lines, and the four clock signal lines connected to adjacent transmission circuits are all different.

3. The driving circuit according to claim 2, characterized in that, The plurality of clock signal lines include at least a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line, and the gate drive group includes a first gate drive circuit, a second gate drive circuit, a third gate drive circuit and a fourth gate drive circuit. The first gate driving circuit and the third gate driving circuit are each electrically connected to two of the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line. The second gate driving circuit and the fourth gate driving circuit are each electrically connected to the other two of the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line.

4. The driving circuit according to claim 3, characterized in that, Between the start times of two adjacent active levels of the first clock signal line, the width between the start time of the active level of the first clock signal line and the start time of the active level of the second clock signal line, the width between the start time of the active level of the second clock signal line and the start time of the active level of the third clock signal line, and the width between the start time of the active level of the third clock signal line and the start time of the active level of the fourth clock signal line are all 2H.

5. The driving circuit according to claim 4, characterized in that, Each of the gate drive circuits includes a first transistor and a second transistor connected in series; wherein, The gate of the first transistor in the first gate driving circuit is electrically connected to the first clock signal line, and the drain of the second transistor in the first gate driving circuit is electrically connected to the third clock signal line. The gate of the first transistor in the second gate driving circuit is electrically connected to the second clock signal line, and the drain of the second transistor in the second gate driving circuit is electrically connected to the fourth clock signal line. The gate of the first transistor in the third gate driving circuit is electrically connected to the third clock signal line, and the drain of the second transistor in the third gate driving circuit is electrically connected to the first clock signal line. The gate of the first transistor in the fourth gate driving circuit is electrically connected to the fourth clock signal line, and the drain of the second transistor in the fourth gate driving circuit is electrically connected to the second clock signal line.

6. The driving circuit according to any one of claims 1 to 5, characterized in that, The output circuit includes a first coupling capacitor, one end of which is connected to the high potential line, and the other end of which is connected to the third node. In the gate drive group, the high-potential lines connected to any of the first coupling capacitors are different.

7. The driving circuit according to claim 6, characterized in that, The gate drive group includes a first gate drive circuit, a second gate drive circuit, a third gate drive circuit, and a fourth gate drive circuit, and the multiple high-potential lines include a first high-potential line, a second high-potential line, a third high-potential line, and a fourth high-potential line arranged at intervals. The output circuit further includes a first output transistor, the gate of which is electrically connected to the third node, the source of which is electrically connected to one of the plurality of high potential lines, and the drain of which is electrically connected to the gate output terminal of the gate driving circuit for outputting the gate control signal. In this circuit, the first coupling capacitor of the first gate driving circuit and the source of the first output transistor are both electrically connected to the first high-potential line; the first coupling capacitor of the second gate driving circuit and the source of the first output transistor are both electrically connected to the second high-potential line; the first coupling capacitor of the third gate driving circuit and the source of the first output transistor are both electrically connected to the third high-potential line; and the first coupling capacitor of the fourth gate driving circuit and the source of the first output transistor are both electrically connected to the fourth high-potential line.

8. The driving circuit according to any one of claims 1 to 5, characterized in that, The output circuit includes a first coupling capacitor, one end of which is connected to the high potential line, and the other end of which is connected to the third node. In the gate drive group, the high-potential line connected to any of the first coupling capacitors is the same.

9. The driving circuit according to claim 8, characterized in that, The gate drive group includes a first gate drive circuit, a second gate drive circuit, a third gate drive circuit and a fourth gate drive circuit, and the multiple high-potential lines include a first high-potential line, a second high-potential line, a third high-potential line, a fourth high-potential line and a fifth high-potential line arranged at intervals. The output circuit further includes a first output transistor, the gate of which is electrically connected to the third node, the source of which is electrically connected to one of the plurality of high potential lines, and the drain of which is electrically connected to the gate output terminal of the gate driving circuit for outputting the gate control signal. In this circuit, the source of the first output transistor of the first gate driving circuit is electrically connected to the first high-potential line, the source of the first output transistor of the second gate driving circuit is electrically connected to the second high-potential line, the source of the first output transistor of the third gate driving circuit is electrically connected to the third high-potential line, the source of the first output transistor of the fourth gate driving circuit is electrically connected to the fourth high-potential line, and the first coupling capacitors of the first gate driving circuit, the second gate driving circuit, the third gate driving circuit, and the fourth gate driving circuit are all electrically connected to the fifth high-potential line.

10. The driving circuit according to claim 7 or 9, characterized in that, The cascade circuit includes a cascade receiving circuit and a cascade output circuit, and the cascade output circuit and the cascade receiving circuit are connected to the first node and the second node. The gate drive circuit further includes a stage transmission frequency divider circuit. One end of the stage transmission frequency divider circuit is connected to the stage transmission receiving circuit at the fourth node, and the other end of the stage transmission frequency divider circuit is connected to the stage transmission output circuit at one of the first node and the second node. The stage transmission frequency divider circuit is used to control the signal of one of the first node and the second node according to the frequency division control signal, so as to control the stage transmission output circuit to output the stage transmission signal of this stage.

11. The driving circuit according to claim 10, characterized in that, The frequency division control signal includes a first frequency division signal and a second frequency division signal, and the frequency division signal line includes a first frequency division signal line for transmitting the first frequency division signal and a second frequency division signal line for transmitting the second frequency division signal; The first frequency division signal line is electrically connected to the output frequency division circuit, and the second frequency division signal line is electrically connected to the cascade frequency division circuit.

12. The driving circuit according to claim 11, characterized in that, The output frequency divider circuit includes: A first frequency divider transistor, the source of which is electrically connected to the first node or the second node, and the drain of which is electrically connected to the third node; The second frequency divider transistor has its gate electrically connected to the fifth node of the cascade circuit, its source electrically connected to the first frequency divider signal line, and its drain electrically connected to the gate of the first frequency divider transistor.

13. The driving circuit according to claim 12, characterized in that, The frequency divider circuit includes: The third frequency divider transistor has its gate electrically connected to the second frequency divider signal line, its source electrically connected to the stage receiver circuit, and its drain electrically connected to the first node or the second node.

14. The driving circuit according to claim 10, characterized in that, The stage transmission output circuit includes: The first stage transmission transistor has its gate electrically connected to the first node, its source electrically connected to a high-level source, and its drain electrically connected to the stage transmission output terminal in the gate driving circuit used to output the stage transmission signal. The second-stage transmission transistor has its gate electrically connected to the second node, its source electrically connected to a low-level source, and its drain electrically connected to the stage transmission output terminal.

15. The driving circuit according to claim 10, characterized in that, The output circuit includes: The second output transistor has its gate electrically connected to either the first node or the second node, its source electrically connected to a low-level source, and its drain electrically connected to the gate output terminal.

16. The driving circuit according to claim 10, characterized in that, The cascade receiver circuit includes: An input circuit includes an input transistor, the gate of which is loaded with a first type of clock signal, the source of which is configured as the input terminal of the input circuit, and the drain of which is configured as the output terminal of the input circuit. The first control circuit includes a first transistor, a second transistor, a third transistor, and a seventh transistor. The gate of the seventh transistor is electrically connected to the drain of the input transistor. The source of the seventh transistor is loaded with a first type of clock signal. The gate of the first transistor is loaded with the first type of clock signal. The source of the first transistor is connected to a low-level source. The drain of the first transistor is electrically connected to the gate of the second transistor and the drain of the seventh transistor. The drain of the second transistor is electrically connected to the source of the third transistor. The source of the second transistor and the gate of the third transistor are both loaded with a second type of clock signal. The drain of the third transistor is electrically connected to the fourth node. The second control circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor. The gate of the fourth transistor is loaded with a control signal, the source of the fourth transistor is loaded with a high-level source, and the drain of the fourth transistor is electrically connected to the second node. The gate of the fifth transistor is electrically connected to the drain of the first transistor, the source of the fifth transistor is loaded with a high-level source, the drain of the fifth transistor is electrically connected to the source of the sixth transistor, the drain of the sixth transistor is loaded with a second type of clock signal, and the gate of the sixth transistor is loaded with the stage transmission signal of the upper-level gate drive circuit. The first capacitor is electrically connected between the gate and drain of the sixth transistor.

17. The driving circuit according to claim 16, characterized in that, The second control circuit also includes: The tenth transistor has a source loaded with the stage transmission signal of the gate drive circuit above, a gate loaded with the first type of clock signal, and a drain electrically connected to the gate of the sixth transistor. The eleventh transistor has its gate and source electrically connected to the gate of the sixth transistor, and its drain electrically connected to the second node.

18. A display panel, characterized in that, The display panel includes the driving circuitry as described in any one of claims 1 to 17.

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