Method and system for prolonging service life of flash memory in single-chip microcomputer

Abstract

The application relates to the field of embedded data storage technology and discloses a method and system for prolonging the service life of a single-chip machine internal FLASH simulated EEPROM, which comprises the following steps: first, initializing the FLASH, dividing the FLASH into a main data area, a mapping table area, a backup area and a transaction log area, selecting a physical block through a dynamic wear leveling algorithm when writing data, safely updating the mapping table through a transaction mechanism, performing cyclic redundancy check when reading data, starting a cascaded recovery from the backup area or the transaction log area if the check fails, and finally, updating the transaction log to record operations and forming a closed-loop management process. Through a dynamic wear leveling and data classification management mechanism, the application realizes global and uniform distribution of write load in a storage array, selects a physical block with the least number of erasing and writing times when writing, and can also identify the access frequency of data and actively migrate cold data which is seldom changed.

Description

Technical Field

[0001] This invention relates to the field of embedded data storage technology, specifically to a method and system for improving the lifespan of a microcontroller's internal FLASH-simulated EEPROM. Background Technology

[0002] Embedded systems are widely used in many fields such as consumer electronics, industrial control, and automotive electronics. The core of these systems, the microcontroller (MCU), typically integrates FLASH memory. To achieve persistent storage of configuration parameters, operation logs, and other data without adding external hardware, the FLASH memory within the MCU is commonly used in engineering to simulate the function of EEPROM. This approach effectively reduces product costs and hardware size. However, FLASH storage media has a limited physical erase / write lifespan; direct data reading and writing will quickly deplete its lifespan. Therefore, an efficient management method is needed to ensure its long-term stable operation.

[0003] Existing technologies offer several solutions to this problem. To extend the lifespan of FLASH memory, some solutions employ wear leveling algorithms, such as cyclically rotating addresses to distribute write operations across different physical blocks, which to some extent avoids repeated erasure and writing of a single address. To ensure basic data integrity, other solutions add a Cyclic Redundancy Check (CRC) code when storing data. By comparing the checksum during data retrieval, errors such as bit flips can be effectively detected during data storage.

[0004] However, the aforementioned existing technologies still have shortcomings in practical applications. First, simple wear leveling algorithms do not differentiate between data access characteristics. In practice, frequently updated hot data can subject the physical block group storing it to far greater write and erase pressure than other areas, forming localized wear hotspots. This means the overall lifespan of the storage system is still limited by the premature failure of this localized area. Second, abnormal interruptions during data writing are a problem that existing technologies struggle to handle comprehensively. A single data update involves multiple steps, including data writing and address mapping updates. If an unexpected power outage occurs during this process, the system will fall into a logical error state where data and address mappings are inconsistent. Relying solely on CRC checks cannot recover from this state, posing a risk of data loss. Finally, existing technologies typically manage bad blocks passively, marking physical blocks as damaged only after read / write failures. This "post-mortem" approach not only fails to prevent data loss due to sudden physical block failures but also cannot predict the health status of the storage array, thus compromising the overall reliability of the system. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a method and system for improving the lifespan of a microcontroller's internal FLASH-simulated EEPROM. It solves the problems of short lifespan and insufficient data reliability caused by insufficient wear equalization leading to premature aging in local areas, inconsistent data states during abnormal write interruptions, and passive bad block management.

[0006] To address the aforementioned technical problems, the first aspect of this invention provides a method for improving the lifespan of a microcontroller's internal FLASH-simulated EEPROM.

[0007] The method includes: Initialization is performed when the microcontroller starts up, and the FLASH physical space is divided into multiple logical areas. The multiple logical areas are divided into a main data area, a mapping table area, a backup area, and a transaction log area. Based on the partitioning results, in response to the data write request, the target physical block is selected in the main data area using a dynamic wear leveling algorithm and the data is written using a double buffering strategy. Based on the write result of the target physical block, the mapping table area is updated using a transaction mechanism so that the logical address points to the target physical block; In response to a data read request, data is read and cyclic redundancy check is performed based on the updated mapping table area, and if the cyclic redundancy check fails, data is restored from the backup area or the transaction log area. After completing any of the data writing, data reading, or data recovery operations, update the transaction log area.

[0008] Preferably, the initialization during microcontroller startup includes: checking whether there are log entries in the transaction log area with a pre-committed status; if there are log entries with a pre-committed status, then completing the unfinished operations corresponding to the log entry or performing a rollback according to the content of the log entry, so as to ensure that the data status of the main data area and the mapping table area are consistent.

[0009] Preferably, the step of selecting a target physical block in the main data area using a dynamic wear leveling algorithm includes: maintaining an erase / write count counter for each physical block in the main data area; and, in response to the data write request, scanning the erase / write count counters of all available physical blocks and selecting the physical block with the smallest count value as the target physical block.

[0010] Preferably, the dynamic wear leveling algorithm further includes: dividing the data into hot data and cold data according to the historical access frequency of the data; when the number of erase / write operations of the physical block storing cold data exceeds a preset migration threshold, actively migrating the cold data in the physical block to a new physical block with a lower number of erase / write operations.

[0011] Preferably, updating the mapping table area using a transaction mechanism includes: before updating the mapping table area, creating a log record with a pre-committed status in the transaction log area; and after the mapping table area is successfully updated, updating the status of the corresponding log record in the transaction log area to committed.

[0012] Preferably, when the cyclic redundancy check fails, the step of restoring data from the backup area or the transaction log area includes: firstly, attempting to read a copy of the data from the backup area for restoration; if restoration from the backup area fails, then querying the committed operation records in the transaction log area, and restoring the data based on the operation records back to the last correct version before the data was corrupted.

[0013] Preferably, updating the transaction log area includes: recording the type of the current operation, which includes data writing, data reading, or data recovery; recording the logical address corresponding to the current operation; and recording the timestamp of the current operation.

[0014] Preferably, the method further includes performing predictive bad block management via a background task. The management includes: when a physical block P... i EC meets the conditions i >Th EC or SER i >Th SER At that time, the physical block P i This block is identified as an aging block and triggers data migration and bad block marking; where P i For identifying physical blocks, EC i For the physical block P i The number of erase / write cycles, SER i For the physical block P i The soft error rate within the preset time window, Th EC The preset write / erase cycle threshold, Th SER This is a preset soft error rate warning threshold.

[0015] Preferably, the predictive bad block management further includes: monitoring and recording a bad block marking area for failed blocks; when the number of failed blocks recorded in the bad block marking area exceeds a preset capacity warning threshold, the released physical blocks are supplemented to the main data area by reducing the space of the transaction log area or the backup area.

[0016] A second aspect of the present invention provides a system for improving the lifespan of a microcontroller's internal FLASH emulation EEPROM.

[0017] The system includes: The storage management module is used to logically divide the FLASH physical space during system initialization and is responsible for maintaining the bad block marking area and dynamically reconstructing the storage area. The wear leveling module is used to maintain the number of erase / write cycles for each physical block and select the target physical block for data write requests based on the dynamic wear leveling algorithm. The data operation module is used to perform data writing and address mapping updates based on a transaction mechanism, and to perform cyclic redundancy checks when reading data; The error handling and recovery module is used to perform cascaded data recovery when verification fails, and to perform predictive bad block management through background tasks; The control module is used to receive external operation commands and coordinate the collaborative work of the storage management module, wear leveling module, data operation module, and error handling and recovery module.

[0018] In summary, this application includes at least one of the following beneficial technical effects: 1. This invention achieves a global and uniform distribution of write load in the storage array through a dynamic wear leveling and data classification management mechanism. It not only selects the physical block with the fewest erase / write cycles during writing, but also identifies the data access frequency and actively migrates cold data that does not change frequently. Existing technologies often only passively respond to write requests or use fixed address rotation. This approach cannot avoid concentrated erasure / write in local storage areas, which limits the effective lifespan of the entire FLASH medium.

[0019] 2. This invention introduces a solution that combines transactional write processes with cascading data recovery, ensuring the atomicity of any write operation. At the same time, it constructs a defense-in-depth system from backup to log backtracking. Compared with protection methods that rely on single data verification or simple copies, the solution of this invention solves the logical errors caused by the inconsistency between data and metadata status when power is lost during a write operation. It also provides a more comprehensive recovery path for data corruption and makes up for the risk of failure of a single recovery method.

[0020] 3. This invention possesses proactive maintenance and adaptive capabilities. By analyzing operational data, it can predict and isolate aging blocks in advance to prevent problems before they occur. When physical wear accumulates, it can also dynamically reconstruct the storage area layout to ensure the continuity of core functions. This changes the existing technology's mode of passively marking bad blocks only after data errors occur, solves the problem of sudden functional failures caused by the accumulation of bad blocks in the storage system, and endows the system with the ability to self-adjust under long-term wear. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the system functional modules of the present invention; Figure 2This is a schematic diagram of the FLASH logical storage space of the present invention; Figure 3 This is a schematic diagram of the method flow of the present invention; Explanation of reference numerals in the attached diagram: 100, Control module; 200, Storage management module; 300, Wear leveling module; 400, Data operation module; 500, Error handling and recovery module. Detailed Implementation

[0022] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] See attached document Figure 1 , Figure 1 This is a functional module diagram of a system for improving the lifespan of a microcontroller's internal FLASH emulation EEPROM according to an embodiment of the present invention. The system may include: a control module 100, a storage management module 200, a wear leveling module 300, a data operation module 400, and an error handling and recovery module 500.

[0024] The control module 100 is used to receive read and write operation instructions from the upper-layer application of the microcontroller, and coordinate other functional modules in the system to execute the corresponding operation process according to the instruction type.

[0025] The storage management module 200 is connected to the control module 100. This module is used to logically divide the specified FLASH physical space into regions during system initialization. This module is also responsible for maintaining the bad block marking area, registering the addresses of all confirmed invalid physical blocks, and executing dynamic storage area reconstruction instructions initiated by the error handling and recovery module 500.

[0026] Wear leveling module 300 is connected to control module 100. This module maintains and updates the erase / write count counter for each available physical block in the FLASH memory. Upon responding to a write request, this module selects a target physical block address for data operation module 400 based on its internal dynamic wear leveling algorithm.

[0027] The data operation module 400 is connected to the control module 100, the wear leveling module 300, and the error handling and recovery module 500. This module is used to perform specific physical read and write operations. During a write operation, it receives the target physical block address provided by the wear leveling module 300, performs a transaction-based data write, and updates the address mapping relationship in the mapping table area. During a read operation, it is responsible for calculating and comparing the cyclic redundancy check (CRC) code, and reporting the error to the control module 100 if the check fails.

[0028] The error handling and recovery module 500 is connected to the control module 100. When this module receives a data recovery command from the control module 100, it executes a cascaded data recovery process. This module also performs predictive bad block management through background tasks, analyzes the health status of physical blocks, and issues dynamic storage area reconstruction commands to the storage management module 200 when necessary.

[0029] See attached document Figure 2 , Figure 2 This is a schematic diagram of the FLASH logical storage space according to an embodiment of the present invention. During system initialization, the storage management module 200 logically divides a continuous FLASH physical space into multiple functional areas.

[0030] The main data area is used to store the actual data of the user application layer. All data write operations ultimately store the data content in one or more physical blocks within this area.

[0031] The mapping table area is used to store the mapping relationship between logical addresses and physical block addresses. After a successful write operation, the data operation module 400 updates the contents of this area to ensure that the logical address can correctly point to the physical location of the newly written data.

[0032] The backup area is used to store copies of critical data. This critical data includes copies of the mapping table area and copies of high-value user data determined according to a preset strategy. This area is accessed by the error handling and recovery module 500 during the first stage of the data recovery process.

[0033] The transaction log area is used to record the status of all data change operations. During write operations, the data operation module 400 records the "pre-commit" and "committed" status of the operation in this area to ensure the atomicity of the operation. This area is also used by the error handling and recovery module 500 for deep data backtracking and recovery.

[0034] The bad block marking area is used to record the addresses of all physical blocks that have been determined to be permanently invalid or have reached retirement criteria. The storage management module 200 is responsible for adding addresses to this area, and all modules in the system will exclude addresses recorded in this area when selecting physical blocks.

[0035] See attached document Figure 3 , Figure 3 This is a flowchart illustrating a method for improving the lifespan of a microcontroller's internal FLASH simulated EEPROM according to an embodiment of the present invention.

[0036] The method may include: S10, Execute system initialization. When the microcontroller starts up, it divides the FLASH physical space into logical regions and performs transaction consistency checks for self-healing recovery.

[0037] S20, execute the data write process. When responding to a data write request, the target physical block is selected through a dynamic wear leveling algorithm, the data is written using a double-buffering strategy, and the mapping table area is updated using a transaction mechanism.

[0038] S30 executes the data read and recovery process. When responding to a data read request, data is read and cyclic redundancy check is performed based on the mapping table area, and cascading data recovery is initiated if the check fails.

[0039] S40 performs background maintenance and log updates. After completing data writing or data recovery operations, it updates the transaction log area and performs predictive bad block management and system adaptive refactoring through background tasks.

[0040] The following section will elaborate on each step of this method.

[0041] In step S10, the system performs initialization. After the microcontroller is powered on or reset, the storage management module 200 logically divides a preset FLASH physical space into regions. This division operation is performed during the first use of the FLASH, formatting it to generate a main data area, a mapping table area, a backup area, a transaction log area, and a bad block marking area. The number of physical blocks occupied by each logical region can be configured according to application requirements, and their quantitative relationships satisfy: N total =N D +N M +N B +N L +N F ; Where, N total N represents the total number of physical blocks that the system can manage. D The number of physical blocks occupied by the main data area, N M N represents the number of physical blocks occupied by the mapping table area.B N represents the number of physical blocks occupied by the backup area. L N represents the number of physical blocks occupied by the transaction log area. F The number of physical blocks reserved for the bad block marking area in the initial state.

[0042] After the logical region partitioning is completed, or at each subsequent system startup, the control module 100 will have the instruction error handling and recovery module 500 perform a transaction consistency check. This check process first scans all log entries in the transaction log area.

[0043] If a log entry with a "pre-commit" status is found during the scan, it indicates that the previous data write operation associated with that log entry was interrupted before completion. In this case, the error handling and recovery module 500 will parse the metadata recorded in the log entry, which includes the target logical address and physical block address.

[0044] Based on the aforementioned metadata, the error handling and recovery module 500 will perform a recovery operation. This recovery operation includes reading the data of the target physical block recorded in the log entry, re-executing the update of the mapping table area, and then updating the status of the log entry to "committed." This self-healing recovery process ensures that, under any startup conditions, the address mapping relationship recorded in the mapping table area remains deterministically consistent with the state of the data successfully written to the main data area.

[0045] In step S20, the system executes the data write process. This process is initiated when the control module 100 receives a data write request from the upper-layer application. First, the data operation module 400 creates a new log entry in the transaction log area and sets the status of the entry to "pre-commit". This log entry contains the target logical address of this write operation, a summary of the data content, and the target physical block address to be selected subsequently.

[0046] Subsequently, the control module 100 instructs the wear leveling module 300 to select a target physical block. The wear leveling module 300 first scans the erase / write count counters EC of all available physical blocks in the main data area. i The system then selects the physical block with the smallest erase / write count as the target physical block for this write operation. If multiple physical blocks have the same minimum erase / write count, a round-robin strategy is used to select the target block from among these blocks.

[0047] To further optimize wear leveling, the wear leveling module 300 can also execute hot and cold data separation and proactive migration strategies. The system provides each logical address LA with... j Maintain an access frequency counter FC j When the access frequency count of a logical address exceeds a preset access frequency threshold, Th... FCThe corresponding data is classified as hot data, and vice versa. The wear leveling module 300 periodically checks the physical blocks storing cold data through a background task. If a physical block P storing cold data... k Its erase / write cycles EC k Active migration is triggered when the following conditions are met: EC k >α·EC avg ; Where α is a configurable migration coefficient, EC avg This represents the average number of erase / write operations for all manageable physical blocks.

[0048] EC avg The calculation method is as follows: Here, N total EC represents the total number of physical blocks that the system can manage. i Let be the number of erase / write operations for the i-th physical block.

[0049] Once the migration is triggered, the cold data in the physical block will be copied to a new physical block with fewer erase / write cycles.

[0050] After obtaining the target physical block address from the wear leveling module 300, the data operation module 400 executes a double-buffered write strategy. The data to be written is first completely written into a temporary buffer located in the microcontroller's RAM. Simultaneously, the data operation module 400 calculates a 16-bit Cyclic Redundancy Check (CRC) code based on the data stream to be written. In one embodiment, the CRC-16 / CCITT standard is used, and its generator polynomial is: G(x)=x 16 +x 12 +x 5 +1; Then, the data operation module 400 writes the data in the RAM buffer, along with its CRC checksum, into the selected target physical block in one go.

[0051] After the physical block write operation is successfully completed, the data operation module 400 immediately updates the mapping table area, modifies the entry corresponding to the target logical address, and makes it point to the physical block address of the newly written data.

[0052] After the mapping table area is successfully updated, the data operation module 400 updates the status of the log entry corresponding to this operation in the transaction log area from "pre-commit" to "committed". This completes a full data write process.

[0053] In step S30, the system executes a data read and restore process. This process is initiated when the control module 100 receives a data read request from an upper-layer application for a specific logical address. The control module 100 instructs the data operation module 400 to perform the read operation.

[0054] The data operation module 400 first accesses the mapping table area to query the current physical block address corresponding to the logical address. After obtaining the physical block address, the data operation module 400 reads the stored data content and its attached CRC-16 checksum from that address.

[0055] Subsequently, the data operation module 400 recalculates the CRC-16 checksum for the data content just read. Then, it compares the newly calculated checksum with the checksum read from the FLASH memory.

[0056] If the two check codes match exactly, it indicates that the data is complete and error-free. The data operation module 400 returns the read data to the upper-layer application through the control module 100, and the reading process ends normally.

[0057] If the newly calculated checksum does not match the stored checksum, the data is determined to be corrupted. The data operation module 400 reports a data integrity error to the control module 100. The control module 100 then instructs the error handling and recovery module 500 to initiate cascaded data recovery.

[0058] The error handling and recovery module 500 performs recovery according to a preset priority order. First, the module accesses the backup area and attempts to read a copy of the data. If the copy exists and its own CRC check passes, the copy data is used for recovery, that is, it is written back to the main data area through an internal write operation and returned to the upper layer application.

[0059] If no valid copy is found in the backup area, the error handling and recovery module 500 performs the next level of recovery. This module scans the transaction log area, searching for the most recent log record with a "committed" status related to the target logical address. This log record represents the last known correct version of the data before the corruption. The error handling and recovery module 500 recovers the data based on the contents of this log record and returns the recovered data to the upper-layer application.

[0060] In step S40, the system performs background maintenance and log updates. After completing a data write, data read, or data recovery operation, the data operation module 400 can update the transaction log area. This update operation includes recording the type of the completed operation, the logical address corresponding to the operation, and a timestamp. This log information can be used for subsequent system status auditing.

[0061] In addition, the method includes a background maintenance task scheduled by the control module 100. This task is executed by the error handling and recovery module 500 during microcontroller idle periods, and includes predictive bad block management and adaptive system reconfiguration.

[0062] Predictive bad block management proactively monitors the health status of each physical block. The error handling and recovery module 500 continuously analyzes the erase / write count counter maintained by the wear leveling module 300 and records soft errors that can be corrected by CRC during reading of each physical block. When a physical block P... i A physical block is considered an aging block when its status meets the following conditions: (EC i >Th EC )∨(SER i >Th SER ); Among them, P i For identifying physical blocks, EC i For the physical block P i The number of erase / write cycles, SER i For the physical block P i The soft error rate within the preset time window, Th EC The preset write / erase cycle threshold, Th SER This is a preset soft error rate warning threshold.

[0063] Once a physical block is identified as an aging block, the system immediately migrates the valid data stored in it to a new, healthy physical block. After the migration is complete, the storage management module 200 records the address of the aging block in the bad block marker area, making it permanently unusable.

[0064] The system's adaptive refactoring function is activated when the system's physical wear and tear accumulates to a certain level. The error handling and recovery module 500 monitors the number of failed blocks recorded in the bad block marker area. When this number exceeds a preset capacity warning threshold, the module issues a refactoring command to the storage management module 200. Based on this command, the storage management module 200 can reduce the space allocation of the transaction log area or backup area, for example, by freeing up physical blocks by cleaning up the oldest log records. These freed physical blocks are then reassigned to the primary data area to ensure the continuous availability of core data storage functions.

[0065] To further clarify the collaborative working process of the technical solution described in this invention, a specific working scenario example will be used for illustration below.

[0066] This embodiment describes an industrial IoT data acquisition terminal. Deployed in an industrial production site, its main tasks include: acquiring and storing real-time operating parameters such as equipment temperature and pressure at a high frequency (e.g., once per second), which is hot data; and updating its network configuration and sensor calibration parameters at a low frequency (e.g., only during equipment maintenance or calibration), which is cold data. This application scenario places high demands on the long-term reliability of data storage and the ability to operate continuously without human intervention.

[0067] During the initialization phase of the terminal, the storage management module 200 configures the FLASH physical space according to the needs of the scenario. For example, it allocates a large proportion of space to the main data area to accommodate a large number of real-time operating parameters; it allocates enough space to the backup area to store copies of all network configuration and calibration parameters; and it allocates appropriate space to the transaction log area and bad block marking area.

[0068] When the terminal is running normally, and a new operating parameter needs to be recorded, the control module 100 receives a write request. The control module 100 instructs the wear leveling module 300 to select a target physical block. The wear leveling module 300 queries the erase / write counts of all available physical blocks in the main data area and returns the address of the physical block with the lowest current count. The data operation module 400 receives this address and executes the complete write process described in S20. During the continuous recording of multiple operating parameters, due to the intervention of the wear leveling module 300, these data are sequentially written to different physical blocks with the lowest erase / write counts, avoiding concentrated writing to a single physical block.

[0069] In a specific scenario, suppose the terminal experiences an unexpected power outage during the update of the network configuration file (a write operation). The power outage occurs after the data operation module 400 has written the new configuration file data to a new physical block, but before it updates the mapping table area. At this point, a log record with a status of "pre-commit" already exists in the transaction log area corresponding to this operation.

[0070] When the terminal powers on again, the system enters the S10 initialization process. While scanning the transaction log area, the error handling and recovery module 500 detects a log record in the "pre-commit" state. Based on the metadata stored in this record, the module identifies the incomplete mapping table update operation. Subsequently, the error handling and recovery module 500 completes the update, making the corresponding logical address point to the physical block of the newly written data, and updates the status of the log record to "committed." This process ensures that the configuration file data update operation is ultimately completed, guaranteeing data consistency.

[0071] After the terminal has been running for a long time, suppose a certain physical block P agedBecause it repeatedly erases and rewrites cold data stored at different times, its erase / rewrite count is EC. aged The preset write / erase count threshold (Th) has been reached. EC During a background maintenance task, the error handling and recovery module 500 identified this situation while performing predictive bad block management in S40. The system then processed the physical block P. aged The currently stored valid data is migrated to a new physical block with a lower write / erase count, and the mapping table is updated. After the migration is complete, the storage management module 200 moves the physical block P... aged The address is added to the bad block marker area. After this, the physical block is no longer involved in any read or write operations. The entire process is transparent to the upper-layer data acquisition application, and the terminal's functionality remains unaffected.

[0072] The embodiments described in this specific implementation are preferred embodiments of this application and are not intended to limit the scope of protection of this application. Identical components are represented by the same reference numerals. Therefore, all equivalent changes made to the structure, shape, and principle of this application should be included within the scope of protection of this application.

Claims

1. A method for improving the lifespan of a microcontroller's internal FLASH-simulated EEPROM, characterized in that, Includes the following steps: Initialization is performed when the microcontroller starts up, and the FLASH physical space is divided into multiple logical areas. The multiple logical areas are divided into a main data area, a mapping table area, a backup area, a transaction log area, and a bad block marking area. The relationship between the number of physical blocks occupied by each logical region satisfies: ;in, This represents the total number of physical blocks that the system can manage. The number of physical blocks occupied by the main data area. The number of physical blocks occupied by the mapping table area. The number of physical blocks occupied by the backup area. The number of physical blocks occupied by the transaction log area. The number of physical blocks reserved for the bad block marking area in the initial state; the backup area is used to store copies of critical data, including copies of the mapping table area and copies of high-value user data determined according to a preset strategy. Check if there are any log entries in the transaction log area with a status of pre-commit; if there are log entries with a status of pre-commit, complete the unfinished operations corresponding to the log entries or perform a rollback according to the content of the log entries to ensure that the data status of the main data area and the mapping table area is consistent. Based on the partitioning results, in response to data write requests, a target physical block is selected in the main data area using a dynamic wear leveling algorithm, and data is written using a double-buffering strategy. The dynamic wear leveling algorithm includes: maintaining an erase / write count counter for each physical block in the main data area and selecting the physical block with the smallest count as the target physical block; dividing the data into hot and cold data based on historical access frequency, and when a physical block storing cold data... Its number of erase / write cycles Meet the conditions When this occurs, an active migration is triggered to move the cold data in the physical block to a new physical block with a lower number of erase / write cycles. For a configurable migration coefficient, The average number of erase / write cycles for all manageable physical blocks; Based on the write result of the target physical block, the mapping table area is updated using a transaction mechanism so that the logical address points to the target physical block. The update using the transaction mechanism includes: before updating the mapping table area, creating a log record with a pre-committed state in the transaction log area; the log record with a pre-committed state includes the target logical address of this write operation, a summary of the data content, and the target physical block address; after the mapping table area is successfully updated, the status of the corresponding log record in the transaction log area is updated to committed. In response to a data read request, data is read and cyclic redundancy check is performed based on the updated mapping table area. If the cyclic redundancy check fails, a copy of the data is first attempted to be read from the backup area for recovery. If the copy exists and its own cyclic redundancy check passes, the copy data is written back to the main data area for recovery. If recovery from the backup area fails, the operation record in the transaction log area that is related to the logical address of the data, has a committed status, and has the most recent timestamp is queried. The operation record is then used to trace back to the last correct version of the data before it was corrupted for recovery. After completing any of the data write, data read, or data recovery operations, update the transaction log area. Updating the transaction log area includes: recording the type of the current operation, which includes data write, data read, or data recovery; recording the logical address corresponding to the current operation; and recording the timestamp of the current operation. Predictive bad block management is performed via a background task. This predictive bad block management includes: when a physical block... Meet the conditions or At that time, the physical block This block was identified as an aging block and data migration and bad block marking were triggered; among them, For identifying physical blocks, For the physical block The number of erase / write cycles, For the physical block The soft error rate within a preset time window. The preset write / erase cycle warning threshold, A preset soft error rate warning threshold is set; after migrating the valid data in the aging block to a new, healthy physical block, the address of the aging block is recorded in the bad block marking area, so that the aging block is permanently taken out of use; the bad block marking area of ​​failed blocks is monitored and recorded; when the number of failed blocks recorded in the bad block marking area exceeds a preset capacity warning threshold, the space of the transaction log area or the backup area is reduced, and the released physical blocks are supplemented to the main data area.

2. The method for improving the service life of a microcontroller's internal FLASH simulated EEPROM according to claim 1, characterized in that, The step of selecting the target physical block in the main data area using the dynamic wear leveling algorithm includes: Maintain an erase / write count counter for each physical block in the main data area; When responding to the data write request, the erase / write count counters of all available physical blocks are scanned, and the physical block with the smallest count value is selected as the target physical block.

3. A system for improving the lifespan of a microcontroller's internal FLASH-simulated EEPROM, applied to the method for improving the lifespan of a microcontroller's internal FLASH-simulated EEPROM as described in any one of claims 1-2, characterized in that, include: The storage management module is used to logically divide the FLASH physical space during system initialization and is responsible for maintaining the bad block marking area and dynamically reconstructing the storage area. The wear leveling module is used to maintain the number of erase / write cycles for each physical block and select the target physical block for data write requests based on the dynamic wear leveling algorithm. The data operation module is used to perform data writing and address mapping updates based on a transaction mechanism, and to perform cyclic redundancy checks when reading data; The error handling and recovery module is used to perform cascaded data recovery when verification fails, and to perform predictive bad block management through background tasks; The control module is used to receive external operation commands and coordinate the collaborative work of the storage management module, wear leveling module, data operation module, and error handling and recovery module.

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