Flip chip silver mirror light emitting diode chip and method of manufacturing the same

Abstract

The application relates to the technical field of semiconductor devices, in particular to a flip silver mirror light-emitting diode chip and a preparation method thereof. The preparation method is characterized in that: second insulating layer sub-layers with different etching rates are deposited, and a photoetching protection process is combined, so that part of the second insulating layer above the opening can be reserved after BOE etching, thereby avoiding BOE solution drilling and preventing the formation of Al metal cavities, and the ability of the light-emitting diode to resist large current impact is improved; and only Cr and Ni and the like are used as protective sub-layers on the top of the metal connecting layer, and the precious metal Au is not needed to be used as a protective sub-layer, so that the preparation cost of the light-emitting diode chip is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a flip-chip silver mirror light-emitting diode chip and its fabrication method. Background Technology

[0002] Flip-chip LEDs are widely used due to their advantages such as back-side light emission, good solderability, high thrust, and high reliability.

[0003] To reduce manufacturing costs, existing flip-chip LED chips often combine the photolithography process for fabricating the pad layer and the opening process for the second insulating layer below the pad layer into a single operation. Specifically, photolithography is used to fabricate the opening photoresist on the second insulating layer, followed by BOE etching to form the second insulating layer opening, and then evaporation and stripping processes to fabricate the pad layer. However, this method suffers from drilling corrosion during the BOE etching process to form the second insulating layer opening. This causes voids in the Al and Ti metals in the metal interconnect layer on the sidewalls of the openings in the first insulating layer and the Bragg reflector layer below the second insulating layer. The current solution is to fabricate a layer with a thickness greater than [missing information - likely a thickness in another part] on top of the aforementioned metal interconnect layer. Au metal layer, utilizing greater than The Au metal layer prevents the BOE solution from corroding and avoids the formation of voids between Al and Ti metals in the metal bonding layer. However, such a thick Au metal layer greatly increases the manufacturing cost of light-emitting diode chips. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of this invention is to provide a flip-chip silver mirror light-emitting diode chip and its fabrication method.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a method for fabricating a flip-chip silver mirror light-emitting diode chip, comprising the following steps:

[0006] Step 1: Provide a substrate, and deposit an epitaxial layer on the surface of the substrate to form a P-type region and an N-type region;

[0007] Step 2: Sequentially deposit a current blocking layer and a Bragg reflector layer on the surfaces of the N-type region and the P-type region, and form Bragg reflector layer openings and current blocking layer openings;

[0008] Step 3: Fabricate a metal reflective layer on the openings in the current blocking layer and the Bragg reflective layer;

[0009] Step 4: Prepare a first insulating layer on the epitaxial layer after preparing the metal reflective layer, and form a first insulating layer opening, which includes a P-type first insulating layer opening and an N-type first insulating layer opening;

[0010] Step 5: Form a metal connection layer on the first insulating layer and the opening in the first insulating layer;

[0011] Step 6: Sequentially prepare a first sub-layer of the second insulating layer and a second sub-layer of the second insulating layer on the surfaces of the metal bonding layer and the first insulating layer not covered by the metal bonding layer; the corrosion rate of the second sub-layer of the second insulating layer is greater than the corrosion rate of the first sub-layer of the second insulating layer;

[0012] Step 7: Coat the surface of the second sub-layer of the second insulating layer with negative photoresist, expose and develop to form a negative photoresist pattern. The negative photoresist pattern includes a first negative photoresist located in the area around the second sub-layer of the second insulating layer, a second negative photoresist located in the area between the openings of the current blocking layer and the openings of the Bragg reflection layer, a third negative photoresist located in the soldering safety area, and a fourth negative photoresist located in the area between the openings of the N-type first insulating layer.

[0013] Step 8: Etch away the first sublayer of the second insulating layer and the second sublayer of the second insulating layer that are not covered by the negative photoresist, and cause the second negative photoresist and the fourth negative photoresist to fall off, while retaining the first sub-part of the first sublayer of the second insulating layer under the second negative photoresist and the second sub-part of the first sublayer of the second insulating layer under the fourth negative photoresist.

[0014] Step 9: Evaporate metal as the pad layer, then remove the first negative photoresist and the third negative photoresist and the metal on their surfaces to form the P-type pad layer and the N-type pad layer.

[0015] This fabrication method, by depositing second insulating sublayers with different etching rates and combining them with photolithography protection, can retain a portion of the second insulating layer above the Bragg reflector openings and the N-type first insulating layer openings after BOE etching. This avoids BOE solution penetration corrosion, prevents the formation of Al metal voids, and improves the LED's ability to withstand high current surges. Moreover, the metal interconnect layer of this invention does not require the use of precious metal Au as a protective sublayer, reducing the fabrication cost of the LED chip.

[0016] In a preferred embodiment, in step six, the first sublayer and the second sublayer of the second insulating layer are prepared using a PECVD process. When preparing the first sublayer of the second insulating layer, a first flow rate of N2O and a second flow rate of SiH4 are introduced, and the process temperature is a first temperature. When preparing the second sublayer of the second insulating layer, a third flow rate of N2O and a fourth flow rate of SiH4 are introduced, and the process temperature is a second temperature. The first flow rate is greater than the third flow rate, the second flow rate is less than the fourth flow rate, and the first temperature is greater than the second temperature.

[0017] In a preferred embodiment, the first flow rate is 2000 sccm to 2400 sccm, the second flow rate is 80 sccm to 100 sccm, the third flow rate is 1600 sccm to 2000 sccm, the fourth flow rate is 200 sccm to 220 sccm, the first temperature is 300℃ to 340℃, and the second temperature is 200℃ to 230℃.

[0018] In a preferred embodiment, in step seven, the second negative photoresist covers the hole walls of the current blocking layer opening and the Bragg reflection layer opening, and extends to the planes at both ends of the hole walls of the current blocking layer opening and the Bragg reflection layer opening, with an extension length of 2μm-5μm.

[0019] The fourth negative photoresist covers the hole wall of the N-type first insulating layer opening and extends to the planes at both ends of the hole wall of the N-type first insulating layer opening, with an extension length of 2μm-5μm.

[0020] In a preferred embodiment, in step eight, the thickness of the first sub-part of the first sub-layer of the second insulating layer and the thickness of the second sub-part of the first sub-layer of the second insulating layer are both...

[0021] In a preferred embodiment, in step five, the metal interconnect layer comprises, from bottom to top, a superlattice conductive layer and a protective layer.

[0022] In a preferred embodiment, the superlattice conductive layer comprises 3-5 sets of Al metal layer / Ti metal layer stacks, wherein the thickness of the Al metal layer is [missing information]. The thickness of the Ti metal layer is The protective sublayer is a stack of Cr metal layer / Ni metal layer / Ti metal layer, and the thickness of the Cr metal layer is [missing information]. The thickness of the Ni metal layer is The thickness of the Ti metal layer is

[0023] In a preferred embodiment, in step two, the thickness of the current blocking layer is >

[0024] In a preferred embodiment, in step two, the Bragg reflector layer comprises 5 to 10 TiO2 / SiO2 stacks.

[0025] In a preferred embodiment, in step nine, Ti / Ni / AuSn metal is vapor-deposited as a pad layer.

[0026] This application also provides a flip-chip silver mirror light-emitting diode chip, which is prepared using the above-described preparation method.

[0027] The beneficial effects of this invention are:

[0028] The method for fabricating a flip-chip silver mirror light-emitting diode of the present invention controls the etching rate of the second sublayer of the second insulating layer and the first sublayer of the second insulating layer in BOE solution. Combined with photolithography, a portion of the first sublayer of the second insulating layer is retained to protect the opening areas of the current blocking layer and the Bragg reflector layer, as well as the opening area of ​​the N-type first insulating layer. This prevents the BOE solution from penetrating into the hole walls of the current blocking layer and the Bragg reflector layer, as well as the metal interconnect layer above the N-type first insulating layer opening during BOE etching, thus preventing the formation of Al metal voids and improving the light-emitting diode's ability to withstand high current surges. Furthermore, in the solution of the present invention, only Cr, Ni, and Ti metals are needed as protective sublayers on the top of the metal interconnect layer, eliminating the need to use the precious metal Au as a protective sublayer, thereby reducing the fabrication cost of the light-emitting diode chip. Attached Figure Description

[0029] Figure 1 A schematic diagram of the cross-sectional structure of a diode chip after the formation of the P-type and N-type regions;

[0030] Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure of a diode chip obtained by fabricating a Bragg reflector layer and opening a hole in the Bragg reflector layer;

[0031] Figure 3 for Figure 2 A schematic diagram of the cross-sectional structure of a diode chip obtained by fabricating a current blocking layer and opening a hole in the current blocking layer;

[0032] Figure 4 for Figure 3 A schematic diagram of the cross-sectional structure of a diode chip obtained by fabricating a metal reflective layer;

[0033] Figure 5 for Figure 4 A schematic diagram of the cross-sectional structure of a diode chip obtained by fabricating the first insulating layer and opening a hole in the first insulating layer;

[0034] Figure 6 for Figure 5 A schematic diagram of the cross-sectional structure of a diode chip obtained by fabricating a metal interconnect layer;

[0035] Figure 7 for Figure 6 A schematic diagram of the cross-sectional structure of a diode chip obtained by fabricating the first sublayer of the second insulating layer and the second sublayer of the second insulating layer;

[0036] Figure 8 for Figure 7 A schematic diagram of the cross-sectional structure of a diode chip obtained by coating negative photoresist, exposing and developing it, and retaining part of the negative photoresist.

[0037] Figure 9 for Figure 8 A schematic diagram of the cross-sectional structure of the diode chip obtained after BOE etching.

[0038] Figure 10 for Figure 9 A schematic diagram of the cross-sectional structure of a diode chip obtained after evaporating metal as a pad layer.

[0039] Figure 11 for Figure 10 A schematic diagram of the cross-sectional structure of the diode chip obtained after removing the remaining negative photoresist;

[0040] Explanation of key component symbols:

[0041] 10. Substrate; 111. N-type semiconductor layer; 112. Active light-emitting layer; 113. P-type semiconductor layer; 114. Conductive step of N-type semiconductor layer; 12. Current spreading layer; 13. Current blocking layer; 131. Current blocking layer opening; 14. Bragg reflector layer; 141. Bragg reflector layer opening; 15. Metal reflector layer; 16. First insulating layer; 161. P-type first insulating layer opening; 162. N-type first insulating layer opening; 171. 172. P-type metal interconnect layer; 181. N-type metal interconnect layer; 181. First sub-layer of the second insulating layer; 1811. First sub-section of the first sub-layer of the second insulating layer; 1812. Second sub-section of the first sub-layer of the second insulating layer; 182. Second sub-layer of the second insulating layer; 191. First negative photoresist; 192. Second negative photoresist; 193. Third negative photoresist; 194. Fourth negative photoresist; 201. P-type pad layer; 202. N-type pad layer. Detailed Implementation

[0042] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0043] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing alternative embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0045] This invention provides a method for fabricating a flip-chip silver mirror light-emitting diode chip, comprising the following steps:

[0046] Step 1: Provide a substrate and deposit an epitaxial layer on the surface of the substrate to form P-type and N-type regions.

[0047] Optionally, refer to Figure 1 Step one specifically includes:

[0048] A substrate 10 is provided, which can be one of GaN, Al2O3 and Si. The epitaxial layer can be deposited by metal chemical vapor deposition (MOCVD), in which an N-type semiconductor layer 111, an active light-emitting layer 112 and a P-type semiconductor layer 113 are deposited sequentially on the substrate 10 to form the epitaxial layer.

[0049] Then, indium tin oxide is deposited as a current spreading layer 12 on the surface of the P-type semiconductor layer 113 using a magnetron sputtering process, and a P-type region is formed on the epitaxial layer.

[0050] Next, photoresist is coated on the surface of the current spreading layer 12. Then, exposure and development are used to remove part of the photoresist, exposing part of the current spreading layer. Then, indium tin oxide etching solution is used to remove the exposed current spreading layer, exposing the underlying P-type semiconductor layer. Then, inductively coupled plasma etching process is used to remove the exposed P-type semiconductor layer and the active light-emitting layer under this part of the P-type semiconductor, forming the N-type semiconductor layer conductive step 114. Then, the photoresist is removed, and an N-type region is formed on the epitaxial layer.

[0051] Step 2: Sequentially deposit a current blocking layer and a Bragg reflection layer on the surfaces of the N-type region and the P-type region, and form Bragg reflection layer openings and current blocking layer openings.

[0052] Optionally, refer to Figures 2-3 Step two specifically includes:

[0053] A current blocking layer is deposited on the surfaces of the N-type and P-type regions using a PECVD process. Specifically, SiO2 is deposited as the current blocking layer 13 on the surfaces of the current spreading layer 12, the P-type semiconductor layer 113 not covered by the current spreading layer 12, and the conductive steps 114 of the N-type semiconductor layer. The thickness of the current blocking layer 13 is greater than [missing information].

[0054] Next, a stack of TiO2 and SiO2 is alternately deposited on the current blocking layer 13 for several cycles using an electron beam evaporation process as a Bragg reflector layer 14, wherein the alternating deposition cycle of TiO2 and SiO2 is 5 to 10.

[0055] Photoresist is coated on the surface of the Bragg reflector layer 14. Then, exposure and development are used to remove part of the photoresist, exposing the Bragg reflector layer under the photoresist. Then, inductively coupled plasma etching process is used to remove the exposed part of the Bragg reflector layer, forming the Bragg reflector layer opening 141. Then, the photoresist is removed.

[0056] Next, photoresist is applied to the Bragg reflector opening 141 and the remaining surface of the Bragg reflector. Then, exposure and development are used to remove part of the photoresist, exposing the current blocking layer 13 under the photoresist. Then, BOE etching solution is used to remove the exposed current blocking layer, forming the current blocking layer opening 131. Finally, the photoresist is removed.

[0057] Step 3: Prepare a metal reflective layer on the opening in the current blocking layer and the Bragg reflective layer.

[0058] Optionally, refer to Figure 4 Step three specifically includes:

[0059] Photoresist is applied to the opening 131 of the current blocking layer and the exposed area of ​​the current blocking layer, as well as to the Bragg reflective layer 14. Then, exposure and development are used to remove part of the photoresist. Then, Ag / Ni / Ti / Ni / Ti / Ni / Ti / Ni / Ti metal is deposited sequentially using an electron beam evaporation process. Then, the metal on the photoresist is removed using a blue film stripping process. Finally, the photoresist is removed to obtain the metal reflective layer 15.

[0060] Step 4: Prepare a first insulating layer on the epitaxial layer after preparing the metal reflective layer, and form a first insulating layer opening, which includes a P-type first insulating layer opening and an N-type first insulating layer opening.

[0061] Optionally, refer to Figure 5 Step four specifically includes:

[0062] An Al2O3 thin film is deposited on the metal reflective layer 15 using the ALD (atomic layer deposition) process, and then a SiO2 thin film is deposited on the Al2O3 thin film using the PECVD process to form the first insulating layer 16.

[0063] Then, photoresist is coated on the surface of the first insulating layer 16. Then, exposure and development are used to remove part of the photoresist, exposing part of the first insulating layer. Then, inductively coupled plasma etching is used to remove part of the first insulating layer exposed on the metal reflective layer, forming a P-type first insulating layer opening 161. At the same time, inductively coupled plasma etching is used to remove the current blocking layer, Bragg reflective layer and first insulating layer on the N-type semiconductor layer conductive step 114 until the N-type semiconductor layer conductive step is exposed, forming an N-type first insulating layer opening 162. Then, the photoresist is removed.

[0064] Step 5: Form a metal connection layer on the first insulating layer and the opening in the first insulating layer.

[0065] Optional, see reference Figure 6 Step five specifically includes:

[0066] Photoresist is coated on the surface of the first insulating layer 16 and the opening of the first insulating layer. Then, exposure and development are performed to remove part of the photoresist. Then, a certain amount of metal is deposited using an electron beam evaporation process. Then, a blue film stripping process is used to remove the metal located on the photoresist. Then, the photoresist is removed to form a metal interconnect layer. The metal interconnect layer includes a P-type metal interconnect layer 171 located above the epitaxial layer and an N-type metal interconnect layer 172 located above the conductive steps of the N semiconductor layer.

[0067] Optionally, the metal interconnect layer comprises, from bottom to top, a superlattice conductive layer and a protective layer. The superlattice conductive layer comprises 3 to 5 sets of Al metal layer / Ti metal layer stacks, wherein the thickness of the Al metal layer is between [missing information]. The thickness of the Ti metal layer is between The protective sublayer is a stack of Cr metal layers / Ni metal layers / Ti metal layers from top to bottom, wherein the thickness of the Cr metal layer is between The thickness of the Ni metal layer is between The thickness of the Ti metal layer is between

[0068] Step 6: Sequentially prepare a first sub-layer of the second insulating layer and a second sub-layer of the second insulating layer on the surfaces of the metal bonding layer and the first insulating layer not covered by the metal bonding layer; the corrosion rate of the second sub-layer of the second insulating layer is greater than the corrosion rate of the first sub-layer of the second insulating layer.

[0069] Optional, see reference Figure 7 Step six specifically includes:

[0070] A first sublayer 181 of a second insulating layer is prepared on the surface of a P-type metal interconnect layer 171, an N-type metal interconnect layer 172, and a first insulating layer 16 not covered by the metal interconnect layer using a first PECVD process. Then, a second sublayer 182 of a second insulating layer is prepared on the first sublayer 181 of the second insulating layer using a second PECVD process.

[0071] To ensure that the corrosion rate of the second sublayer 182 of the second insulating layer is greater than that of the first sublayer 181 of the second insulating layer, BOE solution etching is typically used. The process can be configured such that a first flow rate of N2O and a second flow rate of SiH4 are introduced during the first PECVD process, and the process temperature is set to a first temperature; and a third flow rate of N2O and a fourth flow rate of SiH4 are introduced during the second PECVD process, and the process temperature is set to a second temperature. In this configuration, the first flow rate is greater than the third flow rate, the second flow rate is less than the fourth flow rate, and the first temperature is greater than the second temperature. This ensures that the corrosion rate of the second sublayer of the second insulating layer in the BOE solution is greater than that of the first sublayer of the second insulating layer in the BOE solution.

[0072] Optionally, the first flow rate is 2000 sccm to 2400 sccm, the second flow rate is 80 sccm to 100 sccm, the third flow rate is 1600 sccm to 2000 sccm, the fourth flow rate is 200 sccm to 220 sccm, the first temperature is 300℃ to 340℃, and the second temperature is between 200℃ and 230℃.

[0073] Step 7: Coat the surface of the second sub-layer of the second insulating layer with negative photoresist, expose and develop to form a negative photoresist pattern. The negative photoresist pattern includes a first negative photoresist located in the area surrounding the second sub-layer of the second insulating layer, a second negative photoresist located in the area between the openings of the current blocking layer and the openings of the Bragg reflector layer, a third negative photoresist located in the soldering safety area, and a fourth negative photoresist located in the area between the openings of the N-type first insulating layer.

[0074] Optional, see reference Figure 8 Step seven specifically includes:

[0075] A negative photoresist is completely coated on the surface of the second sublayer 182 of the second insulating layer. Then, exposure and development are used to remove part of the photoresist to form a negative photoresist pattern. The negative photoresist pattern includes a first negative photoresist 191 located in the area around the second sublayer of the second insulating layer, a second negative photoresist 192 located in the area of ​​the opening wall of the current blocking layer and the Bragg reflection layer, a third negative photoresist 193 located in the soldering safety area, and a fourth negative photoresist 194 located in the area of ​​the opening wall of the N-type first insulating layer.

[0076] In a preferred embodiment, the second negative photoresist 192 not only covers the hole walls of the current blocking layer opening and the Bragg reflector layer opening, but also extends to the planes at both ends of the hole walls of the current blocking layer opening and the Bragg reflector layer opening. This ensures that the insulating layer retained in subsequent steps also has an extension, preventing BOE corrosion. Preferably, the extension length is 2μm-5μm; if it is greater than 5μm, the second negative photoresist may not detach in subsequent steps; if it is less than 2μm, the effect of preventing BOE corrosion is weakened.

[0077] Similarly, the fourth negative photoresist 194 not only covers the hole wall of the N-type first insulating layer opening, but also extends to the planes at both ends of the hole wall of the N-type first insulating layer opening, with an extension length of 2μm-5μm.

[0078] Step 8: Etch away the first sublayer of the second insulating layer and the second sublayer of the second insulating layer that are not covered by the negative photoresist, and cause the second negative photoresist and the fourth negative photoresist to fall off, leaving the first sub-part of the first sublayer of the second insulating layer under the second negative photoresist and the second sub-part of the first sublayer of the second insulating layer under the fourth negative photoresist.

[0079] Optionally, refer to Figure 9 Step eight specifically includes:

[0080] When BOE etching solution is used, the first and second sublayers of the second insulating layer at locations without negative photoresist protection will be completely etched away. At the same time, since the BOE solution can enter from the side, and because the etching rate of the second sublayer of the second insulating layer is greater than that of the first sublayer, the second sublayers of the second insulating layer under the second negative photoresist 192 and the fourth negative photoresist 194 will be completely etched away before the BOE etching ends. Therefore, the second negative photoresist 192 and the fourth negative photoresist 194 will be detached during BOE etching.

[0081] In addition, because the second negative photoresist 192 and the fourth negative photoresist 194 are present at the beginning of the etching stage, the second insulating layer under these two photoresists is more difficult to etch than the area without photoresist. Therefore, when the first sublayer of the second insulating layer in the area protected by the negative photoresist is completely etched away, the first sublayer of the second insulating layer under the second negative photoresist 192 and the fourth negative photoresist 194 will still have a certain thickness remaining. That is, when the BOE etching is completed and the first sublayer of the second insulating layer in the area without negative photoresist protection is completely etched away, the first sublayer of the second insulating layer above the hole walls of the current blocking layer opening 131 and the Bragg reflection layer opening 141 still retains the first sub-part 1811 of the first sublayer of the second insulating layer, and the first sublayer of the second insulating layer above the hole wall of the N-type first insulating layer opening 162 still retains the second sub-part 1812 of the first sublayer of the second insulating layer.

[0082] Thus, due to the presence of the first sub-part 1811 of the first sub-layer of the second insulating layer and the second sub-part 1812 of the first sub-layer of the second insulating layer, the BOE solution cannot penetrate into the walls of the current blocking layer opening 131 and the Bragg reflector layer opening 141, as well as the metal interconnect layer above the N-type first insulating layer opening 162, during the BOE etching process. This prevents the formation of Al metal voids and improves the LED's ability to withstand high current surges. Moreover, the top of the metal interconnect layer of this invention only requires Cr, Ni, or Ti metals as a protective sub-layer, eliminating the need for the noble metal Au, thereby reducing the manufacturing cost of the LED chip.

[0083] Optionally, the thickness H of the first sub-part of the first sub-layer of the second insulating layer and the second sub-part of the first sub-layer of the second insulating layer are both within the range of... If the thickness H is greater than In areas without negative photoresist protection, the first sublayer of the second insulating layer is at risk of incomplete corrosion; if the thickness is less than... BOE is at risk of corrosion during drilling.

[0084] Step 9: Evaporate metal as the pad layer, then remove the first negative photoresist and the third negative photoresist and the metal on their surfaces to form the P-type pad layer and the N-type pad layer.

[0085] Optional, see reference Figures 10-11 Step nine specifically includes:

[0086] First, Ti / Ni / AuSn metals are sequentially deposited using an electron beam evaporation process to form a P-type pad layer 201 and an N-type pad layer 202 as pad layers. Then, the metals located on the first negative photoresist 191 and the third negative photoresist 193 are removed using a blue film stripping process. Finally, the first negative photoresist 191 and the third negative photoresist 193 are removed using a photoresist removal process.

[0087] The following description, in conjunction with specific embodiments, provides further details.

[0088] Example 1

[0089] This invention provides a method for fabricating a flip-chip silver mirror light-emitting diode, comprising the following steps:

[0090] S1: Provide a GaN substrate, and sequentially prepare an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer on the substrate using metal chemical vapor deposition.

[0091] Indium tin oxide is deposited as a current spreading layer on the surface of the P-type semiconductor layer using a magnetron sputtering process, and a P-type region is formed on the epitaxial layer.

[0092] Then, photoresist is coated on the surface of the indium tin oxide current spreading layer. Then, exposure and development are used to remove part of the photoresist, exposing part of the indium tin oxide. Then, the exposed indium tin oxide is removed using an indium tin oxide etching solution, exposing the P-type semiconductor layer under this part of the indium tin oxide. Then, inductively coupled plasma etching process is used to remove the exposed P-type semiconductor layer and the active light-emitting layer under this part of the P-type semiconductor, forming an N-type semiconductor layer conductive step. Then, the photoresist is removed, and a P-type region is formed on the epitaxial layer.

[0093] S2: Using PECVD technology, SiO2 is deposited as a current blocking layer on the surface of the N-type region and the P-type region, i.e., the current spreading layer, the P-type semiconductor layer not covered by the current spreading layer, and the N-type semiconductor conductive step. The thickness of the current blocking layer is [missing information].

[0094] Next, an electron beam evaporation process is used to alternately deposit a stack of TiO2 and SiO2 as a Bragg reflector layer on the current blocking layer, with the alternating deposition cycle of TiO2 and SiO2 being 8.

[0095] Photoresist is coated on the surface of the Bragg reflector layer. Then, exposure and development are used to remove part of the photoresist, exposing the Bragg reflector layer underneath. Then, inductively coupled plasma etching is used to remove the exposed part of the Bragg reflector layer, forming an opening in the Bragg reflector layer. Finally, the photoresist is removed.

[0096] Photoresist is applied to the opening in the Bragg reflector layer and the remaining surface of the Bragg reflector layer. Then, exposure and development are used to remove part of the photoresist, exposing the current blocking layer under the photoresist. The exposed current blocking layer is then removed using BOE etching solution to form the current blocking layer opening. Finally, the photoresist is removed.

[0097] S3: Photoresist is applied to the openings in the current blocking layer and the exposed areas of the current blocking layer, as well as to the Bragg reflective layer. Then, exposure and development are used to remove part of the photoresist. Then, Ag / Ni / Ti / Ni / Ti / Ni / Ti / Ni / Ti metal is sequentially deposited as a metal reflective layer using an electron beam evaporation process. Then, the metal on top of the photoresist is removed using a blue film stripping process, and then the photoresist is removed.

[0098] S4: An Al2O3 thin film is deposited on the metal reflective layer using the ALD process, and then a SiO2 thin film is deposited on the Al2O3 thin film using the PECVD process to form the first insulating layer.

[0099] Then, photoresist is coated on the surface of the first insulating layer. Then, exposure and development are used to remove part of the photoresist, exposing part of the first insulating layer. Then, inductively coupled plasma etching is used to remove part of the insulating layer exposed on the metal reflective layer, forming a P-type first insulating layer opening. At the same time, inductively coupled plasma etching is used to remove the current blocking layer, Bragg reflective layer and first insulating layer on the conductive steps of the N-type semiconductor layer until the conductive steps of the N-type semiconductor layer are exposed, forming an N-type first insulating layer opening. Then, the photoresist is removed.

[0100] S5: Photoresist is coated on the first insulating layer and the surface of the openings in the first insulating layer. Then, exposure and development are performed to remove part of the photoresist. Next, an electron beam evaporation process is used to sequentially deposit a superlattice conductive layer and a protective layer to form a metal interconnect layer. The superlattice conductive layer includes four sets of Al / Ti metal layer stacks, with the Al metal layer having a thickness of [missing information]. The thickness of the Ti metal layer is The protective sublayer is a stack of Cr metal layers / Ni metal layers / Ti metal layers from top to bottom, with the Cr metal layer having a thickness of [missing information]. The thickness of the Ni metal layer is The thickness of the Ti metal layer is

[0101] Then, the metal on the photoresist is removed using a blue film stripping process, and then the photoresist is removed to form a metal interconnect layer; the metal interconnect layer includes a P-type metal interconnect layer above the epitaxial layer and an N-type metal interconnect layer above the conductive steps of the N semiconductor layer.

[0102] S6: The first sublayer of the second insulating layer is prepared on the surface of the metal connection layer and the first insulating layer not covered by the metal connection layer using the first PECVD process. During the first PECVD process, 2200 sccm of N2O and 90 sccm of SiH4 are introduced, and the process temperature is 330°C.

[0103] Then, a second sublayer of the second insulating layer is prepared on the first sublayer of the second insulating layer using a second PECVD process. During the second PECVD process, 1800 sccm of N2O and 210 sccm of SiH4 are introduced, and the process temperature is 220℃.

[0104] S7: A negative photoresist is completely coated on the surface of the second sub-layer of the second insulating layer, and then a negative photoresist pattern is formed by exposure and development. The negative photoresist pattern includes a first negative photoresist located in the area around the second sub-layer of the second insulating layer, a second negative photoresist located in the area of ​​the opening wall of the current blocking layer and the Bragg reflection layer, a third negative photoresist located in the soldering safety area, and a fourth negative photoresist located in the area of ​​the opening wall of the N-type first insulating layer.

[0105] The second negative photoresist not only covers the walls of the current blocking layer opening and the Bragg reflector layer opening, but also extends to the planes at both ends of the opening wall, with an extension length of 2 μm. Similarly, the fourth negative photoresist not only covers the walls of the opening located in the N-type first insulating layer, but also extends to the planes at both ends of the opening wall, with an extension length of 2 μm.

[0106] S8: Using BOE etching solution, the first and second sublayers of the second insulating layer in the areas not protected by negative photoresist are completely etched away. Because the etching rate of the second sublayer of the second insulating layer is greater than that of the first sublayer of the second insulating layer, the second sublayer of the second insulating layer under the second negative photoresist and under the fourth negative photoresist will be completely etched away before the BOE etching ends, and the second and fourth negative photoresists will fall off. Moreover, after the etching is completed, the first sublayer of the first sublayer of the second insulating layer and the second sublayer of the first sublayer of the second insulating layer are retained under the second and fourth negative photoresists, respectively.

[0107] The thickness H of the first sub-section of the first sub-layer of the second insulating layer and the second sub-section of the first sub-layer of the second insulating layer are both... Since both the second negative photoresist and the fourth negative photoresist extend and cover the planes at both ends of the hole wall, the first sub-part of the first sub-layer of the second insulating layer and the second sub-part of the first sub-layer of the second insulating layer also have corresponding extensions, and the length L of the extension is 2μm.

[0108] S9: Using electron beam evaporation, Ti / Ni / AuSn metals are sequentially deposited on the chip surface obtained in the above steps to form P-type pad layers and N-type pad layers. Then, the metals located on the first negative photoresist and the third negative photoresist are removed using a blue film stripping process. Finally, the first negative photoresist and the third negative photoresist are removed using a photoresist removal process.

[0109] Example 2

[0110] The difference between this embodiment and Embodiment 1 is that the thickness H of the first sub-part of the first sub-layer of the second insulating layer and the second sub-part of the first sub-layer of the second insulating layer is... The length L of the extension is 2 μm.

[0111] Example 3

[0112] The difference between this embodiment and Embodiment 1 is that the thickness H of the first sub-part of the first sub-layer of the second insulating layer and the second sub-part of the first sub-layer of the second insulating layer is... The length L of the extension is 5 μm.

[0113] Comparative Example

[0114] The comparative example uses existing methods to prepare the second insulating layer. The difference from Example 1 is in steps S5-S8, while the rest are the same. Steps S5-S8 are as follows:

[0115] S5: Photoresist is coated on the first insulating layer and the surface of the openings in the first insulating layer. Then, exposure and development are performed to remove part of the photoresist. Next, an electron beam evaporation process is used to sequentially deposit a superlattice conductive layer and a protective layer to form a metal interconnect layer. The superlattice conductive layer includes four sets of Al / Ti metal stacks, with the Al metal thickness being... The thickness of Ti metal is The protective sublayer is a top-down stack of Au / Cr / Ni / Ti metals, with an Au metal thickness of [missing information]. Cr metal thickness is

[0116] Ni metal thickness is The thickness of Ti metal is

[0117] Then, the metal on the photoresist is removed using a blue film stripping process, and then the photoresist is removed to form a metal interconnect layer; the metal interconnect layer includes a P-type metal interconnect layer above the epitaxial layer and an N-type metal interconnect layer above the conductive steps of the N semiconductor layer.

[0118] S6: A second insulating layer is prepared on the surface of the metal bonding layer and the first insulating layer not covered by the metal bonding layer using a PECVD process. During the PECVD process, 1700 sccm of N2O and 170 sccm of SiH4 are introduced, and the process temperature is 270℃.

[0119] S7: A negative photoresist is completely coated on the surface of the second insulating layer, and then a negative photoresist pattern is formed by exposure and development. The negative photoresist pattern includes a first negative photoresist located in the area surrounding the second sublayer of the second insulating layer, and a third negative photoresist located in the soldering safety area.

[0120] S8: Using BOE etching solution, the second insulating layer at the location without negative photoresist protection will be completely etched away, forming an opening in the second insulating layer.

[0121] In this comparative example, if a layer with a thickness greater than [missing information] is not prepared on the top layer of the protective sublayer of the metal connection layer... If the Au metal layer is missing, it will cause corrosion of the BOE solution, and the Al and Ti metals in the metal bonding layer will form voids.

[0122] A 1400μm × 1400μm LED chip was prepared according to the above embodiments and comparative examples, and subjected to a long-term high-current aging test at room temperature (25℃). The high current was three times the operating current. The chip brightness was recorded before aging as the initial brightness. During the aging process, the chip brightness was measured every 24 hours as the real-time brightness. When the ratio of the real-time brightness to the initial brightness was less than 90%, the chip was considered to have failed. The operating current during the aging test was 1000mA, and the high-current for aging was 3000mA. The test results are shown in Table 1.

[0123] Table 1. Aging test results of the examples and comparative examples.

[0124]

[0125] The technical features of the embodiments described above can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A method for fabricating a flip-chip silver mirror light-emitting diode, characterized in that, Includes the following steps: Step 1: Provide a substrate, and deposit an epitaxial layer on the surface of the substrate to form a P-type region and an N-type region; Step 2: Sequentially deposit a current blocking layer and a Bragg reflector layer on the surfaces of the N-type region and the P-type region, and form Bragg reflector layer openings and current blocking layer openings; Step 3: Fabricate a metal reflective layer on the openings in the current blocking layer and the Bragg reflective layer; Step 4: Prepare a first insulating layer on the epitaxial layer after preparing the metal reflective layer, and form a first insulating layer opening, which includes a P-type first insulating layer opening and an N-type first insulating layer opening; Step 5: Form a metal connection layer on the first insulating layer and the opening in the first insulating layer; Step 6: Sequentially prepare a first sub-layer of the second insulating layer and a second sub-layer of the second insulating layer on the surfaces of the metal bonding layer and the first insulating layer not covered by the metal bonding layer; the corrosion rate of the second sub-layer of the second insulating layer is greater than the corrosion rate of the first sub-layer of the second insulating layer; Step 7: Coat the surface of the second sub-layer of the second insulating layer with negative photoresist, expose and develop to form a negative photoresist pattern. The negative photoresist pattern includes a first negative photoresist located in the area around the second sub-layer of the second insulating layer, a second negative photoresist located in the area between the openings of the current blocking layer and the openings of the Bragg reflection layer, a third negative photoresist located in the soldering safety area, and a fourth negative photoresist located in the area between the openings of the N-type first insulating layer. Step 8: Etch away the first sublayer of the second insulating layer and the second sublayer of the second insulating layer that are not covered by the negative photoresist, and cause the second negative photoresist and the fourth negative photoresist to fall off, while retaining the first sub-part of the first sublayer of the second insulating layer under the second negative photoresist and the second sub-part of the first sublayer of the second insulating layer under the fourth negative photoresist. Step 9: Evaporate metal as the pad layer, then remove the first negative photoresist and the third negative photoresist and the metal on their surfaces to form the P-type pad layer and the N-type pad layer.

2. The preparation method according to claim 1, characterized in that, In step six, the first sublayer of the second insulating layer and the second sublayer of the second insulating layer are prepared using the PECVD process. When preparing the first sublayer of the second insulating layer, N2O with a first flow rate and SiH4 with a second flow rate are introduced, and the process temperature is the first temperature. When preparing the second sublayer of the second insulating layer, N2O with a third flow rate and SiH4 with a fourth flow rate are introduced, and the process temperature is the second temperature. The first flow rate is greater than the third flow rate, the second flow rate is less than the fourth flow rate, and the first temperature is greater than the second temperature.

3. The preparation method according to claim 2, characterized in that, The first flow rate is 2000 sccm to 2400 sccm, and the second flow rate is 80 sccm to 100 sccm. The third flow rate is 1600 sccm to 2000 sccm, and the fourth flow rate is 200 sccm to 220 sccm. The first temperature is 300℃~340℃, and the second temperature is 200℃~230℃.

4. The preparation method according to claim 1, characterized in that, In step seven, The second negative photoresist covers the hole walls of the current blocking layer opening and the Bragg reflection layer opening, and extends to the planes at both ends of the hole walls of the current blocking layer opening and the Bragg reflection layer opening, with an extension length of 2μm-5μm; The fourth negative photoresist covers the hole wall of the N-type first insulating layer opening and extends to the planes at both ends of the hole wall of the N-type first insulating layer opening, with an extension length of 2μm-5μm.

5. The preparation method according to claim 1, characterized in that, In step eight, the thickness of the first sub-section of the first sub-layer of the second insulating layer and the second sub-section of the first sub-layer of the second insulating layer are both...

6. The preparation method according to claim 1, characterized in that, In step five, the metal interconnect layer comprises, from bottom to top, a superlattice conductive layer and a protective layer.

7. The preparation method according to claim 6, characterized in that, The superlattice conductive electronic layer comprises 3-5 sets of Al metal layer / Ti metal layer stacks, wherein the thickness of the Al metal layer is [missing information]. The thickness of the Ti metal layer is The protective sublayer is a stack of Cr metal layer / Ni metal layer / Ti metal layer, and the thickness of the Cr metal layer is [missing information]. The thickness of the Ni metal layer is The thickness of the Ti metal layer is 8. The preparation method according to claim 1, characterized in that, In step two, the thickness of the current blocking layer is > The Bragg reflector layer comprises 5 to 10 TiO2 / SiO2 stacks.

9. The preparation method according to claim 1, characterized in that, In step nine, Ti / Ni / AuSn metal is vapor-deposited as the pad layer.

10. A flip-chip silver mirror light-emitting diode chip, characterized in that, It is prepared by the preparation method described in any one of claims 1 to 9.

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