A flip silver mirror light emitting diode chip preparation method and flip silver mirror light emitting diode chip

Abstract

The present application relates to the technical field of semiconductor devices, in particular to a flip silver mirror light emitting diode chip preparation method and a flip silver mirror light emitting diode chip. The preparation method improves the preparation process of the P-type first insulation layer via hole and the N-type first insulation layer via hole, sets part of the exposure area on the photoetching plate, retains part of the photoresist of the P-type area opening, and the insulation layer above the P-type area opening can still be retained after etching, so that the Cl ion corrosion is avoided, the P-type first insulation layer via hole and the N-type first insulation layer via hole can be prepared together, the preparation cost of the light emitting diode chip is greatly reduced without batch preparation, and a thicker noble metal is not needed to be prepared on the top layer of the metal reflection layer to serve as a protective layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a method for fabricating a flip-chip silver mirror light-emitting diode (LED) chip and the flip-chip silver mirror LED chip itself. Background Technology

[0002] Flip-chip LEDs are widely used due to their advantages such as back-side light emission, good solderability, high thrust, and high reliability.

[0003] Existing flip-chip LED chips require the fabrication of both a P-type first insulating layer via above the metal reflective layer and an N-type first insulating layer via above the conductive steps of the N-type semiconductor layer. When fabricating the N-type first insulating layer via using inductively coupled plasma (ICP-P) technology, Cl2 must be used. However, the Cl ions ionized by Cl2 react with the Ni metal on the top layer of the metal reflective layer, reducing the protective ability of the Ni metal against the Ag metal.

[0004] There are two existing solutions. The first solution involves preparing the N-type and P-type first insulating layer vias separately, using Cl2 to prepare the N-type vias and CF4 to prepare the P-type vias. The second solution involves preparing an additional layer on top of the metal reflective layer with a thickness greater than [missing information]. Au metal is used as a protective layer to prevent Cl ions from reacting with Ni metal. Method one requires additional fabrication steps, significantly increasing the cost of the LED chip; Method two requires the addition of the noble metal Au, similarly significantly increasing the cost of the LED chip. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this invention is to provide a method for fabricating a flip-chip silver mirror light-emitting diode chip and the flip-chip silver mirror light-emitting diode chip prepared by the method.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: a method for fabricating a flip-chip silver mirror light-emitting diode chip, comprising the following steps:

[0007] Step 1: Provide a substrate, deposit an epitaxial layer on the surface of the substrate, and form P-type and N-type regions;

[0008] Step 2: Sequentially deposit a current blocking layer and a Bragg reflection layer on the surfaces of the N-type region and the P-type region, and form vias in the Bragg reflection layer and vias in the current blocking layer;

[0009] Step 3: Fabricate a metal reflective layer on the current blocking layer via and the Bragg reflective layer;

[0010] Step 4: Prepare a first insulating layer on the epitaxial layer after preparing the metal reflective layer, then coat the first insulating layer with photoresist, and expose and develop it using a photomask. The photomask includes a completely opaque area, a partially transparent area, and a completely transparent area. The partially transparent area corresponds to the position of the P-type first insulating layer via, and the completely transparent area corresponds to the position of the N-type first insulating layer via.

[0011] The photoresist corresponding to the fully transparent area is fully developed to form an N-type photoresist opening;

[0012] The photoresist portion corresponding to the light-transmitting area is developed to form a P-type photoresist opening;

[0013] Step 5: Etching, exposing the conductive step surface of the N-type semiconductor layer at the N-type photoresist opening, forming an N-type first insulating layer via; the first insulating layer remains at the P-type photoresist opening;

[0014] Step 6: Remove the remaining first insulating layer at the P-type photoresist opening to form a P-type first insulating layer through-hole; finally, remove the photoresist.

[0015] The fabrication method of this invention sets a partial exposure area on the photomask, so that a certain thickness of photoresist remains at the P-type photoresist opening after photolithography. After etching, a certain thickness of the first insulating layer remains at the P-type photoresist opening. Then, the remaining insulating layer is etched away with BOE solution. In this way, Cl ions cannot come into contact with the Ni metal on the top layer of the metal reflective layer during the etching process. It is also not necessary to fabricate the P-type and N-type first insulating layer vias in two separate steps, nor is it necessary to fabricate a thick noble metal protective layer on the top layer of the metal reflective layer, which greatly reduces the fabrication cost of the light-emitting diode chip.

[0016] In a preferred embodiment, in step four, the transmittance of a portion of the light-transmitting area of ​​the photomask to the wavelength used for exposure is 70%-90%.

[0017] In a preferred embodiment, in step four, the undeveloped remaining photoresist thickness at the P-type photoresist opening is H, and the undeveloped remaining photoresist thickness H at the P-type photoresist opening is...

[0018] In a preferred embodiment, in step five, the remaining thickness of the first insulating layer at the P-type photoresist opening is H1, where H1 is...

[0019] In a preferred embodiment, in step five, inductively coupled plasma etching is used, with an upper etching power of 800W-1200W and a lower etching power of 200W-400W. The etching gas includes BCl3 and Cl2, with a BCl3 flow rate of 15sccm-30sccm and a Cl2 flow rate of 80sccm-100sccm.

[0020] In a preferred embodiment, in step six, the first insulating layer at the opening of the P-type photoresist is removed using a BOE solution. The BOE solution is a mixture of NH4F solution and HF solution, wherein the concentration of NH4F solution is 35wt% to 40wt%, the concentration of HF solution is 2wt% to 3wt%, and the volume ratio of NH4F solution to HF solution is 40:1 to 30:1.

[0021] In a preferred embodiment, in step three, the metal reflective layer is an Ag / Ni / Ti / Ni stack, wherein the thickness of the Ag metal layer is [missing information]. The thickness of the Ni metal layer above the Ag metal layer is: The thickness of the Ti metal layer above the Ni metal layer is The thickness of the Ni metal layer above the Ti metal layer is

[0022] In a preferred embodiment, in step two, the thickness of the current blocking layer is >

[0023] In a preferred embodiment, in step two, the Bragg reflector layer comprises 5 to 10 TiO2 / SiO2 stacks.

[0024] In a preferred embodiment, the preparation method of the present invention may further include the following steps:

[0025] Step 7: Form a metal connection layer on the first insulating layer and the through-hole of the first insulating layer, wherein the metal connection layer includes a P-type metal pad layer and an N-type metal pad layer;

[0026] Step 8: Prepare a second insulating layer on the metal connection layer, and form P-type second insulating layer vias and N-type second insulating layer vias.

[0027] This application also provides a flip-chip silver mirror light-emitting diode chip, which is prepared using the above-described flip-chip light-emitting diode chip preparation method.

[0028] The beneficial effects of this invention are:

[0029] The method for fabricating a flip-chip silver mirror light-emitting diode of the present invention improves the photolithography structure by using different transmittance for different regions, retaining part of the photoresist for the P-type region openings, and ensuring that a certain thickness of insulating layer remains above the P-type region openings after etching, thus avoiding Cl ion corrosion during the etching process. Moreover, the P-type first insulating layer vias and N-type first insulating layer vias can be fabricated together without batch processing, and there is no need to fabricate a thick noble metal protective layer on top of the metal reflective layer, which greatly reduces the fabrication cost of the light-emitting diode chip. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the cross-sectional structure of the flip-chip light-emitting diode obtained in step one of the embodiments of the present invention;

[0031] Figure 2 This is a schematic diagram of the cross-sectional structure of the flip-chip light-emitting diode obtained in step two of the embodiments of the present invention;

[0032] Figure 3 This is a schematic diagram of the cross-sectional structure of the flip-chip light-emitting diode obtained in step three of the present invention.

[0033] Figure 4 This is a schematic diagram of the cross-sectional structure of the flip-chip light-emitting diode obtained in step four of this embodiment of the invention;

[0034] Figure 5 This is a schematic diagram of the cross-sectional structure of the flip-chip light-emitting diode obtained in step five of this embodiment of the invention;

[0035] Figure 6 This is a schematic diagram of the cross-sectional structure of the flip-chip light-emitting diode obtained in step six of this embodiment of the invention;

[0036] Figure 7 This is a schematic diagram of the cross-sectional structure of the flip-chip light-emitting diode obtained in step seven of this embodiment of the invention;

[0037] Figure 8 This is a schematic diagram of the cross-sectional structure of the flip-chip light-emitting diode obtained in step eight of the present invention.

[0038] Key component symbols: 10. Substrate; 111. N-type semiconductor layer; 112. Active light-emitting layer; 113. P-type semiconductor layer; 114. Conductive step of N-type semiconductor layer; 12. Current spreading layer; 13. Current blocking layer; 131. P-type current blocking layer via; 132. N-type current blocking layer via; 14. Bragg reflector layer; 141. P-type Bragg reflector layer via; 142. N-type Bragg reflector layer via; 15. Metal reflector. Layers; 16, First insulating layer; 161, P-type first insulating layer via; 162, N-type first insulating layer via; 17, Photoresist; 171, P-type photoresist opening; 172, N-type photoresist opening; 181, Completely opaque area; 182, Partially transparent area; 183, Completely transparent area; 191, P-type metal pad layer; 192, N-type metal pad layer; 201, P-type second insulating layer via; 202, N-type second insulating layer via. Detailed Implementation

[0039] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0040] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing alternative embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0042] The method for fabricating a flip-chip silver mirror light-emitting diode provided in this invention mainly improves the method for fabricating P-type first insulating layer vias and N-type first insulating layer vias.

[0043] Specifically, refer to Figures 1-8 It includes the following steps:

[0044] Step 1: Provide a substrate, deposit an epitaxial layer on the surface of the substrate, and form P-type and N-type regions.

[0045] Optionally, refer to Figure 1 Step one specifically includes:

[0046] An N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113 are sequentially fabricated on a substrate 10 using metal chemical vapor deposition (MOCVD). The substrate 10 can be one of GaN, Al2O3, and Si.

[0047] Next, indium tin oxide is deposited as a current spreading layer 12 on the surface of the P-type semiconductor layer 113 using a magnetron sputtering process to form a P-type region.

[0048] Then, photoresist is coated on the surface of the current spreading layer 12. Then, exposure and development are used to remove part of the photoresist, exposing part of the current spreading layer 12. Then, indium tin oxide etching solution is used to remove the exposed current spreading layer 12, exposing the P-type semiconductor layer underneath. Then, inductively coupled plasma etching process is used to remove the exposed P-type semiconductor layer and the active light-emitting layer under this part of the P-type semiconductor, forming the N-type semiconductor layer conductive step 114. Then, the photoresist is removed to form the N-type region.

[0049] Step 2: Sequentially deposit a current blocking layer and a Bragg reflection layer on the surfaces of the N-type region and the P-type region, and form Bragg reflection layer vias and current blocking layer vias.

[0050] Optionally, refer to Figure 2 Step two specifically includes:

[0051] SiO2 is deposited as a current blocking layer 13 on the surfaces of the current spreading layer 12, the P-type semiconductor layer 113 not covered by the current spreading layer 12, and the conductive steps 114 of the N-type semiconductor layer using a PECVD process. The thickness of the current blocking layer 13 is greater than [missing information].

[0052] Next, a stack of TiO2 and SiO2 is alternately deposited on the current blocking layer 13 for several cycles using an electron beam evaporation process as a Bragg reflector layer 14, wherein the alternating deposition cycle of TiO2 and SiO2 is 5 to 10.

[0053] Photoresist is coated on the surface of the Bragg reflector layer 14. Then, exposure and development are used to remove part of the photoresist, exposing the Bragg reflector layer under the photoresist. Then, inductively coupled plasma etching is used to remove the exposed part of the Bragg reflector layer, forming P-type Bragg reflector via 141 and N-type Bragg reflector via 142. Then, the photoresist is removed.

[0054] Next, photoresist is coated inside the P-type Bragg reflector via 141 and the N-type Bragg reflector via 142 and on the surface of the remaining Bragg reflector layer 14. Then, exposure and development are used to remove part of the photoresist, exposing the current blocking layer 13 under the photoresist. Then, BOE etching solution is used to remove the exposed current blocking layer, forming the P-type current blocking layer via 131 and the N-type current blocking layer via 132. Finally, the photoresist is removed.

[0055] Step 3: Prepare a metal reflective layer on the current blocking layer via and the Bragg reflective layer.

[0056] Optionally, refer to Figure 3 Step three specifically includes:

[0057] Photoresist is applied to the exposed areas of P-type current blocking layer vias 131 and N-type current blocking layer vias 132. Then, exposure and development are used to remove part of the photoresist. Then, Ag / Ni / Ti / Ni metal is sequentially deposited as a metal reflective layer 15 using an electron beam evaporation process. Then, the metal on top of the photoresist is removed using a blue film stripping process. Finally, the photoresist is removed.

[0058] Optionally, in the metal reflective layer 15, the thickness of the Ag metal layer is... The thickness of the Ni metal layer above the Ag metal layer is The thickness of the Ti metal layer above the Ni metal layer is The thickness of the Ni metal layer above the Ti metal layer is

[0059] Step 4: Prepare a first insulating layer on the epitaxial layer after preparing the metal reflective layer, then coat the first insulating layer with photoresist, and perform exposure and development using a photomask. The photomask includes a completely opaque area, a partially transparent area, and a completely transparent area. The partially transparent area corresponds to the location of the P-type first insulating layer via, and the completely transparent area corresponds to the location of the N-type first insulating layer via. The photoresist corresponding to the completely transparent area is fully developed to form an N-type photoresist opening; the photoresist corresponding to the partially transparent area is partially developed to form a P-type photoresist opening.

[0060] Optionally, refer to Figure 4 Step four specifically includes:

[0061] A SiO2 film is deposited on the metal reflective layer 15 using a PECVD process to form a first insulating layer 16. Then, photoresist 17 is coated on the first insulating layer 16, and exposure is performed using a photomask. The photomask includes a completely opaque region 181, a partially transparent region 182, and a completely transparent region 183. The partially transparent region 182 corresponds to the position of the P-type first insulating layer via 161, the completely transparent region 183 corresponds to the position of the N-type first insulating layer via 162, and the completely opaque region 181 corresponds to the remaining region.

[0062] After exposure and development, the photoresist corresponding to the fully transparent area 183 is fully developed, forming an N-type photoresist opening 172; the photoresist corresponding to the partially transparent area 182 is partially developed, forming a P-type photoresist opening 171, where there is a certain thickness of undeveloped residual photoresist; and the photoresist corresponding to the completely opaque area 181 is completely retained.

[0063] Preferably, the transmittance of the partially transparent area 182 for the wavelength used in the exposure is 70%-90%, such as 70%, 75%, 80%, 85%, 90%, etc.; the thickness of the undeveloped remaining photoresist is determined by the transmittance of the partially transparent area. The greater the transmittance, the smaller the remaining thickness, and the smaller the transmittance, the larger the remaining thickness. Within the transmittance range of 70%-90%, it is easy to operate and the control precision is also better.

[0064] Preferably, at the P-type photoresist opening 171, the thickness of the undeveloped remaining photoresist is H, and H is controlled within... This facilitates subsequent etching processes.

[0065] Step 5: Etching, exposing the surface of the N-type semiconductor layer conductive step at the N-type photoresist opening to form an N-type first insulating layer via; the first insulating layer remains at the P-type photoresist opening.

[0066] Optionally, refer to Figure 5 Step five specifically includes:

[0067] By etching at the N-type photoresist opening 172, the conductive step surface of the N-type semiconductor layer is exposed, forming an N-type first insulating layer via 162. At the P-type photoresist opening 171, due to the remaining photoresist, a certain thickness of the first insulating layer will remain under the same etching conditions. In this way, during the etching process, the metal reflective layer below the P-type photoresist opening will not directly contact the etching gas, thus avoiding corrosion.

[0068] Preferably, the remaining thickness of the first insulating layer at the P-type photoresist opening 171 is H1, H 1， for It can provide good protection. The thickness H1 is determined by the thickness H; the larger H is, the larger H1 is, and the smaller H is, the smaller H1 is.

[0069] Preferably, inductively coupled plasma etching is used, with an upper etching power of 800W-1200W and a lower etching power of 200W-400W. The etching gas includes BCl3 and Cl2, with the BCl3 flow rate at 15sccm-30sccm and the Cl2 flow rate at 80sccm-100sccm.

[0070] Step 6: Remove the remaining first insulating layer at the P-type photoresist opening to form a P-type first insulating layer through-hole; finally, remove the photoresist.

[0071] Optionally, refer to Figure 6 Step six specifically includes:

[0072] The remaining first insulating layer with a thickness of H1 at the P-type photoresist opening 171 is removed by etching with BOE solution to form a P-type first insulating layer through-hole 161; then the photoresist is removed, specifically, the remaining photoresist can be removed with a photoresist remover to expose the first insulating layer 16 it covers.

[0073] Preferably, the BOE solution is a mixture of NH4F solution and HF solution, wherein the concentration of NH4F solution is 35wt% to 40wt%, the concentration of HF solution is 2wt% to 3wt%, and the volume ratio of NH4F solution to HF solution is 40:1 to 30:1, which results in a better corrosion effect.

[0074] In one specific embodiment, the thickness of the undeveloped remaining photoresist is H. The remaining thickness H1 of the first insulating layer after etching is The BOE solution is a mixture of 38 wt% NH4F solution and 2 wt% HF solution, with a volume ratio of NH4F solution to HF solution of 40:1, and the BOE corrosion time is 50 s.

[0075] In one specific embodiment, the thickness of the undeveloped remaining photoresist is H. The remaining thickness H1 of the first insulating layer after etching is The BOE solution is a mixture of 38 wt% NH4F solution and 2 wt% HF solution, with a volume ratio of NH4F solution to HF solution of 35:1, and the BOE corrosion time is 75 s.

[0076] In one specific embodiment, the thickness of the undeveloped remaining photoresist is H. The remaining thickness H1 of the first insulating layer after etching is The BOE solution is a mixture of 38 wt% NH4F solution and 2 wt% HF solution, with a volume ratio of NH4F solution to HF solution of 30:1, and the BOE corrosion time is 100 s.

[0077] In some embodiments, the preparation method of the present invention further includes:

[0078] Step 7: Form a metal connection layer on the first insulating layer and the through-hole of the first insulating layer, the metal connection layer including a P-type metal pad layer and an N-type metal pad layer.

[0079] Step 8: Prepare a second insulating layer on the surface of the metal connection layer and the first insulating layer not covered by the metal connection layer, and form P-type second insulating layer through holes and N-type second insulating layer through holes.

[0080] Optionally, refer to Figure 7 Step seven specifically includes:

[0081] Photoresist is coated on the surface of the first insulating layer 16 and the P-type first insulating layer via 161 and N-type first insulating layer via 162. Then, exposure and development are performed to remove part of the photoresist. Then, Al / Ti / Pt / Ni / Au / Ti metal is deposited using an electron beam evaporation process. Then, the metal on the photoresist is removed using a blue film stripping process. Finally, the photoresist is removed to form a metal interconnect layer. The metal interconnect layer includes a P-type metal pad layer 191 and an N-type metal pad layer 192.

[0082] Optionally, refer to Figure 8 Step eight specifically includes:

[0083] Next, SiO2 is deposited as a second insulating layer on the surface of the metal interconnect layer 19 and the first insulating layer 16 not covered by the metal interconnect layer 19 using a PECVD process. Then, photoresist is coated on the surface of the second insulating layer, and then exposed and developed to remove part of the photoresist, exposing part of the second insulating layer. Then, the exposed second insulating layer is removed using BOE etching solution, and then the photoresist is removed to form a P-type second insulating layer via 201 and an N-type second insulating layer via 202.

[0084] The technical features of the embodiments described above can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A method for fabricating a flip-chip silver mirror light-emitting diode, characterized in that, Including the following steps: Step 1: Provide a substrate, deposit an epitaxial layer on the surface of the substrate, and form P-type and N-type regions; Step 2: Sequentially deposit a current blocking layer and a Bragg reflection layer on the surfaces of the N-type region and the P-type region, and form vias in the Bragg reflection layer and vias in the current blocking layer; Step 3: Fabricate a metal reflective layer on the current blocking layer via and the Bragg reflective layer; Step 4: Prepare a first insulating layer on the epitaxial layer after preparing the metal reflective layer, then coat the first insulating layer with photoresist, and expose and develop it using a photomask. The photomask includes a completely opaque area, a partially transparent area, and a completely transparent area. The partially transparent area corresponds to the position of the P-type first insulating layer via, and the completely transparent area corresponds to the position of the N-type first insulating layer via. The photoresist corresponding to the fully transparent area is fully developed to form an N-type photoresist opening; The photoresist portion corresponding to the light-transmitting area is developed to form a P-type photoresist opening; Step 5: Etching, exposing the conductive step surface of the N-type semiconductor layer at the N-type photoresist opening, forming an N-type first insulating layer via; the first insulating layer remains at the P-type photoresist opening; Step 6: Remove the remaining first insulating layer at the P-type photoresist opening to form a P-type first insulating layer through-hole; finally, remove the photoresist.

2. The preparation method according to claim 1, characterized in that, In step four, the light-transmitting area of ​​the photomask has a transmittance of 70%-90% for the wavelength used in the exposure.

3. The preparation method according to claim 1, characterized in that, In step four, the thickness of the remaining undeveloped photoresist at the P-type photoresist opening is H. The thickness H of the remaining undeveloped photoresist at the P-type photoresist opening is...

4. The preparation method according to claim 1, characterized in that, In step five, the remaining thickness of the first insulating layer at the P-type photoresist opening is H1, where H1 is...

5. The preparation method according to claim 1, characterized in that, In step five, inductively coupled plasma etching is used. The upper etching power is 800W-1200W, and the lower etching power is 200W-400W. The etching gas includes BCl3 and Cl2. The flow rate of BCl3 is 15sccm-30sccm, and the flow rate of Cl2 is 80sccm-100sccm.

6. The preparation method according to claim 1, characterized in that, In step six, the first insulating layer at the opening of the P-type photoresist is removed using a BOE solution. The BOE solution is a mixture of NH4F solution and HF solution, wherein the concentration of NH4F solution is 35wt% to 40wt%, the concentration of HF solution is 2wt% to 3wt%, and the volume ratio of NH4F solution to HF solution is 40:1 to 30:

1.

7. The preparation method according to claim 1, characterized in that, In step four, the metal reflective layer is an Ag / Ni / Ti / Ni stack, wherein the thickness of the Ag metal layer is [missing information]. The thickness of the Ni metal layer above the Ag metal layer is: The thickness of the Ti metal layer above the Ni metal layer is The thickness of the Ni metal layer above the Ti metal layer is 8. The preparation method according to claim 1, characterized in that, In step two, the thickness of the current blocking layer is greater than... The Bragg reflector layer comprises 5 to 10 TiO2 / SiO2 stacks.

9. The preparation method according to claim 1, characterized in that, It also includes the following steps: Step 7: Form a metal connection layer on the first insulating layer and the through-hole of the first insulating layer, wherein the metal connection layer includes a P-type metal pad layer and an N-type metal pad layer; Step 8: Prepare a second insulating layer on the surface of the metal connection layer and the first insulating layer not covered by the metal connection layer, and form P-type second insulating layer through holes and N-type second insulating layer through holes.

10. A flip-chip silver mirror light-emitting diode chip, characterized in that, It is prepared by the preparation method according to any one of claims 1 to 9.

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