Semiconductor device and method for manufacturing semiconductor device

Abstract

The semiconductor device (1) includes: an electron travel layer (103); an electron supply layer (104) disposed on the electron travel layer (103) with a larger band gap than the electron travel layer (103); a gate electrode (303) disposed on the electron supply layer (104); a contact layer (212) embedded in a through recess (211) that passes through the electron supply layer (104) at a position across the gate electrode (303); a first insulating layer (201) disposed on a portion of the electron supply layer (104) where the gate electrode (303) is not disposed; and a second insulating layer (202) disposed on the first insulating layer (201) in contact with the contact layer (212) but not in contact with the gate electrode (303), wherein the linear thermal expansion coefficient of the second insulating layer (202) is larger than the linear thermal expansion coefficient of the electron supply layer (104).

Description

Technical Field

[0001] This invention relates to semiconductor devices and methods for manufacturing the same, and particularly to group III nitride semiconductor devices using group III nitride semiconductors and methods for manufacturing the same. Background Technology

[0002] Group III nitride semiconductor devices, particularly gallium nitride (GaN) or aluminum gallium nitride (AlGaN), exhibit high insulation breakdown voltages due to the wide band gap of the materials. Furthermore, heterostructures such as AlGaN / GaN can be readily formed in group III nitride semiconductor devices.

[0003] In AlGaN / GaN heterostructures, due to the difference in piezoelectric polarization caused by the lattice constant difference between the materials and the difference in spontaneous polarization between AlGaN and GaN, a high concentration of electrons (two-dimensional electron gas) is generated on the GaN layer side at the interface between the AlGaN and GaN layers, forming a channel of the two-dimensional electron gas layer. Group III nitride semiconductor devices utilizing this two-dimensional electron gas-based channel are used in high-frequency power devices and other applications due to their high electron saturation velocity, high insulation resistance, and high thermal conductivity.

[0004] In these group III nitride semiconductor devices, in order to improve characteristics, it is preferable to minimize parasitic resistance components such as the contact between the ohmic electrode and the two-dimensional electron gas layer (hereinafter referred to as "ohmic contact") and the resistance of the channel based on the two-dimensional electron gas within the group III nitride semiconductor device.

[0005] Previously, techniques for reducing ohmic contact resistance have been proposed in group III nitride semiconductor devices that utilize channels based on two-dimensional electron gases. For example, Patent Document 1 discloses a technique in which, in order to reduce ohmic contact resistance, a recess (hereinafter referred to as "through-recess") is formed in the portion of the group III nitride semiconductor device in which an ohmic electrode is formed, penetrating an electron supply layer composed of AlGaN, is formed, and a contact layer is formed by selectively regrowing low-energy barrier materials such as n-GaN and n-InGaN.

[0006] Existing technical documents Patent documents Patent Document 1: Japanese Patent Application Publication No. 2019-114581 Summary of the Invention

[0007] The problem that the invention aims to solve However, if a through-recess is formed in the electron supply layer as disclosed in Patent Document 1, it is inevitable that the two-dimensional electron gas layer and the contact layer embedded in the through-recess will essentially become point-connected. Furthermore, if a through-recess is formed in the electron supply layer, not only will crystal defects be generated at the interface between the GaN-based two-dimensional electron gas layer (channel layer) and the contact layer during the formation of the through-recess, but also, due to atmospheric pollutants and bonding defects, a region with reduced carrier (electron) concentration will be created on the side adjacent to the through-recess in the electron supply layer, resulting in a decrease in the maximum drain current.

[0008] This disclosure was made in view of such a problem, with the aim of providing a semiconductor device and a method thereof capable of suppressing the reduction of maximum drain current.

[0009] Methods for solving problems To achieve the above objectives, a technical solution of the first semiconductor device disclosed herein includes: an electron travel layer; an electron supply layer disposed on the electron travel layer, having a band gap larger than that of the electron travel layer; a gate electrode disposed on the electron supply layer; a source-side contact layer and a drain-side contact layer embedded in a recess that penetrates the electron supply layer at a position separated from the gate electrode; a first insulating layer disposed on a portion of the electron supply layer where the gate electrode is not disposed; and a second insulating layer disposed on the first insulating layer in contact with the source-side contact layer and / or the drain-side contact layer and not in contact with the gate electrode, wherein the linear thermal expansion coefficient of the second insulating layer is larger than that of the electron supply layer.

[0010] Furthermore, one technical solution of the second semiconductor device disclosed herein includes: an electron travel layer; an electron supply layer disposed on the electron travel layer, having a band gap larger than that of the electron travel layer; a gate electrode disposed on the electron supply layer; a contact layer embedded in a recess that passes through the electron supply layer at a position separated from the gate electrode; a source electrode or a drain electrode disposed on the contact layer; a first insulating layer disposed on a portion of the electron supply layer where the gate electrode is not disposed; and a second insulating layer disposed on the first insulating layer in contact with the contact layer but not in contact with the gate electrode, wherein the second insulating layer has a nitride layer or a composite layer of oxide and nitride.

[0011] In addition, one technical solution of the semiconductor device manufacturing method of the present invention includes the following steps: forming an electron supply layer on an electron travel layer with a band gap larger than the electron travel layer; forming a first insulating layer on the electron supply layer without being exposed to the atmosphere; forming a through recess that penetrates the first insulating layer and the electron supply layer and reaches the electron travel layer; embedding and forming a contact layer in the through recess; forming a second insulating layer on the first insulating layer; forming a source electrode and a drain electrode on the contact layer in contact with the contact layer; removing the portion of the second insulating layer other than the portion in contact with the contact layer to expose the first insulating layer and form a first insulating layer exposure portion; and removing the portion of the first insulating layer in the first insulating layer exposure portion that is separated from the second insulating layer to form a gate electrode, wherein the second insulating layer has an oxynitride layer or a composite layer of oxide and nitride.

[0012] Invention Effects According to this disclosure, a semiconductor device capable of suppressing the reduction of maximum drain current can be obtained. Attached Figure Description

[0013] Figure 1 This is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 1.

[0014] Figure 2 This is a schematic diagram showing the conduction band of the energy band of the semiconductor device according to Embodiment 1.

[0015] Figure 3A This is a cross-sectional view showing the process of forming a semiconductor laminate structure, a first insulating layer, and a second insulating layer in the manufacturing method of the semiconductor device according to Embodiment 1.

[0016] Figure 3B This is a cross-sectional view showing the process of forming a through recess in the manufacturing method of the semiconductor device according to Embodiment 1.

[0017] Figure 3C This is a cross-sectional view showing the process of forming a contact layer in the manufacturing method of the semiconductor device according to Embodiment 1.

[0018] Figure 3D This is a cross-sectional view showing the process of forming source and drain electrodes in the manufacturing method of the semiconductor device according to Embodiment 1.

[0019] Figure 3E This is a cross-sectional view showing the process of patterning the second insulating layer in the manufacturing method of the semiconductor device according to Embodiment 1.

[0020] Figure 3FThis is a cross-sectional view showing the process of forming a gate electrode in the manufacturing method of the semiconductor device according to Embodiment 1.

[0021] Figure 4 This is a cross-sectional view showing the structure of a semiconductor device in a modified example of Embodiment 1.

[0022] Figure 5 This is a cross-sectional view showing the structure of the semiconductor device in Embodiment 2.

[0023] Figure 6 This is a schematic diagram showing the conduction band of the energy band of the semiconductor device in Embodiment 2.

[0024] Figure 7A This is a cross-sectional view showing the process of forming a semiconductor laminate structure and a first insulating layer in the manufacturing method of the semiconductor device according to Embodiment 2.

[0025] Figure 7B This is a cross-sectional view showing the process of forming a through recess in the manufacturing method of the semiconductor device according to Embodiment 2.

[0026] Figure 7C This is a cross-sectional view showing the process of forming a contact layer in the manufacturing method of the semiconductor device according to Embodiment 2.

[0027] Figure 7D This is a cross-sectional view showing the process of forming a second insulating layer in the manufacturing method of the semiconductor device according to Embodiment 2.

[0028] Figure 7E This is a cross-sectional view showing the process of forming the source electrode and the drain electrode in the manufacturing method of the semiconductor device in Embodiment 2.

[0029] Figure 7F This is a cross-sectional view showing the process of patterning the second insulating layer in the semiconductor device manufacturing method of Embodiment 2.

[0030] Figure 7G This is a cross-sectional view showing the process of forming a gate electrode in the manufacturing method of the semiconductor device according to Embodiment 2. Detailed Implementation

[0031] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. The embodiments shown herein represent specific examples of the present disclosure. Therefore, the numerical values, shapes, constituent elements, arrangements and connections of constituent elements, and steps (processes) and their order shown in the following embodiments are examples and are not intended to limit the present disclosure. Therefore, any constituent elements in the following embodiments that are not described in the independent claims representing the highest-level concept of the present disclosure will be described as arbitrary constituent elements.

[0032] Furthermore, these figures are schematic diagrams and may not be strictly representational. Therefore, the scales and other parameters may not be consistent across different figures. In all figures, substantially identical structures are labeled with the same reference numerals, and repetitive descriptions are omitted or simplified.

[0033] Furthermore, in this specification, the terms "upper," "above," "lower," and "below" in the context of semiconductor device structure do not refer to "upper" (vertically above) and "lower" (vertically below) in absolute spatial identification, but rather to terms defined by relative positional relationships based on the stacking order in a stacked structure. Additionally, the terms "upper" and "lower" apply not only to cases where two constituent elements are arranged spaced apart from each other and other constituent elements exist between them, but also to cases where two constituent elements are arranged close together and connected.

[0034] Furthermore, in this specification and accompanying drawings, the x-axis, y-axis, and z-axis represent the three axes of a three-dimensional orthogonal coordinate system. In various embodiments, the two axes parallel to the upper surface of the substrate of the semiconductor device are designated as the x-axis and y-axis, and the direction orthogonal to the upper surface is designated as the z-axis direction. In the embodiments described below, the positive z-axis direction is sometimes referred to as "up" and the negative z-axis direction as "down." Additionally, in this specification, "top view" refers to the view of the substrate of the semiconductor device from the positive z-axis direction.

[0035] (Implementation Method 1) First, use Figure 1 The semiconductor device 1 of Embodiment 1 will be described. Figure 1 This is a cross-sectional view showing the structure of the semiconductor device 1 according to Embodiment 1.

[0036] In this embodiment, the case where the semiconductor device 1 is a high electron mobility transistor (HEMT) having a Schottky junction gate structure will be described.

[0037] like Figure 1 As shown, the semiconductor device 1 includes a substrate 101, a buffer layer 102, an electron travel layer 103, an electron supply layer 104, a first insulating layer 201, a second insulating layer 202, a source electrode 301, a drain electrode 302, and a gate electrode 303. The buffer layer 102, the electron travel layer 103, and the electron supply layer 104 are a semiconductor laminate structure 100 made of semiconductor materials.

[0038] Substrate 101 is, for example, a silicon substrate made of Si. In this embodiment, substrate 101 is a silicon substrate made of a single Si crystal with a (111) plane as its main surface. However, substrate 101 is not limited to a silicon substrate; it may also be a substrate made of sapphire, SiC, GaN, or AlN, which serves as the substrate for forming a nitride semiconductor layer. The resistivity of substrate 101 is, for example, 1 kΩ or more. Alternatively, a substrate with a resistivity of 20 Ω or less may also be used as substrate 101.

[0039] A buffer layer 102 is disposed on the substrate 101. The buffer layer 102 is, for example, a 2 μm thick group III nitride semiconductor layer composed of multiple stacked layers of AlN and AlGaN. In this case, 20 to 100 pairs of AlN and AlGaN can be stacked as one pair. Alternatively, the buffer layer 102 may also be composed of Al... 1-α Ga α The structure is composed of multiple N (0 ≤ α < 0.8) stacked layers, and includes a superlattice structure. Furthermore, the buffer layer 102 can also be composed of a single layer or multiple layers of group III nitride semiconductors such as InGaN or AlInGaN. Additionally, the carbon concentration of the buffer layer 102 can be set to 1 × 10⁻⁶. 19 atoms / cm 3 This results in high resistance in the buffer layer 102.

[0040] An electron travel layer 103 is disposed on top of the buffer layer 102. In this embodiment, the electron travel layer 103 is, for example, a GaN layer made of GaN with a thickness of 150 nm. Furthermore, the group III nitride semiconductor constituting the electron travel layer 103 is not limited to GaN. The electron travel layer 103 may be made of group III nitride semiconductors such as InGaN, AlGaN, and AlInGaN. In addition, the electron travel layer 103 may contain n-type impurities.

[0041] An electron supply layer 104 is disposed above the electron travel layer 103. The electron supply layer 104 has a larger band gap compared to the electron travel layer 103. In this embodiment, the electron supply layer 104 is, for example, an AlGaN layer with a thickness of 13 nm composed of AlGaN with an Al composition ratio of 30%. A high concentration of two-dimensional electron gas is generated on the electron travel layer 103 side of the heterojunction interface between the electron supply layer 104 and the electron travel layer 103, forming a channel for a two-dimensional electron gas layer 105. Therefore, the semiconductor device 1 has a two-dimensional electron gas layer 105. The two-dimensional electron gas layer 105 is composed of a first two-dimensional electron gas layer 105A and a second two-dimensional electron gas layer 105B with different electron concentrations, as detailed later.

[0042] Furthermore, the Al content in the electron supply layer 104, which is composed of AlGaN, is not limited to 30%. The Al content in the electron supply layer 104 can be 20% to 100%. Additionally, the group III nitride semiconductor constituting the electron supply layer 104 is not limited to AlGaN. The electron supply layer 104 can be composed of a group III nitride semiconductor such as AlInGaN containing In. Furthermore, the electron supply layer 104 can contain n-type impurities.

[0043] A cap layer may be provided on the electron supply layer 104. For example, a GaN layer with a thickness of approximately 1-2 nm made of GaN can be used as the cap layer. Furthermore, a spacer layer may be provided between the electron travel layer 103 and the electron supply layer 104. For example, an AlN layer with a thickness of approximately 1 nm made of AlN can be used as the spacer layer.

[0044] A first insulating layer 201 is disposed on the electron supply layer 104. The first insulating layer 201 is a SiN layer made of SiN. In this embodiment, the first insulating layer 201 is a 2nm thick SiN layer made of In-situ SiN. In addition, In-situ means that it is formed without exposure to the atmosphere. Therefore, the first insulating layer 201 made of In-situ SiN is a SiN layer formed without exposure to the atmosphere after the electron supply layer 104 is formed.

[0045] By constructing the first insulating layer 201 from In-situ SiN, the uneven distribution of oxygen at the interface between the first insulating layer 201 and the electron supply layer 104 can be eliminated. By eliminating the uneven distribution of oxygen at the interface between the first insulating layer 201 and the electron supply layer 104, the generation of interface states is suppressed. This prevents an increase in the interface potential and suppresses the decrease in the electron concentration of the two-dimensional electron gas.

[0046] The thickness of the first insulating layer 201 is preferably 2 nm or more and 30 nm or less. By making the thickness of the first insulating layer 201 2 nm or more, it is possible to suppress the uneven distribution of oxygen at the interface between the first insulating layer 201 and the electron supply layer 104 due to natural oxidation. On the other hand, if the thickness of the first insulating layer 201 exceeds 30 nm, wafer warping will occur during the fabrication of the semiconductor device 1, and the quality of the semiconductor device 1 will be reduced. Therefore, the thickness of the first insulating layer 201 is preferably 30 nm or less. In other words, by making the thickness of the first insulating layer 201 30 nm or less, wafer warping can be suppressed.

[0047] Furthermore, the first insulating layer 201 is preferably oxygen-free. If the first insulating layer 201 contains oxygen, the interface states at the interface between the first insulating layer 201 and the electron supply layer 104 increase, the potential at the interface between the first insulating layer 201 and the electron supply layer 104 rises, and the electron concentration of the two-dimensional electron gas decreases. By making the first insulating layer 201 oxygen-free, the decrease in the electron concentration of the two-dimensional electron gas can be suppressed.

[0048] An opening 201a is provided in the first insulating layer 201. The opening 201a is formed in the first insulating layer 201 in the region where the gate electrode 303 is disposed. Therefore, the first insulating layer 201 is disposed on the portion of the electron supply layer 104 where the gate electrode 303 is not disposed. In this embodiment, the gate electrode 303 disposed in the opening 201a of the first insulating layer 201 reaches the electron supply layer 104. That is, the gate electrode 303 is in contact with the electron supply layer 104.

[0049] A through recess 211 is provided in the electron supply layer 104. In this embodiment, the through recess 211 is provided in such a way that it penetrates the first insulating layer 201 and the electron supply layer 104 and reaches the electron travel layer 103. The through recess 211 reaches the interior of the electron travel layer 103, and a recess is provided in the electron travel layer 103.

[0050] The distance from the upper surface of the electron travel layer 103 to the bottom of the bottom surface of the through-recess 211 is preferably 10 nm or less. For example, the distance from the upper surface of the electron travel layer 103 to the bottom of the bottom surface of the through-recess 211 is 5 nm. Furthermore, the elevation angle of the bottom surface of the through-recess 211 from the center to the side is preferably 10 degrees or less, more preferably 5 degrees or less. Therefore, when forming the through-recess 211 by dry etching, the occurrence of crystal defects on the side of the through-recess 211 can be reduced, and the decrease in maximum drain current can be suppressed.

[0051] The through-recess 211 is provided corresponding to the area where the source electrode 301 and the drain electrode 302 are provided. Specifically, a pair of through-recesses 211 are provided opposite each other with the gate electrode 303 in between.

[0052] A contact layer 212 is provided in the through-recess 211. The contact layer 212 is provided in such a way that it is embedded in the through-recess 211. The contact layer 212 provided on one side of the pair of through-recesses 211 is a source-side contact layer 212A, and the contact layer 212 provided on the other side of the pair of through-recesses 211 is a drain-side contact layer 212B. The source-side contact layer 212A and the drain-side contact layer 212B are provided at a position separated from the gate electrode 303.

[0053] The contact layer 212 is, for example, an n-GaN layer composed of n-type GaN. Furthermore, the material constituting the contact layer 212 is not limited to n-type GaN; it can also be composed of group III nitride semiconductors such as InGaN, AlGaN, and AlInGaN, which contain Si, Ge, or other donors as n-type impurities. Alternatively, it can be composed of a multilayer electrode film consisting of sequentially stacked Ti and Al layers. Additionally, the material constituting the contact layer 212 can also be Ti, Ta, Al, Au, Hf, Ru, and Cu.

[0054] A source electrode 301 or a drain electrode 302 is disposed on the contact layer 212. Specifically, the source electrode 301 is disposed on the source-side contact layer 212A, and the drain electrode 302 is disposed on the drain-side contact layer 212B. The source electrode 301 and the drain electrode 302 are disposed opposite each other with respect to the gate electrode 303. The source electrode 301 and the drain electrode 302 are, for example, multilayer electrode films composed of a Ti film with a thickness of 30 nm and an Al film with a thickness of 200 nm stacked sequentially, but are not limited to this. Alternatively, the source electrode 301 and the drain electrode 302 may also be composed of Ti, Ta, W, Al, Au, Hf, Ru, and Cu.

[0055] The gate electrode 303 is disposed on the electron supply layer 104. Specifically, the gate electrode 303 is disposed on the electron supply layer 104 through an opening 201a provided in the first insulating layer 201.

[0056] The gate electrode 303 is, for example, a multilayer electrode film composed of a TiN film and an Al film sequentially stacked. However, the gate electrode 303 is not limited to a TiN and Al film stack; it can also be composed of transition metal nitrides and carbides. Specifically, the gate electrode 303 can also be composed of TiN, WN, TaN, or HfN. Furthermore, the gate electrode 303 can also be composed of Ti, Ta, W, Al, Pd, Pt, Hf, Ru, and Cu, or compounds containing these elements, and can be a multilayer electrode film composed of multiple stacked structures. Additionally, other insulating layers or p-type nitride semiconductor layers can be provided between the electron supply layer 104 and the gate electrode 303.

[0057] The second insulating layer 202 is disposed on the first insulating layer 201. In this embodiment, the second insulating layer 202 is in contact with the first insulating layer 201.

[0058] Furthermore, the second insulating layer 202 is disposed in contact with the contact layer 212. Specifically, the second insulating layer 202 is in contact with the source-side contact layer 212A and / or the drain-side contact layer 212B. That is, the second insulating layer 202 only needs to be in contact with one of the source-side contact layer 212A and the drain-side contact layer 212B. In this embodiment, the second insulating layer 202 is in contact with both the source-side contact layer 212A and the drain-side contact layer 212B. In addition, the second insulating layer 202 can be divided into multiple parts. In this case, one of the multiple second insulating layers 202 may be in contact with the source-side contact layer 212A, and another of the multiple second insulating layers 202 may be in contact with the drain-side contact layer 212B.

[0059] Furthermore, the second insulating layer 202 is configured not to contact the gate electrode 303. That is, the second insulating layer 202 is disposed separately from the gate electrode 303. In other words, preferably, the second insulating layer 202 does not come too close to the gate electrode 303.

[0060] In the cross-sectional view, the width of the second insulating layer 202 connected to one of the source-side contact layer 212A and the drain-side contact layer 212B is preferably less than the distance between the gate-side end of the second insulating layer 202 and the second insulating layer 202-side end of the gate electrode 303. Specifically, the width of the second insulating layer 202 is preferably 1 μm or less. In particular, the width of the second insulating layer 202 connected to the drain-side contact layer 212B (the second insulating layer 202 on the drain electrode 302 side) is preferably 1 μm or less. This suppresses leakage current between the gate electrode 303 and the drain electrode 302. Furthermore, as long as the second insulating layer 202 on the drain electrode 302 side is separated from the gate electrode 303, the second insulating layer 202 on the source electrode 301 side can also be connected to the gate electrode 303. This reduces the access resistance between the source electrode 301 and the gate electrode 303, thereby increasing the maximum drain current.

[0061] An opening 202a is provided in the second insulating layer 202. The opening 202a is formed in the region of the second insulating layer 202 where the gate electrode 303 is disposed. The opening width of the opening 202a in the second insulating layer 202 is greater than the opening width of the opening 201a in the first insulating layer 201.

[0062] The linear thermal expansion coefficient of the second insulating layer 202 is greater than that of the electron supply layer 104. Furthermore, the tensile stress of the second insulating layer 202 is greater than that of the first insulating layer 201. In this embodiment, the density of the second insulating layer 202 is greater than that of the first insulating layer 201. That is, the density of the first insulating layer 201 is less than that of the second insulating layer 202. Moreover, in this embodiment, the first insulating layer 201 and the second insulating layer 202 are made of the same material, but the density of the second insulating layer 202 is greater than that of the first insulating layer 201.

[0063] In this embodiment, similar to the first insulating layer 201, the second insulating layer 202 is a SiN layer made of SiN. Specifically, the second insulating layer 202 is, for example, a SiN layer made of SiN with a layer thickness of 10 nm. Furthermore, the layer thickness of the second insulating layer 202 is not limited to 10 nm. For example, the layer thickness of the second insulating layer 202 can be set to 10 nm or more and 30 nm or less. In this embodiment, the layer thickness of the second insulating layer 202 is thicker than the layer thickness of the first insulating layer 201, but it is not limited to this. That is, the layer thickness of the second insulating layer 202 can also be thinner than the layer thickness of the first insulating layer 201. Additionally, the layer thickness of the second insulating layer 202 can increase from the gate electrode 303 toward the contact layer 212. In this case, the increase in the layer thickness of the second insulating layer 202 can be continuous or discontinuous. Furthermore, in this embodiment, the second insulating layer 202 is a single layer, but it can also be multiple layers.

[0064] By configuring the semiconductor device 1 with this structure, the electron concentration of the two-dimensional electron gas layer 105 can be made different in the portion where the second insulating layer 202 is present and the portion where the second insulating layer 202 is not present. Specifically, the two-dimensional electron gas layer 105 has a first two-dimensional electron gas layer 105A located outside the second insulating layer 202 and a second two-dimensional electron gas layer 105B located below the second insulating layer 202, wherein the electron concentration of the second two-dimensional electron gas layer 105B is greater than that of the first two-dimensional electron gas layer 105A. In addition, the contact layer 212 in contact with the second insulating layer 202 and the second two-dimensional electron gas layer 105B are electrically ohmically connected.

[0065] Here, use Figure 2 Explain the mechanism by which the electron concentration of the second two-dimensional electron gas layer 105B is higher than that of the first two-dimensional electron gas layer 105A. Figure 2 This is a schematic diagram showing the conduction band of the energy band of the semiconductor device 1 according to Embodiment 1.

[0066] exist Figure 2 In the middle, the solid line A is parallel to... Figure 1 The diagram shows the part corresponding to the single-dot dashed line A, and the dashed line B is the part corresponding to... Figure 1 The diagram shows the portion corresponding to the dashed line B. That is, Figure 2 The solid line A in the diagram represents the adjacent portion of the gate electrode 303, i.e., the gate adjacent portion (i.e., the portion where only the first insulating layer 201 is provided above the first insulating layer 201 without the second insulating layer 202). Additionally, Figure 2 The dashed line B in the figure is a diagram of the adjacent portion of the contact layer 212, namely the contact adjacent portion (that is, the portion on which the second insulating layer 202 is provided above the first insulating layer 201).

[0067] As described above, in the semiconductor device 1 of this embodiment, the linear thermal expansion coefficient of the second insulating layer 202 is greater than that of the electron supply layer 104. Thus, by providing a second insulating layer 202 with a larger linear thermal expansion coefficient than the electron supply layer 104, the tensile stress applied to the contact area of ​​the electron supply layer 104 increases. Consequently, the piezoelectric polarization of the electron supply layer 104 increases, and the potential at the interface between the electron supply layer 104 and the electron travel layer 103 decreases. As a result, the electron concentration of the second two-dimensional electron gas layer 105B increases. That is, the electron concentration of the second two-dimensional electron gas layer 105B, located below the second insulating layer 202, is relatively larger than the electron concentration of the first two-dimensional electron gas layer 105A, which is not located below the second insulating layer 202.

[0068] In this way, by making the electron concentration of the second two-dimensional electron gas layer 105B higher than that of the first two-dimensional electron gas layer 105A, the decrease in electron concentration at the side adjacent portion of the through-recess 211 in the electron supply layer 104 can be reduced. As a result, the decrease in the maximum drain current can be suppressed. Moreover, since the electron concentration at the gate adjacent portion corresponding to the first two-dimensional electron gas layer 105A is maintained, the leakage current between the gate electrode 303 and the drain electrode 302 can also be reduced. That is, with the structure of the semiconductor device 1 of this embodiment, the gate-drain leakage current can be reduced while suppressing the decrease in the maximum drain current. In addition, the second insulating layer 202 contributes significantly to the increase in two-dimensional electron gas, thereby reducing the deviation of the drain current caused by the side condition deviation (etching condition deviation) of the through-recess 211.

[0069] Furthermore, in the semiconductor device 1 of this embodiment, the second insulating layer 202 may contain oxygen. For example, the oxygen-containing second insulating layer 202 may be composed of SiON or SiO2.

[0070] In this way, by making the second insulating layer 202 an oxygen-containing layer (oxide layer, etc.) such as SiON or SiO2, compared with the case where the second insulating layer 202 is a nitrogen-containing nitride layer such as SiN, the coefficient of thermal expansion of the second insulating layer 202 can be increased, and the tensile stress of the second insulating layer 202 can be further increased. As a result, the electron concentration of the second two-dimensional electron gas layer 105B can be further increased compared with the electron concentration of the first two-dimensional electron gas layer 105A. Therefore, the decrease in electron concentration at the side adjacent portion of the through recess 211 in the electron supply layer 104 can be further reduced, and the decrease in maximum drain current can be further suppressed.

[0071] Furthermore, in the semiconductor device 1 of this embodiment, the first insulating layer 201 and the second insulating layer 202 may also contain halogens such as fluorine (F) or chlorine (Cl), but the halogen concentration of both the first insulating layer 201 and the second insulating layer 202 is preferably 1×10⁻⁶. 18 atoms / cm 3 The following is because the halogens contained in the semiconductor layer and the insulating layer have high electronegativity, thus becoming a negative fixed charge. Therefore, by making the halogen concentration of the first insulating layer 201 1×10⁻⁶, 18 atoms / cm 3 This reduces the negative fixed charge in the first insulating layer 201. Consequently, the potential rise at the interface between the electron supply layer 104 and the electron travel layer 103 can be eliminated, and the reduction in electron concentration in the second two-dimensional electron gas layer 105B due to halogens can be prevented.

[0072] In the semiconductor device 1 of this embodiment, the tensile stress of the second insulating layer 202 is greater than that of the first insulating layer 201. This allows for a further increase in the electron concentration of the second two-dimensional electron gas layer 105B relative to the electron concentration of the first two-dimensional electron gas layer 105A. Consequently, the decrease in electron concentration at the side adjacent portion of the through-recess 211 in the electron supply layer 104 can be further mitigated, and the decrease in maximum drain current can be further suppressed. Furthermore, the thicker the second insulating layer 202, the greater its tensile stress. For example, it is preferable that the thickness of the second insulating layer 202 is greater than that of the first insulating layer 201.

[0073] In the semiconductor device 1 of this embodiment, the first insulating layer 201 and the second insulating layer 202 are made of the same material, and the density of the second insulating layer 202 is greater than that of the first insulating layer 201. A higher density of the second insulating layer 202 results in higher mechanical strength, thus increasing the tensile stress exerted by the second insulating layer 202 on the electron supply layer 104. Therefore, by making the density of the second insulating layer 202 greater than that of the first insulating layer 201, the electron concentration of the second two-dimensional electron gas layer 105B relative to the electron concentration of the first two-dimensional electron gas layer 105A can be further increased. This further mitigates the decrease in electron concentration at the side adjacent portion of the through-recess 211 in the electron supply layer 104, and further suppresses the decrease in the maximum drain current.

[0074] Next, use Figures 3A to 3F The manufacturing method of the semiconductor device 1 of this embodiment will be described. Figures 3A to 3F This is a cross-sectional view showing each step of the manufacturing method of the semiconductor device 1 according to Embodiment 1. Figure 3A The process of forming a semiconductor stacked structure 100 and a first insulating layer 201 and a second insulating layer 202 is shown. Figure 3B The process of forming the through recess 211 is shown. Figure 3C The process of forming contact layer 212 is shown. Figure 3D The process of forming the source electrode 301 and the drain electrode 302 is shown. Figure 3E The process of patterning the second insulating layer 202 is shown. Figure 3F The process of forming the gate electrode 303 is shown.

[0075] First, such as Figure 3A As shown, a semiconductor stack structure 100 comprising a buffer layer 102, an electron travel layer 103, and an electron supply layer 104 is formed on a substrate 101 by metal-organic chemical vapor deposition (MOCVD) (semiconductor stack structure formation process).

[0076] In this embodiment, on a substrate 101 made of Si, in the +c plane direction ( <0001> A buffer layer 102 with a thickness of 2 μm and composed of AlN and AlGaN, an electron transport layer 103 with a thickness of 200 nm and composed of GaN, and an electron supply layer 104 with a thickness of 20 nm and composed of AlGaN with an Al composition ratio of 25% are epitaxially grown sequentially in the direction of the semiconductor stack, thereby forming a semiconductor stack structure 100.

[0077] Next, a first insulating layer 201 made of SiN and a second insulating layer 202 made of SiN are sequentially formed on the semiconductor stack structure 100 (first insulating layer and second insulating layer formation process). In this embodiment, after the semiconductor stack structure 100 is formed, the first insulating layer 201 and the second insulating layer 202 are formed continuously in the same semiconductor crystal growth apparatus (MOCVD furnace). That is, the first insulating layer 201 is formed on the electron supply layer 104 without exposure to the atmosphere, and the second insulating layer 202 is formed on the first insulating layer 201 without exposure to the atmosphere. In this way, by forming the first insulating layer 201 directly above the electron supply layer 104 without exposure to the atmosphere, there is no uneven distribution of oxygen between the electron supply layer 104 and the first insulating layer 201. Under this configuration, a high concentration of two-dimensional electron gas is generated on the electron travel layer 103 side of the heterogeneous interface between the electron supply layer 104 and the electron travel layer 103, forming a two-dimensional electron gas layer 105.

[0078] Furthermore, the film-forming conditions for forming the first insulating layer 201 and the second insulating layer 202 include, for example, a growth temperature of 900~1150°C and feed gases of SiH4 and NH3. Additionally, to prevent halogens from being introduced as impurities into the first insulating layer 201 and the second insulating layer 202, it is preferable not to use halogens during dry cleaning of the MOCVD furnace. Furthermore, even if halogens are used during dry cleaning, they can be removed from the MOCVD furnace after dry cleaning using N2, NH3, or the like.

[0079] Next, as Figure 3B As shown, a portion of the semiconductor stacked structure 100 is removed to form a through recess 211 (through recess formation process). In this embodiment, since the first insulating layer 201 and the second insulating layer 202 are formed on the semiconductor stacked structure 100, a portion of the first insulating layer 201 and the second insulating layer 202 are also removed together with the semiconductor stacked structure 100.

[0080] Specifically, firstly, after coating the second insulating layer 202 with a photoresist, the photoresist is patterned using photolithography, thereby forming a mask (resist mask) on the second insulating layer 202 except for the region where the contact layer 212 is formed (i.e., the region where the source electrode 301 and drain electrode 302 are formed). That is, the photoresist forms openings in the region where the contact layer 212 is formed. Specifically, the photoresist has openings in each region where the source-side contact layer 212A and the drain-side contact layer 212B are formed.

[0081] Next, dry etching is performed using the resist with the opening as a mask to form a through recess 211 that penetrates the first insulating layer 201, the second insulating layer 202, and the electron supply layer 104, reaching the electron travel layer 103. Specifically, as Figure 3B As shown, two through-recesses 211 are formed corresponding to the regions forming the source-side contact layer 212A and the drain-side contact layer 212B. By forming the through-recesses 211, a portion of the electron travel layer 103 is exposed. Then, the mask (resist) and the polymer generated by dry etching are removed.

[0082] Furthermore, in this embodiment, the through-hole recess 211 is formed by dry etching, but it is not limited to this. Specifically, the through-hole recess 211 can also be formed by wet etching.

[0083] Next, as Figure 3C As shown, a contact layer 212 is embedded in the through recess 211 (contact layer forming process).

[0084] Specifically, using the second insulating layer 202 as a mask, MOCVD is applied to embed n into the two through recesses 211. + -GaN regrowth. This allows for the selective embedding of GaN-based structures into the two through-recesses 211. + - A GaN-based contact layer 212. Furthermore, the contact layer 212 embedded in one of the two through-recesses 211 is a source-side contact layer 212A, and the contact layer 212 embedded in the other of the two through-recesses 211 is a drain-side contact layer 212B.

[0085] In this embodiment, Si is doped as an n-type impurity, with a thickness of 100 nm. + -GaN regeneration forms the contact layer 212. The Si doping concentration of the contact layer 212 is, for example, 2 × 10⁻⁶. 19 / cm 3 Furthermore, not limited to regrowth, the contact layer 212 can also be formed by sputtering, or it can be formed by ion implantation and plasma treatment without forming the through recess 211.

[0086] Next, as Figure 3D As shown, a source electrode 301 and a drain electrode 302 are formed on the contact layer 212 in a grounded manner (source electrode / drain electrode forming process).

[0087] Specifically, after forming a laminated film by sequentially depositing a 30 nm thick Ti film and a 200 nm thick Al film by evaporation or sputtering, the unwanted laminated film is removed by lift-off, thereby forming a source electrode 301 and a drain electrode 302 of a predetermined shape composed of the Ti and Al film laminated film on the contact layer 212. In this embodiment, the source electrode 301 is formed on the source-side contact layer 212A, and the drain electrode 302 is formed on the drain-side contact layer 212B. Then, the resist mask and polymer are removed.

[0088] Next, heat treatment is performed. As a result, the two-dimensional electron gas layer 105 and the contact layer 212 are electrically ohmically connected.

[0089] In addition, in this embodiment, the source electrode 301 and the drain electrode 302 are formed by vapor deposition and stripping, but are not limited thereto. For example, after forming a stacked film by sequentially depositing Ti film and Al film by sputtering, the stacked film can be patterned using photolithography and dry etching to form the source electrode 301 and drain electrode 302 of a predetermined shape.

[0090] Next, as Figure 3E As shown, the second insulating layer 202 is patterned, and the portion of the second insulating layer 202 where the gate electrode 303 is disposed is removed (second insulating layer patterning process).

[0091] Specifically, after applying the resist, the resist is patterned into a predetermined shape using photolithography, forming a continuous mask (resist mask) in the region where the source electrode 301 and drain electrode 302 are formed and in the region separated from the region where the gate electrode 303 is formed (the predetermined region for gate electrode formation). In this case, when viewed from above, the end of the patterned resist on the drain electrode 302 side is located between the gate electrode 303 and the contact layer 212, and the end of the patterned resist on the gate electrode 303 side is located between the gate electrode 303 and the contact layer 212. Then, the portion of the second insulating layer 202 other than the portion in contact with the contact layer 212 is removed by dry etching, thereby exposing the first insulating layer 201 and forming the first insulating layer exposed portion 201s. At this time, the second insulating layer 202 located below the patterned resist (resist mask) remains. That is, the portion of the second insulating layer 202 in contact with the contact layer 212 remains. Then, the resist and polymer are removed. As a result, a second insulating layer 202 with an opening 202a can be formed in the region where the gate electrode 303 is formed. At this time, the electron concentration of the two-dimensional electron gas located below the portion where the second insulating layer 202 is not formed becomes lower. Therefore, in the two-dimensional electron gas layer 105, a first two-dimensional electron gas layer 105A with a relatively low electron concentration and a second two-dimensional electron gas layer 105B with a relatively high electron concentration are generated.

[0092] Next, as Figure 3F As shown, the first insulating layer 201, which is separated from the second insulating layer 202 in the first insulating layer 201 exposed portion 201s, is removed to form the gate electrode 303 (gate electrode formation process).

[0093] Specifically, after applying a photoresist to the exposed portion 201s of the first insulating layer 201, a mask (photoresist mask) is formed outside the region where the gate electrode 303 is formed (the predetermined region for gate electrode formation) using photolithography. Next, the first insulating layer 201 is selectively removed using dry etching to form an opening 201a in the first insulating layer 201, exposing the electron supply layer 104. Then, the mask (photoresist mask) and the polymer generated by dry etching are removed. Afterward, the gate electrode 303 is formed in the opening 201a. Specifically, after forming a stacked film consisting of a 50 nm thick TiN film and a 450 nm thick Al film sequentially deposited by sputtering, the stacked film is patterned using photolithography and dry etching to form... Figure 3F The gate electrode 303 is of the specified shape shown. Then, the mask and the polymer produced by dry etching are removed.

[0094] Thus, after Figures 3A to 3F A series of processes to complete Figure 1 The semiconductor device 1 shown has the following structure.

[0095] In addition, Figure 3A When forming the second insulating layer 202, the second insulating layer 202 is preferably formed at a higher temperature than the first insulating layer 201. That is, the formation temperature of the second insulating layer 202 is preferably higher than the formation temperature of the first insulating layer 201. In other words, the formation temperature of the first insulating layer 201 is preferably lower than the formation temperature of the second insulating layer 202. Therefore, even if the first insulating layer 201 and the second insulating layer 202 are made of the same material such as SiN, the tensile stress of the second insulating layer 202 can be further enhanced relative to the first insulating layer 201, thereby further increasing the electron concentration of the second two-dimensional electron gas layer 105B.

[0096] (A variation of Implementation Method 1) Next, use Figure 4 A variation of Implementation 1 will be described. Figure 4 This is a cross-sectional view showing the structure of a semiconductor device 1A, a modified example of Embodiment 1.

[0097] like Figure 4 As shown, the semiconductor device 1A of this modified example differs from the semiconductor device 1 of Embodiment 1 in the structure of the first insulating layer 201A and the second insulating layer 202A. Specifically, in the semiconductor device 1 of Embodiment 1, the first insulating layer 201 and the second insulating layer 202 are separate, but in the semiconductor device 1A of this modified example, the first insulating layer 201A and the second insulating layer 202A are made of the same material and are formed by an integral insulating layer 203. That is, in this modified example, the first insulating layer 201A and the second insulating layer 202A are part of the insulating layer 203. Therefore, the first insulating layer 201A is the first insulating layer portion of the insulating layer 203, and the second insulating layer 202A is the second insulating layer portion of the insulating layer 203.

[0098] Specifically, a recess 203A is provided in the insulating layer 203. In the insulating layer 203, the portion with the recess 203A (i.e., the portion forming the gate electrode 303) is composed only of the first insulating layer 201A (first insulating layer portion), while the portion without the recess 203A is composed of the first insulating layer 201A (first insulating layer portion) and the second insulating layer 202 (second insulating layer portion). Therefore, the thickness of the portion of the insulating layer 203 containing the second insulating layer 202A (second insulating layer portion) is thicker than the thickness of the portion of the insulating layer 203 containing the first insulating layer 201A (first insulating layer portion). As an example, the thickness of the portion of the insulating layer 203 with the recess 203A is 5 nm, and the thickness of the portion of the insulating layer 203 without the recess 203A is 25 nm. Furthermore, from the viewpoint of avoiding damage to the electron supply layer 104 by dry etching, the thickness of the portion of the insulating layer 203 in which the recess 203A is formed is preferably 2 nm or more.

[0099] Furthermore, in manufacturing the semiconductor device 1A of this modified example, the first insulating layer 201A and the second insulating layer 202A are formed using the same material. Specifically, an insulating layer 203 with a thickness of 25 nm made of In-situ SiN is formed on the electron supply layer 104, and then a recess 203A is formed in the insulating layer 203 by dry etching in a manner that separates it from the gate electrode 303. Thus, it is possible to form... Figure 4 Insulating layer 203 in the shape shown.

[0100] The same effects as in Embodiment 1 can be obtained in the semiconductor device 1A of this modified example. Specifically, in this modified example, the electron concentration of the second two-dimensional electron gas layer 105B is also greater than the electron concentration of the first two-dimensional electron gas layer 105A. As a result, the decrease in electron concentration at the side adjacent portion of the through recess 211 in the electron supply layer 104 can be mitigated, thereby suppressing the decrease in the maximum drain current.

[0101] Furthermore, in this modified example, the first insulating layer 201A and the second insulating layer 202A can be integrally formed using the same material, so compared with the above-described embodiment 1, the semiconductor device 1A can be easily manufactured.

[0102] (Implementation Method 2) Next, use Figure 5 The semiconductor device 2 of Embodiment 2 will be described. Figure 5 This is a cross-sectional view showing the structure of the semiconductor device 2 according to Embodiment 2. Furthermore, the following description focuses on the differences from Embodiment 1, omitting or simplifying descriptions of commonalities.

[0103] The semiconductor device 2 of this embodiment differs from the semiconductor device 1 of Embodiment 1 in that the structure of the second insulating layer 202B is different. Specifically, the second insulating layer 202 of the semiconductor device 1 of Embodiment 1 is made of SiN, but the second insulating layer 202B of the semiconductor device 2 of this embodiment is made of a nitride layer such as SiON. Furthermore, the semiconductor device 2 of this embodiment, like that of Embodiment 1, is a HEMT with a Schottky junction gate structure.

[0104] In this embodiment, the second insulating layer 202B is made of SiON with a thickness of 20 nm. However, the thickness of the second insulating layer 202B is not limited to 20 nm. As an example, the thickness of the second insulating layer 202B is 2 nm or more and 200 nm or less.

[0105] Furthermore, the second insulating layer 202B in this embodiment, like the second insulating layer 202 in embodiment 1 above, is disposed on the first insulating layer 201 in contact with the contact layer 212 and not grounded to the gate electrode 303.

[0106] By configuring the semiconductor device 2 in this way, the electron concentration of the two-dimensional electron gas layer 105 can be made different in the portion where the second insulating layer 202B is present and in the portion where the second insulating layer 202B is not present. Specifically, the two-dimensional electron gas layer 105 has a first two-dimensional electron gas layer 105A located not below the second insulating layer 202B and a second two-dimensional electron gas layer 105B located below the second insulating layer 202B, wherein the electron concentration of the second two-dimensional electron gas layer 105B is greater than the electron concentration of the first two-dimensional electron gas layer 105A.

[0107] By configuring the semiconductor device 2 in this way, similarly to Embodiment 1 described above, the electron concentration of the two-dimensional electron gas layer 105 can be made different in the portion where the second insulating layer 202B is present and in the portion where the second insulating layer 202B is not present. Specifically, the two-dimensional electron gas layer 105 has a first two-dimensional electron gas layer 105A located not below the second insulating layer 202B and a second two-dimensional electron gas layer 105B located below the second insulating layer 202B, wherein the electron concentration of the second two-dimensional electron gas layer 105B is greater than the electron concentration of the first two-dimensional electron gas layer 105A.

[0108] Here, in this embodiment, the following is used Figure 6 Explain the mechanism by which the electron concentration of the second two-dimensional electron gas layer 105B is higher than that of the first two-dimensional electron gas layer 105A. Figure 6 This is a schematic diagram showing the conduction band of the energy band of the semiconductor device 2 in Embodiment 2.

[0109] exist Figure 6 In the middle, the solid line A is parallel to... Figure 5The diagram shows the part corresponding to the single-dot dashed line A, and the dashed line B is the part corresponding to... Figure 5 The diagram shows the portion corresponding to the dashed line B. That is, Figure 6 The solid line A in the diagram represents the adjacent portion of the gate electrode 303, i.e., the gate adjacent portion (i.e., the portion where only the first insulating layer 201 is provided above the first insulating layer 201 without the second insulating layer 202B). Additionally, Figure 2 The dashed line B in the figure is a diagram of the adjacent portion of the contact layer 212, namely the contact adjacent portion (that is, the portion on which the second insulating layer 202B is provided above the first insulating layer 201).

[0110] In this embodiment, since the second insulating layer 202B is composed of a nitride layer such as SiON, it has a positive fixed charge. Because the second insulating layer 202B has a positive fixed charge, the potential of the electron supply layer 104 decreases, and the potential at the interface between the electron supply layer 104 and the electron travel layer 103 decreases. Consequently, the electron concentration of the second two-dimensional electron layer gas 105B located below the second insulating layer 202B increases. That is, the electron concentration of the second two-dimensional electron layer 105B is relatively larger than that of the first two-dimensional electron layer 105A.

[0111] Thus, the semiconductor device 2 of this embodiment can also achieve a higher electron concentration in the second two-dimensional electron gas layer 105B than in the first two-dimensional electron gas layer 105A. This mitigates the decrease in electron concentration at the side adjacent portion of the through-recess 211 in the electron supply layer 104, thereby suppressing the decrease in maximum drain current. Furthermore, in this embodiment, since the electron concentration at the gate adjacent portion corresponding to the first two-dimensional electron gas layer 105A is maintained, the leakage current between the gate electrode 303 and the drain electrode 302 can also be reduced. That is, in the semiconductor device 2 of this embodiment, similar to Embodiment 1 described above, the suppression of the decrease in maximum drain current and the reduction of the gate-drain leakage current can be achieved simultaneously. In addition, the second insulating layer 202 contributes significantly to the increase in two-dimensional electron gas, thereby reducing the deviation of the drain current caused by the side condition deviation (etching condition deviation) of the through-recess 211.

[0112] Furthermore, in this embodiment, the second insulating layer 202B is composed of a nitride layer, but it is not limited to this. Specifically, the second insulating layer 202B may also be a composite layer of oxides and nitrides. In other words, the second insulating layer 202B may also be a composite layer of layers made of the same material as the first insulating layer 201 and oxide layers. For example, the second insulating layer 202B may also be a structure formed by stacking SiN, SiO2, and SiN. In this way, even if the second insulating layer 202B is not a nitride layer but a composite layer of oxide layers, it still has a positive fixed charge. Therefore, the electron concentration of the second two-dimensional electron gas layer 105B located below the second insulating layer 202B increases, which can suppress the decrease in the maximum drain current.

[0113] In this case, the SiO2 film constituting a portion of the second insulating layer 202B is preferably an extremely thin interfacial oxide layer with a thickness of less than 1 nm. Thus, the SiO2 is excited by the nitride and acquires a positive fixed charge, thereby achieving the same effect as when using SiON with a positive fixed charge.

[0114] Furthermore, in the semiconductor device 2 of this embodiment, the second insulating layer 202B may also include an n-type semiconductor layer. The n-type semiconductor layer included in the second insulating layer 202B may be, for example, a group III semiconductor such as n-type GaN, or a group IV semiconductor such as n-type polysilicon. Because the second insulating layer 202B includes an n-type semiconductor layer, the electron concentration of the second two-dimensional electron gas layer 105B is greater than that of the first two-dimensional electron gas layer 105A. Therefore, the decrease in electron concentration at the side adjacent portion of the through-recess 211 in the electron supply layer 104 can be mitigated, thus suppressing the decrease in the maximum drain current.

[0115] Furthermore, in the semiconductor device 2 of this embodiment, similarly to that of Embodiment 1, the halogen concentration of the first insulating layer 201 is preferably 1×10⁻⁶. 18 atoms / cm 3 Therefore, it is possible to reduce the negative fixed charge in the first insulating layer 201, eliminate the potential rise at the interface between the electron supply layer 104 and the electron travel layer 103, and eliminate the reduction in electron concentration in the first two-dimensional electron gas layer 105A and the second two-dimensional electron gas layer 105B due to halogens.

[0116] Next, use Figures 7A to 7G The manufacturing method of the semiconductor device 2 in this embodiment will be described. Figures 7A to 7G This is a cross-sectional view showing each step of the manufacturing method of the semiconductor device 2 according to Embodiment 2. Figure 7A The process of forming a semiconductor stacked structure 100 and a first insulating layer 201 is shown. Figure 7BThe process of forming the through recess 211 is shown. Figure 7C The process of forming contact layer 212 is shown. Figure 7D The process of forming the second insulating layer 202B is shown. Figure 7E The process of forming the source electrode 301 and the drain electrode 302 is shown. Figure 7F The process of patterning the second insulating layer 202B is shown. Figure 7G The process of forming the gate electrode 303 is shown.

[0117] First, such as Figure 7A As shown, similarly to the first embodiment, a semiconductor stacked structure 100 including a buffer layer 102, an electron travel layer 103 and an electron supply layer 104 is formed on a substrate 101 by MOCVD.

[0118] Next, a first insulating layer 201 is formed on the semiconductor stack structure 100 (first insulating layer formation process). In this embodiment, after the semiconductor stack structure 100 is formed, the first insulating layer 201 is continuously formed in the same semiconductor crystal growth apparatus (MOCVD furnace). That is, the first insulating layer 201 is formed on the electron supply layer 104 without exposure to the atmosphere. In this way, by forming the first insulating layer 201 on the electron supply layer 101 without exposure to the atmosphere, oxygen is not unevenly distributed between the electron supply layer 104 and the first insulating layer 201. Under this configuration, a high concentration of two-dimensional electron gas is generated on the electron travel layer 103 side of the heterogeneous interface between the electron supply layer 104 and the electron travel layer 103, forming a two-dimensional electron gas layer 105.

[0119] Next, as Figure 7B As shown, a portion of the semiconductor stacked structure 100 is removed to form a through recess 211 (through recess formation process). In this embodiment, a first insulating layer 201 is formed on the semiconductor stacked structure 100, so a portion of the first insulating layer 201 is also removed along with the semiconductor stacked structure 100.

[0120] Specifically, after coating the first insulating layer 201 with a photoresist, the photoresist is patterned using photolithography, thereby forming a mask in the area except for the region where the contact layer 212 is formed (i.e., the region where the source electrode 301 and drain electrode 302 are formed). That is, an opening is formed in the region of the photoresist where the contact layer 212 is formed. Specifically, an opening is formed in each region where the source-side contact layer 212A and the drain-side contact layer 212B are formed.

[0121] Next, by using a resist with an opening as a mask, dry etching is performed to form a through recess 211 that penetrates the first insulating layer 201 and the electron supply layer 104 to reach the electron travel layer 103. Specifically, as Figure 7B As shown, two through-recesses 211 are formed corresponding to the regions forming the source-side contact layer 212A and the drain-side contact layer 212B, respectively. By forming the through-recesses 211, a portion of the electron travel layer 103 is exposed. Subsequently, the mask (resist) and the polymer generated by dry etching are removed.

[0122] Next, as Figure 7C As shown, a contact layer 212 is embedded in the through recess 211 (contact layer forming process).

[0123] Specifically, similar to Embodiment 1 described above, the first insulating layer 201 is used as a mask, and MOCVD is applied to embed it into the two through recesses 211 to make n + -GaN regrowth. This allows for the selective embedding of GaN-based structures into the two through-recesses 211. + - A GaN-based contact layer 212. Furthermore, the contact layer 212 embedded in one of the two through-recesses 211 is a source-side contact layer 212A, and the contact layer 212 embedded in the other of the two through-recesses 211 is a drain-side contact layer 212B.

[0124] Next, as Figure 7D As shown, a second insulating layer 202B is formed on the first insulating layer 201 (second insulating layer formation process).

[0125] Specifically, a second insulating layer 202B, consisting of SiON as a nitrogen oxide, with a thickness of 20 nm, is formed on the first insulating layer 201. The film formation conditions for forming the second insulating layer 202B are, for example, a growth temperature of 900~1150°C, and SiH4 and NH3 are preferably used as raw material gases.

[0126] Furthermore, the second insulating layer 202B composed of SiON can also be formed by heat treatment at a temperature below 800°C in an oxygen and nitrogen atmosphere after the formation of SiO2. In this case, a second insulating layer 202B composed of SiON with a positive fixed charge can also be formed. Alternatively, heat treatment can be omitted, and a plasma nitriding treatment using NH3 plasma can be performed after the formation of SiO2, thereby forming a second insulating layer 202B composed of SiON with a positive fixed charge.

[0127] Next, as Figure 7EAs shown, a source electrode 301 and a drain electrode 302 are formed on the contact layer 212 in a grounded manner (source electrode / drain electrode forming process).

[0128] Specifically, after removing a portion of the second insulating layer 202B to expose the contact layer 212, similar to Embodiment 1 described above, a Ti film and an Al film are sequentially deposited by vapor deposition to form a laminated film. Unwanted laminated films are then removed by a stripping method. This allows a source electrode 301 and a drain electrode 302 of a predetermined shape, composed of a laminated Ti film and an Al film, to be formed on the contact layer 212. In this embodiment, the source electrode 301 is formed on the source-side contact layer 212A, and the drain electrode 302 is formed on the drain-side contact layer 212B.

[0129] Then, by performing heat treatment, the two-dimensional electron gas layer 105 and the contact layer 212 are electrically ohmically connected.

[0130] Next, as Figure 7F As shown, the second insulating layer 202B is patterned, and the portion of the second insulating layer 202B where the gate electrode 303 is disposed is removed (second insulating layer patterning process).

[0131] Specifically, similar to Embodiment 1 described above, after applying the resist, the resist is patterned into a predetermined shape using photolithography, forming a continuous mask (resist mask) in the region where the active electrode 301 and drain electrode 302 are formed and in the region separated from the region where the gate electrode 303 is formed (the predetermined region for gate electrode formation). Then, using dry etching, the portion of the second insulating layer 202B that is in contact with the contact layer 212 is removed, thereby exposing the first insulating layer 201 and forming the first insulating layer exposed portion 201s. At this time, the second insulating layer 202B located below the patterned resist (resist mask) remains. That is, the portion of the second insulating layer 202B in contact with the contact layer 212 remains. Then, the resist and polymer are removed. Thus, a second insulating layer 202B with an opening 202a in the region where the gate electrode 303 is formed can be formed. At this time, the electron concentration of the two-dimensional electron gas located below the portion where the second insulating layer 202B is not formed becomes lower. Therefore, in the two-dimensional electron gas layer 105, a first two-dimensional electron gas layer 105A with a relatively low electron concentration and a second two-dimensional electron gas layer 105B with a relatively high electron concentration are generated.

[0132] Next, as Figure 7GAs shown, the gate electrode 303 is formed by removing the portion of the first insulating layer 201 that is separated from the second insulating layer 202B in the first insulating layer exposed portion 201s (gate electrode formation process). Specifically, the gate electrode 303 can be formed in the same manner as in Embodiment 1 described above.

[0133] Thus, after Figures 7A to 7G A series of processes to complete Figure 4 Semiconductor device 2 with the structure shown.

[0134] In addition, Figure 7D When forming the second insulating layer 202B in the process, the formation temperature of the second insulating layer 202 is preferably higher than the formation temperature of the first insulating layer 201. That is, the formation temperature of the first insulating layer 201 is preferably lower than the formation temperature of the second insulating layer 202B. As a result, the tensile stress of the second insulating layer 202B can be enhanced relative to the first insulating layer 201, thereby further increasing the electron concentration of the second two-dimensional electron gas layer 105B.

[0135] (Other variations) The semiconductor device of this disclosure has been described above based on Embodiment 1 and Embodiment 2, but this disclosure is not limited to Embodiment 1 and Embodiment 2.

[0136] For example, in Embodiments 1 and 2 described above, the electron travel layer 103 and the electron supply layer 104 are made of group III nitride semiconductors, but are not limited thereto. Specifically, the electron travel layer 103 and the electron supply layer 104 may also be made of other semiconductor materials such as group III arsenide semiconductors.

[0137] Furthermore, in Embodiment 1 described above, the second insulating layer 202 is made of SiN, but it is not limited to this. For example, in Embodiment 1 described above, the second insulating layer 202 may also be an oxygen-containing layer such as SiON or SiO2. Therefore, compared to the case where the second insulating layer 202 is SiN, the coefficient of thermal expansion of the second insulating layer 202 can be increased. This further increases the tensile stress of the second insulating layer 202, and further increases the electron concentration of the second two-dimensional electron gas layer 105B relative to the electron concentration of the first two-dimensional electron gas layer 105A. Therefore, the decrease in electron concentration at the side adjacent portion of the through-recess 211 in the electron supply layer 104 can be further reduced, and the decrease in the maximum drain current can be further suppressed. Furthermore, in the first embodiment described above, by making the second insulating layer 202 SiON, similarly to the second embodiment described above, the second insulating layer 202 can be a layer with a positive fixed charge. Therefore, the electron concentration of the second two-dimensional electron gas layer 105B located below the second insulating layer 202 is further increased, and the decrease in the maximum drain current can be further suppressed.

[0138] Furthermore, in Embodiment 2, similarly to Embodiment 1, the linear thermal expansion coefficient of the second insulating layer 202B can be greater than that of the electron supply layer 104, and the tensile stress of the second insulating layer 202B can be greater than that of the first insulating layer 201. This further increases the electron concentration of the second two-dimensional electron gas layer 105B, thereby further suppressing the decrease in the maximum drain current.

[0139] Furthermore, this disclosure also includes various modifications conceived by those skilled in the art to the above embodiments, and methods of arbitrarily combining the constituent elements and functions of the embodiments without departing from the spirit of this disclosure. Additionally, this disclosure also includes solutions obtained by arbitrarily combining two or more claims from the multiple claims recited in the claims at the time of filing this application, to the extent that they are not technically contradictory. For example, when a dependent claim recited in the claims at the time of filing this application is designated as a plurality of claims or a plurality of dependent claims by referencing all superior claims to the extent that they are not technically contradictory, the combination of all claims contained in such plurality of claims or plurality of dependent claims is also included in this disclosure.

[0140] Industrial applicability The technology disclosed herein can be used in semiconductor devices such as switching transistors for use in communication equipment, inverters, and power supply circuits that require high-speed operation. In particular, the technology disclosed herein is applicable to high-frequency power devices where heat generation caused by ohmic contact resistance has a significant impact.

[0141] Explanation of reference numerals in the attached figures 1.1A,2 Semiconductor Devices 100 Semiconductor Stacked Structure 101 substrate 102 Buffer Layer 103 Electronic Travel Layer 104 Electronic Supply Layer 105 Two-Dimensional Electron Gas Layer 105A First Two-Dimensional Electron Gas Layer 105B Second Two-Dimensional Electron Gas Layer 201, 201A First Insulation Layer 201a opening 201s first insulation layer exposed part 202, 202A, 202B, 203 Second Insulation Layer 202a opening 203A recess 211 Through-depression 212 contact layer 212A source-side contact layer 212B Drain-side Contact Layer 301 source electrode 302 drain electrode 303 gate electrode

Claims

1. A semiconductor device, characterized in that, have: Electronic travel layer; An electron supply layer is disposed on the electron travel layer, and its band gap is larger than that of the electron travel layer; A gate electrode is disposed on the electron supply layer; The source-side contact layer and the drain-side contact layer are buried in the recess that runs through the electron supply layer at a position separated from the gate electrode. A first insulating layer is disposed on the portion of the electron supply layer where the gate electrode is not disposed; as well as A second insulating layer, which is connected to the source-side contact layer and / or the drain-side contact layer but not grounded to the gate electrode, is disposed on the first insulating layer. The linear thermal expansion coefficient of the second insulating layer is larger than that of the electron supply layer. The halogen concentration of both the first and second insulating layers is 1×10⁻⁶. 18 atoms / cm 3 the following.

2. The semiconductor device according to claim 1, characterized in that, There is no uneven distribution of oxygen between the first insulating layer and the electron supply layer.

3. The semiconductor device according to claim 1 or 2, characterized in that, The first insulating layer does not contain oxygen.

4. The semiconductor device according to claim 1 or 2, characterized in that, The second insulating layer contains oxygen.

5. The semiconductor device according to claim 1 or 2, characterized in that, In cross-section, the width of the second insulating layer is less than 1 μm.

6. The semiconductor device according to claim 1 or 2, characterized in that, The tensile stress of the second insulating layer is greater than that of the first insulating layer.

7. The semiconductor device according to claim 1 or 2, characterized in that, The first insulating layer and the second insulating layer are made of the same material. The density of the first insulating layer is smaller than the density of the second insulating layer.

8. The semiconductor device according to claim 1 or 2, characterized in that, The electron travel layer and the electron supply layer are made of group III nitride semiconductors.

9. A semiconductor device, characterized in that, have: Electronic travel layer; An electron supply layer is disposed on the electron travel layer, and its band gap is larger than that of the electron travel layer; A gate electrode is disposed on the electron supply layer; The contact layer is embedded in a recess that passes through the electron supply layer at a position across the gate electrode; The source electrode or drain electrode is disposed on the contact layer; A first insulating layer is disposed on the portion of the electron supply layer where the gate electrode is not disposed; as well as A second insulating layer, which is in contact with the contact layer but not grounded to the gate electrode, is disposed on the first insulating layer. The second insulating layer has a nitrogen oxide layer or a composite layer of oxides and nitrides. The halogen concentration of the first insulating layer is 1×10 18 atoms / cm 3 the following.

10. The semiconductor device according to claim 9, characterized in that, The second insulating layer includes an n-type semiconductor layer.

11. The semiconductor device according to claim 9 or 10, characterized in that, The electron travel layer and the electron supply layer are made of group III nitride semiconductors.

12. A semiconductor device, characterized in that, have: Electronic travel layer; An electron supply layer is disposed on the electron travel layer, and its band gap is larger than that of the electron travel layer; A gate electrode is disposed on the electron supply layer; The source-side contact layer and the drain-side contact layer are buried in the recess that runs through the electron supply layer at a position separated from the gate electrode. A first insulating layer is disposed on the portion of the electron supply layer where the gate electrode is not disposed; as well as A second insulating layer, which is connected to the source-side contact layer and / or the drain-side contact layer but not grounded to the gate electrode, is disposed on the first insulating layer. The linear thermal expansion coefficient of the second insulating layer is larger than that of the electron supply layer. In cross-section, the width of the second insulating layer is less than 1 μm.

13. The semiconductor device according to claim 12, characterized in that, There is no uneven distribution of oxygen between the first insulating layer and the electron supply layer.

14. The semiconductor device according to claim 12 or 13, characterized in that, The first insulating layer does not contain oxygen.

15. The semiconductor device according to claim 12 or 13, characterized in that, The second insulating layer contains oxygen.

16. The semiconductor device according to claim 12 or 13, characterized in that, The halogen concentration of both the first and second insulating layers is 1×10⁻⁶. 18 atoms / cm 3 the following.

17. The semiconductor device according to claim 12 or 13, characterized in that, The tensile stress of the second insulating layer is greater than that of the first insulating layer.

18. The semiconductor device according to claim 12 or 13, characterized in that, The first insulating layer and the second insulating layer are made of the same material. The density of the first insulating layer is smaller than the density of the second insulating layer.

19. The semiconductor device according to claim 12 or 13, characterized in that, The electron travel layer and the electron supply layer are made of group III nitride semiconductors.

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