Distributed multi-station data synchronization acquisition method and system based on white rabbit technology

Abstract

The application provides a distributed multi-station data synchronization acquisition method and system based on white rabbit technology, and relates to the field of radar data acquisition.The method comprises the following steps: based on white rabbit WR technology, data interaction is carried out between a WR switch and a WR node through an optical fiber, so that the WR node outputs two-way phase-related 10MHz signals and PPS signals; the PPS signals are sent to a data acquisition board as a reference clock, and the 10MHz signals are sent to a clock power division circuit to divide a first target signal and a second target signal; the first target signal is sent to an FPGA as a system running clock, and the second target signal is sent to a clock generation chip circuit to generate an ADC sampling clock and a system reference clock.The application utilizes white rabbit technology to distribute time and frequency, and realizes distributed multi-station data synthesis through a PPS synchronization acquisition instruction, so that the ability and detection distance of a detection target are increased, and the application is convenient, reliable and superior in performance.

Description

Technical Field

[0001] This application relates to the field of radar data acquisition technology, specifically to a distributed multi-site data synchronization acquisition method and system based on White Rabbit technology. Background Technology

[0002] White Rabbit (WR) clock synchronization technology is a distributed synchronization and timing technology that integrates Synchronous Ethernet (Sync-E), the Precision Timing Protocol (IEEE 1588v2), and digital phase measurement technology. It can achieve sub-nanosecond clock distribution across multiple nodes within a range of several kilometers. This technology is compatible with standard Ethernet protocols, does not consume additional network bandwidth, and is directly integrated with the data link, resulting in a simple structure and low cost. This method is effectively applied to long-distance, multi-node, high-precision time synchronization applications and is also widely used in distributed network measurement and control, time unification systems, industrial automation control, distributed base stations and remote radio frequency systems, power grid synchronization, adaptive array antennas, distributed multi-static radar, indoor positioning, and many other applications.

[0003] Distributed radar, due to its multi-angle and multi-path detection methods, has advantages in spatial diversity gain and detection performance compared to traditional monostation radar. This means it requires less transmit power for the same detection range, exhibiting low intercept characteristics, or it can have a larger detection range for the same transmit power. Multi-angle detection can obtain high-scattering-coefficient echoes from targets with a higher probability, resulting in superior performance in observing small targets.

[0004] While distributed radar offers many advantages, the geographically dispersed nature of multiple stations presents significant engineering challenges. Compared to monostatic radar, the primary technical hurdle for distributed fully coherent radar lies in the synchronization of time, space, and phase among the individual radar units. Because distributed fully coherent radar requires signals from each unit to satisfy temporal and phase coherence, the synchronization accuracy requirements are extremely high. Currently, fiber optic transmission for time and frequency synchronization is commonly used. However, this method is susceptible to environmental factors, resulting in short transmission distances, time accuracy typically at the nanosecond level, and limited target detection capabilities and ranges. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this application provides a distributed multi-site data synchronization acquisition method and system based on White Rabbit technology, which solves the problems of short transmission distance, low time accuracy, and weak target detection capability faced by current distributed radars when acquiring data.

[0006] To achieve the above objectives, this application provides the following technical solution:

[0007] In a first aspect, embodiments of this application provide a distributed multi-site data synchronization acquisition method based on White Rabbit technology. This method includes: acquiring a GPS / reference clock source, a WR switch, multiple WR nodes, fiber optic lines, and multiple data acquisition boards; based on White Rabbit WR technology, data interaction is performed between the WR switch and WR nodes via fiber optics, enabling the WR nodes to output two coherent 10MHz signals and a PPS signal; the PPS signal output by the WR nodes is sent to the data acquisition boards as a reference clock, and the 10MHz signal output by the WR nodes is sent to the clock power divider circuit of the data acquisition boards to separate a first target signal and a second target signal; the first target signal is sent to the FPGA on the data acquisition boards as a system operating clock, and the second target signal is sent to a clock generation chip circuit to generate an ADC sampling clock and a system reference clock with the same frequency and coherent phase; based on the data acquisition boards, external control commands are received through a data interface to initiate data acquisition, and the data from multiple data acquisition boards is fused and processed and output through the data interface.

[0008] According to a first aspect of the embodiments of this application, the GPS / reference clock source is used to provide UTC time code and two clock signals: the two clock signals include a 10MHz signal and a PPS signal; the WR switch adopts high-precision distributed time synchronization technology based on fiber optic Ethernet technology, and can perform sub-nanosecond precision time synchronization between tens of thousands of nodes in a spatial distance of less than 10km, so as to be applied to long-distance multi-node high-precision time synchronization occasions.

[0009] According to a first aspect of the embodiments of this application, the WR switch synchronizes with the upper-level clock as a slave clock and synchronizes with the lower-level clock as a master clock to complete cross-boundary clock synchronization; wherein, the clock synchronization process based on the WR switch includes: frequency synchronization and time synchronization representing absolute time information.

[0010] According to a first aspect of the embodiments of this application, the 10MHz signal and PPS signal output by each WR node are respectively the same frequency and have fixed phase as the 10MHz signal and PPS signal input by the WR switch; the number of data acquisition boards is the same as the number of WR nodes, and the data acquisition boards include a clock power divider circuit, an FPGA, a clock generation chip circuit, an ADC, and a data interface circuit.

[0011] According to a first aspect of the embodiments of this application, a clock power divider circuit is used to distribute the input clock and generate multiple clocks. The output clock of the clock power divider circuit is the same as the input signal in frequency and phase, and has low latency and low clock jitter characteristics. A clock generation chip circuit is used to generate an ADC sampling clock and a system reference clock. The system reference clock serves as a reference clock for the ADC and the FPGA to achieve synchronization of ADC data acquisition and FPGA reception. The clock generation chip circuit configures the operating mode and output frequency through a configuration interface to realize multiple sampling clocks and operating modes. The ADC adopts a wideband analog-to-digital converter based on the JESD204B protocol to directly sample the input high-frequency signal. The FPGA is the main control chip of the data acquisition board. It implements system data acquisition and reception control through programming, configures the ADC and the clock generation chip circuit, and realizes command reception, synchronization, and data packet output.

[0012] According to a first aspect of the embodiments of this application, the aforementioned method based on a data acquisition board receives external control commands through a data interface, initiates data acquisition, fuses data from multiple data acquisition boards, and outputs the data through the data interface. Specifically, this may include: sending a system reference clock to the FPGA as a reference and using the PPS signal as a time reference; upon receiving an acquisition control command, initiating acquisition by multiple data acquisition boards when the next pulse of the PPS signal arrives, to ensure that multiple data acquisition boards acquire data at the same time.

[0013] According to a first aspect of the embodiments of this application, the data interface achieves a communication rate of more than 10Gb / s through optical fiber. The data collected based on the data interface is transmitted to the host computer of the system through optical fiber based on the communication protocol to realize data reception and processing. The WR node and the data acquisition board are located at different site locations, and the distribution distance between some sites is greater than 10km. Multiple sites can synchronously collect and receive the same target signal and perform multi-site data fusion processing.

[0014] Secondly, embodiments of this application provide a distributed multi-site data synchronization acquisition system based on White Rabbit technology. The distributed multi-site data synchronization acquisition system based on White Rabbit technology includes: an acquisition module, a data interaction module, a first input module, a second input module, and an acquisition module.

[0015] Specifically, the acquisition module is used to acquire GPS / reference clock sources, WR switches, multiple WR nodes, fiber optic lines, and multiple data acquisition boards; the data interaction module is used to perform data interaction between the WR switches and WR nodes through fiber optics based on the White Rabbit WR technology, so that the WR nodes output two coherent 10MHz signals and a PPS signal; the first input module is used to input the PPS signal output by the WR node into the data acquisition board as a reference clock, and input the 10MHz signal output by the WR node into the clock power divider circuit of the data acquisition board to separate the first target signal and the second target signal; the second input module is used to input the first target signal into the FPGA on the data acquisition board as the system operating clock, and input the second target signal into the clock generation chip circuit to generate an ADC sampling clock and a system reference clock with the same frequency and coherent phase; the acquisition module is used to receive external control commands through the data interface based on the data acquisition board, start data acquisition, perform fusion processing on the data from multiple data acquisition boards, and output the data through the data interface.

[0016] Thirdly, embodiments of this application provide an electronic device, which includes: a processor, a memory, and a program stored in the memory and executable on the processor. When the program is executed by the processor, it implements the distributed multi-site data synchronization acquisition method based on the White Rabbit technology described in the first aspect.

[0017] Fourthly, embodiments of this application provide a computer-readable storage medium storing a program or instructions that, when executed by a processor, implement the distributed multi-site data synchronization acquisition method based on the White Rabbit technology described in the first aspect.

[0018] This application provides a distributed multi-site data synchronization acquisition method and system based on White Rabbit technology. Compared with existing technologies, it has the following advantages:

[0019] This application utilizes a wired communication method, integrating synchronous Ethernet, a precise timing protocol, and digital phase measurement technology using the White Rabbit technique. This allows for the technical distribution of time and frequency across multiple stations, achieving sub-nanosecond time synchronization and resulting in improved stability and reliability. The data acquisition boards at multiple stations operate at the same frequency and maintain a fixed phase. Through FPGA software design, data acquisition from multiple stations at the same time for the same target can be achieved, enabling the synthesis of target signal data. This application utilizes the White Rabbit technique for time and frequency distribution and achieves distributed multi-site data synthesis through PPS synchronous acquisition commands, increasing the target detection capability and range. It is convenient to implement, highly reliable, and offers superior performance. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart illustrating a distributed multi-site data synchronization and acquisition method based on White Rabbit technology provided in an embodiment of this application;

[0022] Figure 2 This is a schematic diagram of the structure of a distributed multi-site data synchronization acquisition system based on White Rabbit technology provided in an embodiment of this application;

[0023] Figure 3 This is an exemplary block diagram of a distributed multi-site data synchronization and acquisition system based on White Rabbit technology provided in an embodiment of this application;

[0024] Figure 4 This is an architecture diagram of the digital acquisition board provided in the embodiments of this application;

[0025] Figure 5 This is a clock power divider circuit diagram provided in an embodiment of this application;

[0026] Figure 6 This is a circuit diagram of a clock generation chip provided in an embodiment of this application;

[0027] Figure 7 This is an ADC circuit diagram provided in an embodiment of this application;

[0028] Figure 8 This is a diagram of an optical fiber transceiver circuit provided in an embodiment of this application;

[0029] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention are described clearly and completely. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0032] This application provides a distributed multi-site data synchronization acquisition method and system based on White Rabbit technology, which solves the problems of short transmission distance, low time accuracy, and weak target detection capability faced by current distributed radars when acquiring data.

[0033] The technical solution in this application is to solve the above-mentioned technical problems, and the general idea is as follows:

[0034] White Rabbit (WR) clock synchronization technology is a distributed synchronization and timing technology that integrates Synchronous Ethernet (Sync-E), the Precision Timing Protocol (IEEE 1588v2), and digital phase measurement technology. It can achieve sub-nanosecond clock distribution across multiple nodes within a range of several kilometers. This technology is compatible with standard Ethernet protocols, does not consume additional network bandwidth, and is directly integrated with the data link, resulting in a simple structure and low cost. This method is effectively applied to long-distance, multi-node, high-precision time synchronization applications and is also widely used in distributed network measurement and control, time unification systems, industrial automation control, distributed base stations and remote radio frequency systems, power grid synchronization, adaptive array antennas, distributed multi-static radar, indoor positioning, and many other applications.

[0035] Distributed radar, due to its multi-angle and multi-path detection methods, has advantages in spatial diversity gain and detection performance compared to traditional monostation radar. This means it requires less transmit power for the same detection range, exhibiting low intercept characteristics, or it can have a larger detection range for the same transmit power. Multi-angle detection can obtain high-scattering-coefficient echoes from targets with a higher probability, resulting in superior performance in observing small targets.

[0036] Distributed radar has the following advantages: (1) Distributed radar can receive electromagnetic scattering information from targets more effectively, improving the sensitivity of the system and enabling the detection of targets at greater distances. (2) Distributed radar can receive electromagnetic scattering information from targets that cannot be received by monostatic radar, thus having an advantage in detecting stealth targets. (3) If a separate transmit and receive system structure is adopted, the receiver of the distributed radar is in a passive state, and electronic warfare means cannot determine the location of the receiver, thus effectively improving the survivability of the radar. (4) Distributed radar has high reliability; even if part of the transmitter and receiver of the radar system is damaged, it will not lead to the complete paralysis of the entire radar system. (5) Since the spatial distance between each radar unit is relatively far, distributed radar has a long baseline, which can effectively improve the positioning accuracy of targets. (6) Distributed radar can receive scattering information from targets at different angles, which helps to improve the target identification capability of the radar system.

[0037] While distributed radar offers many advantages, the presence of multiple stations in different locations presents numerous technical challenges. Compared to monostatic radar, the primary technical difficulty of distributed fully coherent radar lies in the synchronization of time, space, and phase among the individual radar units. Because distributed fully coherent radar requires that the signals from each unit satisfy temporal and phase coherence, the synchronization accuracy requirements are extremely high. Currently available synchronization methods can be broadly categorized into radio signal methods and wired communication methods, based on the signal transmission method. Current synchronization methods utilizing fiber optic transmission of time and frequency are susceptible to environmental factors, resulting in short transmission distances, time accuracy typically at the nanosecond level, weak target detection capabilities, and limited detection range.

[0038] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0039] The following section first introduces a distributed multi-site data synchronization acquisition method based on White Rabbit technology provided in the embodiments of this application.

[0040] This application provides a flowchart illustrating a distributed multi-site data synchronization and acquisition method based on White Rabbit technology, as shown in the embodiments below. Figure 1 As shown, the distributed multi-site data synchronization acquisition method based on White Rabbit technology may include the following steps S110-S150.

[0041] S110, GPS / reference clock source acquisition, WR switch, multiple WR nodes, fiber optic lines, and multiple data acquisition boards;

[0042] S120, based on White Rabbit WR technology, enables data exchange between the WR switch and the WR node via optical fiber, so that the WR node outputs two coherent 10MHz signals and PPS signals.

[0043] S130. The PPS signal output by the WR node is sent to the data acquisition board as a reference clock, and the 10MHz signal output by the WR node is sent to the clock power divider circuit of the data acquisition board to separate the first target signal and the second target signal.

[0044] S140. The first target signal is sent to the FPGA on the data acquisition board as the system running clock, and the second target signal is sent to the clock generation chip circuit to generate an ADC sampling clock and a system reference clock with the same frequency and phase.

[0045] S150, based on a data acquisition board, receives external control commands through a data interface, starts data acquisition, merges and processes data from multiple data acquisition boards, and outputs the data through the data interface.

[0046] The above is a specific implementation of a distributed multi-site data synchronization acquisition method based on White Rabbit technology provided in this application. It can be understood that this application uses a wired communication method based on White Rabbit technology, which enables multiple sites to achieve precise synchronization of time, frequency and phase within a radius of 10km. This application utilizes White Rabbit technology to integrate synchronous Ethernet, precision timing protocol and digital phase measurement technology, which can technically achieve the distribution of time and frequency among multiple sites, achieve sub-nanosecond time synchronization, and have better stability and reliability. It can also be further upgraded on this basis to obtain a higher time synchronization reference.

[0047] Furthermore, the data acquisition boards at multiple stations operate at the same frequency and maintain a fixed phase. Through FPGA software design, data acquisition from multiple stations at the same time for the same target can be achieved, enabling data synthesis of the target signal. The clock frequencies between stations are precisely synchronized with the master node clock frequency (±10). -11 (Long-term accuracy) to achieve large-scale, multi-node clock distribution and synchronization mechanism, with time synchronization accuracy reaching the sub-nanosecond level, which can well realize the synchronous acquisition of the same target signal by multiple stations and realize multi-site data fusion.

[0048] Based on this, this application utilizes the White Rabbit technology for time and frequency distribution, and achieves distributed multi-site data synthesis through PPS synchronous acquisition commands, thereby increasing the ability to detect targets and the detection range. It is convenient to implement, highly reliable, and has superior performance.

[0049] In some embodiments, the GPS / reference clock source is used to provide UTC time code and two clock signals: the two clock signals include a 10MHz signal and a PPS signal; the WR switch adopts high-precision distributed time synchronization technology based on fiber optic Ethernet technology, and can perform sub-nanosecond time synchronization between tens of thousands of nodes in a spatial distance of less than 10km, so as to be applied to long-distance multi-node high-precision time synchronization occasions.

[0050] In the embodiments of this application, it is understood that this application is based on WR technology, utilizing GPS / reference clock sources, WR switches, WR nodes, fiber optic links, and data acquisition boards to achieve multi-site data synchronous acquisition and data fusion by sending synchronous acquisition commands to each site. The GPS / reference clock source includes BeiDou GPS, a high-stability atomic clock or a high-stability quartz crystal oscillator, and outputs a high-stability clock signal, time code, and two clock signals (10MHz signal and PPS signal), which are transmitted to the WR switch via fiber optic cable as the main time and frequency reference for the entire system.

[0051] In some embodiments, the WR switch synchronizes with the upper-level clock as a slave clock and with the lower-level clock as a master clock to complete cross-domain clock synchronization; wherein, the clock synchronization process based on the WR switch includes: frequency synchronization and time synchronization representing absolute time information.

[0052] In the embodiments of this application, it can be understood that the WR switch is based on a regular switch with added WR function support, and provides features such as QoS support, link redundancy, and fast switching to meet the high real-time requirements of the clock and control system. The WR switch has multiple SFP fiber ports, which can be arbitrarily configured as uplink or downlink ports, and synchronizes with lower-level WR slave nodes or switches via fiber optic links.

[0053] In some embodiments, the 10MHz signal and PPS signal output by each WR node have the same frequency and fixed phase as the 10MHz signal and PPS signal input by the WR switch, respectively.

[0054] In this embodiment, it is understood that the WR node has two SFP fiber ports, which can receive data from the upstream WR switch, perform phase-locked loop (PLL) on the received clock, and communicate with other WR nodes via the SFP for frequency and time synchronization. The WR node outputs two clock signals: 10MHz and PPS. The 10MHz and PPS signals between multiple WR nodes have the same frequency and phase correlation as the system's 10MHz and PPS signals, and are time-synchronized.

[0055] In some embodiments, the number of data acquisition boards is the same as the number of WR nodes. The data acquisition boards include a clock power divider circuit, an FPGA, a clock generation chip circuit, an ADC, and a data interface circuit.

[0056] The clock power divider circuit is used to distribute the input clock and generate multiple clocks. The output clock of the clock power divider circuit is the same as the input signal in frequency and phase, and has low delay and low clock jitter characteristics.

[0057] The clock generation chip circuit is used to generate the ADC sampling clock and the system reference clock. The system reference clock serves as the reference clock for both the ADC and the FPGA to achieve synchronization between ADC data acquisition and FPGA reception. The clock generation chip circuit can be configured with the operating mode and output frequency through a configuration interface to achieve multiple sampling clocks and operating modes.

[0058] The ADC uses a wideband analog-to-digital converter based on the JESD204B protocol to directly sample the input high-frequency signal;

[0059] The FPGA is the main control chip of the data acquisition board. It is programmed to realize the system data acquisition and reception control, configure the ADC and clock generation chip circuits, and realize command reception, synchronization and data packet output.

[0060] In this embodiment, it is understood that the data acquisition board includes an ADC, an FPGA, a clock distribution chip, a 100MHz high-stability crystal oscillator, a clock generation circuit, a power supply circuit, and an SFP fiber optic interface. The power supply circuit generates multiple voltages, which are connected to various devices and circuits on the data acquisition board. The clock distribution circuit distributes the input 10MHz signal, generating two 10MHz signals, one connected to the FPGA and the other to the clock generation chip. The clock generation chip includes a two-stage phase-locked loop (PLL). The 100MHz high-stability crystal oscillator is connected to the clock input of the clock generation chip. The first-stage PLL of the clock generation chip performs phase-locking on the input 10MHz signal and the 100MHz high-stability clock. The second-stage PLL generates a 2.4GHz clock from the 100MHz signal through frequency multiplication and phase-locking. Then, a frequency divider circuit generates multiple ADC sampling clocks and a system reference clock. The ADC sampling clocks are connected to the sampling clock pins of the ADC chip, and the system reference clock is connected to the FPGA and the ADC. The data output of the ADC is connected to the FPGA. The acquired data is sent to the FPGA for data decoding via the JESD204B interface protocol. After the FPGA processes the ADC signal, it receives the synchronous acquisition command from the remote computer through the SFP fiber optic interface. The data from multiple data acquisition boards are sent to the remote host computer, which performs data fusion processing. This enables the fusion processing of the same target signal from multiple stations.

[0061] In one example, the aforementioned data acquisition board receives external control commands through a data interface, initiates data acquisition, fuses data from multiple data acquisition boards, and outputs the data through the data interface. Specifically, S150 may include the following steps:

[0062] S210. Send the system reference clock to the FPGA as a reference, and use the PPS signal as a time reference;

[0063] S220. Upon receiving the acquisition control command, when the next pulse of the PPS signal arrives, the acquisition of multiple data acquisition boards is initiated to ensure that multiple data acquisition boards acquire data at the same time.

[0064] In one example, the data interface achieves a communication rate greater than 10Gb / s via optical fiber. Data collected based on the data interface is transmitted to the system's host computer via optical fiber based on a communication protocol to achieve data reception and processing.

[0065] The WR nodes and data acquisition boards are located at different sites, with some sites being more than 10km apart. Multiple sites can synchronously acquire and receive the same target signal and perform multi-site data fusion processing.

[0066] In some embodiments, this application provides a distributed multi-site data synchronization and acquisition system 300 based on White Rabbit technology, such as... Figure 2 As shown, the distributed multi-site data synchronization and acquisition system 300 based on White Rabbit technology may include the following modules:

[0067] The acquisition module 310 is used to acquire GPS / reference clock sources, WR switches, multiple WR nodes, fiber optic lines, and multiple data acquisition boards;

[0068] The data interaction module 320 is used to perform data interaction between the WR switch and the WR node through optical fiber based on the White Rabbit WR technology, so that the WR node outputs two coherent 10MHz signals and PPS signals.

[0069] The first input module 330 is used to send the PPS signal output by the WR node into the data acquisition board as a reference clock, and to send the 10MHz signal output by the WR node into the clock power divider circuit of the data acquisition board to separate the first target signal and the second target signal.

[0070] The second input module 340 is used to input the first target signal into the FPGA on the data acquisition board as the system running clock, and to input the second target signal into the clock generation chip circuit to generate an ADC sampling clock and a system reference clock with the same frequency and phase.

[0071] The acquisition module 350 is used to receive external control commands through a data interface based on a data acquisition board, start data acquisition, fuse data from multiple data acquisition boards, and output the data through the data interface.

[0072] According to embodiments of this application, any and multiple modules among the acquisition module 310, data interaction module 320, first input module 330, second input module 340, and acquisition module 350 can be combined into one module, or any one of these modules can be split into multiple modules. Alternatively, at least some of the functions of one or more of these modules can be combined with at least some of the functions of other modules and implemented in one module.

[0073] Figure 2 Each module in the system shown has the function of implementing each step in the aforementioned distributed multi-site data synchronization acquisition method based on White Rabbit technology, and can achieve its corresponding technical effect. For the sake of brevity, it will not be elaborated here.

[0074] It should also be noted that, please refer to Figure 3 There are n WR nodes and n data acquisition boards. This invention comprises two parts: system clock generation and distribution, and data acquisition.

[0075] Clock generation and distribution are primarily based on the White Rabbit technology. The White Rabbit switch distributes the 10MHz, PPS, and timecode from the GPS / reference clock source to multiple White Rabbit nodes, each corresponding to a data acquisition board. Because the White Rabbit technology can distribute time and frequency across multiple sites, each site's data acquisition board can obtain a 10MHz frequency and PPS signal for time synchronization, serving as the basic clock for the acquisition board.

[0076] This method technically ensures that multiple distributed sites can achieve synchronous data collection and fusion. This invention employs WR technology, leveraging mature commercial COTS components, enabling very convenient and rapid implementation of WR-based applications or modifications.

[0077] For example, WR nodes can be implemented in several ways: carrier board mode, daughterboard mode, and IP core mode, which can be selected according to specific needs. Both WR switches and WR nodes are based on WR technology and are connected to each other via fiber optic links. Through data exchange, time and frequency synchronization between WR switches and WR nodes is achieved.

[0078] The working process of this invention system is as follows: After receiving the reference clock (10MHz, PPS, and timecode) signal, the WR switch sends information to the WR node through optical fiber, synchronizing the local clock of the WR node with the clock frequency of the WR switch. The two clock signals (10MHz and PPS) output by the WR node are then fed into the data acquisition board. Figure 4 As shown, the data acquisition board divides the 10MHz signal into two clock signals: one goes to the FPGA, and the other goes to the clock generation chip circuit. These two signals are then phase-locked with the on-board 100MHz clock. On-chip frequency multiplication, phase-locking, and frequency division are performed to generate the sampling clock and system reference clock required by the ADC. The ADC converts the input RF signal using the sampling clock and sends it to the FPGA. Since both the ADC sampling clock and the system reference clock are coherent with the input 10MHz signal, the sampling clock and reference clock of each station are also coherent signals. The synchronous acquisition command, under the action of the PPS, outputs data through the fiber optic interface, enabling synchronous acquisition of the same RF signal from multiple stations, data synthesis, and distributed multi-site data acquisition and fusion.

[0079] The following is combined Figures 5-8 The invention will be further described below. For example... Figure 5 As shown, the 10MHz signal from the WR node, after being connected to XS1, is coupled to the CLK0 pin of the clock power divider chip D10 through capacitor C424. After passing through D10, it is split into two 10MHz differential signals with the same frequency and phase: CLK10M_A_P / N and CLK10M_B_P / N. Capacitors C348-C356, C639-C640, C662-C667, and C674-C675 provide filtering and decoupling for the power supply.

[0080] like Figure 6 As shown, one 10MHz clock from the D10 power divider enters the REF_A port. The REF_SEL port is a selection port, allowing selection of whether the input reference clock for the clock generation circuit is REF_A or REF_B. The VCXO_IN port receives a 100MHz high-stability clock. The 10MHz signal from REF_A is phase-locked with the 100MHz high-stability clock through PLL1, then fed into PLL2 for frequency multiplication and phase locking, outputting a 2.4GHz clock. After passing through two stages of phase-locked loops, it is divided, delayed, and driven by the clock distribution module before being output. The clock generation chip circuit has multiple outputs, generating signals including the ADC sampling clock CLK_P / N and the reference clock SYSREF_P / N. The SYSREF_REQ signal is used to synchronize the multiple output signals of the clock generation chip circuit. The PPS signal from the WR node enters the FPGA, is synchronized with the synchronous acquisition command, and then output, enabling synchronous acquisition by data acquisition boards at multiple sites.

[0081] like Figure 7 As shown, one RF signal enters XS1, is coupled through capacitor C17, and then sent to balun T5. This converts the analog single-ended signal into a differential signal, which is then filtered by a filter consisting of capacitors C18, C19, C20, and resistors R41, R42, R43, R44, R45, and R46. After filtering, the signal is sent to the analog differential inputs pins 5 and 6 of D3, where it undergoes analog-to-digital conversion under the influence of the sampling clock CLK_P / N. The ADC's SYSREF_P / N pin is used for data reference synchronization with the FPGA.

[0082] Figure 6 The reference clock SYSREF generated by the clock generation chip is sent to the FPGA and ADC. This reference clock is used to synchronize the multiple AD data streams sent by the ADC before they are processed by the FPGA. The FPGA configures its operating mode through the ADC chip's SPI interface (SDIO, SCLK, CSB). Another RF signal passes through XS2, undergoes a single-ended to differential conversion, and then enters the ADC for sampling. The sampling process is the same as described above.

[0083] Two RF signals from the same acquisition board are acquired via an ADC. Since the sampling clock and the reference clock SYSREF are the same, the two acquired digital signals are identical in time and phase for the same ADC. For different acquisition boards at multiple sites, their acquisition clocks and reference signal frequencies and phases are also the same. Therefore, the digital signals from multiple acquisition boards can be combined to achieve beamforming of digital signals.

[0084] like Figure 8 As shown, D11 is a fiber optic transceiver module. One end, the GTX_T / R port, connects to the FPGA's GTX high-speed port, while the other end, via fiber optic cable, connects to a remote host computer. This transceiver module employs multi-channel transmission and reception, operating in single-mode to meet longer transmission distance requirements. The FPGA receives synchronous acquisition control commands through the fiber optic module. Correlated with the PPS pulse, it controls the ADC's sampling time, obtaining multiple AD data streams. After internal data processing within the FPGA, the data is transmitted through the fiber optic transceiver module. Data from multiple sites is transmitted via fiber optic cable to the remote host computer for data fusion processing, achieving distributed site data acquisition and processing.

[0085] In some embodiments, this application provides an electronic device, the structural schematic of which is shown below. Figure 9 As shown.

[0086] The electronic device may include a processor 410 and a memory 420 storing computer program instructions.

[0087] Specifically, the processor 410 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0088] Memory 420 may include mass storage for data or instructions. For example, and not limitingly, memory 420 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 420 may include removable or non-removable (or fixed) media. Where appropriate, memory 420 may be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, memory 420 is non-volatile solid-state memory.

[0089] Memory 420 may include read-only memory (ROM), random access memory (RAM), disk storage media device, optical storage media device, flash memory device, electrical, optical, or other physical / tangible memory storage device. Therefore, typically, memory 420 includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it can perform the operations described in any of the distributed multi-site data synchronization acquisition methods based on White Rabbit technology in the above embodiments.

[0090] The processor 410 reads and executes computer program instructions stored in the memory 420 to implement any of the distributed multi-site data synchronization acquisition methods based on the White Rabbit technology in the above embodiments.

[0091] In one example, the electronic device may also include a communication interface 430 and a bus 400. For example, Figure 9 As shown, the processor 410, memory 420, and communication interface 430 are connected via bus 400 and communicate with each other.

[0092] The communication interface 430 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0093] Bus 400 includes hardware, software, or both, that couples components of an online data traffic metering device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 400 may include one or more buses. Although specific buses are described and illustrated in embodiments of this application, any suitable bus or interconnect is contemplated herein.

[0094] Furthermore, in conjunction with the distributed multi-site data synchronization acquisition method based on White Rabbit technology in the above embodiments, this application embodiment can provide a computer storage medium for implementation. This computer storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement any of the distributed multi-site data synchronization acquisition methods based on White Rabbit technology in the above embodiments.

[0095] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0096] The functional blocks shown in the above block diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0097] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0098] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0099] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A distributed multi-site data synchronization acquisition method based on white rabbit technology, characterized in that, include: Acquire a reference clock source, WR switch, multiple WR nodes, fiber optic lines, and multiple data acquisition boards; Based on the White Rabbit WR technology, data interaction is performed between the WR switch and the WR node via optical fiber, so that the WR node outputs two coherent 10MHz signals and PPS signals. The PPS signal output by the WR node is sent to the data acquisition board as a reference clock, and the 10MHz signal output by the WR node is sent to the clock power divider circuit of the data acquisition board to separate the first target signal and the second target signal. The first target signal is sent to the FPGA on the data acquisition board as the system operating clock, and the second target signal is sent to the clock generation chip circuit to generate an ADC sampling clock and a system reference clock with the same frequency and phase. Based on the data acquisition board, external control commands are received through the data interface to start data acquisition, and data from multiple data acquisition boards are fused and processed and output through the data interface.

2. The distributed multi-site data synchronization acquisition method based on White Rabbit technology as described in claim 1, characterized in that, The reference clock source is used to provide UTC timecode and two clock signals: the two clock signals include a 10MHz signal and a PPS signal; The WR switch adopts high-precision distributed time synchronization technology based on fiber optic Ethernet technology, and can perform sub-nanosecond time synchronization between tens of thousands of nodes in a spatial distance of less than 10km, so as to be applied to long-distance multi-node high-precision time synchronization occasions.

3. The distributed multi-site data synchronization acquisition method based on White Rabbit technology as described in claim 1, characterized in that, The WR switch synchronizes with the upper-level clock as a slave clock and with the lower-level clock as a master clock to complete cross-domain clock synchronization. The clock synchronization process based on the WR switch includes frequency synchronization and time synchronization, which represents absolute time information.

4. The distributed multi-site data synchronization acquisition method based on White Rabbit technology as described in claim 1, characterized in that, The 10MHz signal and PPS signal output by each WR node have the same frequency and fixed phase as the 10MHz signal and PPS signal input by the WR switch, respectively. The number of data acquisition boards is the same as the number of WR nodes. The data acquisition boards include a clock power divider circuit, an FPGA, a clock generation chip circuit, an ADC, and a data interface circuit.

5. The distributed multi-site data synchronization acquisition method based on White Rabbit technology as described in claim 4, characterized in that, The clock power divider circuit is used to distribute the input clock and generate multiple clocks. The output clock of the clock power divider circuit is the same as the input signal in frequency and phase, and has low latency and low clock jitter characteristics. The clock generation chip circuit is used to generate the ADC sampling clock and the system reference clock. The system reference clock serves as the reference clock for the ADC and the FPGA to achieve synchronization of ADC data acquisition and FPGA reception. The clock generation chip circuit can be configured with its operating mode and output frequency through a configuration interface to achieve multiple sampling clocks and operating modes. The ADC uses a wideband analog-to-digital converter based on the JESD204B protocol to directly sample the input high-frequency signal. The FPGA is the main control chip of the data acquisition board. It is programmed to realize the system data acquisition and reception control, configure the ADC and the clock generation chip circuit, and realize command reception, synchronization and data packet output.

6. The distributed multi-site data synchronization acquisition method based on White Rabbit technology as described in claim 1, characterized in that, The process, based on the data acquisition board, receives external control commands through a data interface, initiates data acquisition, fuses data from multiple data acquisition boards, and outputs the data through the data interface, including: The system reference clock is fed into the FPGA as a reference, and the PPS signal is used as a time reference. Upon receiving the acquisition control command, when the next pulse of the PPS signal arrives, the acquisition of multiple data acquisition boards is initiated to ensure that the multiple data acquisition boards acquire data at the same time.

7. The distributed multi-site data synchronization acquisition method based on White Rabbit technology as described in claim 1, characterized in that, The data interface achieves a communication rate greater than 10Gb / s through optical fiber. Data collected based on the data interface is transmitted to the system host computer through optical fiber based on the communication protocol to realize data reception and processing. The WR node and the data acquisition board are located at different sites, and some of the sites are more than 10km apart. Multiple sites can synchronously acquire and receive the same target signal and perform multi-site data fusion processing.

8. A distributed multi-site data synchronization and acquisition system based on White Rabbit technology, characterized in that, include: The acquisition module is used to acquire the reference clock source, WR switch, multiple WR nodes, fiber optic lines, and multiple data acquisition boards; The data interaction module is used to perform data interaction between the WR switch and the WR node through optical fiber based on the White Rabbit WR technology, so that the WR node outputs two coherent 10MHz signals and PPS signals; The first input module is used to input the PPS signal output by the WR node into the data acquisition board as a reference clock, and to input the 10MHz signal output by the WR node into the clock power divider circuit of the data acquisition board to separate the first target signal and the second target signal. The second input module is used to input the first target signal into the FPGA on the data acquisition board as the system operating clock, and to input the second target signal into the clock generation chip circuit to generate an ADC sampling clock and a system reference clock with the same frequency and phase coherence. The acquisition module is used to receive external control commands through a data interface based on the data acquisition board, start data acquisition, perform data fusion processing on data from multiple data acquisition boards, and output the data through the data interface.

9. An electronic device, characterized in that, include: A processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the distributed multi-site data synchronization acquisition method based on the White Rabbit technology as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a program or instructions that, when executed by a processor, implement the distributed multi-site data synchronization acquisition method based on the White Rabbit technology as described in any one of claims 1 to 7.

Images