Cross switches, on-chip systems and their access control methods, chips

Abstract

A crossbar switch, a system-on-a-chip, and an access control method and chip thereof are disclosed. The crossbar switch includes M input ports, N output ports, and K multiplexers, where M and K are natural numbers greater than or equal to 1, and N is a natural number greater than 1 and greater than M. At least one of the multiplexers includes one input terminal and n output terminals, where n is a natural number greater than 1 and less than or equal to N. The input terminal of at least one multiplexer is connected to one of the input ports, and the n output terminals of at least one multiplexer are connected one-to-one with the n output ports.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of integrated circuit technology, and particularly to a cross switch, a system-on-a-chip and its access control method, and a chip. Background Technology

[0002] With the development of Artificial Intelligence (AI) technology, the scale and complexity of AI systems are constantly increasing, and the requirements for data transmission bandwidth and performance are also becoming more demanding. As the network interconnection path in the system, the crossbar switch is also becoming increasingly complex. Traditional crossbar switches typically employ a fully connected interconnect architecture. While this architecture allows parallel access between multiple input and output ports, its complexity increases quadratically with the number of ports, leading to problems such as increased chip area, higher power consumption, and increased transmission latency. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a crossbar switch, including: M input ports, N output ports and K multiplexers, where M and K are both natural numbers greater than or equal to 1, and N is a natural number greater than 1 and N is greater than M; At least one of the multiplexers includes one input terminal and n output terminals, where n is a natural number greater than 1 and less than or equal to N. The input terminal of the at least one multiplexer is connected to one of the input ports, and the n output terminals of the at least one multiplexer are connected to the n output ports in a one-to-one correspondence.

[0005] For example, K=M, and the M input terminals of the multiplexer are connected one-to-one with the M input ports.

[0006] For example, N = M + n - 1, and the n output terminals of the i-th multiplexer are connected one-to-one with the i-th to the (i+n-1)-th output ports, where i is a natural number between 0 and M-1.

[0007] For example, each of the N output ports is connected to one of the N first structures. ,in, The yield rate of the first structure connected to the output port.

[0008] For example, at least one of the multiplexers includes a control terminal, and at least one of the multiplexers is configured to connect the input terminal to one of the n output terminals according to control information received by the control terminal.

[0009] This disclosure also provides a system-on-a-chip, including a cross switch as described in any embodiment of this disclosure, and further including N first structures, wherein the N output ports are connected one-to-one with the N first structures.

[0010] For example, at least one of the first structures includes a storage controller and a storage block connected to the storage controller, and N output ports are connected one-to-one with the N storage controllers.

[0011] For example, at least one of the storage blocks includes X storage cells, which are continuously addressed from the address of the j-th storage cell connected to the first input port to the address of the j-th storage cell connected to the M-th input port, where j is a natural number between 0 and X-1, and X is a natural number greater than 1.

[0012] For example, K=M, at least one of the multiplexers includes a control terminal, and the i-th multiplexer is configured to connect the input terminal to one of the n output terminals according to control information received by the control terminal, so that the i-th input port is connected to the i-th yield-compliant first structure through the i-th multiplexer, where i is a natural number between 0 and M-1.

[0013] For example, the system-on-chip further includes a control unit connected to the control terminals of the K multiplexers. The control unit is configured to send control information to the control terminals of the K multiplexers according to a pre-configured two-dimensional relationship correspondence table. The two-dimensional relationship correspondence table is generated based on the yield of N first structures and is used to indicate the corresponding connection relationship between the input terminals of the K multiplexers and their respective n output terminals.

[0014] For example, the two-dimensional relationship correspondence table is stored in the format of a binary matrix or a one-dimensional array.

[0015] This disclosure also provides a chip including a system-on-a-chip as described in any embodiment of this disclosure.

[0016] This disclosure also provides an access control method for a system-on-a-chip based on any embodiment of this disclosure, including: The computing unit sends read or write requests to multiple storage controllers simultaneously via the crossbar switch, and the read or write requests carry the destination address information of the target storage block. Multiple storage controllers simultaneously perform read or write operations on the destination addresses of multiple target storage blocks based on the destination address information of the target storage blocks carried in the read or write requests.

[0017] The crossbar switch, system-on-a-chip and its access control method and chip provided in this disclosure, by setting M input ports, N output ports and K multiplexers, where M and K are natural numbers greater than or equal to 1, and N is a natural number greater than 1 and greater than M; at least one of the multiplexers includes one input terminal and n output terminals, where n is a natural number greater than 1 and less than or equal to N, the input terminal of at least one multiplexer is connected to one of the input ports, and the n output terminals of at least one multiplexer are connected one-to-one with the n output ports, greatly reducing the complexity of the crossbar switch, thereby reducing the chip area, reducing chip power consumption, reducing transmission delay, and increasing feasibility.

[0018] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0019] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0020] Figure 1 This is a schematic diagram of the structure of a first type of cross switch, as an exemplary embodiment of the present disclosure; Figure 2 This is a schematic diagram of the structure of a second type of cross switch, as an exemplary embodiment of this disclosure; Figure 3 This is a schematic diagram of the structure of a third type of cross switch, as an exemplary embodiment of this disclosure; Figure 4 This is a schematic diagram of the structure of a system-on-a-chip, which is an exemplary embodiment of the present disclosure. Figure 5 This is a schematic diagram illustrating the principle of addressing storage units in multiple storage blocks in related technologies. Figure 6 This is a schematic diagram illustrating the principle of addressing storage cells in multiple storage blocks according to an embodiment of the present disclosure; Figure 7 This is a schematic diagram of the structure of another on-chip system as an exemplary embodiment of the present disclosure; Figure 8 This is a flowchart illustrating an access control method for a system-on-a-chip, which is an exemplary embodiment of this disclosure. Detailed Implementation

[0021] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments and features described herein can be combined arbitrarily.

[0022] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" indicate that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, but do not exclude other elements or objects.

[0023] like Figure 1 As shown, this embodiment of the present disclosure provides a crossbar switch, including: M input ports, N output ports and K demuxes, where M and K are both natural numbers greater than or equal to 1, and N is a natural number greater than 1 and N is greater than M; At least one multiplexer includes one input terminal and n output terminals, where n is a natural number greater than 1 and less than or equal to N. The input terminal of the at least one multiplexer is connected to one input port, and the n output terminals of the at least one multiplexer are connected to n output ports in a one-to-one correspondence.

[0024] The cross switch of this disclosure embodiment, by setting M input ports, N output ports and K multiplexers, where M and K are natural numbers greater than or equal to 1, and N is a natural number greater than 1 and greater than M; at least one multiplexer includes one input terminal and n output terminals, where n is a natural number greater than 1 and less than or equal to N, one input terminal of at least one multiplexer is connected to a corresponding input port, and the n output terminals of at least one multiplexer are connected one-to-one with the n output ports, greatly reduces the complexity of the cross switch, thereby reducing chip area, reducing chip power consumption and reducing transmission delay, and increasing feasibility.

[0025] In some exemplary implementations, K=M, the inputs of the M multiplexers are connected one-to-one with the M input ports (i.e., the input of one multiplexer is connected to one input port), and the n outputs of each multiplexer are connected one-to-one with the n output ports.

[0026] like Figure 2 As shown, the cross switch of this disclosure includes: M input ports, N output ports and M multiplexers, 1≤M<N. Each multiplexer includes one input terminal and n output terminals, 1<n≤N. The input terminal of each multiplexer is connected to one input port, and the n output terminals of each multiplexer are connected to the n output ports in a one-to-one correspondence.

[0027] In some exemplary implementations, N = M + n - 1, and the n outputs of the i-th multiplexer are connected one-to-one with the i-th to the (i+n-1)-th output ports, where i is a natural number between 0 and M-1.

[0028] For example, Figure 3 The example described uses N=40, M=K=32, and n=9. However, this disclosure does not impose any restrictions on these values. The number of output ports N, the number of input ports M, the number of multiplexers K, and the number of output ports n of each multiplexer can all be set according to actual needs.

[0029] like Figure 3 As shown, the input terminals of the 0th to 31st multiplexers are connected one-to-one with the 0th to 31st input terminals. The 9 output terminals of the 0th multiplexer are connected one-to-one with the 0th to 8th output ports. The 9 output terminals of the 1st multiplexer are connected one-to-one with the 1st to 9th output ports. ... The 9 output terminals of the i-th multiplexer are connected one-to-one with the i-th to i+8th output ports. ... The 9 output terminals of the 30th multiplexer are connected one-to-one with the 30th to 38th output ports. The 9 output terminals of the 31st multiplexer are connected one-to-one with the 31st to 39th output ports.

[0030] In some exemplary embodiments, N output ports are connected one-to-one with N first structures. ,in, The yield rate of the first structure connected to the output port.

[0031] For example, assume the yield of the first structure If the percentage is 80%, and the total number of first structures is 40, meaning the total number of output ports N is 40, then the number of output ports included in each multiplexer is... The total number of input ports is M = N - n + 1 = 40 - 9 + 1 = 32.

[0032] In some exemplary implementations, such as Figure 4 As shown, the first structure may include a DRAM controller and a DRAM bank. However, this disclosure is not limiting in this regard. In the embodiments of this disclosure, the first structure may be configured according to the actual application scenario of the crossbar switch.

[0033] In AI systems, high-bandwidth memory access to DRAM is required; however, many current DRAM banks cannot meet the corresponding bandwidth demands. One solution is to use multiple DRAM banks in parallel, meaning multiple DRAM banks operate simultaneously to supply the system's high-bandwidth read / write requirements. Considering DRAM product yield issues, not all DRAM banks will function correctly after tape-out; therefore, redundancy is necessary. For example, assuming 32 DRAM banks are needed, considering yield (assuming a DRAM bank yield of at least 80%), we need to deploy 40 DRAM banks to ensure at least 40 * 80% = 32 functional DRAM banks are available. After tape-out, the 32 functional DRAM banks are selected from the 40 for use. This deployment method requires a crossbar switch to convert between 32 input ports and 40 output ports. If routing exists between each input port and each output port, the complexity of the crossbar switch becomes extremely high.

[0034] Considering that this disclosure uses multiple DRAM banks in parallel, it is only necessary to ensure that the crossbar switch can simultaneously read data from 32 normally functioning DRAM banks. That is, it is only necessary to ensure that each input port of the crossbar switch is connected to at least one normally functioning DRAM bank. Since at least 32 out of 40 DRAM banks are normally functioning, meaning at least one out of every nine DRAM banks is normally functioning, each input port only needs to have a route between it and nine DRAM banks to guarantee that each input port is connected to at least one normally functioning DRAM bank. Figure 4 As shown.

[0035] In some exemplary embodiments, at least one multiplexer includes a control terminal, and the at least one multiplexer is configured to connect an input terminal to one of n output terminals based on control information received from the control terminal.

[0036] In this embodiment of the disclosure, the specific configuration of which output terminal among the n output terminals the input terminal of each multiplexer is connected to can be determined based on whether the yield of the first structure connected to each output terminal meets the standard, as detected beforehand. For example, taking the first structure as including a DRAM controller and a DRAM bank as an example, the 0th to the 39th DRAM banks are sequentially tested to see if they can work normally. Based on the test results, the input terminal of the i-th multiplexer is connected to the output terminal connected to the i-th normally working DRAM bank. For example, if the 0th DRAM bank is functioning correctly (i.e., the 0th functioning DRAM bank is the 0th DRAM bank), then the input of the 0th multiplexer is connected to the output of the 0th output port; if the 1st DRAM bank is not functioning correctly but the 2nd DRAM bank is functioning correctly (i.e., the 1st functioning DRAM bank is the 2nd DRAM bank), then the input of the 1st multiplexer is connected to the output of the 2nd output port; if the 3rd and 4th DRAM banks are not functioning correctly but the 5th DRAM bank is functioning correctly (i.e., the 2nd functioning DRAM bank is the 5th DRAM bank), then the input of the 2nd multiplexer is connected to the output of the 5th output port; ...; until the input of the 31st multiplexer finds a corresponding connected output.

[0037] In this embodiment of the disclosure, the control information received by the control terminal of the multiplexer can be sent by the control unit. For example, the control unit can be a chip core; however, this disclosure does not limit this.

[0038] In this embodiment of the disclosure, the input terminal of each multiplexer is connected to one input port through hardware configuration, and the n output terminals of each multiplexer are connected to the n output ports one-to-one, so that there is a physical route between one input port and the n output ports. Then, the input terminal of each multiplexer is connected to one of the n output terminals through software configuration, so that each input port is connected to a first structure that can work normally.

[0039] In this embodiment of the disclosure, the control unit can be connected to the control terminals of K multiplexers. The control unit is configured to send control information to the control terminals of the K multiplexers according to a pre-configured two-dimensional relationship correspondence table. The two-dimensional relationship correspondence table is generated based on the yield of N first structures and is used to indicate the corresponding connection relationship between the input terminals of the K multiplexers and their respective n output terminals.

[0040] In this embodiment of the disclosure, N first structures can be numbered in advance, so that the number of the first structure that can work normally can be obtained according to the yield test, and then a two-dimensional relationship correspondence table can be generated according to the number of the first structure that can work normally.

[0041] An exemplary two-dimensional relationship correspondence table is shown in Table 1. In Table 1, the horizontal axis represents the number of 40 output ports or the number of 40 first structures, and the vertical axis represents the number of 32 input ports or the number of 32 multiplexers. This two-dimensional relationship correspondence table can be simplified into a 40*32-bit binary matrix.

[0042] Furthermore, as shown in Table 1, since the input of the i-th multiplexer is only connected to the output of the i-th working DRAM bank, meaning that one input port is only connected to one corresponding output port, for each input port, the connected output port must be one of the output ports between the 0th and 39th output ports. That is, the output port corresponding to each input port can be represented by a single byte of value. Therefore, this two-dimensional correspondence table can also be represented by an 8*32-bit array configured in software. For example, the two-dimensional correspondence table corresponding to Table 1 can be represented as [0, 2, 3, 4, 5, 6, 7, 9, 10, 11, ..., 35, 36]. The array contains 32 elements, and each array element can be represented as an 8-bit binary number. Table 1 In some exemplary embodiments, at least one storage block includes X storage cells, with the address of the j-th storage cell connected to the first input port to the address of the j-th storage cell connected to the M-th input port being consecutively addressed, where j is a natural number between 0 and X-1, and X is a natural number greater than 1.

[0043] like Figure 5 As shown, when addressing the memory cells of multiple DRAM banks, the related technologies address the memory cells of each DRAM bank consecutively. For example, assuming that each DRAM bank includes X memory cells, the address of the memory cell of the 0th working DRAM bank (i.e., DRAM bank0) is 0 to X-1, the address of the memory cell of the 1st working DRAM bank (i.e., DRAM bank2) is X to 2X-1, ..., and the address of the memory cell of the 31st working DRAM bank (i.e., DRAM bank36) is 30X to 31X-1.

[0044] like Figure 6As shown, this embodiment of the present disclosure addresses high-bandwidth memory access by interleaving the addressing of memory cells in multiple DRAM banks. For example, using the two-dimensional correspondence table shown in Table 1, assuming each DRAM bank includes X memory cells, the addresses of the memory cells in the 0th working DRAM bank (DRAM bank0) are 0, 32, 64, ..., 30X; the addresses of the memory cells in the 1st working DRAM bank (DRAM bank2) are 1, 33, 65, ..., 30X+1, ...; and the addresses of the memory cells in the 31st working DRAM bank (DRAM bank36) are 31, 63, 95, ..., 31X-1. Thus, when performing read / write operations on multiple consecutive memory cells, data from multiple memory cells can be read and written simultaneously in a single operation, thereby achieving high-bandwidth DRAM read / write operations.

[0045] The cross switch structure design of this disclosure embodiment greatly reduces the connection complexity between the input port and the DRAM bank, thereby reducing the chip area, chip power consumption, and transmission latency, and greatly enhancing feasibility.

[0046] like Figure 7 As shown in the embodiments of this disclosure, a system-on-a-chip is also provided, including: a cross switch as described in any embodiment of this disclosure, and further including N first structures, with N output ports connected one-to-one with the N first structures.

[0047] In some exemplary implementations, such as Figure 7 As shown, at least one first structure includes a storage controller and a storage block connected to the storage controller, and N output ports are connected one-to-one with the N storage controllers.

[0048] However, this disclosure does not limit this, and the first structure can be configured according to the actual application scenario of the cross switch.

[0049] In some exemplary embodiments, at least one storage block includes X storage cells, with the address of the j-th storage cell connected to the first input port to the address of the j-th storage cell connected to the M-th input port being consecutively addressed, where j is a natural number between 0 and X-1, and X is a natural number greater than 1.

[0050] like Figure 6As shown, this embodiment of the present disclosure addresses high-bandwidth memory access by interleaving the addressing of storage cells in multiple storage blocks. For example, taking the two-dimensional correspondence table shown in Table 1 as an example, assuming each storage block includes X storage cells, the addresses of the storage cells in the 0th working storage block (i.e., storage block 0) are 0, 32, 64, ..., 30X; the addresses of the storage cells in the 1st working storage block (i.e., storage block 2) are 1, 33, 65, ..., 30X+1, ...; and the addresses of the storage cells in the 31st working storage block (i.e., storage block 36) are 31, 63, 95, ..., 31X-1. Thus, when performing read / write operations on multiple consecutively addressed storage cells, data in multiple storage cells can be read and written simultaneously in a single read / write operation.

[0051] In some exemplary embodiments, K=M, at least one multiplexer includes a control terminal, and the i-th multiplexer is configured to connect an input terminal to one of n output terminals according to control information received from the control terminal, such that the i-th input port is connected to the i-th first structure with acceptable yield through the i-th multiplexer, where i is a natural number between 0 and M-1.

[0052] In this embodiment of the disclosure, the specific configuration of which output terminal among the n output terminals the input terminal of each multiplexer is connected to can be determined based on whether the yield of the first structure connected to each output terminal meets the standard, as detected beforehand. For example, taking the first structure as including a DRAM controller and a DRAM bank as an example, the 0th to the 39th DRAM banks are sequentially tested to see if they can work normally. Based on the test results, the input terminal of the i-th multiplexer is connected to the output terminal connected to the i-th normally working DRAM bank. For example, taking the two-dimensional relationship correspondence table shown in Table 1 as an example, if the 0th DRAM bank is working properly, that is, the 0th working DRAM bank is the 0th DRAM bank, then connect the input terminal of the 0th multiplexer to the output terminal connected to the 0th output port; if the 1st DRAM bank is not working properly but the 2nd DRAM bank is working properly, that is, the 1st working DRAM bank is the 2nd DRAM bank, then connect the input terminal of the 1st multiplexer to the output terminal connected to the 2nd output port; if the 3rd and 4th DRAM banks are not working properly but the 5th DRAM bank is working properly, that is, the 2nd working DRAM bank is the 5th DRAM bank, then connect the input terminal of the 2nd multiplexer to the output terminal connected to the 5th output port; ...; until the input terminal of the 31st multiplexer finds the corresponding connected output terminal.

[0053] In some exemplary embodiments, the system-on-chip further includes a control unit connected to the control terminals of the K multiplexers. The control unit is configured to send control information to the control terminals of the K multiplexers according to a pre-configured two-dimensional relationship mapping table. The two-dimensional relationship mapping table is generated based on the yield of N first structures and is used to indicate the corresponding connection relationship between the input terminals of the K multiplexers and their respective n output terminals.

[0054] For example, the control unit may be a chip core; however, this disclosure is not limiting in this regard.

[0055] In some exemplary embodiments, the two-dimensional relational mapping table can be stored as a binary matrix or a one-dimensional array.

[0056] For example, the two-dimensional relationship correspondence table shown in Table 1 can be stored as a 40*32-bit binary matrix, or it can be stored as a one-dimensional array such as [0, 2, 3, 4, 5, 6, 7, 9, 10, 11, ..., 35, 36], with 32 elements in the array, and each array element can be represented by a binary number of one byte length.

[0057] This disclosure also provides a chip, including: a system-on-a-chip as described in any embodiment of this disclosure.

[0058] like Figure 8 As shown, this disclosure also provides an access control method for a system-on-a-chip based on any embodiment of this disclosure, including: Step 801: The computing unit sends read requests or write requests to multiple storage controllers simultaneously through a crossbar switch. The read request or write request carries the destination address information of the target storage block. Step 802: Multiple storage controllers simultaneously perform read or write operations on the destination addresses of multiple target storage blocks based on the destination address information of the target storage blocks carried in the read or write requests.

[0059] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0060] It should be noted that the above embodiments or implementation methods are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the content specifically shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the implementations without departing from the scope of this disclosure.

Claims

1. A cross switch, comprising: There are M input ports, N output ports, and K multiplexers, where M and K are natural numbers greater than or equal to 1, and N is a natural number greater than 1 and greater than M. At least one of the multiplexers includes one input terminal and n output terminals, where n is a natural number greater than 1 and less than N, and the input terminal of at least one of the multiplexers is connected to one of the input ports respectively; N = M + n - 1, where the n output terminals of the i-th multiplexer are connected one-to-one with the output ports from the i-th to the (i+n-1)-th output ports, and i is a natural number between 0 and M-1.

2. The cross switch according to claim 1, wherein, K=M, where the input terminals of the M multiplexers are connected one-to-one with the M input ports.

3. The cross switch according to claim 2, wherein, The N output ports are connected one-to-one with the N first structures. ,in, The yield rate of the first structure connected to the output port.

4. The cross switch according to claim 1, wherein, At least one of the multiplexers includes a control terminal, and at least one of the multiplexers is configured to connect the input terminal to one of the n output terminals based on control information received by the control terminal.

5. A system-on-a-chip, comprising: The cross switch as described in any one of claims 1 to 4 further includes N first structures, with each of the N output ports connected to one of the N first structures; at least one first structure includes a storage controller and a storage block connected to the storage controller, with each of the N output ports connected to one of the N storage controllers. At least one of the storage blocks includes X storage units, which are continuously addressed from the address of the j-th storage unit connected to the first input port to the address of the j-th storage unit connected to the M-th input port, where j is a natural number between 0 and X-1, and X is a natural number greater than 1.

6. The system-on-a-chip according to claim 5, wherein, K=M, at least one of the multiplexers includes a control terminal, and the i-th multiplexer is configured to connect the input terminal to one of the n output terminals according to the control information received by the control terminal, so that the i-th input port is connected to the i-th first structure with acceptable yield through the i-th multiplexer, where i is a natural number between 0 and M-1.

7. The system-on-a-chip according to claim 6 further includes a control unit connected to the control terminals of the K multiplexers, the control unit being configured to send control information to the control terminals of the K multiplexers according to a pre-configured two-dimensional relationship correspondence table, the two-dimensional relationship correspondence table being generated based on the yield of N first structures and used to indicate the corresponding connection relationship between the input terminals of the K multiplexers and their respective n output terminals.

8. The system-on-a-chip according to claim 7, wherein, The two-dimensional relationship correspondence table is stored in the format of a binary matrix or a one-dimensional array.

9. A chip, comprising: The system-on-a-chip as described in any one of claims 5 to 8.

10. An access control method for a system-on-a-chip based on any one of claims 5 to 8, comprising: The computing unit simultaneously sends read or write requests to multiple storage controllers through the crossbar switch. The read or write request carries the destination address information of the target storage block. The target storage block includes X storage units, and the addresses of the j-th storage unit connected to the first input port to the j-th storage unit connected to the M-th input port are consecutively addressed, where j is a natural number between 0 and X-1, and X is a natural number greater than 1. Multiple storage controllers simultaneously perform read or write operations on the destination addresses of multiple target storage blocks based on the destination address information of the target storage blocks carried in the read or write requests.

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