A remapping-based segmented LCD digital driver architecture

Abstract

The application relates to a segment type LCD digital driver structure based on remapping, which realizes segment type LCD digital driving with arbitrary adjustable common terminal number by the way of remapping pattern data output in a display buffer, and comprises a function register group, a display input register group and a remapping matrix. The function register group contains a remapping common terminal number parameter; the display input register group is used for buffering pattern display data; and the remapping matrix can map the actual value of the display input register group to a segment code terminal of the segment type LCD when a common terminal scanning level arrives. The digital driver structure of the application is simple, accurate in mapping, wide in adaptation range, arbitrary in common terminal number and suitable for the display digital driving of the segment type LCD.

Description

Technical Field

[0001] This invention relates to the field of segment LCD display driving technology, and in particular to a segment LCD digital driver structure based on remapping. Background Technology

[0002] Segment LCDs are widely used in specialized applications where stringent requirements exist, such as household digital water meters, flow meters, and other instruments, due to their advantages including low power consumption, low cost, high reliability, and good readability under strong light. Their display principle involves controlling the display or hiding of segments by applying different voltage combinations to specific segment gates (SEG) and the common gate (COM).

[0003] Currently, common segment LCD driver chips typically have a fixed number of common terminals (COM) (e.g., 4COM, 6COM, or 8COM). This fixed architecture results in insufficient flexibility: on the one hand, when driving LCD screens of different specifications and with different numbers of common terminals, different driver chips need to be selected, increasing system design and material costs; on the other hand, in the early stages of product design, the segment code requirements of the display screen may change, and driver chips with a fixed number of COM cannot adapt to such changes, leading to either wasted or insufficient chip pin resources. Furthermore, in highly integrated SoCs such as metering chips, chip pins are extremely valuable resources, and traditional fixed architectures cannot achieve dynamic multiplexing of pin functions, making it difficult to achieve as many segment code display controls as possible with a limited number of pins.

[0004] Therefore, there is a lack of a driving solution in the existing technology that can flexibly configure the number of common terminals, thereby making efficient use of pin resources and adapting to various segment LCD displays. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a segment LCD digital driver structure based on remapping, used to receive pattern data from a display buffer, and output it to an analog driving module after mapping processing to drive a segment LCD display screen. This structure includes:

[0006] The function register group, configured via the system bus, is used to store drive configuration information, including parameters such as the number of remapped common terminals, the scan clock division factor, and the bias resistor selection parameters.

[0007] The display input register group, which is written to via the system bus, includes multiple 8-bit registers used to buffer the segment code pattern data to be displayed;

[0008] The remapping matrix is ​​electrically connected to both the function register group and the display input register group; and the remapping matrix is ​​configured as follows:

[0009] Receive the common terminal quantity parameter (com_cnt) from the function register group to determine the address upper limit of the current mapping cycle;

[0010] Receive segment code data from the display input register group;

[0011] In response to the common terminal scan level signal, a cyclically incrementing remapped address (rmp_addr) is generated;

[0012] At each scan moment, the rmp_addr bit of each register in the display input register group is extracted and output in parallel to the corresponding segment code end (seg[n]), thereby mapping the digital display data into the scan drive waveform required by the segment LCD.

[0013] In one embodiment of the present invention, the analog driving module has its input end coupled to the segment code data output by the remapping matrix and the COM signal output by the scan timing generator, and its output end coupled to the SEG and COM pins of the LCD panel. It also integrates a configurable bias voltage network consisting of four series voltage divider resistors, the resistance values ​​of which are selected by the function register group.

[0014] In each scan cycle, the remapping matrix outputs the rmp_addr bits of each lcd_tmpn register to the corresponding seg[n] in bit order, thereby realizing dynamic driving of segment LCD with an adjustable number of common terminals from 1 to 8.

[0015] In one embodiment of the present invention, the bias voltage network of the analog drive module provides a 1 / 3 or 1 / 4 bias mode, and the drive capability can vary in the range of 150kΩ to 600kΩ depending on the resistance value selected.

[0016] In one embodiment of the present invention, the scan timing generator uses a 32.768kHz external crystal oscillator as a reference and generates a programmable scan frequency of 64Hz to 512Hz after frequency division.

[0017] In one embodiment of the present invention, the output stage of the analog driving module is a push-pull structure, which can drive a maximum of 320 segments of LCD, and the peak current of each segment is not less than 150μA.

[0018] In one embodiment of the present invention, the function register group completes the online configuration of com_cnt, frequency division coefficient and bias resistance value through a single system bus, and the display is uninterrupted during the configuration process.

[0019] In one embodiment of the present invention, the display input register group supports a double buffering mechanism: the background register writes new data through the bus, and the foreground register is updated all at once when the frame synchronization signal vsync arrives, thus avoiding display flickering.

[0020] In one embodiment of the present invention, the working process of the remapping matrix constitutes a mapping cycle: the remapping address (rmp_addr) starts from 0, increments by 1 in each scan clock cycle, until it reaches the upper limit value set by the com_cnt parameter, then is reset to 0, and a new cycle begins.

[0021] In one embodiment of the present invention, the remapping matrix is ​​implemented using a combinational logic lookup table, and its mapping delay is less than one system clock cycle, ensuring that the SEG output is strictly synchronized with the COM scan.

[0022] In one embodiment of the present invention, when the function register group dynamically changes com_cnt from 8 to 7, the scan timing generator immediately shortens the cycle to 0 to 6 in the next frame, and the unused com[7] pin automatically switches to a high impedance state to achieve a seamless transition.

[0023] Compared with the prior art, the above-mentioned technical solution of the present invention has the following advantages: The segment LCD digital driver structure of the present invention, by introducing a programmable remapping matrix, realizes flexible software configuration of the number of common terminals (COM) (1-8 COM selectable), overcoming the drawback of the fixed number of common terminals in traditional segment LCD driver chips. Its advantages are: 1. Significantly improves the chip pin reuse rate, driving more segment codes with a limited number of pins, reducing chip size and cost; 2. Enhances system flexibility and adaptability, the same driver can adapt to various LCD screens of different specifications, simplifying design and inventory management; 3. Highly integrated functions, with adjustable scanning frequency and driving capability configuration, optimizing power consumption and matching the characteristics of different LCD panels. This structure provides an efficient and reliable display driver solution for devices with high integration requirements such as water meters and flow meters. Attached Figure Description

[0024] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0025] Figure 1 This is a schematic diagram of the remapping-based segment LCD digital driver of the present invention;

[0026] Figure 2 This is a schematic diagram of the remapping 8-common-terminal matrix described in this invention;

[0027] Figure 3 This is the timing diagram of the remapped 8 common terminal output described in this invention;

[0028] Figure 4 This is the timing diagram of the remapped 7 common terminal output described in this invention;

[0029] Figure 5 This is a schematic diagram showing the connection between the metering chip and the 8 common terminal segment LCD described in this invention. Detailed Implementation

[0030] This embodiment provides a segment LCD digital driver structure based on remapping. Its core lies in dynamically configuring the number of common terminals through a programmable remapping matrix, thereby achieving the goal of driving more segment displays with a limited number of pins. The following description, in conjunction with the accompanying drawings, illustrates a specific application example.

[0031] A specific embodiment is illustrated by driving an 8COM, 40SEG segment LCD display in a metering chip, such as... Figure 1 and Figure 5 As shown, the 40 segment output pins (SEG0-SEG39) and 8 common output pins (COM0-COM7) of the metering chip are connected to the corresponding pins of the segment LCD display. The registers inside the digital driver are configured via the system bus as follows:

[0032] The pattern data in the display buffer is output to the subsequent analog drive module via remapping. The analog drive module is powered by 3.3V and has a bias voltage network consisting of four series-connected voltage divider resistors. The digital driver includes a function register set, a display input register set, and a remapping matrix.

[0033] The aforementioned function register group includes parameters for the number of remapped common terminals, the scan clock division factor, and the selection of bias resistor values. Optionally, the number of remapped common terminals can be set to 8com, 7com, 6com, 5com, 4com, 3com, 2com, and 1com. The clock division factor determines the division ratio between the scan clock and the bus operating clock. The bus operating frequency is generated by an external crystal oscillator at 32.768kHz, which can be divided to generate scan clocks of 64Hz, 128Hz, 256Hz, and 512Hz, respectively. The bias resistor can be selected with four values: 150kΩ, 200kΩ, 300kΩ, and 600kΩ, determining different driving capabilities of the analog drive module.

[0034] The aforementioned display input register group contains 40 registers, each with a bit width of 8, used to buffer pattern display data. The register addresses are named lcd_tmpi sequentially from high to low, with i = 0 to 39.

[0035] The aforementioned remapping matrix, when the common terminal scan level arrives, can map the actual value of the display input register group to the segment code terminals of the segment LCD, thereby realizing the corresponding segment code terminals.

[0036] Figure 5 The segment LCD's common terminal (COM) and segment code terminal (SEG) shown are connected to the corresponding pins of the metering chip. Combined with... Figure 2 , 3 The value in the display input register group can be used to illuminate the light. Figure 5 The corresponding segment code terminals are shown. Under special operating conditions, the number of displays required is reduced, that is, the number of common terminals is reduced. To further improve the multiplexing rate of chip pins, the number of COM pins can be flexibly configured through the driver structure designed in this paper, thereby meeting the requirements of special operating conditions.

[0037] Remapping matrix as Figure 2As shown. When the column number is the common terminal com and the row number is the segment code terminal seg, solid dots represent bright segments and hollow dots represent dark segments. When lcd_tmp0 = 0xA1, which is 1010_0001 in binary, the high level is the 0th, 5th, and 7th bits, and the remaining bits are low level dots. Through the mapping matrix, it can be mapped as follows: the intersection of row seg0 with column com0, column com5, and column com7 is a solid dot, and the intersection with other com columns is a hollow dot. The driving effect on the segment LCD is that when the scan level of the 1st common terminal, the 6th common terminal, and the 8th common terminal arrives, the 1st segment code terminal is a bright segment; when the scan level of the other common terminals arrives, the 1st segment code terminal is a dark segment. When lcd_tmp1 = 0xB2, which is 1011_0010 in binary, the high level is the 1st, 4th, 5th, and 7th bits, and the remaining bits are low level. Through the mapping matrix, it can be mapped as follows: the intersection of row seg1 with column com1, column com4, column com5, and column com7 is a solid dot, and the intersection with other com columns is a hollow dot. The driving effect for the segment LCD is that when the scan level of the 2nd, 5th, 6th, and 8th common terminals arrives, the 2nd segment code terminal is a bright segment, and when the scan level of the remaining common terminals arrives, the 2nd segment code terminal is a dark segment. When lcd_tmp2 = 0xc3, which is 1100_0011 in binary, the high level is the 0th, 1st, 6th, and 7th bits, and the remaining bits are low level. Through the mapping matrix, it can be mapped as follows: the intersection of row seg2 with columns com1, com4, com5, and com7 is a solid dot, and the intersection with other com columns is a hollow dot. The driving effect on the segment LCD is that when the scan level of the 1st, 2nd, 7th, and 8th common terminals arrives, the 3rd segment is a bright segment, and when the scan level of the remaining common terminals arrives, the 3rd segment is a dark segment. When lcd_tmp3 = 0xd4, which is 1101_0100 in binary, the high level is the 2nd, 4th, 6th, and 7th bits, and the remaining bits are low level. Through the mapping matrix, it can be mapped as follows: the intersection of row seg3 with columns com2, com4, com6, and com7 is a solid dot, and the intersection with other com columns is a hollow dot. The driving effect for the segment LCD is that when the scanning level of the 3rd, 5th, 7th, and 8th common terminals arrives, the 4th segment is a bright segment, and when the scanning level of the remaining common terminals arrives, the 4th segment is a dark segment. When lcd_tmp4 = 0xe5, which is 1110_0101 in binary, the high level is the 0th, 2nd, 5th, 6th, and 7th bits, and the remaining bits are low level. Through the mapping matrix, it can be mapped as follows: the intersection of row seg4 with column com0, column com2, column com5, column com6, and column com7 is a solid dot, and the intersection with other com columns is a hollow dot. The driving effect for the segment LCD is that when the scan level of the 1st, 3rd, 6th, 7th, and 8th common terminals arrives, the 5th segment is a bright segment, and when the scan level of the remaining common terminals arrives, the 5th segment is a dark segment.When lcd_tmp5 = 0xf6, which is 1111_0110 in binary, the high level is the 1st, 2nd, 4th, 5th, 6th, and 7th bits, and the remaining bits are low level. Through the mapping matrix, it can be mapped as follows: the intersection of row seg5 with columns com1, com2, com4, com5, com6, and com7 is a solid dot, and the intersection with other com columns is a hollow dot. The driving effect on the segment LCD is that when the scan level of the 2nd, 3rd, 5th, 6th, 7th, and 8th common terminals arrives, the 6th segment is a bright segment, and when the scan level of the remaining common terminals arrives, the 6th segment is a dark segment. When lcd_tmp6 = 0x97, which is 1001_0111 in binary, the high level is the 0th, 1st, 2nd, 4th, and 7th bits, and the remaining bits are low level. Through the mapping matrix, it can be mapped as follows: the intersection of row seg6 with column com0, column com1, column com2, column com4, and column com7 is a solid dot, and the intersection with other com columns is a hollow dot. The driving effect for segment LCD is that when the scan level of the 1st, 2nd, 3rd, 5th, and 8th common terminals arrives, the 7th segment is a bright segment, and when the scan level of the remaining common terminals arrives, the 7th segment is a dark segment. When lcd_tmp7 = 0x88, which is 1000_1000 in binary, the high level is the 3rd and 7th bits, and the remaining bits are low level; through the mapping matrix, it can be mapped as follows: the intersection of row seg7 with column com3 and column com7 is a solid dot, and the intersection with other com columns is a hollow dot; the driving effect for segment LCD is that when the scanning level of the 4th and 8th common terminals arrives, the 8th segment code terminal is a bright segment, and when the scanning level of the other common terminals arrives, the 8th segment code terminal is a dark segment.

[0038] Figure 3The timing diagram for remapping the 8 common terminals output is shown. The remapping matrix is ​​based on the remapping address rmp_addr, the upper limit of which is the parameter in com_cnt for the number of common terminals; the remapping address rmp_addr ranges from 0 to the upper limit for one complete mapping; the rmp_addr bit in the display input register group lcd_tmpn (n = 0~39) is output to the segment code terminal seg[n] (n = 0~39), thus completing the digital driving of the segment LCD. First, the display input register group and the function register group are configured through the bus. Specifically, before time T1 begins, the following display data are input sequentially: lcd_tmp0 = 0xA1, lcd_tmp1 = 0xB2, lcd_tmp2 = 0xc3, lcd_tmp3 = 0xd4, lcd_tmp4 = 0xe5, lcd_tmp5 = 0xf6, lcd_tmp6 = 0x97 and lcd_tmp7 = 0x88; the number of common terminals is configured to 8com, i.e., com_cnt = 7. At time T2, the remapping address is 0, and com0 is set to 1; the 0th bit of lcd_tmp0 is output to seg[0], and its value is 1; the 0th bit of lcd_tmp1 is output to seg[1], and its value is 0; the 0th bit of lcd_tmp2 is output to seg[2], and its value is 1; the 0th bit of lcd_tmp3 is output to seg[3], and its value is 0; the 0th bit of lcd_tmp4 is output to seg[4], and its value is 1; the 0th bit of lcd_tmp5 is output to seg[5], and its value is 0; the 0th bit of lcd_tmp6 is output to seg[6], and its value is 1; the 0th bit of lcd_tmp7 is output to seg[7], and its value is 0. At time T3, the remapping address is 1, and com1 is set to 1; the first bit of lcd_tmp0 is output to seg[0], and its value is 0; the first bit of lcd_tmp1 is output to seg[1], and its value is 1; the first bit of lcd_tmp2 is output to seg[2], and its value is 1; the first bit of lcd_tmp3 is output to seg[3], and its value is 0; the first bit of lcd_tmp4 is output to seg[4], and its value is 0; the first bit of lcd_tmp5 is output to seg[5], and its value is 1; the first bit of lcd_tmp6 is output to seg[6], and its value is 1; the first bit of lcd_tmp7 is output to seg[7], and its value is 0.At time T4, the remapping address is 2, and com2 is set to 1; the second bit of lcd_tmp0 is output to seg[0], and its value is 0; the second bit of lcd_tmp1 is output to seg[1], and its value is 0; the second bit of lcd_tmp2 is output to seg[2], and its value is 0; the second bit of lcd_tmp3 is output to seg[3], and its value is 1; the second bit of lcd_tmp4 is output to seg[4], and its value is 1; the second bit of lcd_tmp5 is output to seg[5], and its value is 1; the second bit of lcd_tmp6 is output to seg[6], and its value is 1; the second bit of lcd_tmp7 is output to seg[7], and its value is 0. At time T5, the remapping address is 3, and com3 is set to 1; the 3rd bit of lcd_tmp0 is output to seg[0], and its value is 0; the 3rd bit of lcd_tmp1 is output to seg[1], and its value is 0; the 3rd bit of lcd_tmp2 is output to seg[2], and its value is 0; the 3rd bit of lcd_tmp3 is output to seg[3], and its value is 0; the 3rd bit of lcd_tmp4 is output to seg[4], and its value is 0; the 3rd bit of lcd_tmp5 is output to seg[5], and its value is 0; the 3rd bit of lcd_tmp6 is output to seg[6], and its value is 0; the 3rd bit of lcd_tmp7 is output to seg[7], and its value is 1. At time T6, the remapping address is 4, and com4 is set to 1; the 4th bit of lcd_tmp0 is output to seg[0], and its value is 0; the 4th bit of lcd_tmp1 is output to seg[1], and its value is 1; the 4th bit of lcd_tmp2 is output to seg[2], and its value is 0; the 4th bit of lcd_tmp3 is output to seg[3], and its value is 1; the 4th bit of lcd_tmp4 is output to seg[4], and its value is 0; the 4th bit of lcd_tmp5 is output to seg[5], and its value is 1; the 4th bit of lcd_tmp6 is output to seg[6], and its value is 1; the 4th bit of lcd_tmp7 is output to seg[7], and its value is 0. At time T7, the remapping address is 5, and com5 is set to 1; the 5th bit of lcd_tmp0 is output to seg[0], and its value is 1; the 5th bit of lcd_tmp1 is output to seg[1], and its value is 1; the 5th bit of lcd_tmp2 is output to seg[2], and its value is 0; the 5th bit of lcd_tmp3 is output to seg[3], and its value is 0; the 5th bit of lcd_tmp4 is output to seg[4], and its value is 1; the 5th bit of lcd_tmp5 is output to seg[5], and its value is 1; the 5th bit of lcd_tmp6 is output to seg[6], and its value is 0; the 5th bit of lcd_tmp7 is output to seg[7], and its value is 0.At time T8, the remapping address is 6, and com6 is set to 1; the 6th bit of lcd_tmp0 is output to seg[0], and its value is 0; the 6th bit of lcd_tmp1 is output to seg[1], and its value is 0; the 6th bit of lcd_tmp2 is output to seg[2], and its value is 1; the 6th bit of lcd_tmp3 is output to seg[3], and its value is 1; the 6th bit of lcd_tmp4 is output to seg[4], and its value is 1; the 6th bit of lcd_tmp5 is output to seg[5], and its value is 1; the 6th bit of lcd_tmp6 is output to seg[6], and its value is 0; the 6th bit of lcd_tmp7 is output to seg[7], and its value is 0. At time T9, the remapping address is 7, and com7 is set to 1; the 7th bit of lcd_tmp0 is output to seg[0], and its value is 1; the 7th bit of lcd_tmp1 is output to seg[1], and its value is 1; the 7th bit of lcd_tmp2 is output to seg[2], and its value is 1; the 7th bit of lcd_tmp3 is output to seg[3], and its value is 1; the 7th bit of lcd_tmp4 is output to seg[4], and its value is 1; the 7th bit of lcd_tmp5 is output to seg[5], and its value is 1; the 7th bit of lcd_tmp6 is output to seg[6], and its value is 1; the 7th bit of lcd_tmp7 is output to seg[7], and its value is 1. At time T10, a new remapping loop is started, with the remapping address set to 0 and com0 set to 1. The 0th bit of lcd_tmp0 is output to seg[0], and its value is 1. The 0th bit of lcd_tmp1 is output to seg[1], and its value is 0. The 0th bit of lcd_tmp2 is output to seg[2], and its value is 1. The 0th bit of lcd_tmp3 is output to seg[3], and its value is 0. The 0th bit of lcd_tmp4 is output to seg[4], and its value is 1. The 0th bit of lcd_tmp5 is output to seg[5], and its value is 0. The 0th bit of lcd_tmp6 is output to seg[6], and its value is 1. The 0th bit of lcd_tmp7 is output to seg[7], and its value is 0.

[0039] The specific remapping and driving process: After the driver starts working, the remapping matrix generates a cyclically increasing remapping address rmp_addr (from 0 to 7) under the drive of a 256Hz scan clock.

[0040] like Figure 3As shown in the timing diagram, when rmp_addr = 0, the COM0 pin outputs a valid scan level. At this time, the remapping matrix outputs the 0th bit of each display input register (lcd_tmp0 to lcd_tmp39) to the corresponding segment code (SEG0 to SEG39) in parallel. For example, SEG0 outputs lcd_tmp0[0] = 1 (high level), SEG1 outputs lcd_tmp1[0] = 0 (low level), and so on.

[0041] In the next scan clock cycle, rmp_addr increments to 1, COM1 outputs a valid level, and the matrix outputs the first bit of data from each register to the segment code.

[0042] This process repeats continuously, activating COM0 through COM7 sequentially. Within a complete scan cycle (8 scan clock cycles), each common terminal is activated once in sequence, and all segment code data is mapped onto the LCD in an orderly manner, utilizing the persistence of vision to form a stable display pattern. The relationship between its mapping logic and display effect is as follows: Figure 2 As shown in the matrix diagram.

[0043] like Figure 4 As shown, specifically, at time T1, when rmp_addr is 7, the mapping process ends. At time T2, the parameter in com_cnt for the number of common endpoints is configured to 6; from time T2 to time T8, the remapped address rmp_addr is changed from 0 to 6 in one mapping cycle, and the mapping process is the same as the mapping logic in T3; at time T9, after the previous mapping is completed, a new mapping begins.

[0044] In summary, if the product is updated and the display screen becomes 7 common terminals (7COM), there is no need to replace the chip or modify the circuit. You only need to reconfigure the number of common terminals in the function register group to 7COM (i.e., com_cnt = 6) through software.

[0045] like Figure 4 As shown in the timing diagram, after configuration, the loop limit of the remapped address rmp_addr automatically becomes 6 (from 0 to 6). The driver only uses 7 pins, COM0 to COM6, for scanning. The COM7 pin can be reused as other functional pins (such as key detection or communication interface), which greatly improves the utilization of chip pins and the flexibility of system design.

[0046] The segmented LCD digital driver structure described in this embodiment achieves dynamic adjustment of the number of common terminals through software configuration rather than hardware fixation, effectively solving the problems of poor flexibility and low pin reuse rate of traditional driver chips. It is particularly suitable for embedded display application scenarios that require high integration and flexible adaptation.

[0047] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A segment LCD digital driver structure based on remapping, used to receive pattern data from a display buffer, and output it to an analog driver module after mapping processing to drive a segment LCD display screen, characterized in that, The structure includes: The function register group, configured via the system bus, is used to store drive configuration information, including parameters such as the number of remapped common terminals, the scan clock division factor, and the bias resistor selection parameters. The display input register group, which is written to via the system bus, includes multiple 8-bit registers used to buffer the segment code pattern data to be displayed; The remapping matrix is ​​electrically connected to both the function register group and the display input register group; and the remapping matrix is ​​configured as follows: Receive the number of common terminals from the function register group to determine the upper limit of the address for the current mapping cycle; Receive segment code data from the display input register group; In response to the common terminal scan level signal, a cyclically incrementing remapped address is generated; At each scanning moment, the rmp_addr bit of each register in the display input register group is extracted and output in parallel to the corresponding segment code end, thereby mapping the digital display data to the scanning drive waveform required by the segment LCD; when the function register group dynamically changes com_cnt from 8 to 7, the scanning timing generator immediately shortens the cycle to 0~6 in the next frame, and the unused com[7] pin automatically switches to high impedance state to achieve seamless transition.

2. The segment LCD digital driver structure according to claim 1, characterized in that: The analog drive module has its input end coupled to the segment code data output by the remapping matrix and the COM signal output by the scan timing generator, and its output end coupled to the SEG and COM pins of the LCD panel. It also integrates a configurable bias voltage network consisting of four series voltage divider resistors, the resistance values ​​of which are selected by the function register group. In each scan cycle, the remapping matrix outputs the rmp_addr bits of each lcd_tmpn register to the corresponding seg[n] in bit order, thereby realizing dynamic driving of the segment LCD with an adjustable number of common terminals from 1 to 8.

3. The segmented LCD digital driver structure according to claim 2, characterized in that: The bias voltage network of the analog drive module provides 1 / 3 or 1 / 4 bias modes, and the drive capability can vary from 150 kΩ to 600 kΩ depending on the resistance value.

4. The segmented LCD digital driver structure according to claim 2, characterized in that: The scan timing generator uses a 32.768 kHz external crystal oscillator as a reference and generates a programmable scan frequency of 64 Hz to 512 Hz after frequency division.

5. The segmented LCD digital driver structure according to claim 2, characterized in that: The output stage of the analog driver module is a push-pull structure, which can drive a maximum of 320 segments of LCD, and the peak current of each segment is not less than 150 μA.

6. The segment LCD digital driver structure according to claim 1, characterized in that: The function register group can complete the online configuration of com_cnt, frequency divider coefficient and bias resistor value through a single system bus, and the display is uninterrupted during the configuration process.

7. The segment LCD digital driver structure according to claim 1, characterized in that: The display input register group supports a double buffering mechanism: the background register writes new data through the bus, and the foreground register is updated all at once when the frame synchronization signal vsync arrives, thus avoiding display flickering.

8. The segment LCD digital driver structure according to claim 1, characterized in that: The remapping matrix operates in a mapping cycle: the remapping address (rmp_addr) starts from 0 and increments by 1 in each scan clock cycle until it reaches the upper limit set by the com_cnt parameter, at which point it is reset to 0 and a new cycle begins.

9. The segment LCD digital driver structure according to claim 1, characterized in that: The remapping matrix is ​​implemented using a combinational logic lookup table, and its mapping delay is less than one system clock cycle, ensuring that the SEG output is strictly synchronized with the COM scan.

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