Display driving circuit and display panel

Abstract

The application provides a display driving circuit and a display panel. The display driving circuit comprises a driving signal output unit and a pre-charging unit. The driving signal output unit is used for outputting a display driving signal. The pre-charging unit is connected to an output line of the driving signal output unit outputting the display driving signal, and is used for pre-charging a parasitic capacitance of the output line before the voltage of the display driving signal is stabilized. The pre-charging voltage corresponding to the pre-charging is less than the driving voltage corresponding to the display driving signal. The pre-charging makes the voltage of the parasitic capacitance close to the driving voltage corresponding to the display driving signal. When the effective level (constant high level or constant low level) of the display driving signal arrives, the voltage change range is reduced, the amplitude of the sharp peak current is reduced, the sharp peak current can be effectively inhibited, the liquid crystal polarization is improved, the display effect is improved, and the heat energy loss is reduced.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display driving circuit and a display panel. Background Technology

[0002] With the development of display technology, the demand for display refresh rates is increasing. Higher refresh rates require stronger driving capabilities from the drive circuits. However, with the increased driving capability, the current transmitted by the circuits also increases, which can easily lead to higher display temperatures and increase the risk of liquid crystal polarization.

[0003] During the transmission of the gate driver signal in a liquid crystal display (LCD), parasitic capacitance exists in the transmission line. During signal level transitions (such as from low to high or from high to low), this parasitic capacitance charges, generating a large transient current, also known as a spike current. Figure 1 As shown, the current I_CLK has spikes at the rising and falling edges of the input clock signal CLK_IN. These spikes can cause an increase in the instantaneous power consumption of the transmission line, leading to increased heat loss. The spikes can also cause unnecessary polarization of the liquid crystal molecules, interfering with the stability of the signal and causing display problems such as ghosting and flickering, thus affecting the display effect.

[0004] Currently, the common method is to connect a resistor in series in the clock signal to suppress spike current, but this method introduces additional heat loss. Summary of the Invention

[0005] This invention mainly provides a display driving circuit and a display panel that can suppress peak current and reduce heat loss.

[0006] To solve the above-mentioned technical problems, the first technical solution adopted by the present invention is: to provide a display driving circuit, comprising:

[0007] A drive signal output unit, wherein the drive signal output unit is used to output a display drive signal;

[0008] A pre-charging unit is connected to the output line of the drive signal output unit that outputs the display drive signal. The pre-charging unit is used to pre-charge the parasitic capacitance of the output line before the voltage of the display drive signal stabilizes. The pre-charging voltage is less than the drive voltage of the display drive signal.

[0009] In one embodiment, the pre-charging unit is used to pre-charge the parasitic capacitance of the output line at the rising edge of the display driving signal; and the pre-charging unit is used to pre-charge the parasitic capacitance of the output line at the falling edge of the display driving signal.

[0010] In one embodiment, the display driving circuit further includes:

[0011] A logic selection unit, which is connected to the drive signal output unit and the pre-charge unit, is used to enable the pre-charge unit to perform pre-charge based on the state of the display drive signal.

[0012] In one embodiment, the pre-charging unit includes: a current source and a pre-charging switch, the current source being used to provide a pre-charging current; a first path terminal of the pre-charging switch being connected to the current source, a second path terminal of the pre-charging switch being connected to the output line, a control terminal of the pre-charging switch being connected to the logic selection unit, and the pre-charging switch performing pre-charging in response to a pre-charging start signal output by the logic selection unit;

[0013] In one cycle of the display driving signal, the rising edge of the precharge enable signal is earlier than the rising edge of the display driving signal, and the falling edge of the precharge enable signal is aligned with the rising edge of the display driving signal; the rising edge of the precharge enable signal is earlier than the falling edge of the display driving signal, and the falling edge of the precharge enable signal is aligned with the falling edge of the display driving signal.

[0014] In one embodiment, the display driving circuit further includes an output control unit, which is connected to the logic selection unit and the output line;

[0015] The logic selection unit is further configured to: compare the display driving signal with a threshold voltage to determine whether the display driving signal is at a rising edge or a falling edge;

[0016] In response to the rising edge or falling edge, the logic selection unit outputs a precharge enable signal to control the precharge unit to perform precharge;

[0017] In response to a non-rising edge or a non-falling edge, the logic selection unit controls the output control unit to be in an operating state and outputs the display drive signal.

[0018] In one embodiment, the logic selection unit includes a first selection unit; the pre-charging unit includes a first pre-charging unit connected to the output line and the first selection unit; the output control unit includes a first control unit connected to the output line and the first selection unit.

[0019] The first selection unit is connected to the drive signal output unit and receives the display drive signal. The first selection unit compares the display drive signal with a first threshold voltage. If the display drive signal is a positive voltage and less than the first threshold voltage, it determines that the display drive signal is at a rising edge. The first selection unit outputs the pre-charge enable signal to the first pre-charge unit, controlling the first pre-charge unit to pre-charge the parasitic capacitance of the output line. If the display drive signal is greater than the first threshold voltage, the first selection unit controls the first control unit to be in the working state, thereby outputting the display drive signal.

[0020] In one embodiment, the logic selection unit includes a second selection unit; the pre-charging unit includes a second pre-charging unit connected to the output line and the second selection unit; the output control unit includes a second control unit connected to the output line and the second selection unit.

[0021] The second selection unit is connected to the drive signal output unit and receives the display drive signal. The second selection unit compares the display drive signal with a second threshold voltage. If the display drive signal is a negative voltage and greater than the second threshold voltage, it determines that the display drive signal is at a falling edge. The second selection unit outputs the pre-charge enable signal to the second pre-charge unit, controlling the second pre-charge unit to pre-charge the parasitic capacitance of the output line. If the display drive signal is less than the second threshold voltage, the second selection unit controls the second control unit to be in the working state, thereby outputting the display drive signal.

[0022] In one embodiment, the first pre-charging unit and the second pre-charging unit use different current sources for pre-charging; and the current source corresponding to the first pre-charging unit and the current source corresponding to the second pre-charging unit have the same current but opposite directions.

[0023] In one embodiment, the pre-charge voltage corresponding to the pre-charge is k times the driving voltage corresponding to the display driving signal, where k is less than 1, k is determined based on the driving capability of the display driving circuit, and k is positively correlated with the driving capability of the display driving circuit.

[0024] To solve the above-mentioned technical problems, the second technical solution adopted by the present invention is to provide a display panel, including the display driving circuit described in any one of the above-mentioned claims.

[0025] The beneficial effects of this invention are as follows: Unlike existing technologies, the display driving circuit provided by this invention includes a driving signal output unit and a pre-charging unit. The driving signal output unit outputs a display driving signal. The pre-charging unit is connected to the output line of the driving signal output unit, which outputs the display driving signal, and is used to pre-charge the parasitic capacitance of the output line before the voltage of the display driving signal stabilizes. The pre-charging voltage is lower than the driving voltage corresponding to the display driving signal. By pre-charging, the voltage of the parasitic capacitance approaches the driving voltage corresponding to the display driving signal. When the effective level (constant high level or constant low level) of the display driving signal arrives, the voltage change amplitude decreases, thereby reducing the amplitude of the peak current. This effectively suppresses peak current, improves liquid crystal polarization, enhances display performance, and also reduces heat loss. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 A schematic diagram of generating a spike current for a clock signal;

[0028] Figure 2 A schematic diagram of the structure of a first embodiment of the display driver circuit provided in this application;

[0029] Figure 3 A schematic diagram of the structure of the second embodiment of the display driver circuit provided in this application;

[0030] Figure 4 for Figure 3 The diagram shows a schematic of a choke structure of one embodiment of the display driver circuit.

[0031] Figure 5 for Figure 4 The timing diagram corresponding to the display driver circuit is shown below;

[0032] Figure 6 A schematic diagram of the structure of the third embodiment of the display driving circuit provided in this application;

[0033] Figure 7 for Figure 6 The diagram shows a structural schematic of one embodiment of the display driver circuit.

[0034] Figure 8 for Figure 6 A schematic diagram of another embodiment of the display driver circuit is shown;

[0035] Figure 9 A schematic diagram of the structure of an embodiment of the display panel provided in this application.

[0036] Explanation of reference numerals in the attached figures: Drive signal output unit 11, pre-charge unit 12, parasitic capacitance C, display drive signal CK_OUT, logic selection unit 13, current source 120, pre-charge switch M, pre-charge enable signal MOS_EN, output control unit 14, first selection unit 131, second selection unit 132, first pre-charge unit 121, second pre-charge unit 122, first control unit 141, second control unit 142, first selection switch M1, first comparison unit A1, first threshold voltage U1, first pre-charge switch M3, first current source I1, first control switch M4, first inverter F1, first voltage follower B1, second comparison unit A2, second selection switch M2, second inverter F2, second threshold voltage U2, second pre-charge switch M5, second current source I2, second control switch M6, third inverter F3, second voltage follower B2, display drive circuit 10. Detailed Implementation

[0037] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0038] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0039] In this article, the term "and / or" simply describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Additionally, the character " / " generally indicates that the preceding and following related objects have an "or" relationship. Furthermore, "more" in this article means two or more objects.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0041] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0042] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0043] See Figure 2 , Figure 2 The schematic diagram of the first embodiment of the display driving circuit provided in this application specifically includes: a driving signal output unit 11 and a pre-charge unit 12. The driving signal output unit 11 is used to output a display driving signal CK_OUT. In one embodiment, the driving signal output unit 11 is, for example, disposed in a gate driver, and the display driving signal CK_OUT is, for example, a clock signal output internally by the gate driver, used to provide a time reference for each circuit module, enabling each module to work in a coordinated manner according to a predetermined timing sequence. The pre-charge unit 12 is connected to the output line of the driving signal output unit 11 that outputs the display driving signal CK_OUT, and is used to pre-charge the parasitic capacitance C of the output line before the voltage of the display driving signal CK_OUT stabilizes; wherein the pre-charge voltage corresponding to the pre-charge is less than the driving voltage corresponding to the display driving signal CK_OUT.

[0044] This application uses pre-charging to make the voltage of the parasitic capacitor close to the driving voltage corresponding to the display driving signal. When the effective level of the display driving signal (constant high level or constant low level) arrives, the voltage change amplitude is reduced, thereby reducing the amplitude of the peak current. This can effectively suppress the peak current, improve liquid crystal polarization, improve the display effect, and also reduce heat loss.

[0045] In one embodiment, the pre-charging unit 12 is used to pre-charge the parasitic capacitance C of the output line at the rising edge of the display drive signal CK_OUT; and the pre-charging unit 12 is used to pre-charge the parasitic capacitance C of the output line at the falling edge of the display drive signal CK_OUT.

[0046] Specifically, current spikes are generated at the rising and falling edges of the display drive signal CK_OUT. These spikes cause an increase in instantaneous power consumption in the transmission line, leading to increased heat loss. The spikes can also cause unnecessary polarization of liquid crystal molecules, interfering with signal stability and causing display problems such as ghosting and flickering, thus affecting the display effect. This application pre-charges the parasitic capacitance C of the output line at the rising and falling edges of the display drive signal CK_OUT. This reduces the voltage change amplitude when a constant high or low level arrives, thereby reducing the amplitude of the spike current. This effectively suppresses the spike current, improves liquid crystal polarization, and enhances the display effect.

[0047] Furthermore, in combination Figure 3 The display driving circuit also includes a logic selection unit 13, which is connected to the drive signal output unit 11 and the pre-charge unit 12, and is used to enable the pre-charge unit 12 for pre-charging based on the state of the display drive signal CK_OUT.

[0048] In one embodiment, the pre-charge unit 12 is used to pre-charge the parasitic capacitance C of the output line before the rising or falling edge of the display drive signal CK_OUT. The pre-charge unit 12 determines whether to enable pre-charging based on the state of the drive signal CK_OUT, and can accurately track the rising and falling edges to achieve precise control of pre-charging on the rising and falling edges.

[0049] Specifically, before the rising and falling edges of the display drive signal CK_OUT, the logic selection unit 13 controls the pre-charge unit 12 to turn on, thereby pre-charging the parasitic capacitance C. Combined with... Figure 4 The pre-charging unit 12 includes a current source 120 and a pre-charging switch M. The current source 120 provides the pre-charging current. The first terminal of the pre-charging switch M is connected to the current source 120, the second terminal of the pre-charging switch M is connected to the output line, and the control terminal of the pre-charging switch M is connected to the logic selection unit 13. The pre-charging switch M performs pre-charging in response to the pre-charging enable signal MOS_EN output by the logic selection unit 13. This embodiment utilizes a current source to achieve pre-charging, resulting in a simple circuit structure. In addition to suppressing peak currents, improving liquid crystal polarization, and enhancing display performance, it also enables uniform power consumption distribution, reduces localized temperature rise, and optimizes heat energy distribution.

[0050] For details, see Figure 5 In one cycle of the display drive signal CK_OUT, the rising edge of the precharge enable signal MOS_EN precedes the rising edge of the display drive signal CK_OUT, and the falling edge of the precharge enable signal MOS_EN is aligned with the rising edge of the display drive signal CK_OUT. Furthermore, the rising edge of the precharge enable signal MOS_EN precedes the falling edge of the display drive signal CK_OUT, and the falling edge of the precharge enable signal MOS_EN is aligned with the falling edge of the display drive signal CK_OUT. It can be understood that there are two precharge enable signals MOS_EN in one cycle T of the display drive signal CK_OUT, namely t1 and t2. t1 corresponds to the precharge at the rising edge of the display drive signal CK_OUT, with its rising edge preceding the rising edge of the display drive signal CK_OUT and its falling edge aligned with the rising edge of the display drive signal CK_OUT. t2 corresponds to the precharge at the falling edge of the display drive signal CK_OUT, with its rising edge preceding the falling edge of the display drive signal CK_OUT and its falling edge aligned with the falling edge of the display drive signal CK_OUT.

[0051] In this embodiment, the pre-charge unit 12 can be located in the gate driver, and the logic selection unit 13 can be a timing controller. The timing controller can select to output a pre-charge enable signal MOS_EN to enable the pre-charge unit 12 for pre-charging based on the state of the display drive signal CK_OUT, such as the rising or falling edge of the display drive signal CK_OUT. Figure 5 As shown.

[0052] In one embodiment, the current value of the current source 120 can be designed based on the size of the parasitic capacitance C and the target pre-charge time. Typically, the current of the current source 120 is much smaller than the normal drive current to avoid introducing additional power consumption. Furthermore, the current source 120 in the pre-charge unit 12 is a low current source 120, such as a 1mA current source 120. In other embodiments, the current source 120 can also be 2mA, 3mA, etc., and there is no specific limitation.

[0053] In this embodiment, before the pulse transition (rising or falling edge) of the display driving signal CK_OUT, the logic selection unit 13, such as a timing controller, outputs a pre-charge enable signal MOS_EN to open the pre-charge switch M, initiating the pre-charge phase. The parasitic capacitor C is charged using the current source 120 until its voltage approaches the target voltage. After the pre-charge phase ends, the pre-charge switch M opens, and the display driving signal CK_OUT is output normally. It can be understood that the target voltage is the driving voltage corresponding to the display driving signal CK_OUT. In one embodiment, the pre-charge voltage corresponding to the pre-charge is k times the driving voltage corresponding to the display driving signal CK_OUT, where k is less than 1. k is determined based on the driving capability of the display driving circuit and is positively correlated with the driving capability of the display driving circuit. Specifically, during the pre-charging process, the pre-charging voltage corresponding to the pre-charging will pre-charge the voltage of the parasitic capacitor C to 80%-90% of the target voltage, i.e., k = 80%-90%. The display drive circuit completes the remaining 10%-20%. Theoretically, the larger the value of k, the stronger the peak current suppression, but the smaller the main drive margin, which may require a stronger drive circuit. Therefore, the value of k should be selected within an appropriate range.

[0054] In this application, after pre-charging, the voltage of the parasitic capacitor C is made close to the driving voltage corresponding to the display driving signal CK_OUT. When the effective level (constant high level or constant low level) of the display driving signal CK_OUT arrives, the voltage change amplitude is reduced, thereby reducing the amplitude of the peak current. This can effectively suppress the peak current, improve liquid crystal polarization, and enhance the display effect.

[0055] Assume the pre-charge voltage Vpre is set as follows: Vpre = Vtarget * k (k = 0.8 ~ 0.9), where Vtarget is the target voltage; and the pre-charge time t. precharge for:

[0056]

[0057] Among them, c parasitic I represents the parasitic capacitance C, ΔV represents the difference between the target voltage and the initial voltage, where the initial voltage is the voltage value of the parasitic capacitance C before pre-charging. precharge This represents the pre-charging current. Pre-charging reduces the charge amount ΔQ during the transition phase; specifically, ΔQ = c parasitic *(1-k)*ΔV, the theoretical peak current reduction is 1-k.

[0058] In the original series resistor scheme, the peak current passes through resistor R, resulting in a significant I. 2 The loss of *R, I represents the peak current, t represents time, C represents the parasitic capacitance C, and V is the energy loss of the resistor during a single jump (rising or falling edge). The calculation method is as follows: in, V represents the voltage across resistor R, then the power consumption P = 0.5 * C * V 2 *f, where f represents the frequency of the display drive signal CK_OUT, and the drive circuit may also have 0.5*C*V. 2 The power consumption is *f, so the total power consumption is C*V. 2 *f.

[0059] In the pre-charging scheme of this application, the energy loss of the parasitic capacitor C during each charge and discharge cycle is 0.5*C*V. 2 The total power consumption is 0.5 * C * V 2 Therefore, the power consumption of the pre-charging scheme in this application is: 0.5 * C * (k * V) for the pre-charging portion. 2 *f and the main drive section 0.5*C*((1-k)V) 2 The sum of *f is specifically 0.5*C*V 2 *f*(k 2 +(1-k) 2 Therefore, the pre-charging scheme saves 1-0.5*(k) compared to the original series resistor scheme. 2 +(1-k) 2Assuming k = 0.8, then 1 - 0.5 * (0.64 + 0.04) = 1 - 0.34 = 0.66 is saved. This means the pre-charging scheme of this application saves 66% of power consumption compared to the existing series resistor scheme. Therefore, the scheme of this application can significantly reduce power consumption while suppressing peak current. Compared to the traditional series resistor scheme, it allows power consumption to be evenly distributed in the pre-charging branch and the main drive branch, reducing local temperature rise, optimizing heat distribution, and improving display performance.

[0060] See Figure 6 , Figure 6 In the illustrated embodiment, the display driving circuit further includes an output control unit 14, which is connected to the logic selection unit 13 and the output line. The logic selection unit 13 is also used to compare the display driving signal CK_OUT with a threshold voltage to determine whether the display driving signal CK_OUT is at a rising edge or a falling edge. In response to a rising edge or a falling edge, the logic selection unit 13 outputs a pre-charge enable signal MOS_EN to control the pre-charge unit 12 to perform pre-charge. In response to a non-rising edge or a non-falling edge, the logic selection unit 13 controls the output control unit 14 to be in a working state and outputs the display driving signal CK_OUT.

[0061] Combination Figure 1 It can be understood that transient current occurs when the display drive signal CK_OUT transitions, for example, from a low level to a high level (i.e., the rising edge of the signal) or from a high level to a low level (i.e., the falling edge of the signal). Therefore, this embodiment can detect the rising or falling edge of the display drive signal CK_OUT and output a pre-charge enable signal MOS_EN during the rising or falling edge to control the pre-charge unit 12 to perform pre-charge. When there is no rising or falling edge, it can be inferred that the display drive signal CK_OUT is in a stable state, for example, when it transitions from a low level to a high level and holds at a high level, or when it transitions from a high level to a low level and holds at a low level. This stage is called a level-stable state. In the level-stable state, the logic selection unit 13 controls the output control unit 14 to be in the working state and outputs the display drive signal CK_OUT. It should be noted that the working state of the output unit can be, for example, the output path of the output unit being turned on.

[0062] It should be noted that this embodiment can achieve self-driving without obtaining timing control signals from the outside. Therefore, the display driving circuit of this embodiment can be set in the gate driver.

[0063] In one specific embodiment, combined with Figure 7The logic selection unit 13 includes a first selection unit 131; the pre-charging unit 12 includes a first pre-charging unit 121, which is connected to the output line and the first selection unit 131; the output control unit 14 includes a first control unit 141, which is connected to the output line and the first selection unit 131.

[0064] The first selection unit 131 is connected to the drive signal output unit 11 and receives the display drive signal CK_OUT. The first selection unit 131 compares the display drive signal CK_OUT with the first threshold voltage U1. If the display drive signal CK_OUT is a positive voltage and less than the first threshold voltage U1, it determines that the display drive signal CK_OUT is at the rising edge. The first selection unit 131 outputs a precharge enable signal MOS_EN to the first precharge unit 121, controlling the first precharge unit 121 to precharge the parasitic capacitance C of the output line. If the display drive signal CK_OUT is greater than the first threshold voltage U1, the first selection unit 131 controls the first control unit 141 to be in working state, thereby outputting the display drive signal CK_OUT.

[0065] This embodiment utilizes the cooperation of a first selection unit, a first pre-charge unit, and a first control unit to perform pre-charge when the display drive signal CK_OUT is at the rising edge, which can suppress peak current at the rising edge.

[0066] Combination Figure 8 The drive signal output unit 11 includes a logic unit and a level conversion unit. The logic unit is used to output clock signals CK1-CK10, which are the display drive signals CK_OUT of this application. The level conversion unit is used to perform level conversion on the clock signals.

[0067] Furthermore, the first selection unit 131 includes a first selection switch M1 and a first comparison unit A1; the control terminal and the first path terminal of the first selection switch M1 are connected to the drive signal output unit 11. Specifically, the control terminal of the first selection switch M1 is connected to the logic unit in the drive signal output unit 11, while the first path terminal of the first selection switch M1 is connected to the level conversion unit in the drive signal output unit 11; the first input terminal (inverting input terminal -) of the first comparison unit A1 is connected to the second path terminal of the first selection switch M1, and the second input terminal (non-inverting input terminal +) of the first comparison unit A1 receives the first threshold voltage U1.

[0068] The first pre-charge unit 121 includes a first pre-charge switch M3 and a first current source I1. The control terminal of the first pre-charge switch M3 is connected to the output terminal of the first comparison unit A1, the first path terminal of the first pre-charge switch M3 is connected to the first current source I1, and the second path terminal of the first pre-charge switch M3 is connected to the output line.

[0069] The first control unit 141 includes a first control switch M4, a first inverter F1, and a first voltage follower B1. The output terminal of the first inverter F1 is connected to the output terminal of the first comparator unit A1. The control terminal of the first control switch M4 is connected to the input terminal of the inverter. The first pass terminal of the first control switch M4 is connected to the output line. Therefore, the first input terminal (non-inverting input terminal +) of the first voltage follower B1 is connected to the first input terminal of the first comparator unit A1. The second input terminal (inverting input terminal -) of the first voltage follower B1 is connected to the output terminal of the first voltage follower B1. The second pass terminal of the first control switch M4 is connected to the output terminal of the first voltage follower B1.

[0070] It should be noted that the display drive signal CK_OUT is generally a negative voltage (e.g., -14V) when low and a positive voltage (e.g., 30V) when high. If the display drive signal output unit 11 outputs the display drive signal CK_OUT ( Figure 8In the illustrated embodiment, when the display drive signal CK_OUT (output by the logic unit in the drive signal output unit 11) is greater than 0, it is a positive voltage, further determined to be a high level, with a logic of "1". At this time, the first selection switch M1 receives the high-level signal of logic "1" and is turned on. The display drive signal CK_OUT (output by the level conversion unit at this time) is input to the first comparison unit A1 through the first selection switch M1. The first comparison unit A1 compares the display drive signal CK_OUT with the first threshold voltage U1. If it is less than the first threshold voltage U1, it is determined that the display drive signal CK_OUT is in a voltage ramp-up state, that is, a low level jumps to a high level state, that is, it is on the rising edge. The first comparison unit A1 outputs a high-level signal to control the first pre-charge switch M3 to be turned on. The first current source I1 is used to pre-charge the parasitic capacitance C of the output line through the first pre-charge switch M3. It can be understood that the pre-charge is a constant current charging mode. When the first comparison unit A1 determines that the display drive signal CK_OUT is greater than the first threshold voltage U1, it determines that the display drive signal CK_OUT voltage has completed its ramp-up and is in a constant high-level state. At this time, the first comparison unit A1 outputs a low-level signal, which is converted into a high-level signal by the first inverter F1 and sent to the first control switch M4, controlling the first control switch M4 to conduct. The display drive signal CK_OUT (output by the level conversion unit) is then output through the first selection switch M1, the first voltage follower B1, and the first control switch M4, in a constant voltage output mode, with the display drive signal CK_OUT remaining at a constant high level. It should be noted that the first threshold voltage U1 is a positive voltage, which can be reasonably set according to the maximum positive voltage of the display drive signal CK_OUT. For example, if the maximum positive voltage of the display drive signal CK_OUT is 30V, the first threshold voltage U1 can be set to 29V, 29.5V, etc., without specific limitations. It is understandable that the closer the first threshold voltage U1 is to the maximum positive voltage of the signal under display drive, the more accurate the control of the pre-charging and constant voltage output process.

[0071] Furthermore, the logic selection unit 13 includes a second selection unit 132; the pre-charging unit 12 includes a second pre-charging unit 122, which is connected to the output line and the second selection unit 132; the output control unit 14 includes a second control unit 142, which is connected to the output line and the second selection unit 132.

[0072] The second selection unit 132 is connected to the drive signal output unit 11 and receives the display drive signal CK_OUT. The second selection unit 132 compares the display drive signal CK_OUT with the second threshold voltage U2. If the display drive signal CK_OUT is a negative voltage and is greater than the second threshold voltage U2, it determines that the display drive signal CK_OUT is at a falling edge. The second selection unit 132 outputs a precharge enable signal MOS_EN to the second precharge unit 122, controlling the second precharge unit 122 to precharge the parasitic capacitance C of the output line. If the display drive signal CK_OUT is less than the second threshold voltage U2, the second selection unit 132 controls the second control unit 142 to be in working state, thereby outputting the display drive signal CK_OUT.

[0073] This embodiment utilizes the cooperation of the second selection unit, the second pre-charge unit, and the second control unit to perform pre-charge when the display drive signal CK_OUT is at the falling edge, which can suppress peak current at the falling edge.

[0074] Furthermore, the second selection unit 132 includes a second selection switch M2, a second inverter F2, and a second comparison unit A2; the output terminal of the second inverter F2 is connected to the drive signal output unit 11, specifically, the output terminal of the second inverter F2 is connected to the logic unit in the drive signal output unit 11, the control terminal of the second selection switch M2 is connected to the input terminal of the second inverter F2, the first path terminal of the second selection switch M2 is connected to the drive signal output unit 11, specifically, it is connected to the level conversion unit in the drive signal output unit 11, the first input terminal (non-inverting input terminal +) of the second comparison unit A2 is connected to the second path terminal of the second selection switch M2, and the second input terminal (inverting input terminal -) of the second comparison unit A2 receives the second threshold voltage U2.

[0075] The second pre-charge unit 122 includes a second pre-charge switch M5 and a second current source I2. The control terminal of the second pre-charge switch M5 is connected to the output terminal of the second comparison unit A2, the first path terminal of the second pre-charge switch M5 is connected to the second current source I2, and the second path terminal of the second pre-charge switch M5 is connected to the output line.

[0076] The second control unit 142 includes: a second control switch M6, a third inverter F3, and a second voltage follower B2. The output terminal of the third inverter F3 is connected to the output terminal of the second comparator unit A2. The control terminal of the second control switch M6 is connected to the input terminal of the third inverter F3. The first pass terminal of the second control switch M6 is connected to the output line. Therefore, the first input terminal (non-inverting input terminal +) of the second voltage follower B2 is connected to the first input terminal (non-inverting input terminal +) of the second comparator unit A2. The second input terminal (inverting input terminal -) of the second voltage follower B2 is connected to the output terminal of the second voltage follower B2. The second pass terminal of the second control switch M6 is connected to the output terminal of the second voltage follower B2.

[0077] The display drive signal CK_OUT is typically a negative voltage (e.g., -14V) when low and a positive voltage (e.g., 30V) when high. If the display drive signal output unit 11 outputs the display drive signal CK_OUT ( Figure 8In the illustrated embodiment, when the display drive signal CK_OUT (output by the logic unit in the drive signal output unit 11) is less than 0, it is a negative voltage, further determined to be a low level, with a logic of "0". At this time, the output of the second inverter F2 is 0, and the input is 1. The second selection switch M2 receives a high-level signal of logic "1" and is turned on. The display drive signal CK_OUT (output by the level conversion unit at this time) is input to the second comparison unit A2 through the second selection switch M2. The second comparison unit A2 compares the display drive signal CK_OUT with the second threshold voltage U2. If it is greater than the second threshold voltage U2, it is determined that the display drive signal CK_OUT is in a voltage drop state, that is, a high level jumps to a low level state, that is, it is on the falling edge. The second comparison unit A2 outputs a high-level signal to control the second pre-charge switch M5 to be turned on. The second current source I2 is used to pre-charge the parasitic capacitance C of the output line through the second pre-charge switch M5. It can be understood that the pre-charge is a constant current charging mode. When the second comparison unit A2 determines that the display drive signal CK_OUT is less than the second threshold voltage U2, it determines that the voltage drop of the display drive signal CK_OUT has ended and it is in a constant low-level state. At this time, the second comparison unit A2 outputs a low-level signal, which is converted into a high-level signal by the third inverter F3 and sent to the second control switch M6, controlling the second control switch M6 to conduct. At this time, the display drive signal CK_OUT (which is output by the level conversion unit) is output from the output line through the second selection switch M2, the second voltage follower B2, and the second control switch M6. The output mode is a constant voltage output mode, and the display drive signal CK_OUT is constantly low. It should be noted that the second threshold voltage U2 is a negative voltage, which can be reasonably set according to the minimum negative voltage of the display drive signal CK_OUT. For example, if the minimum negative voltage of the display drive signal CK_OUT is -14V, the second threshold voltage U2 can be set to -13V, -13.5V, etc., without any specific limitation. Understandably, the closer the second threshold voltage U2 is to the minimum negative voltage of the signal under display drive, the more accurate the process control of pre-charging and constant voltage output will be.

[0078] It should be noted that the first pre-charging unit 121 and the second pre-charging unit 122 use different current sources for pre-charging; and the current source corresponding to the first pre-charging unit 121 and the current source corresponding to the second pre-charging unit 122 have the same current but opposite directions. Specifically, the first current source I1 and the second current source I2 have the same current magnitude but opposite directions.

[0079] The purpose of the display driving circuit in this embodiment is to delay the voltage abrupt changes at the rising and falling edges of the display driving signal CK_OUT waveform, effectively suppress peak current, improve liquid crystal polarization, and enhance display efficiency.

[0080] See Figure 9 , Figure 9 This is a schematic diagram of the structure of an embodiment of the display panel provided in this application. The display panel 30 of this application includes the display driving circuit 10 shown in any of the above embodiments. Specifically, the display panel 30 can be, for example, a liquid crystal display, which mainly consists of a backlight device and a display device. The backlight device is used to provide a light source, and the display device is used to change the polarization direction, light intensity, color, etc. of the light through liquid crystal components to achieve display. In addition, the display panel 30 also includes a control circuit, which is further divided into a backlight control circuit that controls the backlight device to provide a light source and a display control circuit that controls the display device. The display driving circuit 10 of this application is a part of the display control circuit. The display control circuit generally includes a timing controller and a gate driver. Figure 4 In the display driver circuit shown, the logic selection unit 13 can be, for example, a timing controller, while the drive signal output unit 11 and the precharge unit 12 can be located in the gate driver. Figure 8 The display driver circuit shown does not require a timing controller for timing control; therefore, Figure 8 The display driver circuit shown can be housed within the gate driver. Alternatively, it can be integrated into other components; this is not a limitation.

[0081] The display panel 30 of this application can precharge the parasitic capacitance C of the output line at the rising and falling edges of the display drive signal CK_OUT, which can reduce the voltage change amplitude when a constant high level or constant low level arrives, thereby reducing the amplitude of the spike current, effectively suppressing the spike current, improving liquid crystal polarization, and improving the display effect.

[0082] The above are merely embodiments of the present invention and do not limit the scope of patent protection of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A display driving circuit, characterized in that, include: A drive signal output unit, wherein the drive signal output unit is used to output a display drive signal; A pre-charging unit is connected to the output line of the drive signal output unit that outputs the display drive signal. The pre-charging unit is used to pre-charge the parasitic capacitance of the output line before the voltage of the display drive signal stabilizes. The pre-charging voltage is less than the drive voltage of the display drive signal. The pre-charging unit is used to pre-charge the parasitic capacitance of the output line at the rising edge of the display driving signal; and the pre-charging unit is used to pre-charge the parasitic capacitance of the output line at the falling edge of the display driving signal.

2. The display driving circuit according to claim 1, characterized in that, The display driving circuit further includes: A logic selection unit, which is connected to the drive signal output unit and the pre-charge unit, is used to enable the pre-charge unit to perform pre-charge based on the state of the display drive signal.

3. The display driving circuit according to claim 2, characterized in that, The pre-charging unit includes a current source and a pre-charging switch. The current source is used to provide a pre-charging current. The first path terminal of the pre-charging switch is connected to the current source, the second path terminal of the pre-charging switch is connected to the output line, and the control terminal of the pre-charging switch is connected to the logic selection unit. The pre-charging switch performs pre-charging in response to the pre-charging start signal output by the logic selection unit. In one cycle of the display driving signal, the rising edge of the precharge enable signal precedes the rising edge of the display driving signal, and the falling edge of the precharge enable signal is aligned with the rising edge of the display driving signal; the rising edge of the precharge enable signal precedes the falling edge of the display driving signal, and the falling edge of the precharge enable signal is aligned with the falling edge of the display driving signal.

4. The display driving circuit according to claim 2, characterized in that, The display driving circuit further includes an output control unit, which is connected to the logic selection unit and the output line; The logic selection unit is further configured to: compare the display driving signal with a threshold voltage to determine whether the display driving signal is at a rising edge or a falling edge; In response to the rising edge or falling edge, the logic selection unit outputs a precharge enable signal to control the precharge unit to perform precharge; In response to a non-rising edge or a non-falling edge, the logic selection unit controls the output control unit to be in an operating state and outputs the display drive signal.

5. The display driving circuit according to claim 4, characterized in that, The logic selection unit includes a first selection unit; the pre-charging unit includes a first pre-charging unit, which is connected to the output line and the first selection unit; the output control unit includes a first control unit, which is connected to the output line and the first selection unit. The first selection unit is connected to the drive signal output unit and receives the display drive signal; The first selection unit compares the display driving signal with a first threshold voltage. If the display driving signal is a positive voltage and less than the first threshold voltage, it determines that the display driving signal is at a rising edge. The first selection unit outputs the pre-charge enable signal to the first pre-charge unit, controlling the first pre-charge unit to pre-charge the parasitic capacitance of the output line. If the display driving signal is greater than the first threshold voltage, the first selection unit controls the first control unit to be in the working state, thereby outputting the display driving signal.

6. The display driving circuit according to claim 5, characterized in that, The logic selection unit includes a second selection unit; the pre-charging unit includes a second pre-charging unit, which is connected to the output line and the second selection unit; the output control unit includes a second control unit, which is connected to the output line and the second selection unit. The second selection unit is connected to the drive signal output unit and receives the display drive signal; the second selection unit compares the display drive signal with a second threshold voltage; if the display drive signal is a negative voltage and greater than the second threshold voltage, then it determines that the display drive signal is at a falling edge; the second selection unit outputs the precharge enable signal to the second precharge unit, controlling the second precharge unit to precharge the parasitic capacitance of the output line; If the display drive signal is less than the second threshold voltage, the second selection unit controls the second control unit to be in the working state, thereby outputting the display drive signal.

7. The display driving circuit according to claim 6, characterized in that, The first pre-charging unit and the second pre-charging unit use different current sources for pre-charging; and the current source corresponding to the first pre-charging unit and the current source corresponding to the second pre-charging unit have the same current but opposite direction.

8. The display driving circuit according to claim 1, characterized in that, The pre-charge voltage corresponding to the pre-charge is k times the driving voltage corresponding to the display driving signal, where k is less than 1. k is determined based on the driving capability of the display driving circuit and is positively correlated with the driving capability of the display driving circuit.

9. A display panel, characterized in that, include: The display driving circuit according to any one of claims 1 to 8.

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