An anti-radiation SRAM memory cell and integrated circuit board

Abstract

The application relates to the technical field of integrated circuit design, and discloses an anti-radiation SRAM storage unit and an integrated circuit board, which are used for solving the problems of many sensitive nodes and the inability to realize multi-node flip self-recovery of the SRAM storage unit in the prior art. The application is composed of four NMOS tubes to reinforce the main storage nodes. When any one of the main storage nodes is a low level, the NMOS tube is not a sensitive node due to the characteristics of the NMOS tube and cannot be bombarded by radiation particles. Another main storage node is matched with a pull-down tube through a logic keeper, and is recovered to the original state through the action of a pull-up tube after a single particle flip. The width-length ratios of the pull-down tubes in the two groups of cross-coupled inverters are greater than those of the pull-up tubes. When a single particle flip event occurs in a redundant storage node, the main storage node corresponding to the redundant storage node can keep the logic unchanged through the setting that the width-length ratio of the pull-down tube is greater than that of the pull-up tube, so that the flip self-recovery of the multi-node is realized.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to an SRAM memory cell. Background Technology

[0002] Modern civil aircraft flight control and avionics systems are highly complex, extensively employing complex electronic devices based on Static Random Access Memory (SRAM), such as microprocessors and Field Programmable Gate Arrays (FPGAs). As integrated circuit process dimensions continue to shrink, especially at 28nm and below, the feature size of SRAM cells decreases and operating voltages drop, making them increasingly sensitive to single-event effects induced by high-energy particles (such as cosmic rays and alpha particles), and highly susceptible to single-event upsets (SEUs). A SEU is the phenomenon where a single high-energy particle in space enters the sensitive region of a semiconductor device, causing the device's logic state to flip. In high-reliability applications such as aerospace and military, soft errors caused by SEUs can even lead to system crashes; therefore, robust design of critical circuits is essential.

[0003] Current technologies typically employ the method of adding multiple redundant storage nodes to improve the radiation resistance of storage cells. This method achieves self-recovery from single-node flips to some extent. However, this structure contains multiple sensitive nodes, and when bombarded by multiple high-energy particles simultaneously, multiple nodes may flip, exceeding its fault tolerance range and thus failing to achieve self-recovery.

[0004] Therefore, how to harden the storage nodes in SRAM storage cells to achieve self-recovery after a single or even multiple nodes experience a SEU (Self-Suspension Unlocking) and improve the radiation resistance of storage cells is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to solve the problem that SRAM memory cells in the current technology have many sensitive nodes and cannot achieve multi-node flip-over self-recovery. Therefore, this invention provides a radiation-resistant SRAM memory cell and an integrated circuit board to reinforce the memory nodes in the SRAM memory cell, realize flip-over self-recovery after a single node or even multiple nodes experience a SEU, and improve the radiation resistance of the memory cell.

[0006] To address the aforementioned technical problems, the present invention provides a radiation-resistant SRAM memory cell, comprising: a first cross-coupled inverter, a second cross-coupled inverter, a logic hold, and a transmitter;

[0007] The first cross-coupled inverter includes four PMOS transistors, namely two pull-up transistors and two pull-down transistors; the second cross-coupled inverter includes four NMOS transistors, namely two pull-up transistors and two pull-down transistors; the aspect ratio of the conductive channel of each pull-down transistor is greater than the aspect ratio of the conductive channel of each pull-up transistor.

[0008] In the first cross-coupled inverter, the gates and drains of the two pull-up transistors are cross-coupled to form the first memory node and the second memory node.

[0009] In the second cross-coupled inverter, the gates and drains of the two pull-down transistors are cross-coupled to form the third and fourth memory nodes;

[0010] The pull-up transistors in the second cross-coupled inverter are connected to the first storage node and the second storage node in the first cross-coupled inverter, respectively.

[0011] The logic hold includes two NMOS transistors, which are respectively connected to two pull-down transistors in the first cross-coupled inverter, and are also connected to the third and fourth memory nodes in the second cross-coupled inverter, in order to maintain the logic consistency between the first memory node and the third memory node, and the logic consistency between the second memory node and the fourth memory node.

[0012] The transmitter includes two NMOS transistors for connecting the second cross-coupled inverter to the word line and bit line connection lines.

[0013] Preferably, the pull-up transistors in the first cross-coupled inverter are the first PMOS transistor P1 and the second PMOS transistor P2, and the pull-down transistors are the third PMOS transistor P3 and the fourth PMOS transistor P4.

[0014] The pull-up transistors in the second cross-coupled inverter are the first NMOS transistor N1 and the second NMOS transistor N2, and the pull-down transistors are the third NMOS transistor N3 and the fourth NMOS transistor N4;

[0015] The two NMOS transistors of the logic hold are the fifth NMOS transistor N5 and the sixth NMOS transistor N6;

[0016] The two NMOS transistors of the transmitter are the seventh NMOS transistor N7 and the eighth NMOS transistor N8;

[0017] The drain of the first PMOS transistor P1 is connected to the first memory node, the gate is connected to the second memory node, the source is connected to the power supply, and the substrate is connected to the power supply.

[0018] The drain of the second PMOS transistor P2 is connected to the second memory node, the gate is connected to the first memory node, the source is connected to the power supply, and the substrate is connected to the power supply.

[0019] The drain of the third PMOS transistor P3 is grounded, its gate is connected to the source of the fifth NMOS transistor N5, the source is connected to the first memory node, and the substrate is grounded.

[0020] The drain of the fourth PMOS transistor P4 is grounded, the gate is connected to the source of the sixth NMOS transistor N6, the source is connected to the second memory node, and the substrate is grounded.

[0021] The drain of the first NMOS transistor N1 is connected to the power supply, the gate is connected to the first memory node, the source is connected to the third memory node, and the substrate is connected to the power supply.

[0022] The drain of the second NMOS transistor N2 is connected to the power supply, the gate is connected to the second memory node, the source is connected to the fourth memory node, and the substrate is connected to the power supply.

[0023] The drain of the third NMOS transistor N3 is connected to the third memory node, the gate is connected to the fourth memory node, the source is grounded, and the substrate is grounded.

[0024] The drain of the fourth NMOS transistor N4 is connected to the fourth memory node, the gate is connected to the third memory node, the source is grounded, and the substrate is grounded.

[0025] The drain of the fifth NMOS transistor N5 is connected to the third memory node, the gate is connected to the fourth memory node, and the substrate is connected to the gate of the third PMOS transistor P3.

[0026] The drain of the sixth NMOS transistor N6 is connected to the fourth memory node, the gate is connected to the third memory node, and the substrate is connected to the gate of the fourth PMOS transistor P4.

[0027] The drain of the seventh NMOS transistor N7 is connected to the third memory node, the gate is connected to the word line WL, the source is connected to the bit line BL, and the substrate is connected to the bit line BL.

[0028] The drain of the eighth NMOS transistor N8 is connected to the complementary bit line BLB, the gate is connected to the word line WL, the source is connected to the fourth memory node, and the substrate is connected to the complementary bit line BLB.

[0029] Preferably, the width-to-length ratio of the conductive channels of the first PMOS transistor P1 and the second PMOS transistor P2 is the same, and the width-to-length ratio of the conductive channels of the third PMOS transistor P3 and the fourth PMOS transistor P4 is the same.

[0030] The first NMOS transistor N1 and the second NMOS transistor N2 have the same width-to-length ratio of their conductive channels, and the third NMOS transistor N3 and the fourth NMOS transistor N4 have the same width-to-length ratio of their conductive channels.

[0031] Preferably, each pull-up transistor is a single-fin field-effect transistor.

[0032] Preferably, the width-to-length ratio of the conductive channels of the third PMOS transistor P3 and the fourth PMOS transistor P4 is twice that of the first PMOS transistor P1 and the second PMOS transistor P2.

[0033] The width-to-length ratio of the conductive channels of the third NMOS transistor N3 and the fourth NMOS transistor N4 is twice that of the first NMOS transistor N1 and the second NMOS transistor N2;

[0034] The width-to-length ratio of the conductive channels of the seventh NMOS transistor N7 and the eighth NMOS transistor N8 is twice that of the third NMOS transistor N3 and the fourth NMOS transistor N4.

[0035] Preferably, during a read operation, both the bit line BL and the complementary bit line BLB are pre-charged to a high level. When the word line WL is at a high level, a differential voltage signal is generated between the bit line BL and the complementary bit line BLB, and the storage unit outputs the stored logic data.

[0036] Preferably, during a write operation, the bit line BL is preset to a high level, the complementary bit line BLB is preset to a low level, and when the word line WL is high, the first storage node and the third storage node are written with a high level, while the second storage node and the fourth storage node are written with a low level.

[0037] Preferably, during a write operation, the bit line BL is preset to a low level, the complementary bit line BLB is preset to a high level, and when the word line WL is high, the first storage node and the third storage node are written to a low level, while the second storage node and the fourth storage node are written to a high level.

[0038] Preferably, both the bit line BL and the complementary bit line BLB are precharged to a high level, and the memory cell remains in its initial state when the word line WL is at a low level.

[0039] To address the aforementioned technical problems, the present invention also provides an integrated circuit board, including the aforementioned radiation-hardened SRAM memory cell, and further including a differential amplifier, wherein the two input terminals of the differential amplifier are respectively connected to bit lines BL and BLB, for reading the differential signal between bit lines BL and BLB.

[0040] This invention provides a radiation-resistant SRAM memory cell. Addressing the problem of current SRAM memory cells having numerous sensitive nodes and lacking self-recovery during multi-node flips, this application uses two sets of cross-coupled inverters to construct the main memory nodes (third and fourth nodes) and corresponding redundant memory nodes (first and second nodes). This application uses four NMOS transistors to form a polarity-hardening device to reinforce the main memory nodes. When any main memory node is at a low level, the characteristics of the NMOS transistors prevent it from becoming a sensitive node when bombarded by radiated particles, thus improving the node's radiation resistance. The other main memory node, through the cooperation of a logic holder and a pull-down transistor, recovers to its original state after a single-event flip (SET) event via a pull-up transistor. When a redundant memory node experiences a SET event, the logic of the corresponding main memory node remains unchanged by setting the pull-down transistor's channel width-to-length ratio to be greater than that of the pull-up transistor, thereby achieving self-recovery during the redundant memory node's flip. Furthermore, the aspect ratio of the conductive channel of the pull-down diode in both sets of cross-coupled inverters is greater than that of the pull-up diode, which enables multi-node flip-over self-recovery and improves the radiation resistance of multi-node memory cells.

[0041] The integrated circuit board provided by this invention has the same beneficial effects as the radiation-resistant SRAM memory cell described above, so it will not be described in detail here. Attached Figure Description

[0042] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 A circuit diagram of a radiation-resistant SRAM memory cell provided in an embodiment of the present invention;

[0044] Figure 2 A simulation waveform diagram of read / write operation of a radiation-resistant SRAM memory cell provided in an embodiment of this application;

[0045] Figure 3 A simulation waveform diagram of a radiation-resistant SRAM memory cell under single-particle incident radiation, provided in an embodiment of this application;

[0046] Figure 4 A simulation waveform diagram of a single-particle incident event for another radiation-resistant SRAM memory cell provided in this application embodiment;

[0047] The attached diagram is labeled as follows: first storage node S0, second storage node S1, third storage node Q, and fourth storage node QN. Detailed Implementation

[0048] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0049] The core of this invention is to provide a radiation-resistant SRAM memory cell and an integrated circuit board, which are used to reinforce the memory nodes in the SRAM memory cell, realize self-recovery after a single node or even multiple nodes experience a SEU, and improve the radiation resistance of the memory cell.

[0050] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0051] Figure 1 A circuit diagram of a radiation-resistant SRAM memory cell provided in an embodiment of the present invention is shown below. Figure 1 As shown, the memory cell includes: a first cross-coupled inverter, a second cross-coupled inverter, a logic hold, and a transmitter;

[0052] The first cross-coupled inverter includes four PMOS transistors, namely two pull-up transistors and two pull-down transistors; the second cross-coupled inverter includes four NMOS transistors, namely two pull-up transistors and two pull-down transistors; the aspect ratio of the conductive channel of the pull-down transistors is greater than that of the conductive channel of the pull-up transistors.

[0053] In the first cross-coupled inverter, the gates and drains of the two pull-up transistors are cross-coupled to form the first memory node S0 and the second memory node S1.

[0054] In the second cross-coupled inverter, the gates and drains of the two pull-down transistors are cross-coupled to form the third memory node Q and the fourth memory node QN;

[0055] The pull-up transistors in the second cross-coupled inverter are connected to the first storage node S0 and the second storage node S1 in the first cross-coupled inverter, respectively.

[0056] The logic hold includes two NMOS transistors, which are respectively connected to the two pull-down transistors in the first cross-coupled inverter, and are also connected to the third storage node Q and the fourth storage node QN in the second cross-coupled inverter, in order to maintain the logic consistency of the first storage node S0 and the third storage node Q, and the logic consistency of the second storage node S1 and the fourth storage node QN.

[0057] The transmitter includes two NMOS transistors used to connect the second cross-coupled inverter to the word line and bit line connections.

[0058] The radiation-hardened SRAM memory cell provided in this application is an extension of the traditional 6T SRAM structure. This memory cell employs a dual-layer cross-coupled structure design, consisting of 12 transistors, including 4 PMOS transistors and 8 NMOS transistors. Structurally, the memory cell can be divided into two symmetrical parts: the upper part consists of a first cross-coupled inverter formed by two pull-up PMOS transistors and two pull-down PMOS transistors, forming two complementary memory nodes, S0 and S1; the lower part consists of a second cross-coupled structure formed by two pull-up NMOS transistors and two pull-down NMOS transistors, forming two complementary memory nodes, Q and QN. The two sets of cross-coupled inverters are connected by logic holders to ensure that the logic of the first memory node S0 and the third memory node Q remains consistent, and the logic of the second memory node S1 and the fourth memory node QN remains consistent. The pull-up transistors in the second cross-coupled inverter are connected to the first memory node S0 and the second memory node S1 in the first cross-coupled inverter, respectively, enabling self-recovery of the memory node flips during a single-event upset. In both sets of cross-coupled inverters, the aspect ratio of the pull-down conductive channels is greater than that of the pull-up conductive channels. This makes the memory node less susceptible to changes in the conduction state of a single transistor connected to that node, thus improving its radiation resistance. The transmitter consists of two NMOS transistors, used to connect the second cross-coupled inverter to the word lines and bit lines, enabling read and write functions.

[0059] This embodiment provides a specific circuit connection method. Specifically, the pull-up transistors in the first cross-coupled inverter are the first PMOS transistor P1 and the second PMOS transistor P2, and the pull-down transistors are the third PMOS transistor P3 and the fourth PMOS transistor P4; the pull-up transistors in the second cross-coupled inverter are the first NMOS transistor N1 and the second NMOS transistor N2, and the pull-down transistors are the third NMOS transistor N3 and the fourth NMOS transistor N4; the two NMOS transistors in the logic hold are the fifth NMOS transistor N5 and the sixth NMOS transistor N6; and the two NMOS transistors in the transmitter are the seventh NMOS transistor N7 and the eighth NMOS transistor N8. In this configuration, the drain of transistor P1 is connected to the first memory node S0, the gate is connected to the second memory node S1, the source is connected to the power supply VDD, and the substrate is connected to the power supply VDD; the drain of the second PMOS transistor P2 is connected to the second memory node S1, the gate is connected to the first memory node S0, the source is connected to the power supply VDD, and the substrate is connected to the power supply VDD; the drain of the third PMOS transistor P3 is grounded, the gate is connected to the source of the fifth NMOS transistor N5, the source is connected to the first memory node S0, and the substrate is grounded; the drain of the fourth PMOS transistor P4 is grounded, the gate is connected to the source of the sixth NMOS transistor N6, the source is connected to the second memory node S1, and the substrate is grounded; the drain of the first NMOS transistor N1 is connected to the power supply VDD, the gate is connected to the first memory node S0, the source is connected to the third memory node Q, and the substrate is connected to the power supply VDD; the drain of the second NMOS transistor N2 is connected to the power supply VDD, the gate is connected to the second memory node S1, and the source is connected to the fourth memory node QN. The substrate is connected to the power supply VDD; the drain of the third NMOS transistor N3 is connected to the third memory node Q, the gate is connected to the fourth memory node QN, the source is grounded, and the substrate is grounded; the drain of the fourth NMOS transistor N4 is connected to the fourth memory node QN, the gate is connected to the third memory node Q, the source is grounded, and the substrate is grounded; the drain of the fifth NMOS transistor N5 is connected to the third memory node Q, the gate is connected to the fourth memory node QN, and the substrate is connected to the gate of the third PMOS transistor P3; the drain of the sixth NMOS transistor N6 is connected to the fourth memory node QN, the gate is connected to the third memory node Q, and the substrate is connected to the gate of the fourth PMOS transistor P4; the drain of the seventh NMOS transistor N7 is connected to the third memory node Q, the gate is connected to the word line WL, the source is connected to the bit line BL, and the substrate is connected to the bit line BL; the drain of the eighth NMOS transistor N8 is connected to the complementary bit line BLB, the gate is connected to the word line WL, the source is connected to the fourth memory node QN, and the substrate is connected to the complementary bit line BLB.

[0060] Based on the above structure, the working principle of the memory cell is as follows: During the hold phase, both bit line BL and complementary bit line BLB are pre-charged to a high level. When word line WL is low, the memory cell remains in its initial state and does not operate. During the read operation, both bit line BL and complementary bit line BLB are pre-charged to a high level. When word line WL is high, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 of the transmitter are turned on. If the logic data stored in the memory cell is "0", then S0=Q=0, S1=QN=1. Bit line BL discharges to ground through the seventh NMOS transistor N7 and the third NMOS transistor N3, generating a differential voltage signal between bit line BL and complementary bit line BLB. This signal can be read by a differential amplifier outside the memory cell. Similarly, if the logic data stored in the memory cell is "1", then S0=Q=1, S1=QN=0, the complementary bit line BLB discharges to ground through the eighth NMOS transistor N8 and the fourth NMOS transistor N4, and a differential voltage signal is generated between the bit line BL and the complementary bit line BLB. This signal can be read by the differential amplifier outside the memory cell.

[0061] During a write operation, when writing a "0", the bit line BL is preset to low and the complementary bit line BLB is preset to high. When the word line WL is high, the first memory node S0 and the third memory node Q are written to low, and the second memory node S1 and the fourth memory node QN are written to high. When writing a "1", the bit line BL is preset to high and the complementary bit line BLB is preset to low. When the word line WL is high, the first memory node S0 and the third memory node Q are written to high, and the second memory node S1 and the fourth memory node QN are written to low.

[0062] In practical implementation, to facilitate the manufacturing of memory cells, the width-to-length ratio of the conductive channels of the first PMOS transistor P1 and the second PMOS transistor P2 is the same, and the width-to-length ratio of the conductive channels of the third PMOS transistor P3 and the fourth PMOS transistor P4 is the same; the width-to-length ratio of the conductive channels of the first NMOS transistor N1 and the second NMOS transistor N2 is the same, and the width-to-length ratio of the conductive channels of the third NMOS transistor N3 and the fourth NMOS transistor N4 is the same.

[0063] To enhance the radiation resistance of radiation-hardened SRAM memory cells, each pull-up transistor can be a single-fin field-effect transistor. When the aspect ratio of the pull-down transistor's conductive channel is greater than that of the pull-up transistor's conductive channel, the aspect ratio of the conductive channels of the third PMOS transistor P3 and the fourth PMOS transistor P4 is twice that of the first PMOS transistor P1 and the second PMOS transistor P2; the aspect ratio of the conductive channels of the third NMOS transistor N3 and the fourth NMOS transistor N4 is twice that of the first NMOS transistor N1 and the second NMOS transistor N2. For the transmitter, the aspect ratio of the conductive channels of the seventh NMOS transistor N7 and the eighth NMOS transistor N8 is twice that of the third NMOS transistor N3 and the fourth NMOS transistor N4.

[0064] This application provides a radiation-resistant SRAM memory cell. Addressing the problem of existing SRAM memory cells having numerous sensitive nodes and lacking self-recovery during multi-node flips, this application uses two sets of cross-coupled inverters to form the main memory node (third memory node Q and fourth memory node QN), and corresponding redundant memory nodes (first memory node S0 and second memory node S1). This application uses four NMOS transistors to form a polarity-hardening device to reinforce the main memory node. When any main memory node is at a low level, the characteristics of the NMOS transistors prevent it from becoming a sensitive node when bombarded by radiated particles, thus improving the node's radiation resistance. The other main memory node, through the cooperation of a logic holder and a pull-down transistor, recovers to its original state after a single-event flip (SET) event via a pull-up transistor. When a redundant memory node experiences a SET event, the logic of the corresponding main memory node remains unchanged by setting the pull-down transistor's channel width-to-length ratio to be greater than that of the pull-up transistor, thereby achieving self-recovery during the redundant memory node's flip. Furthermore, the aspect ratio of the conductive channel of the pull-down diode in both sets of cross-coupled inverters is greater than that of the pull-up diode, which enables multi-node flip-over self-recovery and improves the radiation resistance of multi-node memory cells.

[0065] To verify the functional correctness of the radiation-resistant SRAM memory cell provided in this application, timing analysis of read and write operations was performed on the Hspice simulation platform. Figure 2 A simulation waveform diagram of read / write operation of a radiation-resistant SRAM memory cell provided in this application embodiment is shown below. Figure 2As shown, during the data write operation, the bit lines are first preset: bit line BL is preset to high level, and complementary bit line BLB is preset to low level. When the simulation time reaches 50ns, the word line WL signal is pulled high, triggering the write process of the memory cell and realizing the data conversion from logic "0" to logic "1". At this time, the internal state of the memory cell is: the third memory node Q of the primary memory node outputs a high level, the fourth memory node QN outputs a low level, and the first memory node S0 and the second memory node S1 of the redundant memory nodes maintain a high level and a low level, respectively. When the word line WL signal returns to low level, the memory cell is electrically isolated from the external bit line system to ensure the stable maintenance of internal data. During the verification of the data read operation, bit line BL and complementary bit line BLB are precharged to high level before reading. At 80ns, the read timing is initiated by pulling the word line WL signal high. At this time, a differential voltage signal is generated between the bit lines BL and BLB. After processing by the differential amplifier in the external readout circuit, the stored logic "1" data is successfully output. Using the same verification method, the memory cell successfully completes the write operation of logic "0" at 110ns and completes the read verification of logic "0" at 160ns. The entire simulation process fully demonstrates the operating timing characteristics of the radiation-hardened SRAM memory cell provided in this application, and fully proves the reliability and correctness of this application in terms of the three core functions of data storage, reading and writing.

[0066] To verify the capability of the radiation-resistant SRAM memory cell provided in this application in the face of SEU events, SEU events occurring in each memory node of the memory cell were analyzed and verified through simulation. Specific scenarios include:

[0067] I. Analyze the behavior of storage nodes Q, QN, S0, and S1 after being bombarded by a single-event bombardment when Q=S0=1 and QN=S1=0:

[0068] 1) When the radiation particles bombard the fourth storage node QN, only a "0->0" transient pulse can be generated at node QN, which will not change the logic value of node QN. Therefore, node QN is not a sensitive node at this time.

[0069] 2) When the third storage node Q experiences a SEU, Q changes from logic "1" to logic "0". At this time, the sixth NMOS transistor N6 and the fourth NMOS transistor N4 will be temporarily turned off, but QN will not change. Q will be restored to 1 through the first NMOS transistor N1.

[0070] 3) When the first storage node S0 experiences a SEU, S0 changes from logic "1" to logic "0". This will temporarily turn off the first NMOS transistor N1 and turn on the second PMOS transistor P2. At this time, P2 and P4 are turned on at the same time. However, the width-to-length ratio of the conductive channel of P4 is greater than that of the conductive channel of P2. The potential of node S1 will not change. The temporary shutdown of N1 will not change the potential of Q. The node value of Q remains unchanged at "1". Since node S1 remains unchanged at "0", S0 is eventually restored by the conducting P1.

[0071] 4) When the second storage node S1 experiences a SEU, S1 changes from logic "0" to logic "1", causing N2 to turn on and P1 to turn off. At this time, N2 and N4 are turned on. Since the width-to-length ratio of the conductive channel of N4 is greater than that of N2, the logic value of QN remains unchanged; and because P4 is turned on, P2 is turned off, causing the potential of S1 to return to 0.

[0072] 5) When S0 and S1 both experience SEU, since the width-to-length ratio of the pull-down transistor's conductive channel is greater than that of the pull-up transistor, the QN node will not change. Eventually, the S0 and S1 nodes will be restored to their normal potentials through P4.

[0073] Figure 3 A simulation waveform diagram of a radiation-resistant SRAM memory cell under single-particle incident radiation, provided for an embodiment of this application, is shown below. Figure 3 As shown, the radiation-hardened SRAM memory cell has three sensitive nodes depending on the storage conditions. The response of high-energy particles to these sensitive nodes is simulated using current injection. The node recovery simulation results are as follows: Figure 3 As shown. Specifically, the simulation process first sets up a radiation-hardened SRAM memory cell to complete the processes of writing "1", reading "1", writing "0", and reading "0". A current source is injected at the sensitive node to characterize the effect on the memory cell circuit under the condition of LET=0.8PC / um. Figure 3As shown, the radiation-hardened SRAM memory cell completes a data write operation of "1" at 50 ns. Subsequently, a single-particle pulse injection is performed on the sensitive node S1 at 60 ns to simulate the single-particle bombardment response of a high-energy particle on the node. Node S1 exhibits a rapid voltage rise to above a high level but then recovers to its original low level, indicating that node S1 has complete self-recovery capability under this energy bombardment. Simultaneously, the simulation results also show that the bombardment of node S1 did not cause the other three nodes to flip. Similarly, pulse injections are performed on nodes QN and S0 at 120 ns and 150 ns respectively, and the memory cell also exhibits good self-recovery performance, both recovering to their original logic state. The radiation-hardened SRAM memory cell completes a data write operation of "0" at 110 ns, and the stored state of the nodes within the memory cell can still flip normally. In summary, the simulation results show that when Q is at a low potential, the sensitive nodes QN, S0, and S1 of the radiation-resistant SRAM memory cell can recover from their flips to their original logic levels. The recovery process is consistent with the behavior analysis of the above memory nodes during single-event flips. Therefore, the radiation-resistant SRAM memory cell has the ability to recover from the flips of the sensitive nodes QN, S0, and S1.

[0074] II. Analyze the behavior of storage nodes Q, QN, S0, and S1 after being bombarded by a single-event bombardment when Q=S0=0 and QN=S1=1:

[0075] 1) When a radiating particle bombards the third storage node Q, only a "0->0" transient pulse can be generated at Q, which does not change the logic value of node Q. Therefore, node Q is not a sensitive node at this time.

[0076] 2) When node QN experiences a SEU, node QN changes from logic "1" to logic "0". At this time, N3 and N5 will be temporarily shut down, but Q will not change. Q will be restored to 1 after N2.

[0077] 3) When a SEU occurs at node S0, node S0 changes from logic "0" to logic "1", causing N1 to turn on and P2 to turn off. At this time, N1 and N3 are turned on. Since the width-to-length ratio of the conductive channel of N3 is greater than that of N1, the logic value of node Q remains unchanged; and because P3 is turned on, P1 is turned off, causing the potential of S0 to return to 0.

[0078] 4) When node S1 experiences a SEU, S1 changes from logic "1" to logic "0". This will temporarily turn off N2 and turn on P1. At this time, P1 and P3 are turned on at the same time. However, the width-to-length ratio of the conductive channel of P3 is greater than that of P1. The potential of node S0 will not change. The temporary shutdown of N2 will not change the potential of QN. The value of node QN remains unchanged at "1". Since node S0 remains unchanged at "0", S1 is eventually restored by the conducting transistor P2.

[0079] 5) When nodes S0 and S1 both experience SEU, since the width-to-length ratio of the pull-down channel is greater than that of the pull-up channel, node Q will not change. Eventually, nodes S0 and S1 will be restored to normal potential through P3.

[0080] Figure 4 The simulation waveform of a single-particle incident event for another radiation-resistant SRAM memory cell provided in this application embodiment is shown below. Figure 3 Similarly, when the initial potentials of nodes Q and S0 are both high, and the logic states of nodes QN and S1 are low, a single-event incident simulation is performed. The radiation-resistant SRAM memory cell can also ensure that sensitive nodes Q, S0, and S1 have the ability to flip and recover while ensuring normal read and write operations. The recovery process is completely consistent with the behavior analysis of the memory nodes when they undergo single-event flips.

[0081] In summary, the radiation-hardened SRAM memory cell provided in this application exhibits high symmetry and consistency in both complementary storage states. Whether storing "0" or "1", the memory cell ensures normal read and write operations while guaranteeing rapid self-recovery of the sensitive section, with the recovery process and analysis results being completely consistent. This symmetrical radiation-hardened performance design eliminates storage state dependence, ensuring reliable SEU protection under any data mode, further demonstrating the effectiveness and robustness of the radiation-hardened SRAM memory cell.

[0082] Finally, this application also provides an integrated circuit board, which includes the radiation-hardened SRAM memory cell mentioned in the above embodiments, and also includes a differential amplifier, wherein the two input terminals of the differential amplifier are respectively connected to bit lines BL and BLB, for reading the differential signal between bit lines BL and BLB.

[0083] In specific implementations, the integrated circuit board can be an integrated circuit system with high reliability requirements, such as an FPGA, processor, or memory controller. Its effect is similar to that of the above embodiments, and will not be described again here.

[0084] The radiation-resistant SRAM memory cell and integrated circuit board provided by this invention have been described in detail above. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this invention.

Claims

1. A radiation-resistant SRAM memory cell, characterized in that, include: First cross-coupled inverter, second cross-coupled inverter, logic hold, and transmitter; The first cross-coupled inverter includes four PMOS transistors, namely two pull-up transistors and two pull-down transistors; the second cross-coupled inverter includes four NMOS transistors, namely two pull-up transistors and two pull-down transistors; the aspect ratio of the conductive channel of each pull-down transistor is greater than the aspect ratio of the conductive channel of each pull-up transistor. In the first cross-coupled inverter, the gates and drains of the two pull-up transistors are cross-coupled to form the first memory node and the second memory node. In the second cross-coupled inverter, the gates and drains of the two pull-down transistors are cross-coupled to form the third and fourth memory nodes; The pull-up transistors in the second cross-coupled inverter are connected to the first storage node and the second storage node in the first cross-coupled inverter, respectively. The logic hold includes two NMOS transistors, which are respectively connected to two pull-down transistors in the first cross-coupled inverter, and are also connected to the third and fourth memory nodes in the second cross-coupled inverter, in order to maintain the logic consistency between the first memory node and the third memory node, and the logic consistency between the second memory node and the fourth memory node. The transmitter includes two NMOS transistors for connecting the second cross-coupled inverter to the word line and bit line connection lines; The pull-up transistors in the first cross-coupled inverter are the first PMOS transistor P1 and the second PMOS transistor P2, and the pull-down transistors are the third PMOS transistor P3 and the fourth PMOS transistor P4. The pull-up transistors in the second cross-coupled inverter are the first NMOS transistor N1 and the second NMOS transistor N2, and the pull-down transistors are the third NMOS transistor N3 and the fourth NMOS transistor N4; The two NMOS transistors of the logic hold are the fifth NMOS transistor N5 and the sixth NMOS transistor N6; The two NMOS transistors of the transmitter are the seventh NMOS transistor N7 and the eighth NMOS transistor N8; The drain of the first PMOS transistor P1 is connected to the first memory node, the gate is connected to the second memory node, the source is connected to the power supply, and the substrate is connected to the power supply. The drain of the second PMOS transistor P2 is connected to the second memory node, the gate is connected to the first memory node, the source is connected to the power supply, and the substrate is connected to the power supply. The drain of the third PMOS transistor P3 is grounded, the gate is connected to the source of the fifth NMOS transistor N5, the source is connected to the first memory node, and the substrate is grounded. The drain of the fourth PMOS transistor P4 is grounded, its gate is connected to the source of the sixth NMOS transistor N6, the source is connected to the second memory node, and the substrate is grounded. The drain of the first NMOS transistor N1 is connected to the power supply, the gate is connected to the first memory node, the source is connected to the third memory node, and the substrate is connected to the power supply. The drain of the second NMOS transistor N2 is connected to the power supply, the gate is connected to the second memory node, the source is connected to the fourth memory node, and the substrate is connected to the power supply. The drain of the third NMOS transistor N3 is connected to the third memory node, the gate is connected to the fourth memory node, the source is grounded, and the substrate is grounded. The drain of the fourth NMOS transistor N4 is connected to the fourth memory node, the gate is connected to the third memory node, the source is grounded, and the substrate is grounded. The drain of the fifth NMOS transistor N5 is connected to the third memory node, the gate is connected to the fourth memory node, and the substrate is connected to the gate of the third PMOS transistor P3. The drain of the sixth NMOS transistor N6 is connected to the fourth memory node, the gate is connected to the third memory node, and the substrate is connected to the gate of the fourth PMOS transistor P4. The drain of the seventh NMOS transistor N7 is connected to the third memory node, the gate is connected to the word line WL, the source is connected to the bit line BL, and the substrate is connected to the bit line BL. The drain of the eighth NMOS transistor N8 is connected to the complementary bit line BLB, the gate is connected to the word line WL, the source is connected to the fourth memory node, and the substrate is connected to the complementary bit line BLB.

2. The radiation-resistant SRAM memory cell according to claim 1, characterized in that, The first PMOS transistor P1 and the second PMOS transistor P2 have the same width-to-length ratio of their conductive channels, and the third PMOS transistor P3 and the fourth PMOS transistor P4 have the same width-to-length ratio of their conductive channels. The first NMOS transistor N1 and the second NMOS transistor N2 have the same width-to-length ratio of their conductive channels, and the third NMOS transistor N3 and the fourth NMOS transistor N4 have the same width-to-length ratio of their conductive channels.

3. The radiation-resistant SRAM memory cell according to claim 2, characterized in that, Each pull-up transistor is a single-fin field-effect transistor.

4. The radiation-resistant SRAM memory cell according to claim 3, characterized in that, The width-to-length ratio of the conductive channels of the third PMOS transistor P3 and the fourth PMOS transistor P4 is twice that of the first PMOS transistor P1 and the second PMOS transistor P2. The width-to-length ratio of the conductive channels of the third NMOS transistor N3 and the fourth NMOS transistor N4 is twice that of the first NMOS transistor N1 and the second NMOS transistor N2; The width-to-length ratio of the conductive channels of the seventh NMOS transistor N7 and the eighth NMOS transistor N8 is twice that of the third NMOS transistor N3 and the fourth NMOS transistor N4.

5. The radiation-resistant SRAM memory cell according to claim 1, characterized in that, During a read operation, both the bit line BL and the complementary bit line BLB are precharged to a high level. When the word line WL is high, a differential voltage signal is generated between the bit line BL and the complementary bit line BLB, and the storage unit outputs the stored logic data.

6. The radiation-resistant SRAM memory cell according to claim 1, characterized in that, During a write operation, the bit line BL is preset to a high level, the complementary bit line BLB is preset to a low level, and when the word line WL is high, the first storage node and the third storage node are written with a high level, while the second storage node and the fourth storage node are written with a low level.

7. The radiation-resistant SRAM memory cell according to claim 1, characterized in that, During a write operation, the bit line BL is preset to low level, the complementary bit line BLB is preset to high level, and when the word line WL is high level, the first storage node and the third storage node are written to low level, while the second storage node and the fourth storage node are written to high level.

8. The radiation-resistant SRAM memory cell according to claim 1, characterized in that, Both the bit line BL and the complementary bit line BLB are precharged to a high level, and the memory cell remains in its initial state when the word line WL is at a low level.

9. An integrated circuit board, characterized in that, The device includes the radiation-resistant SRAM memory cell according to any one of claims 1 to 8, and further includes a differential amplifier, wherein the two input terminals of the differential amplifier are respectively connected to bit lines BL and BLB for reading the differential signal between bit lines BL and BLB.

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