Memory management method and memory controller

Abstract

This disclosure discloses a memory management method and a memory controller. The method is applied to a storage device configured with memory modules, and includes: performing multiple operation stages on the memory modules; in each operation stage, sequentially performing read, erase, and write operations on each superblock according to the order of multiple superblocks in the memory module. By improving the execution order of operations and utilizing inter-chip parallel processing capabilities, this disclosure can reduce drastic temperature changes, shorten operation time, and improve operational efficiency and reliability.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, and in particular to a memory management method and a corresponding memory controller. Background Technology

[0002] With the development of storage technology, multi-die (DIE) memory devices are widely used in modern storage systems. To ensure the reliability and lifespan of these devices, aging tests are required before they leave the factory to screen out defective products as early as possible.

[0003] In aging tests of storage devices, traditional testing methods typically employ a chip-by-chip approach, performing an erase operation first, then a write operation, and finally a read operation on the entire storage device. This erase-write-read sequence causes drastic temperature fluctuations within the storage device due to the continuous execution of the same type of high-power operations. The temperature rise during consecutive erase operations is greater than that during consecutive write operations, which in turn is greater than that during consecutive read operations. This results in dramatic temperature variations within the storage device, impacting the stability of the testing environment. Summary of the Invention

[0004] In view of this, the present disclosure provides a memory management method and a memory controller, which solves the technical problem of drastic temperature changes in the prior art by improving the execution order of test operations and optimizing the parallel processing mechanism.

[0005] This disclosure provides one or more embodiments of a memory management method applied to a storage device configured with a memory module. The method includes: performing multiple operation stages on the memory module; in each operation stage, according to the order of multiple superblocks of the memory module, sequentially performing a read operation, an erase operation, and a write operation on each superblock, wherein each superblock includes a physical block of different chips in the memory module.

[0006] This disclosure provides one or more embodiments of a memory controller for controlling a storage device configured with a memory module. The memory controller includes: a memory interface control circuit for electrically connecting to the memory module; and a processor electrically connected to the memory interface control circuit, wherein the processor is further electrically connected to a connection interface circuit of the storage device for electrically connecting to a host system. The processor is configured to: perform multiple operation phases on the memory module; in each operation phase, according to the order of multiple superblocks of the memory module, sequentially perform a read operation, an erase operation, and a write operation on each superblock, wherein each superblock includes a physical block of different chips in the memory module.

[0007] Based on the above, the memory management method and memory controller provided in this disclosure, by adjusting the order of test operations to read, erase, and write, can reduce drastic temperature changes caused by continuous high-power operations of the same type compared to the traditional erase, write, and read order. By performing read, erase, and write operations on a superblock basis, compared to the traditional method of operating on the entire chip, it is possible to achieve a distributed configuration of power load in time and space, avoiding a large-scale concentration of high-power operations in a short period of time, further reducing the formation of local temperature hotspots, and improving temperature control during testing. The superblock includes physical blocks of different chips within the memory module; this organization provides the infrastructure for subsequent parallel processing and test optimization. Attached Figure Description

[0008] Figure 1 This is a block diagram of a host system and storage device according to embodiments of the present disclosure;

[0009] Figure 2 This is a flowchart illustrating a memory management method according to an embodiment of the present disclosure;

[0010] Figure 3 This is a schematic diagram illustrating the memory module structure and superblock configuration according to an embodiment of the present disclosure;

[0011] Figure 4 This is a detailed flowchart illustrating multiple operational stages according to an embodiment of the present disclosure;

[0012] Figure 5 This is a flowchart illustrating a virtual read operation and a read operation according to an embodiment of this disclosure;

[0013] Figure 6 This is a flowchart illustrating the erase and write operations according to an embodiment of the present disclosure;

[0014] Figure 7 This is a flowchart of the final verification procedure according to an embodiment of the present disclosure;

[0015] Figure 8 This is a timing diagram of parallel processing in a write operation according to an embodiment of the present disclosure;

[0016] Figure 9 This is a timing diagram of parallel processing in an erasure operation according to an embodiment of the present disclosure. Detailed Implementation

[0017] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0018] Figure 1 This is a block diagram illustrating a host system and storage device according to embodiments of the present disclosure. Please refer to... Figure 1 The host system 10 is, for example, a personal computer, a laptop computer, or a server. The host system 10 includes a processor 110 (also called a second processor), host memory 120 (also called host RAM), and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled (also called electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 may be disposed on the motherboard of the host system 10.

[0019] The storage device 20 includes a memory controller 210, a memory module 220 (also known as a rewritable non-volatile memory module), and a connection interface circuit 230. The memory controller 210 includes a processor 211 (also known as a first processor), a data management circuit 212, a memory interface control circuit 213, and a buffer memory 214.

[0020] In this embodiment, the host system 10 is electrically connected to the storage device 20 via a data transmission interface circuit 130 and a connection interface circuit 230 to perform data access operations. For example, the host system 10 can store data to or read data from the storage device 20 via the data transmission interface circuit 130.

[0021] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuits 130, the motherboard can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a USB flash drive, memory card, solid-state drive (SSD), or wireless storage device. The wireless storage device can be, for example, a Near Field Communication (NFC) storage device, a WiFi storage device, a Bluetooth storage device, or a Bluetooth Low Energy storage device (e.g., iBeacon), or other storage devices based on various wireless communication technologies. Furthermore, the motherboard can also be electrically connected via the system bus to various I / O devices such as a Global Positioning System (GPS) module, network interface card, wireless transmission device, keyboard, screen, and speaker.

[0022] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. Furthermore, data transmission between the data transmission interface circuit 130 and the connection interface circuit 230 utilizes the Non-Volatile Memory Express (NVMe) communication protocol.

[0023] In another embodiment, the connection interface circuit 230 may be packaged in a chip with the memory controller 210, or the connection interface circuit 230 may be disposed outside a chip containing the memory controller 210.

[0024] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. In this embodiment, the host memory 120 may be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. However, it should be understood that this disclosure is not limited to this, and the host memory 120 may also be other suitable memories.

[0025] The memory controller 210 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the memory module 220 according to the instructions of the host system 10, and to execute the memory management method provided in this disclosure to perform aging processing of the memory module 220.

[0026] More specifically, the processor 211 in the memory controller 210 is hardware with computing capabilities, used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed with multiple control instructions / program codes, and these control instructions / program codes are executed when the storage device 20 is operating to perform operations such as writing, reading, and erasing data.

[0027] Furthermore, the processor 211 is configured to execute the memory management method provided in this disclosure. Specifically, the processor 211 is configured to perform multiple operation stages on the memory module 220. In each operation stage, according to the order of the multiple superblocks of the memory module 220, a read operation, an erase operation, and a write operation are sequentially performed on each superblock, wherein each superblock includes multiple physical blocks belonging to multiple chips of the memory module 220.

[0028] In other embodiments, the control instructions / program code corresponding to the data reading method can be implemented as hardware circuit units to implement the memory management method provided in this disclosure.

[0029] It is worth mentioning that, in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (microprocessor), digital signal processor (DSP), programmable controller, application specific integrated circuits (ASIC), programmable logic device (PLD), or other similar circuit components, and this disclosure is not limited thereto.

[0030] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by each component of the memory controller 210 can also be considered as operations performed by the memory controller 210 itself.

[0031] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 receives instructions from the processor 211 to perform data transfer. For example, it reads data from the host system 10 (e.g., host memory 120) via the connection interface circuit 230 and writes the read data to the memory module 220 via the memory interface control circuit 213. Alternatively, it performs a read operation according to a read instruction from the host system 10, reading data from one or more physical units of the memory module 220 via the memory interface control circuit 213 and writing the read data to the host system 10 via the connection interface circuit 230. In one embodiment, the data management circuit 212 works with the processor 211 to manage the memory module 220, including coordinating the execution order of superblock read, erase, and write operations. In another embodiment, the data management circuit 212 may also be integrated into the processor 211.

[0032] The memory interface control circuit 213 receives instructions from the processor 211 and works with the data management circuit 212 to perform write (also known as programming), read, or erase operations on the memory module 220. In one embodiment, the memory interface control circuit 213 receives instructions from the processor 211 and works with the data management circuit 212 to perform write, read, or erase operations on the memory module 220.

[0033] Furthermore, data to be written to memory module 220 is converted into a format acceptable to memory module 220 via memory interface control circuit 213. Specifically, if processor 211 needs to access memory module 220, processor 211 transmits a corresponding instruction sequence to memory interface control circuit 213 to instruct memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code, memory address, and physical address.

[0034] Furthermore, the memory controller 210 establishes a logical-to-physical address mapping table and a physical-to-logical address mapping table to record the mapping relationship between the logical addresses of logical units (e.g., logical blocks, logical pages) and the physical addresses (physical addresses) of physical units (e.g., physical erase units / physical blocks, physical pages) configured for the memory module 220. In other words, the memory controller 210 can use the logical-to-physical address mapping table (also called the logical-to-physical mapping table) to find the physical unit mapped to a logical unit (e.g., find the physical page mapped to a logical page; find the physical address mapped to a logical address), and the memory controller 210 can use the physical-to-logical address mapping table (also called the physical-to-logical mapping table) to find the logical unit mapped to a physical unit (e.g., find the logical page mapped to a physical page; find the logical address mapped to a physical address).

[0035] The buffer memory 214 is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the memory module 220, and various system data for managing the storage device 20.

[0036] In this embodiment, the buffer memory 214 is also used to store a result table during the operation process. This result table records the execution results of read, erase, and write operations, along with specific information such as the current operation round number, entity block operation mode, superblock number, and entity block location. In this way, the key information regarding operation failures can be grasped through the specific information recorded in the result table for further processing. It should be noted that this disclosure may also use other data formats to record this operation failure information.

[0037] In one embodiment, when any of the read, erase, or write operations fails, the type of the failed operation and the corresponding superblock identifier are recorded in a result table. Based on the operation failure information (operation type and corresponding superblock identifier) ​​recorded in the result table, the processor 211 can implement various subsequent processing strategies to optimize the quality management and production efficiency of the storage device.

[0038] It is worth noting that the identification information recorded in the result table is directly related to the result table information stored in the aforementioned buffer memory 214. Specifically, when an operation fails, the "corresponding superblock identifier" recorded corresponds to the "superblock number" field in the aforementioned result table, while the "operation type that failed" corresponds to the specific operation mode information recorded in the aforementioned result table. This consistency of identification information ensures that the processor 211 can accurately locate the failure location and implement the corresponding processing strategy.

[0039] In one embodiment, the processor 211 performs bad block identification and management operations based on the failure modes (e.g., the types of operations that failed) and location information (e.g., the corresponding superblock identifier, or further including the failed entity blocks) recorded in the result table. Specifically, the processor 211 analyzes the failed superblocks, performs bad block verification operations on the superblocks, determines the availability status of each entity block by repeatedly executing the failed operations, obtains the physical address information of unavailable entity blocks (bad entity blocks), and marks these entity blocks as disabled to establish a corresponding bad block mapping table to mark the locations of unavailable entity blocks.

[0040] In one embodiment, when a bad physical block is detected, the processor 211 may initiate a bad block replacement mechanism, mark the bad physical block as unavailable, and select a replacement physical block from the pool of spare physical blocks to maintain the functional integrity of the storage device. In other words, bad block information can also be pre-calculated during the execution of the multiple operation phases of this disclosure to assist the memory controller 210 in managing the memory module 220.

[0041] In another embodiment, the processor 211 performs quality grading and screening of the storage device based on the accumulated operation failure frequency in the result table. The processor 211 sets quality threshold standards for different application scenarios; for example, it sets a stricter failure rate threshold for high-reliability applications and a relatively lenient standard for consumer applications. Based on the operation result statistics, the processor 211 classifies the storage device into different quality levels and implements a tiered shipping strategy to ensure that products of different quality levels are allocated to their respective target markets. On the other hand, after grading the memory module 220 by quality, this quality grading information can be further utilized for applications. For example, SLC mode can be recommended for physical blocks with lower quality, while TLC mode can be recommended for physical blocks with higher quality.

[0042] In another embodiment, processor 211 implements predictive maintenance strategies using historical operation data in the results table. By analyzing the time-series trends of the operation results, processor 211 can predict potential fault locations and establish an early warning mechanism. When a performance degradation pattern of a specific physical block is detected, processor 211 can develop a preventative maintenance plan, such as adjusting the usage frequency of that physical block or performing data migration in advance, thereby extending the overall lifespan of the storage device.

[0043] In a further embodiment, the operating system feeds back the failure data from the results table to the manufacturing process to achieve process optimization. The manufacturing system analyzes the distribution patterns and correlations of operational failures, and by combining this with unique identifiers such as the hardware identification code and wafer code of the memory module, it can identify key control points in the manufacturing process, such as specific manufacturing batches or process parameter settings. Based on these analysis results, the manufacturing system can optimize production parameter settings and adjust process control strategies, thereby improving the product yield of subsequent production batches and reducing overall manufacturing costs.

[0044] The memory module 220 is electrically connected to the memory controller 210 (specifically, electrically connected to the memory interface control circuit 213) and is used to store user data sent by the host system 10. In this disclosure, the memory module 220 is the object of operation, and the processor 211 performs an aging process on it to verify the reliability and lifespan of the storage device 20, wherein the processing is performed on a superblock basis. A superblock is a logical concept that includes a physical block belonging to multiple chips (CEs).

[0045] In one embodiment, the memory cell structure of the memory module 220 can be understood as a multi-layered physical organization architecture. Specifically, the memory module 220 includes multiple chips, each chip has multiple planes, and each plane contains multiple physical blocks, each physical block consisting of multiple physical pages. It should be noted that this disclosure is not limited to the specific size of each physical page and logical page.

[0046] In flash memory technology, flash memory can be classified into different physical block operation modes based on the number of bits that each storage cell can store. In one embodiment, the physical block operation mode adopted by the memory module 220 may include Single-Level Cell (SLC), Multi-Level Cell (MLC), Triple-Level Cell (TLC), or Quad-Level Cell (QLC), etc. Different types of flash memory have different storage densities, read / write performance, and endurance characteristics.

[0047] Specifically, in Single-Level Cell (SLC) technology, each storage cell stores only 1 bit of data, with only two possible programming states (i.e., "0" or "1"), offering the highest read / write speed and endurance, but with lower storage density. In Multi-Level Cell (MLC) technology, each storage cell can store 2 bits of data, with 4 possible programming states, striking a balance between storage density and performance. In Three-Level Cell (TLC) technology, each storage cell stores 3 bits of data, with 8 possible programming states, providing even higher storage density, but with relatively lower read / write performance and endurance. Quadruple-Level Cell (QLC) technology stores 4 bits per storage cell, with 16 possible programming states, offering the highest storage density, but with compromises in performance and endurance.

[0048] In embodiments employing Three-Level Cell (TLC) technology, the page structure of flash memory has unique characteristics. Each physical storage cell corresponds to three types of pages: Lower Page, Middle Page, and Upper Page. This structure leads to specific programming order requirements and performance characteristics.

[0049] For example, in one embodiment, the processor 211 can be programmed in the order of Lower Page, Middle Page, and Upper Page, and cannot randomly program arbitrary pages. Therefore, when performing copy unit operations, the dependencies between pages need to be carefully considered. Based on the above characteristics, in the read and write operations of this disclosure, the processor 211 needs to reasonably arrange the order of read and write operations according to the page structure characteristics of the block operation mode. When performing multi-plane parallel operations, the processor 211 needs to consider not only the parallelism between planes, but also the characteristics of the block operation mode to optimize overall performance.

[0050] In one embodiment, the memory module 220 includes multiple chips, each chip containing multiple physical blocks. The processor 211 combines physical blocks from different chips into a superblock to achieve parallel operation. Specifically, the superblock construction can be based on various organization strategies: in one embodiment, the processor 211 selects physical blocks with the same number from different chips for combination; in another embodiment, the processor 211 selects physical blocks for combination based on the principle of similar physical location characteristics; in yet another embodiment, the processor 211 selects physical blocks for combination based on sequential characteristics. However, the superblock construction method of this disclosure is not limited to the above strategies, and the processor 211 can adopt other suitable physical block combination methods according to system requirements and performance optimization goals.

[0051] When performing erase or write operations on multiple physical blocks of a superblock, the processor 211 utilizes inter-chip parallel processing capabilities to optimize operation time. Specifically, the processor 211 can send corresponding erase or write operation instructions to the physical blocks of the next chip while the physical blocks of one chip are in a busy state. This time overlap strategy effectively shortens the overall operation time and improves system operating efficiency.

[0052] Figure 3 This is a schematic diagram illustrating the memory module structure and superblock configuration according to an embodiment of the present disclosure.

[0053] Reference Figure 3 In one embodiment, the memory module 220 includes multiple chips, such as a first chip D1 and a second chip D2. Each chip contains multiple planes, such as a first plane PL1 and a second plane PL2. Each plane contains multiple physical blocks, such as a first physical block BK1, a second physical block BK2, up to an Nth physical block BKN (the physical blocks are numbered, for example, from 1 to N).

[0054] In one embodiment, the processor 211 combines physical blocks from different chips into superblocks to achieve parallel processing. Specific construction strategies include, but are not limited to, the following: the processor 211 may select physical blocks with the same number from different chips for combination, or select physical blocks based on the principle of similar physical location characteristics, or combine physical blocks according to sequential characteristics. Taking combinations with the same number as an example, the first superblock VB1 is composed of the first physical block BK1 of the first chip D1 corresponding to planes PL1 and PL2, and the first physical block BK1 of the second chip D2 corresponding to planes PL1 and PL2. The second superblock VB2 is composed of the second physical block BK2 of the first chip D1 corresponding to planes PL1 and PL2, and the second physical block BK2 of the second chip D2 corresponding to planes PL1 and PL2. And so on, the Nth superblock VBN is composed of the Nth physical block BKN of the first chip D1 corresponding to planes PL1 and PL2, and the Nth physical block BKN of the second chip D2 corresponding to planes PL1 and PL2.

[0055] In one embodiment, when executing the memory management method, the processor 211 selects each superblock in sequence according to the order of the multiple superblocks of the memory module 220, for example, starting from the first superblock VB1. For each selected superblock, the processor 211 sequentially performs read operations, erase operations, and write operations. For example, after completing the read, erase, and write operations for superblock VB1, the read, erase, and write operations for the corresponding superblock VB2 can be executed subsequently.

[0056] In one embodiment, when performing erase or write operations on multiple physical blocks of a superblock, the processor 211 utilizes the parallel processing capabilities between chips to optimize the operation. When the physical blocks of the first chip D1 are busy, the processor 211 sends corresponding erase or write operation instructions to the corresponding physical blocks of the second chip D2 without waiting for the operation of the first chip D1 to complete. This parallel processing mechanism allows the operation times of multiple chips to partially overlap, effectively shortening the overall operation time.

[0057] In one embodiment, each entity block contains multiple entity pages, and the write operation includes writing to multiple entity pages of each entity block in the superblock. Through this superblock organization, the processor 211 can simultaneously perform parallel write operations on corresponding entity blocks of multiple chips, further improving the parallelism of the processing.

[0058] In one embodiment, the processor 211 also utilizes a multi-level parallel processing mechanism when performing read operations. When performing a read operation on a superblock, the processor 211 can simultaneously send read operation instructions to the corresponding physical blocks of multiple chips. For example, when reading the first superblock VB1, the processor 211 can read the corresponding first physical block BK1 in the first chip D1 and the second chip D2 in parallel.

[0059] For example, further, in planar parallel reading, processor 211 can simultaneously access physical blocks on different planes within the same chip. When the first plane PL1 of the first chip D1 is performing a read operation, processor 211 can perform a read operation on the corresponding physical block of the second plane PL2 in parallel, realizing parallel read processing within a single chip.

[0060] By using a parallel mechanism for read operations, the processor 211 can complete data verification more quickly in the pre-operation phase and the normal operation phase. Especially in the final verification program, when only read test operations need to be performed, the parallel read mechanism can significantly shorten the verification time and improve the overall test efficiency.

[0061] Figure 2 This is a flowchart illustrating a memory management method according to an embodiment of the present disclosure.

[0062] Reference Figure 2 In one embodiment, the processor 211 executes a memory management method including two core steps to perform systematic aging and quality verification of the memory module 220.

[0063] In one embodiment, in step S210, the processor 211 performs multiple operation stages on the memory module 220 to establish a complete processing execution framework.

[0064] In one embodiment, the plurality of operation phases includes two main phases: a pre-operation phase and a normal operation phase. Each operation phase sequentially performs read, erase, and write operations.

[0065] However, this disclosure is not limited thereto. For example, in other embodiments, the plurality of operation stages may include three main stages: a pre-operation stage, a normal operation stage, and a final verification procedure. The final verification procedure includes only a read operation.

[0066] The following sections detail the pre-operation phase, the normal operation phase, and the final verification procedure.

[0067] [Pre-operation phase]

[0068] The processor 211 first executes a pre-operation phase as the initial phase of the operation sequence. The read operation is a virtual read operation. In this phase, the processor 211 sequentially performs virtual read, erase, and write operations on each superblock. The virtual read operation reads physical blocks that have not yet been written with valid data (e.g., performing a read operation on an empty physical block). Its main purpose is to quickly bring the internal temperature of the storage device to a preset value and ensure consistency with the subsequent normal operation phase. That is, both the pre-operation phase and the normal operation phase include the read, erase, and write operation sequence. The pre-operation phase establishes stable initial environmental conditions for the subsequent normal operation phase.

[0069] [Normal Operation Phase]

[0070] After completing the pre-operation phase, the processor 211 sequentially executes multiple normal operation phases. The read operation in each normal operation phase includes reading the physical blocks of the superblock that have been written with valid data, where the valid data was written via the write operation in the previous operation phase.

[0071] [Final verification procedure execution]

[0072] After all normal operation phases are completed, processor 211 executes the final verification program. This program performs read operations only on each superblock to verify the integrity of the data written during the final normal operation phase.

[0073] Next, in step S220, the processor 211, in each operation stage, sequentially performs read, erase, and write operations on each superblock according to the order of the multiple superblocks of the memory module. Each superblock includes multiple entity blocks belonging to multiple chips of the memory module. Specifically, each superblock is composed of entity blocks from different chips. This organization fully utilizes the parallel processing capabilities between chips, optimizing operational efficiency. It should be noted that the entity blocks of each superblock include entity blocks of the same or different orders from different chips. For example, in one embodiment, a superblock may be composed of entity blocks with the same number from different chips (such as the first entity block of the first chip and the first entity block of the second chip). In another embodiment, a superblock may also be composed of entity blocks with different numbers from different chips (such as the first entity block of the first chip and the third entity block of the second chip), and this disclosure does not limit this.

[0074] More specifically, in one embodiment, for each selected superblock, the processor 211 sequentially performs a read operation, an erase operation, and a write operation. The read operation includes reading each entity page of each entity block in the superblock, the erase operation includes erasing each entity block in the superblock, and the write operation includes writing multiple entity pages of each entity block in the superblock.

[0075] Crucially, the specific operation execution sequence provided in this disclosure, compared to the traditional erase-write-read sequence performed on an entire chip basis, can have a positive impact on the storage device in a variety of operational scenarios:

[0076] In traditional methods, performing a sequence of full erase, full write, and full read operations consecutively can cause drastic temperature fluctuations. Specifically, the temperature rise from consecutive erase operations is greater than that from consecutive write operations, which in turn is greater than that from consecutive read operations. This temperature gradient can cause the storage device to enter protection mode due to excessive temperature fluctuations, affecting the continuity and reliability of operations.

[0077] This disclosure achieves a uniform distribution of temperature changes by employing a read-erase-write operation sequence. The virtual read operation first provides a baseline temperature rise, the subsequent erase operation further increases the temperature, and the final write operation maintains the temperature level, forming a gradual temperature rise pattern. This temperature control strategy reduces abrupt temperature changes and prevents the storage device from triggering its temperature protection mechanism due to overheating.

[0078] By using superblocks as the unit of operation, this disclosure fully utilizes the parallel processing capabilities of multiple chips compared to the traditional single-chip sequential operation mode. When a chip's physical block is busy, the processor 211 can simultaneously send operation instructions to the corresponding physical blocks of other chips, creating an overlap effect in operation time and shortening the overall processing time.

[0079] The virtual read operation in the pre-operation phase establishes a stable initial temperature environment, ensuring that subsequent normal operation phases are conducted under consistent temperature conditions. This temperature stability improves the predictability and repeatability of operational results, enhancing the accuracy of storage device quality assessment.

[0080] Through a result table recording mechanism, the processor 211 can monitor the execution status in real time under various operating scenarios, including performance under different temperature conditions, different chip load states, and different operating modes. This comprehensive monitoring capability enables the system to dynamically adjust processing strategies according to the actual operating environment, ensuring optimal operating performance in various application scenarios.

[0081] During the execution of superblock processing, processor 211 implements a parallel processing strategy for erase and write operations.

[0082] [Parallel processing mechanism for erase operations]

[0083] Combination Figure 3 The memory module structure is illustrated. When processor 211 sends an erase operation instruction to the physical block of the current chip in the current superblock, the physical block enters a busy state to perform the physical erase process. Taking the first superblock VB1 as an example, when processor 211 sends an erase operation instruction to the first physical block BK1 of the first chip D1, the physical block enters a busy state. During this period, processor 211 does not need to wait for the first chip D1 to complete the erase operation, but immediately sends an erase operation instruction to the corresponding first physical block BK1 of the second chip D2 in the same superblock. This mechanism allows the erase operation time windows of multiple chips to overlap, achieving time cascading optimization. Furthermore, within a single chip, processor 211 can also utilize planar parallel processing capabilities to simultaneously perform erase operations on the corresponding physical blocks in the first plane PL1 and the second plane PL2 of the first chip D1, further improving parallel processing efficiency.

[0084] [Parallel processing mechanism for write operations]

[0085] Similarly, after processor 211 sends a write operation instruction to the physical block of the current chip in the current superblock, the physical block enters a busy state to execute the data writing process. Processor 211 uses this time gap to send a write operation instruction to the physical block of another chip in the superblock (e.g., the next chip), forming a parallel execution mode of multi-chip write operations.

[0086] Through the parallel processing strategy described above, the operation execution times of multiple chips within a superblock partially overlap, shortening the processing cycle of a single superblock and thus improving overall operational efficiency.

[0087] [Storage Device Quality Assessment Mechanism]

[0088] In one embodiment, after completing superblock bad block detection, the memory controller 210 executes the following storage device quality assessment process. For example, the processor 211 counts the total number of identified bad blocks in a specific superblock and compares this number with a preset bad block threshold. The preset bad block threshold is determined based on the storage device's technical specifications and quality standards; for example, the bad block threshold may be set as a predetermined percentage (e.g., 2%) of the total number of blocks. When the counted number of bad blocks exceeds the preset bad block threshold, the processor 211 marks the entire storage device as defective and generates defective identification information. The defective identification information may include, for example, the detection time, the specific value exceeding the threshold, and the distribution of major fault types. When the counted number of bad blocks does not exceed the preset bad block threshold, the processor 211 marks the storage device as a qualified product and continues with subsequent bad block management procedures.

[0089] [Failure Detection and Bad Block Identification Mechanism]

[0090] In one embodiment, the processor 211 monitors the execution status and results of operations. When any of the read, erase, or write operations fails on a specific superblock, the processor 211 performs bad block detection on multiple physical blocks of that specific superblock to identify the location (physical address) of the bad physical block in the specific superblock. In other words, this mechanism can be used to create a pre-bad block table or directly remove the bad physical block from the list of available physical blocks.

[0091] In one embodiment, when any of the read, erase, or write operations fails, the type of the failed operation and the corresponding superblock identifier are recorded. For example, such failure information can be recorded using a result table. That is, the information used to record failure information includes at least the operation type and the corresponding superblock identifier.

[0092] [Error correction and verification mechanism]

[0093] In one embodiment, when a read operation fails, the processor 211 initiates an error correction algorithm to perform error correction processing. The error correction algorithm includes at least one of the following techniques: adjusting the read retry level, hardware decoding, and software decoding.

[0094] In another embodiment, the processor 211 records the failure result of the read operation, along with the operation type, superblock identifier, entity block position, and current operation round number, into a result table (or other type of data structure) to ensure the traceability of the operation result.

[0095] In one embodiment, after the write operation is completed, the processor 211 can immediately perform a write verification read to check the accuracy of the written data. This mechanism identifies data integrity issues during the write process by comparing the written data with the read result.

[0096] Similarly, when a write operation fails, the processor 211 initiates a write error correction mechanism. This error correction process includes, for example, performing a write retry operation if an error is detected during write verification, repeatedly executing the write command to attempt to correct the write failure. Furthermore, the processor 211 can implement a write voltage adjustment strategy, improving the success rate of the write operation by increasing the write voltage amplitude or adjusting the write pulse parameters. Finally, the written data is verified again; if successful, the operation phase of the next superblock is executed (if it fails, the result is recorded in the result table).

[0097] Through steps S210 and S220, the memory management method of the present invention realizes the aging process of the memory module, solving the technical problems of drastic temperature changes and long operation time in traditional methods.

[0098] Figure 4 This is a detailed flowchart illustrating multiple operational stages according to an embodiment of the present disclosure.

[0099] Reference Figure 4 In one embodiment, processor 211 executes a complete multi-stage architecture that includes a pre-operation stage, multiple normal operation stages, and a systematic execution sequence of a final verification procedure.

[0100] [Pre-operation phase execution sequence (S410-S440)]

[0101] In one embodiment, the processor 211 first selects the first superblock and initiates the pre-operation phase. In step S410, the processor 211 performs a virtual read operation to read the physical blocks that have not yet been written with valid data, so that the internal temperature of the storage device quickly reaches a preset value. Step S420 performs an erase operation to erase each physical block in the current superblock. Step S430 performs a write operation to write multiple physical pages of each physical block in the current superblock (after the last physical page of the last physical block of each superblock is written, the next superblock can be moved to for the pre-operation phase). The data written is preset write data to facilitate subsequent verification.

[0102] In one embodiment, in step S440, the processor 211 determines whether the current superblock is the last superblock. If the determination result is no, the processor 211 selects the next superblock and returns to step S410 to continue executing the virtual read, erase, and write operation sequence. If the determination result is yes, the pre-operation stage is completed, and the system enters multiple normal operation stages.

[0103] In another embodiment, an additional pre-operation control judgment step (not shown) can be executed after step S440 to determine how many times the pre-operation phase has been executed. Specifically, in the pre-operation control judgment step, the processor 211 determines whether the number of rounds executed in the pre-operation phase has reached a preset target number. The pre-operation phase can be preset to be executed a certain number of times (e.g., 2-3 complete cycles) to ensure that the memory module 220 achieves stable temperature rise and reaches the expected temperature range suitable for subsequent normal operation phase execution. When the number of executions has not reached the preset value, the processor 211 executes the complete pre-operation phase again; when the preset number of executions is reached, the system enters the normal operation phase (e.g., executes step S450).

[0104] It is worth mentioning that, in another embodiment, step S440 can be replaced by a temperature steady-state condition determination. The processor 211 monitors the temperature state of the memory module 220 in real time using a temperature sensor to determine whether the steady-state temperature condition has been met. When it is detected that the temperature of the memory module 220 has steadily risen to a preset temperature threshold suitable for executing the normal operation phase, the processor 211 completes the pre-operation phase and begins executing the normal operation phase (proceeding to step S450). This method achieves intelligent pre-operation control based on actual temperature feedback.

[0105] [Execution sequence of multiple normal operation phases (S450-S490)]

[0106] In one embodiment, processor 211 selects the first superblock and initiates the normal operation phase. In step S450, processor 211 performs a read operation to verify the entity blocks in the superblock that have been written with valid data. Specifically, the read operation in the normal operation phase differs fundamentally from the virtual read operation in the pre-operation phase in terms of the data source:

[0107] It's worth noting that the data sources for virtual read operations and read operations in the normal operation phase differ: virtual read operations read entity blocks that haven't yet been written with valid data; the data read at this stage is in an undefined state or an initial erased state. Read operations in the normal operation phase, however, read valid data that was actually written in the write operation of the previous operation cycle. For example, valid data is written to the corresponding entity block through the write operation of the previous operation phase. For instance, in the first normal operation phase, processor 211 reads the data written in step S430 during the pre-operation phase; in the second normal operation phase, processor 211 reads the data written in the first normal operation phase; and so on, forming a chain-like verification mechanism for operation data.

[0108] Step S460 performs an erase operation, and step S470 performs a write operation. The operation objects and methods are the same as those in S420 and S430 in the pre-operation stage.

[0109] In step S480, processor 211 determines whether the current superblock is the last superblock. If the determination result is no, processor 211 selects the next superblock and returns to step S450. If the determination result is yes, processor 211 determines in step S490 whether the current operation round is the last operation phase. If the determination result is no, processor 211 executes the next normal operation phase, reselects the first superblock, and returns to step S450.

[0110] In one embodiment, the number of execution rounds in the normal operation phase is configured according to the application level and quality requirements of the storage device. For example, the processor 211 can maintain an operation round counter, comparing the current operation round with a preset target round. The preset target round can be determined according to a specific processing strategy, such as being set to 3 rounds, 5 rounds, 10 rounds, or more. When the current operation round is less than the target round (e.g., not the last round of the operation phase), the processor 211 executes the next round of the normal operation phase, reselects the first superblock, and returns to step S450. When the preset round is reached, the system completes multiple rounds of the normal operation phase and enters the final verification procedure phase. This flexible configuration mechanism allows storage device manufacturers to adjust the processing intensity according to product specifications, market positioning, and quality standards, optimizing processing efficiency while ensuring product quality.

[0111] [Final verification procedure execution (S500)]

[0112] When the result of step S490 is yes, processor 211 proceeds to step S500 to execute the final verification procedure. In this procedure, processor 211 performs read operations only on each superblock to verify the integrity of the data written during the final normal operation phase.

[0113] [Operation result output (S510)]

[0114] In step S510, the processor 211 outputs the operation results, including the operation data recorded in the result table throughout the processing. The output content covers the execution results of erase and write operations, the current operation round number, the entity block operation mode, the superblock number, and the entity block location information.

[0115] These multiple operation stages establish the initial processing environment through a pre-operation stage, perform aging verification of the memory module 220 through multiple normal operation stages, and ensure the integrity of the operation data through a final verification program. Each superblock's operation stages before the final verification program are executed according to a read-erase-write sequence, achieving optimized temperature profile control and utilizing parallel mechanisms to optimize processing efficiency.

[0116] Figure 5 This is a flowchart illustrating a virtual read operation and a read operation according to an embodiment of the present disclosure.

[0117] Reference Figure 5 In one embodiment, the processor 211 implements two different types of read operations, corresponding to the virtual read operation in the pre-operation phase and the read operation in the normal operation phase, respectively. Each operation has specific technical features and error handling mechanisms.

[0118] [Implementation Mechanism of Virtual Read Operation in the Pre-operation Phase]

[0119] In one embodiment, during the pre-operation phase, processor 211 performs a virtual read operation S410.

[0120] In detail, in step S411, the processor 211 performs a virtual read operation on the physical blocks in the currently selected superblock that have not yet been written with valid data. This operation causes the internal temperature of the storage device to quickly reach a preset value and ensures consistency with subsequent operation stages.

[0121] The virtual read operation (also known as a pseudo-read operation) reads from blank or uninitialized memory cells, and the read result is usually a predefined empty data pattern. The purpose of this operation is not to retrieve data stored in the physical block, but to activate the internal circuitry of the memory and generate a temperature rise effect, creating a working environment for subsequent erase and write operations. After the virtual read operation is completed, the erase operation can be performed (S420).

[0122] [Verification mechanism for read operations during normal operation phase]

[0123] On the other hand, in one embodiment, during the normal operation phase, the processor 211 performs a standard read operation to verify the integrity and accuracy of the data written in the pre-operation phase. In step S451, the processor 211 performs a read operation on the entity block in the currently selected superblock that has been written with valid data, which was written via the write operation in the previous round of operation phase.

[0124] The read operation verifies data integrity by comparing the read result with preset data, and tests the data retention capability of the storage unit and the functional stability of the read circuit.

[0125] [Read Operation Error Detection and Handling Process]

[0126] Next, in step S452, processor 211 determines whether the read operation was successful. If the determination result is yes, processor 211 directly proceeds to step S460 to perform the erase operation. If the determination result is no, processor 211 activates the error handling mechanism.

[0127] Specifically, in step S453, the processor 211 performs error correction processing using an error correction algorithm. The error correction algorithm includes at least one of adjusting the read retry level, hard bit decoding, and soft bit decoding. Adjusting the read retry level optimizes signal detection by modifying the read voltage threshold; hard bit decoding uses a standard error correction code algorithm to handle fixed-bit errors; and soft bit decoding utilizes probabilistic information for error correction.

[0128] More specifically, the read retry level adjustment technology optimizes signal detection accuracy by dynamically modifying the read voltage threshold, thus addressing the read difficulty caused by charge degradation in the memory cells. The processor 211 adjusts the read reference voltage based on the characteristic patterns of initial read failures, gradually decreasing or increasing the voltage threshold from the standard voltage to adapt to the actual charge distribution state of the memory cells. The processor 211 performs multiple retry operations, each using a different combination of voltage parameters, until the optimal read conditions are found or the preset maximum number of retry attempts is reached.

[0129] In one embodiment, the hard-bit decoding technique employs a standard error-correcting code algorithm to handle deterministic bit errors, achieving data recovery based on error-correction theories such as Hamming codes, BCH codes, or Reed-Solomon codes. The processor 211 treats the read raw data as a deterministic binary sequence and locates and corrects the error position by calculating the check bit and error syndrome. This algorithm has a fixed error-correction capability boundary and is suitable for situations where the number of error bits is within a predetermined range.

[0130] In one embodiment, soft bit decoding technology utilizes probabilistic information for error correction, obtaining reliability information for each bit by analyzing the analog characteristics of the read signal. The processor 211 not only acquires the binary bit information but also collects the confidence level or probability value for each bit. Based on this soft information, the processor 211 employs error correction algorithms such as low-density parity-check codes (LDPC) or Turbo codes, improving the accuracy of data recovery through an iterative decoding process. Soft bit decoding is suitable for severely aged or high-error-rate memory cells and can handle complex error modes that hard bit decoding cannot correct.

[0131] [Error Correction Result Evaluation and Recording Mechanism]

[0132] Next, in step S454, processor 211 determines whether the error correction process was successful. If the determination result is yes, processor 211 proceeds to step S460 to continue performing the erase operation. If the determination result is no, in step S455, processor 211 records the failure result of the read operation (e.g., superblock identifier, related physical address, etc.) in the result table, indicating that the error exceeds the preset error correction capability range.

[0133] It is important to emphasize that the intent of virtual read operations and standard read operations during normal operation is distinct. Virtual read operations are used for environmental preparation during the pre-operation phase, while read operations focus on data integrity verification. Virtual read operations in the pre-operation phase utilize a warm-up mechanism to quickly reach the preset temperature, establishing a thermal environment for subsequent erase and write operations. Standard read operations maintain relatively low power consumption and are primarily used for data verification and integrity checks.

[0134] Figure 6 This is a flowchart illustrating an erase and write operation according to an embodiment of the present disclosure.

[0135] Reference Figure 6 The processor 211 executes the erase operation S420 and the write operation S430 sequentially.

[0136] [Erasing Operation Technique Implementation Mechanism]

[0137] In step S421, processor 211 performs an erase operation on each physical block in the currently selected superblock. The erase operation clears the charge in the memory cell by applying a high-voltage pulse, resetting the memory state to the erase state.

[0138] The erase operation employs a block-level processing mode, with a single operation affecting all memory cells within the entire physical block. The processor 211 sends an erase instruction sequence, including the erase command and the target address, to the target physical block via the memory interface control circuit 213.

[0139] Under the superblock parallel processing framework, the processor 211 can send an erase operation instruction to the corresponding physical block of the next chip when the physical block of one chip is busy, thereby achieving the overlap of erase operation time between multiple chips and shortening the overall operation time.

[0140] [Erase Operation Status Verification and Error Handling]

[0141] In step S422, processor 211 determines whether the erase operation was successful. This determination is based on the status information returned by memory module 220, including an operation completion flag and an error status indicator. If the determination result is yes, processor 211 directly proceeds to step S430 to execute the write operation. If the determination result is no, in step S423, processor 211 records the failure result of the erase operation, along with the current operation round number, physical block operation mode, superblock number, and physical block location information, into the result table.

[0142] Erase failures typically indicate physical degradation of physical blocks or abnormal circuit function, and such errors are difficult to recover from through retry mechanisms. Therefore, erase operations employ a direct recording error handling strategy, saving failure information for subsequent analysis and processing.

[0143] [Write Operation Technical Execution Flow]

[0144] On the other hand, in step S431, processor 211 performs write operations on multiple entity pages of each entity block in the currently selected superblock. The write operation stores preset data into the target storage cell through a charge injection process. This write operation is performed on top of the erase operation to ensure that the storage cell is in the correct initial state.

[0145] The write operation employs a page-level processing mode, writing data to a specific physical page within the physical block. The processor 211 sends preset data and corresponding write instructions to the target physical page via the memory interface control circuit 213. The preset data typically includes known data patterns such as all "0", all "1", alternating pattern, or pseudo-random sequence, to verify the data retention and write capabilities of the memory cell.

[0146] Under the parallel processing framework within the superblock, the processor 211 can send a write operation instruction to the corresponding physical block of the next chip when the physical block of the corresponding chip in the superblock is in a busy state, thereby achieving overlapping write operation times between multiple chips and shortening the overall operation time.

[0147] [Write operation verification and failure handling mechanism]

[0148] Next, in step S432, processor 211 determines whether the write operation was successful. This determination mechanism verifies whether the data has been correctly written to the target location, typically achieved through immediate verification reading or status register checks. If the determination result is yes, processor 211 proceeds to step S440 to determine whether the current superblock is the last superblock. If the determination result is no, in step S433, processor 211 records the failure result of the write operation, along with the current operation round number, entity block operation mode, superblock number, and entity block location information, into the result table.

[0149] Write failures can stem from memory cell degradation, write circuit malfunctions, or data path errors. Write operations employ a direct-logging error handling strategy to ensure the preservation of failure information. These logs provide analytical data for subsequent bad block detection, quality grading, and process optimization.

[0150] [Superblock processing loop control mechanism]

[0151] Next, in step S440, processor 211 determines whether the current superblock is the last superblock, implementing cyclic control of multiple normal operation stages. This determination mechanism ensures that all superblocks complete the complete read-erase-write operation sequence.

[0152] Through a sequential processing mechanism, processor 211 ensures that each superblock is processed according to a uniform sequence of operations, achieving consistency in operational conditions. The order of superblock selection is typically based on a fixed order of physical addresses or other predefined processing strategies.

[0153] [Analysis of the Optimization Effect of Temperature Management]

[0154] The sequential execution of erase and write operations disclosed in this invention helps optimize temperature management. Compared to traditional batch processing, the superblock-based operation sequence reduces the cumulative temperature rise from consecutive high-power operations, and, combined with the preceding read operations, achieves a smoother temperature change curve. This temperature control strategy prevents the storage device from triggering protection mechanisms due to excessive temperature fluctuations, ensuring the continuity and stability of the operation process.

[0155] Figure 7 This is a flowchart of the final verification procedure according to an embodiment of the present disclosure.

[0156] Reference Figure 7The processor 211 implements a final verification procedure, which verifies the integrity of the data written during the final round of normal operation.

[0157] [Final Verification Program Technical Architecture]

[0158] The final verification procedure represents the final stage of the multi-stage operational architecture, focusing on verifying data integrity. This procedure performs only read operations and does not perform any modification operations. Processor 211 selects the first superblock and initiates the execution of the verification sequence.

[0159] [Data Integrity Verification Execution Mechanism]

[0160] In step S501, processor 211 performs a read operation on the currently selected superblock, accessing the valid data written during the last normal operation phase. This read operation uses standard read parameters and does not employ any special read optimization strategies to reflect the data access capabilities of memory module 220 under normal operating conditions.

[0161] In step S502, processor 211 determines whether the read operation was successful. This determination is based on data integrity verification and read status check to ensure that the read result is consistent with the expected data pattern. If the determination result is yes, it indicates that the data integrity of the current superblock is good, and processor 211 directly proceeds to step S506 for loop control determination.

[0162] Error correction and failure management strategies

[0163] When step S502 determines that the read operation has failed, processor 211 initiates an error correction algorithm in step S503 to perform error correction processing. This error correction processing adopts the same technical strategy as in the normal operation phase, including adjusting the read retry level, hard bit decoding, and soft bit decoding at least one of them.

[0164] Next, in step S504, processor 211 determines whether the error correction process was successful. If the determination result is yes, it means that the data has been successfully recovered through the error correction algorithm, and processor 211 proceeds to step S506 to continue executing loop control. If the determination result is no, in step S505, processor 211 records the failure result of the read operation, along with the superblock number, entity block position, and current operation round number, into the result table.

[0165] In one embodiment, error logs in the final verification process are of particular technical significance because these errors occur at the final stage of the complete operating sequence and typically indicate the true performance degradation state of the memory module 220 after undergoing multiple aging stresses. These logs provide crucial data for the final quality assessment and reliability determination.

[0166] [Verification of Loop Control and Result Output Mechanism]

[0167] Next, in step S506, processor 211 determines whether the current superblock is the last superblock, thus implementing loop control of the verification sequence. If the determination result is negative, processor 211 selects the next superblock and returns to step S501, ensuring that all superblocks have completed final verification. If the determination result is positive, it indicates that all superblocks have completed verification, and the program proceeds to step S510.

[0168] In step S510, the processor 211 outputs the operation results, integrating data from multiple operation stages. The output results include operation data from the pre-operation stage, multiple normal operation stages, and the final verification procedure, forming a quality assessment report for the storage device 20.

[0169] [Comprehensive Quality Assessment Report Generated]

[0170] The operation results output includes the operation trajectory from initial environment preparation to final data integrity verification. Using the information recorded in the results table, including operation rounds, operation modes, superblock numbers, entity block locations, and error modes, processor 211 generates a quality analysis report, providing a basis for subsequent block management, equipment classification, and process optimization.

[0171] The final verification procedure's pure read characteristics exhibit minimal power consumption and temperature rise, providing stable termination conditions for the entire operation sequence. This design ensures that no additional stress is applied to the memory module 220 during verification, thereby obtaining truly reliable data integrity assessment results.

[0172] Figure 8 This is a timing diagram of parallel processing in a write operation according to an embodiment of the present disclosure.

[0173] Reference Figure 8 The processor 211 implements a chip-level parallel processing mechanism for superblock write operations. Through timing control and instruction sequence management, it achieves overlapping operation times among multiple chips, thereby shortening the overall operation time.

[0174] [Fundamentals of Parallel Processing Architecture Technology]

[0175] The parallel processing architecture for write operations is based on a multi-chip organization structure of superblocks, utilizing the independent instruction processing capabilities and state management mechanisms of each chip to achieve parallel execution. The processor 211 maintains an independent instruction queue and a readiness / busy, R / BY monitoring system for each chip participating in the superblock operation.

[0176] [Multi-chip coordinated execution mechanism]

[0177] In the current embodiment, the superblock comprises corresponding physical blocks of the first chip D1 and the second chip D2. Each chip is equipped with independent instruction queue processing capabilities, enabling it to receive and execute write instruction sequences WS1 and WS2. The write instruction sequence contains complete operation parameters: the write instruction CMD (including relevant trigger parameters), the target address ADR, and the preset data DT to be written.

[0178] [Timing Control Implementation Strategy]

[0179] For example, at time point T11-T12, processor 211 sends the first write instruction sequence WS1 to the first chip D1, which includes the write instruction CMD, the target address ADR, and the preset data DT. After receiving the instruction, the first chip D1 changes its ready state signal line R / BY from high level to low level, indicating that the first chip D1 enters a busy state and begins to execute the internal processing flow of the write operation.

[0180] In the traditional serial processing mode, the processor 211 needs to wait for the first chip D1 to complete the entire write operation and restore the R / BY signal line to a high level before it can send instructions to the second chip D2. However, the parallel processing mechanism of the present invention sends the second write instruction sequence WS2 to the second chip D2 immediately at time point T21-T22, that is, while the first chip D1 is still busy.

[0181] [Parallel Execution Efficiency Optimization]

[0182] It should be noted that starting at time point T31, both the first chip D1 and the second chip D2 are simultaneously busy, executing their respective write operations in parallel. This parallel processing mechanism allows the operation times of the two chips to partially overlap, thus shortening the overall execution time compared to the serial processing mode and optimizing time efficiency.

[0183] Similarly, at time point T31, processor 211 can send the next write instruction sequence to the next chip without waiting for the second chip D2 to complete its current write operation. This pipelined instruction dispatch mechanism ensures maximum utilization of chip resources and avoids unnecessary waiting time.

[0184] [Status Monitoring and Scheduling Control Mechanism]

[0185] It is worth mentioning that each chip's R / BY signal line provides independent status monitoring capabilities, enabling the processor 211 to track the operational progress of each chip. When a chip is busy, it is internally performing physical operations such as charge injection, verification, and status updates. By monitoring the R / BY signal line status, the processor 211 can send new instructions to other chips at appropriate times, implementing a parallel scheduling strategy.

[0186] [Instruction Sequence Technical Specifications]

[0187] Each chip's instruction queue system can cache and process complex write instruction sequences. The write instruction (CMD) contains key parameters such as operation type identifier, voltage parameters, pulse timing, and verification mode. The target address (ADR) specifies the physical address of a specific physical block and page within the superblock. The preset data (DT) contains preset write data, such as all-"0" mode, all-"1" mode, alternating bit mode, or pseudo-random sequence, used to comprehensively verify the write capability and data retention characteristics of the memory cell.

[0188] Through the aforementioned timing control and parallel processing strategies, the write test operation of this invention utilizes hardware resources and improves the processing efficiency of the write test operation.

[0189] Figure 9 This is a timing diagram of parallel processing in an erasure operation according to an embodiment of the present disclosure.

[0190] Reference Figure 9 The processor 211 performs chip-level parallel processing of the superblock erase operation, achieving time overlap of multi-chip operations by optimizing instruction scheduling timing, thus shortening the execution cycle. The erase operation adopts a block-level parallel processing mechanism, utilizing the independent erase capabilities of each chip within the superblock to achieve parallel execution.

[0191] [Parallel Erase Instruction Scheduling Mechanism]

[0192] Processor 211 assigns erase instruction sequences ES1 and ES2 to the first chip D1 and the second chip D2 participating in the operation, respectively. Each instruction sequence contains an erase instruction CMD and a target address ADR, without the need for a data transfer component.

[0193] [Timing Control and State Management Strategies]

[0194] At time T11, processor 211 sends an erase instruction sequence ES1 to the first chip D1. The instruction sequence transmission is completed within the time period T11-T12 and includes the erase instruction CMD (specifying the erase operation type and voltage parameters) and the target address ADR (identifying the physical address of the target physical block of the first chip D1 within the superblock).

[0195] At time T12, the first chip D1 completes instruction reception, and the ready state signal R / BY switches to a low level, indicating that it has entered a busy state. The first chip D1 begins to execute the internal erase operation sequence, including charge clearing, status verification, and completion confirmation.

[0196] [Implementation of Inter-Chip Parallel Processing]

[0197] At time T21, while the first chip D1 is still busy performing an erase operation, the processor 211 immediately sends the erase instruction sequence ES2 to the second chip D2. This parallel scheduling strategy avoids the time loss of waiting for the first chip D1 to complete its operation, as is done in the traditional serial method. The instruction transmission is completed within the time period T21-T22.

[0198] Starting at time T22, the second chip D2 enters a busy state to perform erase operations. At time T31, both the first chip D1 and the second chip D2 are simultaneously busy, executing their respective erase operations in parallel. The operation times of the two chips overlap, thus optimizing the total execution time compared to the serial mode.

[0199] [Erase Command Sequence Technical Specifications]

[0200] The simplified structure of the erase instruction sequence (which does not need to include a corresponding data portion like write instructions) reflects the technical characteristics of the erase operation. The erase instruction CMD contains parameters such as the operation identifier, erase voltage amplitude, pulse duration, and verification threshold. The target address ADR specifies the physical address of the physical block to be erased within the superblock, including information such as chip selection, plane identifier, and block address.

[0201] By implementing parallel erase operations, this invention provides a time-optimized solution for memory aging tests, improving the overall performance of the test system.

[0202] This embodiment also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code. When the computer-readable code is executed in a processor, the processor performs the steps of the memory management method described above. This computer program product can be implemented specifically through hardware, firmware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied as a computer storage medium; in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0203] The memory management method provided by this invention improves memory aging testing through technological innovation, and solves the technical problems in the prior art.

[0204] (1) By adjusting the test operation sequence to a read-erase-write sequence, the temperature accumulation effect of continuous high-power operations is reduced compared to the traditional erase-write-read sequence. The low-power characteristics of the read operation provide a temperature buffer for subsequent erase and write operations, avoiding drastic temperature changes caused by continuous erase and write operations, and reducing the risk of the storage device entering protection mode.

[0205] (2) Through the inter-chip parallel processing mechanism, when one chip is busy, it can send operation instructions to other chips to achieve overlapping operation time and improve the efficiency of the overall test process.

[0206] (3) The pre-operation phase uses a virtual read test to rapidly preheat the internal temperature of the storage device, establishing initial test conditions. This mechanism ensures that the subsequent normal operation phase is performed under a consistent temperature environment, improving the reproducibility and comparability of test results.

[0207] (4) An error information recording mechanism provides traceability capabilities for information such as test round number, operation mode, superblock number, and physical block location. This recording mechanism supports subsequent bad block identification, quality grading, predictive maintenance, and process optimization analysis, providing a data foundation for the test management of storage devices.

[0208] (5) Using the superblock as the operation unit of the read-erase-write sequence, compared with performing various test operations separately on the whole chip, the power load is distributed in time and space, reducing the formation of local temperature hotspots in a short time and maintaining the temperature stability of the test environment.

[0209] (6) Multi-stage architecture (pre-operation stage - normal operation stage - final verification procedure) is a complete test chain from initial environment preparation to final data integrity verification. The consistency and reliability of aging tests are improved through test sequence design.

[0210] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method applied to a storage device configured with a memory module, characterized by, The method includes: The memory module is subjected to multiple operation phases, including a pre-operation phase and multiple normal operation phases ordered after the pre-operation phase. In each operation phase, according to the order of the multiple superblocks of the memory module, read operation, erase operation, and write operation are sequentially performed on each superblock, wherein each superblock includes physical blocks of different chips in the memory module, and the current operation of the read operation, the erase operation, or the write operation is executed in parallel on the physical blocks of different chips included in the current superblock. In the pre-operation phase, the read operation is a virtual read operation, which includes reading the entity blocks in the superblock that have not yet been written with valid data; In each normal operation phase, the read operation includes reading the entity block in the superblock that has been written with the valid data, which was written via the previous round of write operation.

2. The memory management method of claim 1, wherein, The superblock is composed of physical blocks located at positions in the different chips.

3. The memory management method of claim 1, wherein, The plurality of operational phases also include a final verification procedure ordered after the plurality of normal operational phases, and the method further includes: In the final verification procedure, each superblock is read from the entity block to which the valid data has been written, wherein the valid data was written via the write operation in the previous round of operation phases.

4. The memory management method of claim 1, wherein, The method further includes: When the read operation fails during any normal operation phase, an error correction algorithm is used for error correction processing. The error correction algorithm includes at least one of adjusting the read retry level, hard bit decoding, and soft bit decoding.

5. The memory management method according to claim 1, characterized in that, The method further includes: When the physical block of the current chip in the current superblock that is performing the erase operation is in a busy state, an erase operation command is sent to the physical block of another chip in the superblock. When the physical block of the current chip in the current superblock performing the write operation is busy, a write operation instruction is sent to the physical block of another chip in the superblock.

6. The memory management method according to claim 1, characterized in that, The method further includes: When the read operation, the erase operation, or the write operation on a specific superblock fails, bad block detection is performed on each entity block in the specific superblock to identify bad entity blocks in the specific superblock.

7. The memory management method of claim 1, wherein, The method further includes: When any of the read, erase, or write operations fails, the type of the failed operation and the corresponding superblock identifier are recorded in the result table.

8. A memory controller for controlling a storage device configured with a memory module, the memory controller comprising: The memory controller includes: A memory interface control circuit, for electrically connecting to the memory module; and The processor is electrically connected to the memory interface control circuit, and the processor is also electrically connected to the connection interface circuit of the storage device for electrical connection to the host system. The processor is configured to: The memory module is subjected to multiple operation phases, including a pre-operation phase and multiple normal operation phases ordered after the pre-operation phase. In each operation phase, according to the order of the multiple superblocks of the memory module, read operation, erase operation, and write operation are sequentially performed on each superblock, wherein each superblock includes physical blocks of different chips in the memory module, and the current operation of the read operation, the erase operation, or the write operation is executed in parallel on the physical blocks of different chips included in the current superblock. During the pre-operation phase, the processor performs a virtual read operation as the read operation to read the entity blocks in the superblock that have not yet been written with valid data. In each normal operation phase, the processor performs the read operation to read the entity block in the superblock that has been written with the valid data, which was written via the previous round of write operation.

9. The memory controller according to claim 8, characterized in that, The superblock is composed of physical blocks located at positions in the different chips.

10. The memory controller of claim 8, wherein, The plurality of operational phases also include a final verification procedure ordered after the plurality of normal operational phases, wherein the processor is further configured to: In the final verification procedure, each superblock is read from the entity block to which the valid data has been written, wherein the valid data was written via the write operation in the previous round of operation phases.

11. The memory controller of claim 8, wherein, The processor is also configured to: When the read operation fails during any normal operation phase, an error correction algorithm is used for error correction processing. The error correction algorithm includes at least one of adjusting the read retry level, hard bit decoding, and soft bit decoding.

12. The memory controller of claim 8, wherein, The processor is also configured to: When the physical block of the current chip in the current superblock that is performing the erase operation is in a busy state, an erase operation command is sent to the physical block of another chip in the superblock. When the physical block of the current chip in the current superblock performing the write operation is busy, a write operation instruction is sent to the physical block of another chip in the superblock.

13. The memory controller according to claim 8, characterized in that, The processor is also configured to: When the read operation, the erase operation, or the write operation on a specific superblock fails, bad block detection is performed on each entity block in the specific superblock to identify bad entity blocks in the specific superblock.

14. The memory controller of claim 8, wherein, The memory controller also includes a buffer memory electrically connected to the processor for storing result tables; The processor is also configured to: When any of the read, erase, or write operations fails, the type of the failed operation and the corresponding superblock identifier are recorded in the result table.

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