A method for encapsulating a CPO system

Abstract

This application provides a CPO system packaging method, which includes: using a high-resistivity silicon wafer as a substrate, performing spiral microchannel etching, through-silicon via (TSV) fabrication, electroplating to fill the vias, and back-side thinning to complete the silicon interposer layer processing; integrating silicon photonic chips and electronic chips onto the silicon interposer layer using a diamond microbump array containing a copper core; installing a piezoelectric micropump at the corresponding fluid interface within the silicon interposer layer, and filling the connected channels with a suitable liquid under vacuum; and after passing reliability verification testing, packaging the system using an anti-static shielding bag. The CPO system using this packaging process can achieve efficient heat dissipation, ultra-high integration precision, and strong environmental adaptability.

Description

Technical Field

[0001] This application relates to the field of optoelectronic packaging technology, and more specifically, to a CPO system packaging method. Background Technology

[0002] In the digital age, data traffic in data centers is growing exponentially, posing unprecedented challenges to data transmission speed and latency. CPO packaging technology, by co-packaging the optical engine with the chip, significantly shortens the signal transmission path, becoming a key technological direction for overcoming the bottlenecks of traditional packaging.

[0003] However, existing CPO packaging technology still faces three major problems in practical applications: First, insufficient heat dissipation performance: With the increase in chip integration and computing speed, the heat generation per unit area increases dramatically. Traditional heat dissipation structures are unable to quickly dissipate heat, resulting in excessively high chip junction temperatures, which not only reduce computing efficiency but also shorten device lifespan. Second, low integration accuracy: Alignment deviation between optical and electronic chips will significantly increase signal transmission loss. The alignment accuracy of existing bonding processes is usually above 1μm, which cannot meet the requirements of high-frequency signal transmission. Third, poor system reliability: Under complex operating conditions such as high temperature and humidity and vibration, the packaging structure is prone to loosening and interface aging, affecting system stability.

[0004] Therefore, in order to enable CPO packaging technology to have efficient heat dissipation, ultra-high integration precision and strong environmental adaptability, it is necessary to promote the independent control and high-quality development of CPO packaging technology through process innovation and system optimization. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a CPO system packaging method to address the shortcomings of the prior art.

[0006] The technical solution of the present invention to solve the above-mentioned technical problems is as follows: A CPO system packaging method, comprising the following steps:

[0007] S1. Using a high-resistivity silicon wafer as the substrate, the silicon interlayer is processed by spiral microchannel etching, through-silicon via fabrication, electroplating filling, and back-side thinning.

[0008] S2. Integrate silicon photonics chips and electronic chips into a silicon interposer layer using a diamond microbump array containing a copper core.

[0009] S3. Install the piezoelectric micropump into the corresponding fluid interface in the silicon interlayer, and fill the connected flow channel with the appropriate liquid in a vacuum environment.

[0010] S4. After the reliability verification test is passed, the system is packaged using an anti-static shielding bag.

[0011] Furthermore, in step S1, the process of using a high-resistivity silicon wafer as a substrate, and completing the silicon interposer layer fabrication through spiral microchannel etching, through-silicon via (TSV) fabrication, electroplating for via filling, and back-side thinning, includes:

[0012] S11. Using a high-resistivity silicon wafer as the substrate, a spiral microchannel network is constructed using Bosch deep reactive ion etching technology. The spiral microchannel network includes a main channel and branch channels. The main channel has a size of a1×b1, and the branch channel has a size of a2×b2, where a1∈[45μm,55μm], b1∈[95μm,105μm], a2∈[15μm,25μm], and b2∈[25μm,35μm].

[0013] S12. Based on the high-resistivity silicon wafer with the completed spiral microfluidic network construction, silicon through-holes are prepared with a specified density using a drilling process.

[0014] S13. After electroplating to fill the holes and thinning the back side of the silicon wafer with through-silicon vias, the silicon interposer is processed.

[0015] Furthermore, in step S11, during the microchannel etching process, The plasma ratio was optimized to 3:1, and the verticality of the microchannel sidewall was controlled to be greater than 89° to ensure the regularity of the channel cross-section. By reducing eddy currents and resistance during dielectric fluid flow, local heat dissipation dead zones were avoided.

[0016] Furthermore, in step S12, during the through-silicon via (TSV) fabrication process, a hafnium oxide dielectric layer is uniformly deposited on the sidewall of the TSV using atomic layer deposition (ALD) technology, and a copper layer with a thickness gradient distribution and without voids is formed on the basis of the hafnium oxide dielectric layer using a gradient electrochemical deposition process.

[0017] Furthermore, the integration of the silicon photonics chip and the electronic chip onto the silicon interposer via a diamond microbump array containing a copper core includes:

[0018] S21. Eliminate the natural oxide layer on the surface of the silicon photonics chip and polish the surface of the electronic chip to ensure the flatness of the chip surface;

[0019] S22. The hot-press bonding machine is controlled to perform pressure bonding operations on the contact interface between the silicon photonic chip and the silicon interposer, and the contact interface between the electronic chip and the silicon interposer. During the bonding process, a diamond microbump array is used to connect the silicon photonic chip, the electronic chip and the silicon interposer. A copper core is set inside the diamond microbump, and the copper core is wrapped by a diamond coating layer. By utilizing the high thermal conductivity of diamond and the ability of the copper core to promote low-resistance conductive connection between the chip and the interposer, efficient heat dissipation and improved signal transmission efficiency are achieved.

[0020] Furthermore, in step S22, before the pressure bonding operation, the method further includes: identifying a first alignment mark on the surface of the silicon photonic chip and the electronic chip, and a corresponding matching second alignment mark on the silicon interposer, using a visual recognition tool; and adjusting the positions of the silicon photonic chip, the electronic chip, and the silicon interposer based on the relative positional relationship between the first and second alignment marks, so that they are initially aligned.

[0021] Furthermore, a microchannel interface is etched in a designated edge region of the silicon interposer. In step S3, the piezoelectric micropump is installed at the corresponding fluid interface within the silicon interposer, and the connected channels are filled with a suitable liquid under vacuum conditions, including:

[0022] S31. Connect one end of the microfluidic interface to the main channel of the spiral microfluidic channel inside the silicon interposer, and connect the other end to the fluid inlet and outlet of the piezoelectric micropump through a sealing ring.

[0023] S32. Inject the microchannel adaptable liquid in a vacuum environment, and perform multiple hot and cold cycles after injection to remove residual air bubbles in the channel.

[0024] Furthermore, in step S4, the reliability verification test includes: conducting a long-term stable operation test in a constant temperature and humidity chamber with preset temperature and humidity, and monitoring the junction temperature of the chip in the working state in real time using an infrared thermal imager, recording abnormal situations when the junction temperature exceeds a preset safety threshold; applying random vibration excitation with a specified power spectral density to the chip within a preset frequency range to conduct random vibration testing, and after the test, emitting X-rays to the key structural areas inside the chip to detect whether there is loosening or solder joint detachment inside the chip.

[0025] The beneficial effects of this invention are as follows: Firstly, the spiral microchannel etching of the high-resistivity silicon wafer increases the contact area and contact time between the cooling liquid and the silicon interposer. After the adapting liquid is poured into the connected channels, the cooling liquid can flow fully within the spiral channels, more effectively absorbing the heat generated by the silicon interposer and the chip integrated thereon. Secondly, a diamond microbump array containing a copper core is used to integrate the silicon photonic chip and the electronic chip onto the silicon interposer. The diamond microbumps have extremely high hardness and wear resistance, ensuring that the shape and size of the microbumps remain stable during integration, thereby achieving a high-precision mechanical connection between the chip and the silicon interposer. Simultaneously, the copper core provides excellent electrical connection performance, ensuring signal transmission between chips. Furthermore, the use of an anti-static shielding bag for system packaging effectively prevents damage to sensitive electronic components in the CPO system from static electricity, enhancing the system's adaptability to electrostatic environments. Attached Figure Description

[0026] Figure 1 This is a flowchart illustrating a CPO system packaging method disclosed in this invention. Detailed Implementation

[0027] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0028] like Figure 1 As shown, this application discloses a CPO system packaging method, which includes the following steps:

[0029] Step S1: Using a high-resistivity silicon wafer as the substrate, the silicon interposer is processed by spiral microchannel etching, through-silicon via fabrication, electroplating to fill the vias, and back-side thinning.

[0030] Step S2: The silicon photonic chip and the electronic chip are integrated into the silicon interposer through a diamond microbump array containing a copper core.

[0031] Step S3: Install the piezoelectric micropump into the corresponding fluid interface inside the silicon interposer, and fill the connected flow channel with the appropriate liquid under vacuum.

[0032] Step S4: After the reliability verification test is passed, the system is packaged using an anti-static shielding bag.

[0033] As can be seen from the above, the CPO system packaging method disclosed in this application involves, on the one hand, spiral microchannel etching of a high-resistivity silicon wafer. This spiral microchannel design increases the contact area and contact time between the cooling liquid and the silicon interposer. After the adapting liquid is poured into the connected channels, the cooling liquid can flow fully within the spiral channels, more effectively absorbing the heat generated by the silicon interposer and the chip integrated thereon. On the other hand, a diamond microbump array containing a copper core is used to integrate the silicon photonic chip and the electronic chip onto the silicon interposer. The diamond microbumps have extremely high hardness and wear resistance, ensuring that the shape and size of the microbumps remain stable during the integration process, thereby achieving a high-precision mechanical connection between the chip and the silicon interposer. At the same time, the copper core provides good electrical connection performance, ensuring signal transmission between chips. Furthermore, the use of an anti-static shielding bag for system packaging effectively prevents damage to sensitive electronic components in the CPO system from static electricity, enhancing the system's adaptability to electrostatic environments.

[0034] In one embodiment, step S1, which involves using a high-resistivity silicon wafer as a substrate and performing spiral microchannel etching, through-silicon via fabrication, electroplating to fill the vias, and back-side thinning to complete the silicon interposer processing, includes:

[0035] Step S11: Using a high-resistivity silicon wafer as a substrate, a spiral microchannel network is constructed using Bosch deep reactive ion etching process. The spiral microchannel network includes a main channel and branch channels. The main channel has a size of a1×b1, and the branch channel has a size of a2×b2, where a1∈[45μm,55μm], b1∈[95μm,105μm], a2∈[15μm,25μm], and b2∈[25μm,35μm].

[0036] Specifically, this application uses a 300μm thick high-resistivity silicon wafer (resistivity greater than...). Using a substrate, a dual-channel spiral microfluidic network was constructed using Bosch deep reactive ion etching (DRIE) technology. The main channel is designed to be 50 μm (width) × 100 μm (depth), while the branch channels are designed to be 20 μm (width) × 30 μm (depth), resulting in an aspect ratio of 10:1. This multi-channel, high aspect ratio structure increases the heat dissipation area by 300% compared to traditional planar structures, providing ample space for subsequent dielectric fluid flow and enabling rapid removal of heat transferred from the chip to the silicon interposer.

[0037] Step S12: On the high-resistivity silicon wafer with the spiral microchannel network already constructed, through-silicon vias are prepared at a specified density using a drilling process.

[0038] Specifically, this application uses laser drilling technology to prepare silicon vias with a diameter of 50 μm and a hole density of 100 vias / mm², in order to achieve efficient electrical interconnection in the vertical direction of the chip, meet the requirements of high-frequency signal fast transmission, and improve the overall electrical performance of the device.

[0039] It should be noted that steps S11 and S12, prior to these two steps, include: pretreatment of the silicon substrate using RCA standard cleaning (a wet chemical cleaning process developed by RCA) to remove organic contaminants and metal ions; and defining the pattern structure of the flow channels and through-silicon vias (TSVs) using photolithography. These processes ensure that the TSV metallization process is free from impurities, further guaranteeing the stability of electrical performance.

[0040] Step S13: After electroplating to fill the silicon through-hole structure and thinning the back side of the silicon wafer, the silicon interposer layer is processed.

[0041] Specifically, the electroplating filling process achieves conductivity through precisely controlled uniform deposition of copper ions within the through-silicon vias (TSVs). Furthermore, this application utilizes a back-side thinning process to control the total thickness of the silicon interposer to 250 μm ± 5 μm. This, combined with a thinner silicon substrate than the initial one, further shortens the heat transfer path from the chip to the microchannels, effectively improving heat dissipation efficiency.

[0042] In one embodiment, in step S11, during the microchannel etching process, The plasma ratio was optimized to 3:1, and the verticality of the microchannel sidewall was controlled to be greater than 89° to ensure the regularity of the channel cross-section. By reducing eddy currents and resistance during dielectric fluid flow, local heat dissipation dead zones were avoided.

[0043] It should be noted that, as a flow channel for dielectric fluid, the verticality of the sidewalls of a microchannel directly affects the regularity of the channel cross-section. If the sidewalls are inclined (e.g., verticality less than 85°), the channel cross-section will exhibit a trapezoidal or irregular shape, causing eddies to form in the fluid during flow due to cross-sectional changes, increasing flow resistance and reducing heat dissipation efficiency. Controlling the sidewall verticality to above 89° ensures that the channel cross-section is close to rectangular. At this point, the streamlines are straight, fluid flow resistance is reduced, and the heat exchange efficiency between the dielectric fluid and the channel wall is significantly improved, thereby eliminating localized high-temperature dead zones and ensuring uniform heat dissipation.

[0044] It should be noted that, The 3:1 plasma ratio can balance the etching rate and the sidewall perpendicularity, achieving effective control of the microchannel sidewall perpendicularity greater than 89°, meeting the requirements of high-precision heat dissipation channels.

[0045] In one embodiment, in step S12, during the through-silicon via (TSV) fabrication process, a hafnium oxide dielectric layer is uniformly deposited on the sidewall of the TSV using atomic layer deposition (ALD) technology, and a copper layer with a thickness gradient distribution and without voids is formed on the basis of the hafnium oxide dielectric layer using a gradient electrochemical deposition process.

[0046] Specifically, the hafnium oxide dielectric layer has a thickness of 50 nm, a dielectric constant greater than 20, and a breakdown field strength greater than 5 MV / cm. The high dielectric constant reduces parasitic capacitance losses during signal transmission, while the high breakdown field strength effectively isolates electrical signals from adjacent vias, preventing crosstalk and ensuring signal integrity. The thickness gradient distribution can be understood as the thickness continuously varying with position, rather than being uniform. To improve signal transmission integrity and efficiency and reduce signal attenuation and distortion, this application sets the copper layer thickness to 5 μm-15 μm (the via opening thickness is 20%-30% thicker than the via bottom to compensate for the current skin effect), and its resistivity is less than... With a resistivity close to that of pure copper, it can minimize current transmission loss and meet the electrical requirements of high-speed signals of 112Gbps and above.

[0047] In one embodiment, step S2, integrating the silicon photonic chip and the electronic chip onto the silicon interposer via a diamond microbump array containing a copper core, includes:

[0048] Step S21: Remove the natural oxide layer on the surface of the silicon photonic chip and polish the surface of the electronic chip to ensure the flatness of the chip surface.

[0049] It should be noted that the surface treatment here is not merely "removing obstacles," but rather improving surface properties to create conditions for subsequent high-precision bonding, including:

[0050] (1) For silicon photonic chips, this application adopts Ar plasma cleaning process, with a power of 300W, a gas pressure of 10Pa and a cleaning time of 90s. Through the physical bombardment and chemical etching of plasma, the 5-10nm thick natural oxide layer on the surface of the silicon photonic chip is removed, so that the surface contact angle is less than 10°. The smaller the contact angle, the stronger the hydrophilicity and activity of the chip surface, which can greatly improve the "diamond microbumps" on the chip and silicon interlayer.

[0051] (2) For electronic chips, this application employs chemical mechanical polishing technology, utilizing 50nm particle size Abrasive materials and 3psi pressure are used to control the chip surface roughness Ra to be less than 1nm and the flatness to be less than 0.5μm / 10mm. By eliminating microscopic depressions or protrusions on the chip surface, interface gaps caused by "height differences" during bonding can be avoided, ensuring that the chip can form a uniform contact with the silicon interposer.

[0052] Step S22: Control the hot-press bonding machine to perform pressure bonding operations on the contact interface between the silicon photonic chip and the silicon interposer, and the contact interface between the electronic chip and the silicon interposer. During the bonding process, a diamond microbump array is used to connect the silicon photonic chip, the electronic chip and the silicon interposer. A copper core is set inside the diamond microbumps and is wrapped by a diamond coating layer. By utilizing the high thermal conductivity of diamond and the ability of the copper core to promote low-resistance conductive connection between the chip and the interposer, efficient heat dissipation and improved signal transmission efficiency are achieved.

[0053] Specifically, this application employs a fully automated, high-speed, high-precision hot-press bonding machine. Its optical alignment system has a resolution of 0.1 μm and is equipped with a motion control algorithm, enabling real-time and precise feedback and adjustment of the bonding head position to ensure X / Y axis deviation is less than 0.5 μm and θ angle (i.e., the angular deviation between the chip and the silicon interposer) deviation is less than 0.01°. The bonding process parameters are set as follows: pressure of 200 N, temperature of 180 °C, and holding time of 30 s, to achieve high-quality, high-precision bonding of the silicon photonic chip and the electronic chip on the silicon interposer.

[0054] It should be noted that this application abandons traditional metal bumps and selects diamond as the core material, due to diamond's high thermal conductivity. Diamond has a dielectric strength more than five times that of copper and stable dielectric properties. Using diamond as the core connection material solves the problem of traditional bumps' difficulty in achieving both electrical conductivity and heat dissipation. In addition, traditional bumps only perform the single function of electrical interconnection, while diamond microbumps, through structural design (i.e., copper core + diamond coating layer), can simultaneously achieve the dual functions of low-resistance conductivity and high-efficiency heat dissipation, greatly improving the overall performance of chip interconnection.

[0055] Specifically, considering copper's excellent conductivity, which enables low-resistance conductive connections between the chip and the interposer, this application places the copper core at the core position inside the diamond microbumps. After bonding, the copper core is fully fused with the metal layers of the chip and the interposer, forming a corresponding low-resistance conductive channel. Based on the synergistic effect of diamond's high thermal conductivity and copper's low resistance, power loss is reduced, signal transmission efficiency is improved, and high-speed, stable data exchange between chips is ensured.

[0056] Furthermore, this application utilizes a diamond coating layer to encapsulate the copper core. On one hand, the high thermal conductivity of diamond allows for rapid heat dissipation from the copper core during operation, thus serving a heat dissipation function. On the other hand, the stable dielectric properties of diamond also prevent electrical interference between the copper core and the surrounding environment, ensuring the purity of signal transmission.

[0057] In one embodiment, before the pressure bonding operation in step S22, the method further includes: identifying a first alignment mark on the surface of the silicon photonic chip and the electronic chip, and a corresponding matching second alignment mark on the silicon interposer, using a visual recognition tool; and adjusting the positions of the silicon photonic chip, the electronic chip, and the silicon interposer based on the relative positional relationship between the first and second alignment marks, so that the positions are initially aligned.

[0058] Specifically, this application uses a high-resolution industrial camera to identify a first alignment mark on the surface of the silicon photonics chip and the electronic chip, as well as a corresponding matching second alignment mark on the silicon interposer. Furthermore, during the position adjustment process, this application continuously uses the high-resolution industrial camera to monitor the alignment marks on the silicon photonics chip, the electronic chip, and the silicon interposer in real time. The real-time acquired mark images are then compared and analyzed with the initially identified mark information to dynamically evaluate the effectiveness of the position adjustment.

[0059] In one embodiment, if the phase position deviation between the first and second alignment marks is detected to be greater than a preset threshold during the bonding process, the position of the bonding head can be adjusted to ensure that the three remain aligned during the bonding process.

[0060] In one embodiment, a microchannel interface is etched in a designated edge region of the silicon interposer. In step S3, the piezoelectric micropump is installed at the corresponding fluid interface within the silicon interposer, and the connected channels are filled with a suitable liquid under vacuum conditions, including:

[0061] Step S31: Connect one end of the microfluidic interface to the main channel of the spiral microfluidic channel inside the silicon interposer, and connect the other end to the fluid inlet and outlet of the piezoelectric micropump through a sealing ring.

[0062] Specifically, the core structure of the silicon interposer is a spiral microfluidic network (including main channels and branch channels), and the microfluidic interface is the terminal extension structure of this network. Specifically, during the silicon interposer fabrication process, this application will simultaneously etch an interface port (i.e., a microfluidic interface) communicating with the main channel in a designated edge region of the silicon interposer (e.g., the windward edge selected to allow smooth fluid inflow and outflow based on the fluid flow direction in the spiral microfluidic network). Its size and shape must match the subsequently installed piezoelectric micropump and sealing ring. Essentially, it is a dedicated structure reserved on the silicon interposer to achieve communication between the "external fluid system and the internal microfluidic channel."

[0063] It should be noted that one end of the microchannel interface is directly connected to the main spiral microchannel inside the silicon interposer, ensuring that the Galden HT-230 dielectric fluid (details to be provided later) can smoothly flow into and out of the branch channel, carrying away the heat transferred from the chip to the silicon interposer. The other end connects to the fluid inlet and outlet of the piezoelectric micropump via a sealing ring. The excellent elasticity and sealing performance of the sealing ring effectively prevent leakage of the Galden HT-230 dielectric fluid at the connection point, ensuring stable and continuous fluid transfer between the microchannel and the piezoelectric micropump, thereby maintaining the normal operation of the entire heat dissipation system.

[0064] In one embodiment, this application uses a fluororubber sealing ring with a hardness of 60 Shore A. This ensures that the sealing ring has sufficient elasticity to adapt to the minute deformations and pressure changes between the microchannel interface and the piezoelectric micropump fluid inlet and outlet, while also providing sufficient rigidity to prevent permanent deformation due to excessive compression during long-term use, thereby ensuring long-term stable sealing performance.

[0065] Step S32: In a vacuum environment, the microchannel adaptor liquid is injected, and after injection, multiple hot and cold cycles are performed to remove residual air bubbles in the channel.

[0066] Specifically, this application uses Galden HT-230 dielectric fluid as the heat dissipation medium (its boiling point is greater than 230℃ and its dielectric constant is 3.0), and performs the filling in a vacuum environment with a vacuum degree of less than 10 Pa. After filling, in order to prevent residual air bubbles from causing local overheating in the heat dissipation channel and affecting the stability and reliability of the entire heat dissipation system, this application uses alternating hot and cold temperature changes in the environment to change the internal pressure and density of the fluid, causing the air bubbles to gradually accumulate and escape under the action of pressure changes, thereby eliminating residual air bubbles in the channel.

[0067] In one embodiment, the present application performs 10 cycles of hot and cold cycling in a temperature-controlled environment ranging from -40°C to 85°C to eliminate residual air bubbles.

[0068] In one embodiment, step S4, the reliability verification test includes: conducting a long-term stable operation test in a constant temperature and humidity chamber with preset temperature and humidity, and monitoring the junction temperature of the chip in the working state in real time using an infrared thermal imager, recording abnormal situations when the junction temperature exceeds a preset safety threshold; applying random vibration excitation with a specified power spectral density to the chip within a preset frequency range to conduct random vibration testing, and after the test, emitting X-rays to the key structural areas inside the chip to detect whether there is loosening or solder joint detachment inside the chip.

[0069] It should be noted that this application involves continuously running the chip in normal operating mode for 1000 hours in a constant temperature and humidity chamber at 85℃ and 85% RH, with the junction temperature monitored in real time using an infrared thermal imager, strictly controlling the junction temperature fluctuation within a range of <±2℃. During random vibration testing, this application selects a frequency range of 20Hz-2000Hz, applying vibration excitation with an acceleration power spectral density of 10g, and the entire test process lasts for 10 hours. After the test, X-ray inspection technology is used to confirm whether there is any loosening of the chip structure and whether any solder joints have detached.

[0070] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A CPO system packaging method, characterized in that, Includes the following steps: S1. Using a high-resistivity silicon wafer as the substrate, the silicon interlayer is processed by spiral microchannel etching, through-silicon via fabrication, electroplating filling, and back-side thinning. S2. Integrate silicon photonics chips and electronic chips into a silicon interposer layer using a diamond microbump array containing a copper core. S3. Install the piezoelectric micropump into the corresponding fluid interface in the silicon interlayer, and fill the connected flow channel with the appropriate liquid in a vacuum environment. S4. After the reliability verification test is passed, the system is packaged using an anti-static shielding bag; The process of integrating silicon photonic chips and electronic chips onto a silicon interposer using a diamond microbump array containing a copper core includes: S21. Eliminate the natural oxide layer on the surface of the silicon photonic chip and polish the surface of the electronic chip; S22. Control the hot press bonding machine to perform pressure bonding operations on the contact interface between the silicon photonic chip and the silicon interposer, and the contact interface between the electronic chip and the silicon interposer. During the bonding process, a diamond microbump array is used to connect the silicon photonic chip, the electronic chip and the silicon interposer. A copper core is set inside the diamond microbump, and the copper core is wrapped by a diamond coating layer.

2. The method according to claim 1, characterized in that, In step S1, the process of using a high-resistivity silicon wafer as a substrate, and completing the silicon interposer fabrication through spiral microchannel etching, through-silicon via (TSV) fabrication, electroplating for via filling, and back-side thinning, includes: S11. Using a high-resistivity silicon wafer as the substrate, a spiral microchannel network is constructed using Bosch deep reactive ion etching process. The spiral microchannel network includes a main channel and branch channels. The main channel has a size of (45-55) μm × (95-105) μm, and the branch channel has a size of (15-25) μm × (25-35) μm. S12. Based on the high-resistivity silicon wafer with the completed spiral microfluidic network construction, silicon through-holes are prepared with a specified density using a drilling process. S13. After electroplating to fill the holes and thinning the back side of the silicon wafer with through-silicon vias, the silicon interposer is processed.

3. The method according to claim 2, characterized in that, In step S11, during the microchannel etching process, The plasma ratio was optimized to 3:1, and the verticality of the microchannel sidewalls was controlled to be greater than 89°.

4. The method according to claim 2, characterized in that, In step S12, during the through-silicon via (TSV) fabrication process, a hafnium oxide dielectric layer is uniformly deposited on the sidewall of the TSV using atomic layer deposition (ALD) technology. Then, a copper layer with a thickness gradient distribution and a dense, void-free structure is formed on the basis of the hafnium oxide dielectric layer using a gradient electrochemical deposition process.

5. The method according to claim 4, characterized in that, In step S22, before the pressure bonding operation, the method further includes: identifying a first alignment mark on the surface of the silicon photonic chip and the electronic chip, and a corresponding matching second alignment mark on the silicon interposer, using a visual recognition tool; and adjusting the positions of the silicon photonic chip, the electronic chip, and the silicon interposer based on the relative positional relationship between the first and second alignment marks, so that the positions are initially aligned.

6. The method according to claim 1, characterized in that, A microchannel interface is etched in a designated edge region of the silicon interposer. In step S3, the piezoelectric micropump is installed at the corresponding fluid interface within the silicon interposer, and the connected channels are filled with a suitable liquid under vacuum conditions, including: S31. Connect one end of the microfluidic interface to the main channel of the spiral microfluidic channel inside the silicon interposer, and connect the other end to the fluid inlet and outlet of the piezoelectric micropump through a sealing ring. S32. Inject the microchannel adaptable liquid in a vacuum environment, and perform multiple hot and cold cycles after injection to remove residual air bubbles in the channel.

7. The method according to claim 1, characterized in that, In step S4, the reliability verification test includes: The chip was subjected to long-term stable operation tests in a constant temperature and humidity chamber with preset temperature and humidity. The junction temperature of the chip was monitored in real time during operation using an infrared thermal imager. When the junction temperature exceeded the preset safety threshold, the abnormal situation was recorded. Within a preset frequency range, random vibration excitation with a specified power spectral density is applied to the chip to conduct random vibration tests. After the test, X-rays are emitted to the critical structural areas inside the chip to detect whether there is any loosening or solder joint detachment.

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