A receiving end equalization circuit applied to a SerDes communication system

Abstract

The application discloses a receiving end equalization circuit applied to a SerDes communication system and belongs to the fields of integrated circuits and communication. The circuit comprises cascaded CTLE equalizers and variable gain amplifiers (VGA), the output end of the CTLE equalizer is connected with the input end of the VGA; wherein the CTLE equalizer adopts a source follower, an active inductor and a negative capacitance structure, effectively reduces power consumption, matches an output common mode level and expands bandwidth; the VGA adopts a transconductance enhancement structure and a source follower, not only improves transconductance, reduces output impedance and enhances linearity, but also realizes flexible control of low-frequency gain. Compared with a traditional equalization circuit, the application realizes lower power consumption, smaller area and significantly improved system transmission rate under the premise of simpler structure and easy realization, exhibits more excellent equalization effect and good stability, and provides an efficient and reliable solution for solving the signal equalization problem of a SerDes high-speed serial link.

Description

Technical Field

[0001] This invention relates to a receiver equalization circuit for use in a SerDes communication system, belonging to the fields of integrated circuits and communications. Background Technology

[0002] High-speed wired communication is the cornerstone of emerging technologies such as 5G, hyperscale data centers, and cloud computing. Among these, serial links, operating at speeds of tens of Gb / s and combining high energy efficiency and area efficiency, are a crucial component. With the continuous increase in serial I / O data rates, bandwidth limitation has become a major bottleneck for high-frequency signal transmission. Simultaneously, factors such as channel loss (e.g., attenuation caused by the skin effect) and inter-symbol interference (ISI) pose significant challenges to maintaining signal integrity. To overcome these problems, equalization techniques have become an indispensable component of high-speed serial links.

[0003] Common high-speed serial link equalization schemes include feedforward equalizers (FFE), continuous-time linear equalizers (CTLE), and decision feedback equalizers (DFE). DFE and CTLE are particularly widely used in receiver analog front-ends (AFEs). While DFE excels in mitigating ISI, its high algorithm complexity and design difficulty, coupled with its relatively high power consumption, negatively impact overall system energy efficiency. In contrast, CTLE, as an analog equalizer, is favored for its simple structure, low power consumption, and full-band compensation capabilities, thus finding widespread application in receiver equalization. However, designing high-performance CTLEs still faces numerous challenges, including low power consumption, small area, low bit error rate (BER), higher bandwidth, and superior equalization performance. Furthermore, adaptively adjusting CTLE parameters to cope with channel variations is also a crucial consideration.

[0004] Patent CN115242585B proposes a continuous-time linear equalizer (CTLE) circuit based on feedforward technology. This technology extracts high-frequency signals from the input differential signal through a high-pass frequency selection network for compensation, effectively avoiding the mutual constraint between high-frequency compensation strength and low-frequency gain in traditional structures, thereby improving signal transmission quality. Although this solution meets the low-power requirement, it uses a traditional source degradation structure, resulting in limited high-frequency compensation capability and difficulty in supporting higher-speed signal transmission. Patent CN118200088A proposes an adaptive equalizer circuit and its control method, which can adaptively adjust high-frequency signal compensation according to system state. This circuit can adaptively adjust the variable capacitor value according to changes in transmission channel, ambient temperature, power supply voltage, etc. However, this design neglects the compensation for low-frequency channel loss, which is often ignored due to its relatively gentle slope. Summary of the Invention

[0005] To improve adaptability to different transmission channels, enhance high-frequency compensation capability, and optimize compensation for low-frequency channel loss, this invention provides a receiver equalization circuit for a SerDes communication system. The circuit includes a cascaded continuous-time linear equalizer (CTLE) and a variable gain amplifier (VGA), with the output of the CTLE equalizer connected to the input of the VGA. The CTLE equalizer includes a first source follower, a second source follower, a negative capacitor circuit, and an active inductor circuit; the first source follower circuit is connected to the active inductor circuit, the second source follower is connected to the output terminal of the CTLE equalizer, and the active inductor circuit is connected to the load terminal of the CTLE equalizer; the negative capacitor circuit is connected to the output terminal of the CTLE equalizer and is used to generate a capacitive negative impedance at the output node.

[0006] Optionally, the variable gain amplifier VGA includes a transconductance enhancement structure circuit, which includes: a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a third resistor R3, and a fourth resistor R4. The gate of the third PMOS transistor P3 is connected to the drain of the ninth NMOS transistor N9 and the second terminal of the ninth current source I9, respectively. The source is connected to a voltage source, and the drain is connected to the first terminal of the second resistor R2. The gate of the fourth PMOS transistor P4 is connected to the drain of the tenth NMOS transistor N10 and the second terminal of the tenth current source I10, respectively. The source is connected to a voltage source, and the drain is connected to the second terminal of the second resistor R2. The gate of the fifth PMOS transistor P5 is connected to the drain of the ninth NMOS transistor N9 and the second terminal of the ninth current source I9, respectively. The source is connected to a voltage source, and the drain is connected to the first output terminal of the variable gain amplifier VGA and the first terminal of the third resistor R3. The gate of the sixth PMOS transistor P6 is connected to the drain of the tenth NMOS transistor N10 and the second terminal of the tenth current source I10, respectively. The source is connected to a voltage source, and the drain is connected to the second output terminal of the variable gain amplifier VGA and the first terminal of the fourth resistor R4. The first end of the third resistor R3 is connected to the drain of the fifth PMOS transistor P5 and the first output terminal of the variable gain amplifier VGA, and the second end is grounded; the first end of the fourth resistor R4 is connected to the drain of the sixth PMOS transistor P6 and the second output terminal of the variable gain amplifier VGA, and the second end is grounded.

[0007] Optionally, the variable gain amplifier VGA further includes: a ninth NMOS transistor N9, a tenth NMOS transistor N10, a ninth current source I9, a tenth current source I10, an eleventh current source I11, a twelfth current source I12, and a fourth variable resistor R. S4. The second resistor R2; The gate of the ninth NMOS transistor N9 serves as the first input terminal of the variable gain amplifier VGA, connected to the first output terminal of the CTLE equalizer. Its source is connected to the first terminal of the eleventh current source I11, and its drain is connected to the second terminal of the ninth current source I9. The gate of the tenth NMOS transistor N10 serves as the second input terminal of the variable gain amplifier VGA, connected to the second output terminal of the CTLE equalizer. Its source is connected to the first terminal of the twelfth current source I12, and its drain is connected to the second terminal of the tenth current source I10. The first terminal of the ninth current source I9 is ​​connected to a voltage source, and its second terminal is connected to the drain of the ninth NMOS transistor N9. The first terminal of the tenth current source I10 is connected to a voltage source, and its second terminal is connected to the drain of the tenth NMOS transistor N10. The first terminal of the eleventh current source I11 is connected to the source of the ninth NMOS transistor N9, and its second terminal is grounded. The first terminal of the twelfth current source I12 is connected to the source of the tenth NMOS transistor N10, and its second terminal is grounded. The fourth variable resistor R... S The first end of 4 is connected to the source of the ninth NMOS transistor N9, the second end is connected to the source of the tenth NMOS transistor N10, and the third end is connected to the control voltage Vrctrl; the two ends of the second resistor R2 are respectively connected across the sources of the ninth NMOS transistor N9 and the tenth NMOS transistor N10.

[0008] Optionally, the CTLE equalizer further includes: a first NMOS transistor N1, a second NMOS transistor N2, and a first variable resistor R. S 1. Variable capacitor C S 1. First resistor R1, first load capacitor C L 1. Second load capacitor C L 2. First current source I1, second current source I2; The gate of the first NMOS transistor N1 is connected to the first input terminal of the CTLE equalizer, the source is connected to the first terminal of the first current source I1, and the drain is connected to the drain of the first PMOS transistor P1; the gate of the second NMOS transistor N2 is connected to the second input terminal of the CTLE equalizer, the source is connected to the first terminal of the second current source I2, and the drain is connected to the drain of the second PMOS transistor P2; the first variable resistor R S The first terminal of 1 is connected to the source of the first NMOS transistor N1, the second terminal is connected to the source of the second NMOS transistor N2, and the third terminal is connected to the control voltage Vrctrl; the variable capacitor C SThe first terminal of resistor R1 is connected to the source of the first NMOS transistor N1, the second terminal is connected to the source of the second NMOS transistor N2, and the third terminal is connected to the control voltage Vcctrl; the two ends of the first resistor R1 are respectively connected across the sources of the first NMOS transistor N1 and the second NMOS transistor N2; the first load capacitor C L The first terminal of 1 is connected to the first output terminal of the CTLE equalizer, and the second terminal is grounded; the second load capacitor C L The first end of 2 is connected to the second output end of the CTLE equalizer, and the second end is grounded; the first end of the first current source I1 is connected to the source of the first NMOS transistor N1, and the second end of the first current source I1 is grounded; the first end of the second current source I2 is connected to the source of the second NMOS transistor N2, and the second end of the second current source I2 is grounded.

[0009] Optionally, the first source follower includes: a third NMOS transistor N3, a fourth NMOS transistor N4, a third current source I3, and a fourth current source I4; The gate of the third NMOS transistor N3 is connected to the first terminal of the second variable resistor Rs2, the source is connected to the first terminal of the third current source I3, and the drain is connected to a voltage source; the gate of the fourth NMOS transistor N4 is connected to the first terminal of the third variable resistor Rs3, the source is connected to the first terminal of the fourth current source I4, and the drain is connected to a voltage source; the first terminal of the third current source I3 is connected to the source of the third NMOS transistor N3, and the second terminal is grounded; the first terminal of the fourth current source I4 is connected to the source of the fourth NMOS transistor N4, and the second terminal is grounded.

[0010] Optionally, the second source follower includes a fifth NMOS transistor N5, a sixth NMOS transistor N6, a fifth current source I5, and a sixth current source I6; The gate of the fifth NMOS transistor N5 is connected to the second terminal of the second variable resistor Rs2, the source is connected to the first terminal of the fifth current source I5, and the drain is connected to a voltage source; the gate of the sixth NMOS transistor N6 is connected to the second terminal of the third variable resistor Rs3, the source is connected to the first terminal of the sixth current source I6, and the drain is connected to a voltage source; the first terminal of the fifth current source I5 is connected to the source of the fifth NMOS transistor N5, and the second terminal is grounded; the first terminal of the sixth current source I6 is connected to the source of the sixth NMOS transistor N6, and the second terminal is grounded.

[0011] Optionally, the active inductor circuit includes: a first PMOS transistor P1, a second PMOS transistor P2, and a second variable resistor R. S 2 and the third variable resistor R S 3; The active inductor circuit includes: a first PMOS transistor P1, a second PMOS transistor P2, and a second variable resistor R.S 2 and the third variable resistor R S 3; The gate of the first PMOS transistor P1 is connected to the source of the third NMOS transistor N3, the source is connected to a voltage source, and the drain is connected to the gate of the fifth NMOS transistor N5; the gate of the second PMOS transistor P2 is connected to the source of the fourth NMOS transistor N4, the source is connected to a voltage source, and the drain is connected to the gate of the sixth NMOS transistor N6; the second variable resistor R S The first terminal of 2 is connected to the gate of the third NMOS transistor N3, the second terminal is connected to the drain of the first PMOS transistor P1, and the third terminal is connected to the tuning voltage V. b The third variable resistor R S The first terminal of terminal 3 is connected to the gate of the fourth NMOS transistor N4, the second terminal is connected to the drain of the second PMOS transistor P2, and the third terminal is connected to the tuning voltage V. b .

[0012] Optionally, the negative capacitor circuit includes: a seventh NMOS transistor N7, an eighth NMOS transistor N8, a first capacitor C1, a seventh current source I7, and an eighth current source I8; The gate of the seventh NMOS transistor N7 is connected to the drain of the eighth NMOS transistor N8, the source is connected to the first terminal of the seventh current source I7, and the drain is connected to the first output terminal of the CTLE equalizer; the gate of the eighth NMOS transistor N8 is connected to the drain of the seventh NMOS transistor N7, the source is connected to the first terminal of the eighth current source I8, and the drain is connected to the second output terminal of the CTLE equalizer; the first terminal of the first capacitor C1 is connected to the source of the seventh NMOS transistor N7, and the second terminal is connected to the source of the eighth NMOS transistor N8; the first terminal of the seventh current source I7 is connected to the source of the seventh NMOS transistor N7, and the second terminal is grounded; the first terminal of the eighth current source I8 is connected to the source of the eighth NMOS transistor N8, and the second terminal is grounded.

[0013] A second objective of the present invention is to provide a SerDes communication system, wherein the receiving end of the system is provided with a receiving end equalization circuit as described in any of the preceding claims for use in a SerDes communication system.

[0014] A third objective of this invention is to provide a receiver analog front-end equalization method, the method being implemented based on the receiver equalization circuit applied to a SerDes communication system as described in any of the preceding claims, comprising: receiving an input AC signal from a first input terminal and a second input terminal of a CTLE input balancer, and outputting a signal from a first output terminal and a second output terminal of the variable gain amplifier VGA.

[0015] The beneficial effects of this invention are: This invention provides a receiver analog front-end equalization circuit, including a continuous-time linear equalizer (CTLE) and a variable gain amplifier (VGA). The CTLE employs an active inductor structure, a negative capacitor structure, and a source follower structure, while the VGA employs a transconductance boosting structure, which can significantly improve the circuit performance.

[0016] Furthermore, the continuous-time linear equalizer (CTLE) of this invention employs a source follower structure. The first source follower circuit is connected to an active inductor circuit to reduce the gate voltages of the first PMOS transistor P1 and the second PMOS transistor P2, thereby reducing power consumption. The second source follower circuit is connected to the output of the CTLE equalizer. The signal is ultimately input from the gate and output from the drain of the second source follower, used to reduce the output common-mode level to match the input common-mode level of the next-stage VGA, thereby improving the overall gain and bandwidth. Simultaneously, active inductor peaking technology is used to expand the bandwidth. Compared to traditional passive inductor loads, it significantly reduces the circuit layout area, saves power consumption, and can provide variable impedance by changing the control voltage Vb, improving adaptability to different transmission channels. The cascaded negative capacitor structure at the output can cancel the original first pole of the circuit by introducing an additional zero, further improving gain and bandwidth compared to the traditional CTLE, thereby increasing the system's transmission rate. Furthermore, the variable gain amplifier (VGA) of this invention employs a unique transconductance enhancement structure. Specifically, a transconductance boosting circuit is constructed using the third PMOS transistor P3 and the fourth PMOS transistor P4. Signals are sampled from the drains of the ninth NMOS transistor N9 and the tenth NMOS transistor N10, and a negative feedback loop is formed by a degenerate connection between the drain and source. The third PMOS transistor P3 and the fourth PMOS transistor P4 can be equivalent to an operational amplifier, utilizing their "virtual short" and "virtual open" characteristics to lock the drain voltages of the ninth NMOS transistor N9 and the tenth NMOS transistor N10 to a specific value, thereby achieving accurate sampling of the output voltage. This output voltage sampling method effectively reduces the circuit's output impedance and effectively increases the transconductance gm. To further improve linearity and reduce gain loss due to low impedance, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are configured as source followers, connected between the output terminal and the load resistor. Finally, by adjusting the resistor to control the voltage Vrctrl, the overall low-frequency DC gain of the circuit can be flexibly controlled, thereby meeting the needs of signals with different transmission rates. The overall circuit power consumption of this invention is only 11.3mW, which is lower than that of traditional equalizers. It has a smaller area and a simple structure that is easy to implement. At the same time, it improves the transmission rate of the system and has better equalization effect and good stability. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a complete circuit diagram of the receiver analog front-end equalization circuit of the present invention.

[0019] Figure 2 This is a circuit diagram of a traditional continuous-time linear equalizer (CTLE).

[0020] Figure 3 This is a circuit diagram of a traditional variable gain amplifier (VGA).

[0021] Figure 4 This is a graph showing the amplitude-frequency gain curve of the variable gain amplifier VGA obtained by adjusting the control voltage Vrctrl in Embodiment 2 of the present invention.

[0022] Figure 5 The frequency response curve of the analog front end of the integrated receiver of the present invention as a function of the regulated voltage Vrctrl.

[0023] Figure 6 This is a loss curve for a simulated channel according to the present invention.

[0024] Figure 7 This is an eye diagram of the receiver circuit with and without the PCIe 3.0 channel transmission line turned on and off at 56Gbps, according to Embodiment 2 of the present invention.

[0025] Figure 8 This is an eye diagram of the receiver circuit with and without the signal passing through the PCIe 3.0 channel transmission line at 112Gbps, according to an embodiment of the present invention.

[0026] Figure 9 The image shows the bathtub curves after signal equalization at the receiver of the SerDes high-speed serial link in this embodiment of the invention, with signal rates of 56Gbps and 112Gbps.

[0027] 1. Continuous-Time Linear Equalizer (CTLE) circuit, 101, CTLE equalizer first input terminal, 102, CTLE equalizer second input terminal, 103, first variable resistor R S 1. Control input terminal, 104, variable capacitor C S 1. Control voltage input terminal, 105, second variable resistor R S 2. Control voltage input terminal, 106, third variable resistor R S3. Control voltage input terminal; 107. First output terminal of CTLE equalizer circuit; 108. Second output terminal of CTLE equalizer circuit.

[0028] 2. Variable gain amplifier VGA circuit: 201, CTLE first input terminal; 202, CTLE second input terminal; 203, fourth variable resistor R. S 4. Control voltage input terminal; 204. VGA first output terminal; 205. VGA second output terminal. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0030] Example 1: This embodiment provides a receiver equalization circuit for a SerDes communication system, including a cascaded continuous-time linear equalizer (CTLE) and a variable gain amplifier (VGA), with the output of the CTLE equalizer connected to the input of the VGA. The CTLE equalizer includes a first source follower, a second source follower, a negative capacitor circuit, and an active inductor circuit. The first source follower circuit is connected to the active inductor circuit, the second source follower is connected to the output terminal of the CTLE equalizer, and the active inductor circuit is connected to the load terminal of the CTLE equalizer. The negative capacitor circuit is connected to the output terminal of the CTLE equalizer to generate a capacitive negative impedance at the output node.

[0031] Example 2: This embodiment provides a receiver equalization circuit for a SerDes communication system, including a cascaded continuous-time linear equalizer (CTLE) and a variable gain amplifier (VGA). The CTLE employs an active inductor structure, a negative capacitor structure, and a source follower structure, while the VGA employs a transconductance boosting structure, which can significantly improve the circuit performance.

[0032] The source follower architecture includes a first source follower and a second source follower, such as... Figure 1As shown. The first source follower includes: a third NMOS transistor N3, a fourth NMOS transistor N4, a third current source I3, and a fourth current source I4. The second source follower includes: a fifth NMOS transistor N5, a sixth NMOS transistor N6, a fifth current source I5, and a sixth current source I6. The first source follower circuit is connected to the active inductor circuit to reduce the gate voltage of the first PMOS transistor P1 and the second PMOS transistor P2, thereby reducing power consumption. The second source follower is connected to the output of the CTLE equalizer. The signal is ultimately input from the gate and output from the drain of the second source follower, which is used to reduce the output common-mode level to match the input common-mode level of the next stage VGA, thereby improving the overall gain and bandwidth.

[0033] The active inductor circuit includes: a first PMOS transistor P1, a second PMOS transistor P2, and a second variable resistor R. S 2. Third variable resistor R S 3. Compared to traditional passive inductive loads, it significantly reduces circuit layout area, saves power consumption, and can be controlled by changing the control voltage V. b This provides variable impedance, improving adaptability to different transmission channels.

[0034] The negative capacitor circuit includes: the seventh NMOS transistor N7, the eighth NMOS transistor N8, the first capacitor C1, the seventh current source I7, and the eighth current source I8. It generates a capacitive negative impedance at the output node, thereby canceling out the effect of the capacitance at the output node and increasing the base frequency at the output node.

[0035] The impedance of an active inductor can be described as:

[0036] in, S Represents a complex frequency variable. Indicates the second and third variable resistors R S2 R S3 The resistance value, This represents the equivalent resistance values ​​of the first and second PMOS transistors, P1 and P2. This represents the gate-source capacitance values ​​of the first and second PMOS transistors P1 and P2. This indicates the transconductance of the first and second PMOS transistors P1 and P2.

[0037] Equivalent impedance of a negative capacitor circuit Z NegC It can be described as:

[0038] in, This represents the capacitive reactance of the first capacitor C1. This represents the gate-source capacitance of the seventh NMOS transistor (N7) and the eighth NMOS transistor (N8). S Represents a complex frequency variable. This indicates the transconductance of the seventh and eighth NMOS transistors, N7 and N8.

[0039] The transfer function of the CTLE equalizer in this embodiment can be described as follows:

[0040] in: , , , .

[0041] For the sake of convenience, let the above expression be:

[0042] in, This represents the transconductance of the first and second NMOS transistors N1 and N2. This indicates the transconductance of the seventh and eighth NMOS transistors N7 and N8. Represents a complex frequency variable. This indicates the DC gain of the CTLE equalizer. Represents the first and second load capacitors C L1 and C L2 The capacitance value, Indicates the load resistance value. Indicates the source degradation capacitance value. R S Indicates the source degradation resistance value. This indicates the negative capacitance value.

[0043] Variable gain amplifier VGA circuit, such as Figure 1 As shown, the second stage of the SerDes receiver front-end circuit adjusts the overall low-frequency DC gain of the circuit by controlling the voltage Vrctrl through a resistor, thereby changing the overall low-frequency DC gain of the circuit to adapt to signals with different transmission rates. The transconductance enhancement structure circuit is shown below. Figure 1As shown, the structure includes: a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a third resistor R3, and a fourth resistor R4. The third PMOS transistor P3 and the fourth PMOS transistor P4 can be considered equivalent to operational amplifier structures, while the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are equivalent to source followers. The gates of the third PMOS transistor P3 and the fourth PMOS transistor P4 form the input terminals of the transconductance boost circuit, while their drains are the output terminals and connected to the source degradation resistors. The feedback signal is introduced from the sources of the ninth NMOS transistor N9 and the tenth NMOS transistor N10. This structure effectively applies gain to the transconductance of the ninth NMOS transistor N9 and the tenth NMOS transistor N10, equivalent to the small-signal open-loop gain of a transconductance amplifier. This is the product of their transconductance and the output node impedance; the improved transconductance becomes... .in This represents the transconductance of the ninth NMOS transistor N9 and the tenth NMOS transistor N10. Furthermore, the ninth current source I9, the tenth current source I10, the eleventh current source I11, and the twelfth current source I12 together provide the necessary quiescent current to drive the circuit to operate normally. Figure 4 The graph shows the amplitude-frequency gain curve of the variable gain amplifier VGA obtained by adjusting the control voltage Vrctrl.

[0044] The first and second input terminals of the CTLE of this invention are connected to input AC signals. After being equalized by the analog front-end equalization circuit of the receiver, the signals are output from the first and second output terminals of the VGA. The two-stage cascaded linear equalizer has variable amplitude-frequency gain to achieve channel flattening and compensate for channel loss.

[0045] The verification example proposed in this invention uses PCIe 3.0 protocol hard disk data transfer to verify the feasibility of this invention.

[0046] To verify the performance of the SerDes receiver analog front-end circuit in this embodiment, detailed simulation tests were conducted. In the tests, the circuit was applied to a SerDes receiver, with the transmitter signal rate set to 56 Gb / s and 112 Gb / s. The test signal code was PRBS15, and the modulation formats were NRZ and PAM4, respectively. Figure 5 The frequency response curve of the designed receiver front-end equalization circuit is shown, with a peak frequency at 28 GHz. The source degradation resistor of this circuit adopts an adjustable structure. By changing the control voltage Vrctrl, the DC gain at low frequencies can be flexibly adjusted while keeping the peak gain constant, so as to adapt to channels with different transmission rates and losses. Figure 6 The analog channel model used is shown.

[0047] First, the transmission of a 56 Gb / s signal in the channel was simulated. The channel loss at the Nyquist frequency (28 GHz) was -24.2 dB. After equalization by the receiver simulation front-end circuit designed in this invention, the channel loss was effectively compensated. The eye diagrams before and after equalization are shown below. Figure 7 As shown, the eye diagram is completely closed when the equalization circuit is not enabled; however, when the equalization circuit is enabled, the eye height is approximately 544 mV and the eye width is increased by approximately 0.87 UI, demonstrating an ideal equalization effect.

[0048] Next, the transmission of a 112 Gb / s signal in the channel was simulated. In this scenario, by adjusting the control voltage Vrctrl, we adjusted the DC gain at low frequencies while maintaining the high-frequency gain to avoid over-equalization. The channel loss at the Nyquist frequency of the 112 Gb / s signal was -24.2 dB. After equalization by the designed receiver front-end, the channel loss was effectively compensated, and the eye diagram after equalization is shown below. Figure 8 As shown. When the equalization circuit is not turned on, the eye diagram is completely closed; after equalization, the eye height is about 148 mV, and the eye width is opened by about 8.5 ps, which also achieves the ideal equalization effect.

[0049] The signal bathtub curve obtained at the receiver of the SerDes communication system in this simulation experiment is as follows: Figure 9 As shown, both the 56 Gb / s NRZ signal and the 112 Gb / s PAM4 signal can be used at 10 -9 The successful opening at the bit error rate proves the feasibility of the designed SerDes analog front-end equalizer, which significantly improves the signal integrity of high-speed links. The above results show that the receiver analog front-end circuit designed in this invention can achieve good equalization performance at different transmission rates, effectively improving signal integrity.

[0050] In summary, the SerDes receiver analog front-end circuit designed in this invention innovatively employs a continuous-time linear equalizer (CTLE) combining an active inductor, a source follower, and a negative capacitor circuit, as well as a variable gain amplifier (VGA) integrating a transconductance boosting circuit. This unique design enables the circuit to achieve greater bandwidth and higher high-frequency gain. Furthermore, by flexibly adjusting the resistance value of the source degradation resistor through adjustable control voltage, precise control of the low-frequency DC gain is achieved, thereby dynamically adapting to different transmission rates. In practical verification, the receiver front-end circuit designed in this invention successfully and effectively equalizes signals of different rates passing through the PCIe 3.0 channel, significantly reducing tailing effects at the system level and effectively suppressing inter-symbol interference (ISI), thus significantly improving signal integrity.

[0051] Some steps in the embodiments of the present invention can be implemented using software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk.

[0052] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A receiver equalization circuit for use in a SerDes communication system, characterized in that, The circuit includes a cascaded continuous-time linear equalizer (CTLE) and a variable gain amplifier (VGA), with the output of the CTLE equalizer connected to the input of the VGA. The CTLE equalizer includes a first source follower, a second source follower, a negative capacitor circuit, and an active inductor circuit; the first source follower circuit is connected to the active inductor circuit, the second source follower is connected to the output terminal of the CTLE equalizer, and the active inductor circuit is connected to the load terminal of the CTLE equalizer. The negative capacitor circuit is connected to the output terminal of the CTLE equalizer and is used to generate a capacitive negative impedance at the output node. The first source follower includes: a third NMOS transistor N3, a fourth NMOS transistor N4, a third current source I3, and a fourth current source I4; the second source follower includes a fifth NMOS transistor N5, a sixth NMOS transistor N6, a fifth current source I5, and a sixth current source I6; the active inductor circuit includes: a first PMOS transistor P1, a second PMOS transistor P2, and a second variable resistor R. S 2 and the third variable resistor R S 3; The negative capacitor circuit includes: a seventh NMOS transistor N7, an eighth NMOS transistor N8, a first capacitor C1, a seventh current source I7, and an eighth current source I8; The drain of the third NMOS transistor N3 is connected to a voltage source; the drain of the fourth NMOS transistor N4 is connected to a voltage source; the first terminal of the third current source I3 is connected to the source of the third NMOS transistor N3, and the second terminal is grounded; the first terminal of the fourth current source I4 is connected to the source of the fourth NMOS transistor N4, and the second terminal is grounded. The gate of the fifth NMOS transistor N5 is connected to the second terminal of the second variable resistor Rs2, and the drain is connected to a voltage source; the gate of the sixth NMOS transistor N6 is connected to the second terminal of the third variable resistor Rs3, and the drain is connected to a voltage source; the first terminal of the fifth current source I5 is connected to the source of the fifth NMOS transistor N5, and the second terminal is grounded; the first terminal of the sixth current source I6 is connected to the source of the sixth NMOS transistor N6, and the second terminal is grounded. The gate of the first PMOS transistor P1 is connected to the source of the third NMOS transistor N3, the source is connected to a voltage source, and the drain is connected to the gate of the fifth NMOS transistor N5; the gate of the second PMOS transistor P2 is connected to the source of the fourth NMOS transistor N4, the source is connected to a voltage source, and the drain is connected to the gate of the sixth NMOS transistor N6; the second variable resistor R S The first terminal of 2 is connected to the gate of the third NMOS transistor N3, the second terminal is connected to the drain of the first PMOS transistor P1, and the third terminal is connected to the tuning voltage V. b The third variable resistor R S The first terminal of terminal 3 is connected to the gate of the fourth NMOS transistor N4, the second terminal is connected to the drain of the second PMOS transistor P2, and the third terminal is connected to the tuning voltage V. b ; The gate of the seventh NMOS transistor N7 is connected to the drain of the eighth NMOS transistor N8, and the drain is connected to the first output terminal of the CTLE equalizer; the gate of the eighth NMOS transistor N8 is connected to the drain of the seventh NMOS transistor N7, and the drain is connected to the second output terminal of the CTLE equalizer; the first terminal of the first capacitor C1 is connected to the source of the seventh NMOS transistor N7, and the second terminal is connected to the source of the eighth NMOS transistor N8; the first terminal of the seventh current source I7 is connected to the source of the seventh NMOS transistor N7, and the second terminal is grounded; the first terminal of the eighth current source I8 is connected to the source of the eighth NMOS transistor N8, and the second terminal is grounded.

2. The equalization circuit for the receiver in a SerDes communication system according to claim 1, characterized in that, The variable gain amplifier VGA includes a transconductance enhancement structure circuit, which includes: a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a third resistor R3, and a fourth resistor R4. The gate of the third PMOS transistor P3 is connected to the drain of the ninth NMOS transistor N9 and the second terminal of the ninth current source I9, respectively. The source is connected to a voltage source, and the drain is connected to the first terminal of the second resistor R2. The gate of the fourth PMOS transistor P4 is connected to the drain of the tenth NMOS transistor N10 and the second terminal of the tenth current source I10, respectively. The source is connected to a voltage source, and the drain is connected to the second terminal of the second resistor R2. The gate of the fifth PMOS transistor P5 is connected to the drain of the ninth NMOS transistor N9 and the second terminal of the ninth current source I9, respectively. The source is connected to a voltage source, and the drain is connected to the first output terminal of the variable gain amplifier VGA and the first terminal of the third resistor R3. The gate of the sixth PMOS transistor P6 is connected to the drain of the tenth NMOS transistor N10 and the second terminal of the tenth current source I10, respectively. The source is connected to a voltage source, and the drain is connected to the second output terminal of the variable gain amplifier VGA and the first terminal of the fourth resistor R4. The first end of the third resistor R3 is connected to the drain of the fifth PMOS transistor P5 and the first output terminal of the variable gain amplifier VGA, and the second end is grounded; the first end of the fourth resistor R4 is connected to the drain of the sixth PMOS transistor P6 and the second output terminal of the variable gain amplifier VGA, and the second end is grounded.

3. The equalization circuit for the receiver in a SerDes communication system according to claim 1, characterized in that, The variable gain amplifier VGA also includes: a ninth NMOS transistor N9, a tenth NMOS transistor N10, a ninth current source I9, a tenth current source I10, an eleventh current source I11, a twelfth current source I12, and a fourth variable resistor R. S 4. The second resistor R2; The gate of the ninth NMOS transistor N9 serves as the first input terminal of the variable gain amplifier VGA, connected to the first output terminal of the CTLE equalizer. Its source is connected to the first terminal of the eleventh current source I11, and its drain is connected to the second terminal of the ninth current source I9. The gate of the tenth NMOS transistor N10 serves as the second input terminal of the variable gain amplifier VGA, connected to the second output terminal of the CTLE equalizer. Its source is connected to the first terminal of the twelfth current source I12, and its drain is connected to the second terminal of the tenth current source I10. The first terminal of the ninth current source I9 is ​​connected to a voltage source, and its second terminal is connected to the drain of the ninth NMOS transistor N9. The first terminal of the tenth current source I10 is connected to a voltage source, and its second terminal is connected to the drain of the tenth NMOS transistor N10. The first terminal of the eleventh current source I11 is connected to the source of the ninth NMOS transistor N9, and its second terminal is grounded. The first terminal of the twelfth current source I12 is connected to the source of the tenth NMOS transistor N10, and its second terminal is grounded. The fourth variable resistor R... S The first end of 4 is connected to the source of the ninth NMOS transistor N9, the second end is connected to the source of the tenth NMOS transistor N10, and the third end is connected to the control voltage Vrctrl; the two ends of the second resistor R2 are respectively connected across the sources of the ninth NMOS transistor N9 and the tenth NMOS transistor N10.

4. The equalization circuit for the receiver in a SerDes communication system according to claim 1, characterized in that, The CTLE equalizer also includes: a first NMOS transistor N1, a second NMOS transistor N2, and a first variable resistor R. S 1. Variable capacitor C S 1. First resistor R1, first load capacitor C L 1. Second load capacitor C L 2. First current source I1, second current source I2; The gate of the first NMOS transistor N1 is connected to the first input terminal of the CTLE equalizer, the source is connected to the first terminal of the first current source I1, and the drain is connected to the drain of the first PMOS transistor P1; the gate of the second NMOS transistor N2 is connected to the second input terminal of the CTLE equalizer, the source is connected to the first terminal of the second current source I2, and the drain is connected to the drain of the second PMOS transistor P2; the first variable resistor R S The first terminal of 1 is connected to the source of the first NMOS transistor N1, the second terminal is connected to the source of the second NMOS transistor N2, and the third terminal is connected to the control voltage Vrctrl; the variable capacitor C S The first terminal of resistor R1 is connected to the source of the first NMOS transistor N1, the second terminal is connected to the source of the second NMOS transistor N2, and the third terminal is connected to the control voltage Vcctrl; the two ends of the first resistor R1 are respectively connected across the sources of the first NMOS transistor N1 and the second NMOS transistor N2; the first load capacitor C L The first terminal of 1 is connected to the first output terminal of the CTLE equalizer, and the second terminal is grounded; the second load capacitor C L The first end of 2 is connected to the second output end of the CTLE equalizer, and the second end is grounded; the first end of the first current source I1 is connected to the source of the first NMOS transistor N1, and the second end of the first current source I1 is grounded; the first end of the second current source I2 is connected to the source of the second NMOS transistor N2, and the second end of the second current source I2 is grounded.

5. A SerDes communication system, characterized in that, The receiving end of the system is provided with a receiving end equalization circuit as described in any one of claims 1-4 for use in a SerDes communication system.

6. A receiver analog front-end equalization method, characterized in that, The method is based on the receiver equalization circuit applied to the SerDes communication system as described in any one of claims 1-4, and includes: receiving an input AC signal from the first and second input terminals of the CTLE input balancer, and outputting a signal from the first and second output terminals of the variable gain amplifier VGA.

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