3D non-uniform network-on-chip topology

Abstract

The application provides a 3D non-uniform network-on-chip topology structure, comprising a plurality of local devices and a plurality of inter-layer network routers, the inter-layer network routers are connected to form a ring structure; the local device is configured to receive and / or send transmission data; the inter-layer network router is configured to send the transmission data to the local device when the corresponding local device is in an idle state, and is further configured to circulate the transmission data through the remaining inter-layer network routers when the corresponding local device is in a busy state, and send the transmission data to the corresponding local device when the corresponding local device returns to the idle state; a plurality of layer router network layers comprising a plurality of interconnected intra-layer network routers; the intra-layer network router and the inter-layer network router are configured to independently transmit the request, response and transmission data respectively. The application solves the problems of easy deadlock and congestion of the existing architecture through the above structure.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit network topology technology, and in particular to a 3D non-uniform on-chip network topology. Background Technology

[0002] With the continuous development of semiconductor technology, integrating a large number of computing cores on a single chip has become a reality. However, the problem of data exchange between nodes is becoming increasingly prominent, severely restricting the performance improvement of multi-core processors and multi-processor system chips. Traditional on-chip interconnect solutions are limited by insufficient scalability and cannot support the high-efficiency communication requirements of large-scale systems.

[0003] To overcome these bottlenecks, Network-on-Chip (NoC) technology emerged, significantly improving system bandwidth utilization and scalability by constructing a miniature networked interconnect architecture, providing an effective solution for large-scale core integration. Meanwhile, 3D IC technology, utilizing through-silicon vias (TSVs), enables vertical stacking of multiple silicon wafers to form heterogeneous integrated systems. This technology drastically shortens interconnect distances, reduces communication latency and power consumption, and significantly improves integration density and space utilization, becoming a key technology driving the development of high-performance chips. The rapid evolution of artificial intelligence technology further drives changes in computing architecture. The application of large-scale neural networks has spurred demand for modular, distributed acceleration chips. Their flexible and varied data exchange modes rely more heavily on efficient non-uniform communication architectures, placing higher bandwidth, lower latency, and stronger scalability requirements on-chip interconnects.

[0004] However, the multidimensional interconnect complexity introduced by 3D integration technology poses a serious challenge to traditional two-dimensional network-on-chip (2D NoC): extended cross-layer communication paths and heterogeneous resource distribution lead to decreased scalability and reliability, making it difficult to meet the needs of large-scale heterogeneous systems. Particularly noteworthy is that in inconsistent communication scenarios, the network-on-chip needs to independently manage high-intensity data and control flows. Traditional architectures are highly susceptible to deadlock or livelock risks due to resource conflicts and dependency cycles, severely restricting system stability and performance optimization. Summary of the Invention

[0005] This application provides a 3D non-uniform on-chip network topology to solve the problems of deadlock and congestion that are prone to occur in existing architectures.

[0006] The structure includes:

[0007] The system comprises several local devices and several inter-layer network routers, with each local device corresponding to one of the inter-layer network routers. All the inter-layer network routers are interconnected to form a ring structure. Each local device is configured to receive and / or send transmission data. Each inter-layer network router is configured to send the transmission data to the corresponding local device when the local device is idle. Furthermore, each inter-layer network router is configured to circulate the transmission data through the remaining inter-layer network routers when the corresponding local device is busy, and to send the transmission data back to the corresponding local device when the local device returns to an idle state.

[0008] The system comprises several router network layers, each connected to an inter-layer network router. Each router network layer includes several interconnected intra-layer network routers. The router network layers are configured to send the transmitted data to the inter-layer network routers. The intra-layer network routers are configured to independently perform request, response, and transmitted data transmission, respectively.

[0009] Preferably, the intra-layer network router includes an edge router and an intermediate router. The edge router is an intra-layer network router located on both sides of the edge of the router's network layer, and the intermediate router is an intra-layer network router located between the two edge routers.

[0010] The edge router is connected to the inter-layer network router, and the intermediate router is connected to four intra-layer network routers in the horizontal direction. The four intra-layer network routers include the intermediate router adjacent to the current intermediate router and / or the adjacent edge router.

[0011] Preferably, the structure further includes:

[0012] At least one memory, and at least one of the inter-layer network routers connected to one of the memory; the memory is configured as a shared storage resource for the on-chip network and to store valid data accessible to multiple local devices.

[0013] Preferably, both the intra-layer network router and the inter-layer network router include:

[0014] A request channel, configured to process requests for the transmitted data;

[0015] A data channel configured to process the transmission of the transmitted data;

[0016] A response channel, configured to process responses to the transmitted data.

[0017] Preferably, both the intra-layer network router and the inter-layer network router include three independent network sub-routers at each layer, and the three network sub-routers correspond to the request channel, the data channel, and the response channel, respectively.

[0018] Preferably, the local device includes a master device and a slave device, wherein the master device is the sender of the transmitted data and the slave device is the receiver of the transmitted data.

[0019] The master device is configured as follows:

[0020] The request is sent to the slave device through the request channels of the intra-layer network router and the inter-layer network router;

[0021] After the slave device responds through the response channel corresponding to the intra-layer network router and the inter-layer network router, it caches the transmitted data into the slave device's data buffer through the data channel corresponding to the intra-layer network router and the inter-layer network router.

[0022] The slave device is configured as follows:

[0023] When a request sent by the master device is obtained through the request channel corresponding to the intra-layer network router and the inter-layer network router, a response is made through the response channel corresponding to the intra-layer network router and the inter-layer network router, and the data buffer is allocated for the transmitted data.

[0024] After obtaining the transmission data through the data channels of the corresponding intra-layer network router and inter-layer network router, the transmission data is cached in the data buffer.

[0025] Preferably, the inter-layer network sub-router includes:

[0026] Two flow control units, which are configured to:

[0027] Determine the sending end and receiving end of the transmitted data;

[0028] The transmission data is sent to the adjacent inter-layer network router and the corresponding slave or master device of the inter-layer network router according to the sending end and receiving end of the transmission data.

[0029] Preferably, the inter-layer network sub-router further includes:

[0030] An output sliding buffer is provided at the output end of each flow control unit; the output sliding buffer is configured to balance the data processing relationship between adjacent nodes; the adjacent nodes include adjacent intra-layer network routers or inter-layer network routers;

[0031] An input slip buffer is provided at the input of each of the flow control units; the input slip buffer is configured to balance the data processing relationship between adjacent nodes.

[0032] Preferably, the flow control unit is further configured to:

[0033] Determine whether the local device corresponding to the network router in the current layer is the target master device or the target slave device;

[0034] If not, the transmitted data is sent to the next layer inter-layer network router;

[0035] If so, determine whether the target master device or the target slave device is in an idle state;

[0036] If so, the transmitted data is sent to the target master device or the target slave device through the corresponding inter-layer network router;

[0037] If not, the transmitted data is circulated through the remaining inter-layer network routers, and when the corresponding local device returns to an idle state, the transmitted data is sent to the corresponding target master device or the target slave device.

[0038] As described above, this application provides a 3D non-uniform on-chip network topology, which includes several local devices and several inter-layer network routers. Each local device corresponds one-to-one with an inter-layer network router, and all inter-layer network routers are interconnected to form a ring structure. Each local device is configured to receive and / or send transmission data. Each inter-layer network router is configured to send the transmission data to the corresponding local device when the local device is idle. The inter-layer network router is also configured to circulate the transmission data through the remaining inter-layer network routers when the corresponding local device is busy, and to send the transmission data back to the corresponding local device when the local device returns to idle. Several router network layers are also included, each corresponding to one of the inter-layer network routers. Each router network layer includes several interconnected intra-layer network routers. Each router network layer is configured to send the transmission data to the inter-layer network routers. Each intra-layer network router is configured to independently perform request, response, and transmission data transmission. This application solves the problems of deadlock and congestion that are prone to occur in existing architectures through the above structure. Attached Figure Description

[0039] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of a 3D non-uniform on-chip network topology according to this application;

[0041] Figure 2 Schematic diagrams of fully connected rings and semi-ring structures in existing network topologies;

[0042] Figure 3 This is a schematic diagram illustrating the causes of deadlock in a network based on the AXI4 protocol.

[0043] Figure 4 This is a diagram illustrating the process of inter-protocol write request conversion in a 3D non-consistent on-chip network topology according to this application;

[0044] Figure 5 This is a schematic diagram of an inter-layer network router in a 3D non-uniform on-chip network topology according to this application;

[0045] Figure 6 A schematic diagram illustrating the causes of blockage diffusion;

[0046] Figure 7This is a schematic diagram of a long-distance route in a 3D non-uniform on-chip network topology according to this application;

[0047] Figure 8 This is a schematic diagram of an in-layer network router in a 3D non-uniform on-chip network topology according to this application. Detailed Implementation

[0048] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0049] It should be noted that the brief descriptions of terms in this application are only for the convenience of understanding the embodiments described below, and are not intended to limit the embodiments of this application. Unless otherwise stated, these terms should be understood in their ordinary and common meaning.

[0050] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0051] Figure 2 This diagram illustrates the fully connected ring and semi-ring structures in the existing network topology.

[0052] See Figure 2 As can be seen, the height of the intra-layer topology is configurable, and common types include ring structures, mesh structures, concentrated mesh (cmesh) structures, and torus structures. Inter-layer connections are made using ring topologies, which can be either fully connected rings or semi-rings with disconnected ends. The structure provided in this embodiment consists of intra-layer topologies and inter-layer interconnection topologies.

[0053] Each layer of on-chip network edge nodes connects to the ring network responsible for inter-layer communication via dedicated interfaces. This design offers high structural flexibility, allowing users to configure which edge nodes in each layer directly interconnect with the ring network based on system application requirements, topology layout, and performance metrics. Through custom configuration, this architecture can achieve customized optimizations for high-performance computing, AI acceleration, or heterogeneous packaging in different scenarios.

[0054] Figure 1 This is a schematic diagram of a 3D non-uniform on-chip network topology according to this application.

[0055] See Figure 1 As can be seen, this embodiment provides a 3D non-uniform on-chip network topology, the structure including:

[0056] The system comprises several local devices and several inter-layer network routers, with each local device corresponding to one of the inter-layer network routers. All the inter-layer network routers are interconnected to form a ring structure. Each local device is configured to receive and / or send transmission data. Each inter-layer network router is configured to send the transmission data to the corresponding local device when the local device is idle. Furthermore, each inter-layer network router is configured to circulate the transmission data through the remaining inter-layer network routers when the corresponding local device is busy, and to send the transmission data back to the corresponding local device when the local device returns to an idle state.

[0057] The system comprises several router network layers, each corresponding to one of the inter-layer network routers. Each router network layer includes several interconnected intra-layer network routers. The router network layers are configured to send the transmitted data to the inter-layer network routers. The intra-layer network routers are configured to independently perform request, response, and data transmission, respectively.

[0058] Specifically, in this embodiment, Figure 1 A 4-layer 3D on-chip network is shown, with 8 dark nodes at the edge of each layer connected to an inter-layer interconnect ring network. For clarity, the diagrams of the middle two layers are partially omitted, and only one inter-layer interconnect ring network is shown.

[0059] The intra-layer network routers include edge routers and intermediate routers. The edge routers are intra-layer network routers located on both sides of the edge of the router network layer, and the intermediate routers are intra-layer network routers located between the two edge routers. The edge routers are connected to the inter-layer network routers. The intermediate routers are connected to four intra-layer network routers in the horizontal direction. The four intra-layer network routers include intermediate routers adjacent to the current intermediate router and / or adjacent edge routers.

[0060] Among them, the inter-layer network router connected through the local device is connected to the router network layer and performs data transmission.

[0061] When the local device is currently busy, the inter-layer network router sends the transmitted data to the other inter-layer network routers in the ring structure, and then sends the transmitted data back to the local device when the local device returns to an idle state. This embodiment achieves "remote routing" in this way, thereby avoiding data congestion.

[0062] Furthermore, in some embodiments, the structure further includes:

[0063] The structure also includes:

[0064] At least one memory, and at least one of the inter-layer network routers connected to one of the memory; the memory is configured as a shared storage resource for the on-chip network and to store valid data accessible to multiple local devices.

[0065] Specifically, in this embodiment, shared storage resources are provided to the local device through memory, thereby providing the data foundation for the local device.

[0066] In the AXI4-based interconnect architecture, there is a strong dependency between the write address channel and the write data channel. That is, the write data must be transmitted strictly in the order of the address packets. Although this mechanism can guarantee the consistency of order, it may seriously affect the system performance in high-concurrency scenarios and even cause protocol-level deadlock.

[0067] like Figure 3 As shown, the following is a typical deadlock scenario: Master device 0 sequentially issues write address requests AW_00 and AW_01, while master device 1 sequentially issues AW_10 and AW_11. AW_00 and AW_11 are both destined for slave device 0, while AW_10 and AW_01 are both destined for slave device 1. Assume that the transmission paths of AW_00 and AW_10 require traversing an on-chip interconnect network with a delay of at least T ticks, while AW_01 and AW_11 do not traverse this path and have shorter transmission delays.

[0068] In this scenario, the following possibilities exist: AW_01 arrives at selector 0 of slave device 0 before AW_10, and AW_11 arrives at selector 1 of slave device 1 before AW_00. According to the channel arbitration rules of the AXI4 protocol, the two selectors will lock the port corresponding to the first arriving AW request and wait for the write data (W channel) valid signal on the ports where W_01 and W_11 are located, respectively.

[0069] However, since AW_00 and AW_10 requests were issued earlier than AW_01 and AW_11, their corresponding write data W_00 and

[0070] W_10 will also be sent earlier. Taking W_10 as an example, when W_10 arrives at selector 0 of slave device 0, selector 0 is locked and waiting for data to be valid on port W_01, so W_10 cannot be accepted. Meanwhile, data transmission for W_01 needs to wait for W_00 to complete, and W_00 cannot complete at selector 1 of slave device 1 because it is waiting for data to be valid on port W_11. W_11's data cannot be sent because it is waiting for W_10 to release its path, ultimately forming a mutually waiting loop, leading to a system deadlock.

[0071] It can be seen that the root cause of the deadlock is the dependency relationship between the AW and W channels, which leads to the formation of a loop. To fundamentally solve the deadlock problem, this design adopts the concept of the Coherent Hub Interface (CHI) protocol in the inter-layer ring network structure, decoupling the write address channel and the write data channel, optimizing data transmission efficiency while completely avoiding the aforementioned deadlock.

[0072] In AXI4 transactions, the source and destination of a transaction are identified only by IDs, while CHI uses SrcID (source ID) and TgtID (destination ID), allowing for flexible matching of address routing and data flow. This design also employs a similar mechanism, enabling write address requests to be transmitted first, while write data can pass through the network at a more optimal time, without being restricted by address transactions.

[0073] A typical inter-protocol request translation diagram is as follows: Figure 4 On the master device side, when the AXI4 protocol generates a write address request, the translation bridge converts the request into a CHI protocol write-no-snoop (Write No Snoop) write transaction request. This type of request is suitable for storage access in non-cache-consistent scenarios, where the target address to be written to does not require cache consistency checks or operations.

[0074] The converted WriteNoSnp request contains key information such as the transaction ID (TxnID), target device ID (TgtID), address information, and data length, and is transmitted to the target slave device via the on-chip network.

[0075] When a WriteNoSnp request arrives at the target slave device, the slave device needs to request a data buffer for this write transaction to receive subsequent data transmissions. After the data buffer is allocated, the slave device returns a Complete Data Buffer ID Response (CompDBIDResp) to the master device. The data buffer ID (DBID) carried in this response packet identifies the specific buffer location where the data sent in this write transaction should be stored.

[0076] Through the above mechanism, it is ensured that the slave device has successfully completed the allocation of the data buffer before the master device officially sends the write data. This means that the data can be received by the slave device, effectively avoiding problems such as packet loss and deadlock caused by the target device having no available buffer space, and ensuring the stability of data transmission and the efficient operation of the system as a whole.

[0077] After receiving the CompDBIDResp response, the master device can send a Non-Coherent Buffered Write Data Completion Acknowledge (NCBWrDataCompAck) request via the on-chip network. This request carries the complete write data and is ultimately stored in the data buffer allocated to the target slave device.

[0078] Under the network internal private protocol system proposed in this invention, NCBWrDataCompAck requests support multi-phase data transmission, that is, a single transaction can contain multiple data flow control units, and supports out-of-order transmission of data phases and multi-channel parallel writing, which significantly improves the network's data transmission bandwidth and the system's parallel processing capability.

[0079] Figure 5 This is a schematic diagram of an inter-layer network router in a 3D non-uniform on-chip network topology according to this application.

[0080] Figure 8 This is a schematic diagram of an in-layer network router in a 3D non-uniform on-chip network topology according to this application.

[0081] See Figure 5 and Figure 8As can be seen, this embodiment does not employ the traditional Virtual Channel (VC) mechanism. Instead, the router hardware is divided into three independent resource areas: a request channel, a data channel, and a response channel. Each channel independently and completely occupies one of these resource areas. This structure not only ensures physical isolation and non-interference between the channels, resolving the deadlock problem, but also simplifies the logic design and enhances code reusability.

[0082] Among them, see Figure 8 The intra-layer network router's architecture is divided into three parts: request layer, response layer, and data layer, to effectively avoid request deadlock. Typically, the intra-layer router located in the middle has four ports (east, south, west, and north) for interconnecting with adjacent intra-layer network routers, and also has a local port for connecting to local devices.

[0083] The core of an intra-layer network router consists of an input / output buffer unit, an address decoder, and a fully connected crossbar switch. The address decoding rules are statically determined during the parameterization phase, ensuring the determinism of the routing path and simplifying control logic. The fully connected crossbar switch is responsible for establishing data paths between any port and all other ports.

[0084] It should be noted that, unlike inter-layer ring network routers which have non-blocking bypass routing capabilities, intra-layer network routers do not involve bypass routing mechanisms. Therefore, all of their ports are completely identical in function and control logic, including the data path for connecting to local devices.

[0085] In this configuration, the device responsible for receiving data is called the slave device, and the device responsible for sending data is called the master device. The master device is configured to send requests to the slave device through the request channels of the intra-layer network router and the inter-layer network router; after the slave device responds through the response channels of the corresponding intra-layer network router and the inter-layer network router, the master device buffers the transmitted data into the slave device's data buffer through the data channels of the corresponding intra-layer network router and the inter-layer network router.

[0086] The slave device is configured to respond through the response channel of the corresponding intra-layer network router and the inter-layer network router when it receives a request sent by the master device through the request channel of the corresponding intra-layer network router and the inter-layer network router, and allocate the data buffer for the transmitted data; after receiving the transmitted data through the data channel of the corresponding intra-layer network router and the inter-layer network router, it caches the transmitted data in the data buffer.

[0087] Further, see Figure 5 The inter-layer network sub-router includes:

[0088] An output sliding buffer is provided at the output end of each flow control unit; the output sliding buffer is configured to balance the data processing relationship between adjacent nodes; the adjacent nodes include adjacent intra-layer network routers or inter-layer network routers;

[0089] An input slip buffer is provided at the input of each of the flow control units; the input slip buffer is configured to balance the data processing relationship between adjacent nodes.

[0090] Specifically, in this embodiment, from a data flow perspective, the router's data sources mainly include two parts: one is the input from the interconnection link of neighboring nodes, and the other is the data injected by the local device. Similarly, the path for data leaving the router also has two possibilities: one is to continue transmission along the network link to neighboring nodes, and the other is to be sent to the local device. All data input and output operations will pass through the data skid buffer.

[0091] Furthermore, the intra-layer network sub-router includes two flow control units, which are configured to determine the sender and receiver of the transmitted data; and send the transmitted data to the slave or master device corresponding to the intra-layer network router and the inter-layer network router according to the sender and receiver of the transmitted data.

[0092] Specifically, in this embodiment, for data sent from the local device to the network, the injection path first passes through the flow control unit. This unit integrates address decoding logic to parse the destination address information of the data and determine which side of the router the data should be sent through, ensuring that the data can correctly and efficiently enter the network and ultimately reach the target node. The flow control unit uses deterministic dimension-order routing, and the address decoding rules are statically completed during parameterization.

[0093] Specifically, for data originating from a link with an adjacent node, the router first determines whether the final destination of the data is a local node device. If the destination address does not belong to the local node, the data will be directly forwarded in the next clock cycle, continuing along the link to the next node. If the destination is a local device, the router needs to further determine whether the local device currently has the capability to receive data—if it does, the data will be received normally (i.e., "popped"); if it does not, to avoid affecting the overall transmission efficiency on the link, the data will not remain within the router, but will automatically continue to be transmitted along the link to the next node, performing a detour routing operation, thereby achieving a non-blocking data forwarding mechanism.

[0094] For inter-layer ring networks, this embodiment specifically introduces a non-blocking detour routing mechanism to solve the link congestion problem that may be caused by traditional blocking routing.

[0095] like Figure 6 As shown, a typical congestion propagation scenario is as follows: The multiplexer in router 1 simultaneously receives input requests from three different links. Port 0's target is local device 0, while ports 1 and 2 target other nodes or devices in the network, respectively. Assuming device 0 is currently busy and unable to receive new data requests, according to traditional congestion-based design, data on port 0 will remain in front of the multiplexer waiting for device 0 to become available. However, due to the arbitration and resource-sharing relationships within the multiplexer, the congestion on port 0 propagates throughout the entire multiplexer, causing ports 1 and 2, even with different targets and independent paths, to be unable to forward data normally.

[0096] This localized congestion will inevitably spread to the entire network. Specifically, upstream nodes of ports 1 and 2 will be unable to forward data, leading to further congestion and affecting more links and nodes, creating a congestion "broadcast" effect. More seriously, if ports 1 and 2 connect to intra-layer networks, a short-term busy signal from a single device (device 0) can trigger a chain reaction, causing widespread intra-layer communication disruptions, and even partial paralysis of multi-layer on-chip network areas. This cascading congestion severely restricts the overall system performance and stability, and is unacceptable, especially in high-concurrency, high-bandwidth AI acceleration application scenarios.

[0097] To address the aforementioned issues and improve network robustness and throughput, this embodiment introduces a non-blocking detour routing strategy in the inter-layer ring network architecture. For example... Figure 7 The core idea of ​​this strategy is that when a data packet arrives at a router and finds that its target device is temporarily unable to receive data, the packet will not stop or block its current path. Instead, it will continue to the next node via the network link, attempting to reach the target device through other paths. In this way, even if a local device experiences temporary busyness or link resource conflicts, the overall data flow can still maintain continuity, avoiding the impact of a single point of blockage on global communication. The specific implementation method is as follows:

[0098] The flow control unit determines whether the local device corresponding to the current inter-layer network router is the target master device or the target slave device. If it is not the target master device or the target slave device, the transmission data is sent to the next layer inter-layer network router. If it is the target master device or the target slave device, it determines whether the target master device or the target slave device is in an idle state. If the target master device or the target slave device is in an idle state, the transmission data is sent to the target master device or the target slave device through the corresponding inter-layer network router. If the target master device or the target slave device is in a busy state, the transmission data is transmitted cyclically through the remaining inter-layer network routers, and when the corresponding local device returns to an idle state, the transmission data is sent to the corresponding target master device or the target slave device.

[0099] This design not only effectively suppresses congestion propagation and improves network link utilization, but also enhances the stability and robustness of the system under high load and complex data flow scenarios. It is particularly suitable for high-performance data interaction needs in multi-layer heterogeneous computing systems, 3D integrated chips (3DIC), and AI deep computing architectures.

[0100] The advantages of this embodiment include:

[0101] 1. A 3D on-chip network architecture with configurable intra-layer topology and inter-layer ring connection is proposed, which breaks through the scalability bottleneck of traditional two-dimensional NoC and supports multiple intra-layer topologies such as Mesh, Ring, Torus, and Cmesh. Combined with the ring network, inter-layer interconnection is completed at the edge node, avoiding the complexity and reliability problems caused by multi-directional connection of all nodes.

[0102] 2. The innovative use of a ring network to achieve inter-layer connections at the edge nodes within the layer is different from the existing technology where each router needs to connect in multiple directions (up, down, left, and right). This greatly simplifies the inter-layer interconnection structure, reduces node design complexity, and improves system reliability and manufacturing cost advantages.

[0103] 3. A deadlock-free private protocol for non-consistent networks is proposed. Drawing on the CHI protocol, it completely decouples the write address channel and the write data channel, avoiding deadlock caused by strong dependencies under the AXI4 protocol. It supports out-of-order data transmission and multi-channel concurrent transmission, improving system parallelism and throughput performance.

[0104] 4. A non-blocking detour routing strategy was designed in the inter-layer ring network. When the target device is busy and unable to receive data, the data can be automatically detoured to continue transmission, avoiding the spread of link blockage, improving the overall link utilization, and ensuring the stability and efficiency of the system under high concurrency and high load scenarios.

[0105] The overall design scheme of this invention can effectively improve the network communication performance of 3D non-consistent systems, avoid system bottlenecks caused by overly complex link structures, deadlocks, or local congestion, and is especially suitable for high-performance application requirements such as large-scale AI computing, 3D heterogeneous integration, and deep data interaction.

[0106] For ease of explanation, the above description has been provided in conjunction with specific embodiments. However, the discussion in some embodiments is not intended to be exhaustive or to limit the embodiments to the specific forms disclosed above. Various modifications and variations can be obtained based on the above teachings. The selection and description of the above embodiments are for the purpose of better explaining the contents of this disclosure, thereby enabling those skilled in the art to better utilize the embodiments.

Claims

1. A 3D non-uniform on-chip network topology, characterized in that, The structure includes: The system comprises several local devices and several inter-layer network routers, with each local device corresponding to one of the inter-layer network routers. All the inter-layer network routers are interconnected to form a ring structure. Each local device is configured to receive and / or send transmission data. Each inter-layer network router is configured to send the transmission data to the corresponding local device when the local device is idle. Furthermore, each inter-layer network router is configured to circulate the transmission data through the remaining inter-layer network routers when the corresponding local device is busy, and to send the transmission data back to the corresponding local device when the local device returns to an idle state. The system comprises several router network layers, each corresponding to an inter-layer network router. Each router network layer includes several interconnected intra-layer network routers. The router network layer is configured to send the transmitted data to the inter-layer network routers. The intra-layer network routers are configured to independently perform request, response, and transmitted data transmission, respectively. Both the intra-layer network router and the inter-layer network router include: A request channel, configured to process requests for the transmitted data; A data channel configured to process the transmission of the transmitted data; A response channel, configured to process a response to the transmitted data; Both the intra-layer network router and the inter-layer network router include three independent network sub-routers at each layer, and the three network sub-routers at each layer correspond to the request channel, the data channel and the response channel, respectively. The local device includes a master device and a slave device, wherein the master device is the sender of the transmitted data and the slave device is the receiver of the transmitted data. The master device is configured as follows: The request is sent to the slave device through the request channels of the intra-layer network router and the inter-layer network router; After the slave device responds through the response channel corresponding to the intra-layer network router and the inter-layer network router, it caches the transmitted data into the slave device's data buffer through the data channel corresponding to the intra-layer network router and the inter-layer network router. The slave device is configured as follows: When a request sent by the master device is obtained through the request channel corresponding to the intra-layer network router and the inter-layer network router, a response is made through the response channel corresponding to the intra-layer network router and the inter-layer network router, and the data buffer is allocated for the transmitted data. After obtaining the transmission data through the data channels of the corresponding intra-layer network router and inter-layer network router, the transmission data is cached in the data buffer.

2. The 3D non-uniform on-chip network topology according to claim 1, characterized in that, The in-layer network router includes edge routers and intermediate routers. The edge routers are in-layer network routers located on both sides of the edge of the router's network layer, and the intermediate routers are in-layer network routers located between the two edge routers. The edge router is connected to the inter-layer network router, and the intermediate router is connected to four intra-layer network routers in the horizontal direction. The four intra-layer network routers include the intermediate router adjacent to the current intermediate router and / or the adjacent edge router.

3. The 3D non-uniform on-chip network topology according to claim 1, characterized in that, The structure also includes: At least one memory, and at least one of the inter-layer network routers connected to one of the memory; the memory is configured as a shared storage resource for the on-chip network and to store valid data accessible to multiple local devices.

4. The 3D non-uniform on-chip network topology according to claim 1, characterized in that, The network sub-routers include: Two flow control units, which are configured to: Determine the sending end and receiving end of the transmitted data; The transmission data is sent to the slave or master device corresponding to the intra-layer network router and the inter-layer network router according to the sending end and receiving end of the transmission data.

5. A 3D non-uniform on-chip network topology according to claim 4, characterized in that, The inter-layer network sub-router also includes: An output sliding buffer is provided at the output end of each flow control unit; the output sliding buffer is configured to balance the data processing relationship between adjacent nodes; the adjacent nodes are adjacent inter-layer network routers; An input slip buffer is provided at the input of each of the flow control units; the input slip buffer is configured to balance the data processing relationship between adjacent nodes.

6. A 3D non-uniform on-chip network topology according to claim 4, characterized in that, The flow control unit is also configured to: Determine whether the local device corresponding to the current inter-layer network router is the target master device or the target slave device; If not, the transmitted data is sent to the next layer inter-layer network router; If so, determine whether the target master device or the target slave device is in an idle state; If so, the transmitted data is sent to the target master device or the target slave device through the corresponding inter-layer network router; If not, the transmitted data is circulated through the remaining inter-layer network routers, and when the corresponding local device returns to an idle state, the transmitted data is sent to the corresponding target master device or the target slave device.

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