Driving circuit, driving module and display device

Abstract

Provided are a driving circuit, a driving module and a display device. The driving circuit comprises a first noise reduction circuit and a second noise reduction circuit (12) and an output noise reduction circuit (13); the first noise reduction circuit comprises a first noise reduction control circuit (11) and a first transistor (M1); the gate of the first transistor (M1) and the second electrode of the first transistor (M1) are electrically connected to a first noise reduction node (PD1), and the first electrode of the first transistor (M1) is electrically connected to a first noise reduction clock signal line (CK1); the first noise reduction control circuit (11) controls the potential of the first noise reduction node (PD1) under the control of a first noise reduction clock signal and the potential of a first node (PU); the second noise reduction circuit (12) controls the potential of a second noise reduction node (PD2) under the control of a noise reduction control signal and the potential of the first node (PU); and the output noise reduction circuit (13) reduces noise of a driving signal under the control of the potential of the first noise reduction node (PD1) and the potential of the second noise reduction node (PD2). The display device adopting the driving circuit can realize a narrow frame.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a driving circuit, a driving module, and a display device. Background Technology

[0002] In recent years, with the development of display technology and people's increasing demands for advanced display technology, narrow bezel LCD monitors have become a trend.

[0003] In related display panels, GOA (Gate On Array) modules are used. GOA modules integrate the gate driving circuit on the array substrate of the display panel to achieve high integration and low cost. However, due to the requirements of product reliability, GOA modules use more signal lines and have a complex gate driving circuit structure design, which results in them occupying more space in the display panel and is not conducive to the narrow bezel design of the display panel. Summary of the Invention

[0004] In a first aspect, embodiments of this disclosure provide a driving circuit, including a first noise reduction circuit, a second noise reduction circuit, and an output noise reduction circuit;

[0005] The first noise reduction circuit includes a first noise reduction control circuit and a first transistor;

[0006] The gate and the second terminal of the first transistor are both electrically connected to the first noise reduction node, and the first terminal of the first transistor is electrically connected to the first noise reduction clock signal line.

[0007] The first noise reduction control circuit is electrically connected to the first noise reduction clock signal line, the first noise reduction node and the first node respectively, and is used to control the potential of the first noise reduction node under the control of the first noise reduction clock signal provided by the first noise reduction clock signal line and the potential of the first node.

[0008] The second noise reduction circuit is electrically connected to the noise reduction control line, the first node, and the second noise reduction node, and is used to control the potential of the second noise reduction node under the control of the noise reduction control signal provided by the noise reduction control line and the potential of the first node.

[0009] The output noise reduction circuit is electrically connected to the first noise reduction node, the second noise reduction node and the drive signal output terminal respectively, and is used to reduce the noise of the drive signal provided by the drive signal output terminal under the control of the potential of the first noise reduction node and the potential of the second noise reduction node.

[0010] Optionally, the noise reduction control line is a second noise reduction clock signal line.

[0011] Optionally, the noise reduction control line is a first voltage line.

[0012] Optionally, the first noise reduction control circuit is also electrically connected to the second voltage line, and is used to control the connection between the first noise reduction node and the first noise reduction clock signal line under the control of the first noise reduction clock signal, and to control the connection between the first noise reduction node and the second voltage line under the control of the potential of the first node.

[0013] Optionally, the second noise reduction circuit is also electrically connected to the second noise reduction control node and the second voltage line, respectively, for controlling the connection between the second noise reduction control node and the second noise reduction clock signal line under the control of the first noise reduction clock signal, controlling the connection between the second noise reduction control node and the second voltage line under the control of the potential of the first node, controlling the connection between the second noise reduction node and the second noise reduction clock signal line under the control of the potential of the second noise reduction control node, and controlling the connection between the second noise reduction node and the second voltage line under the control of the potential of the first node.

[0014] Optionally, the second noise reduction circuit is also electrically connected to the second voltage line, and is used to control the connection between the noise reduction control line and the second noise reduction node under the control of the noise reduction control signal provided by the noise reduction control line, and to control the connection between the second noise reduction node and the second voltage line under the control of the potential of the first node.

[0015] Optionally, the second noise reduction circuit is also electrically connected to the second voltage line, and is used to control the connection between the second noise reduction node and the second noise reduction clock signal line under the control of the second noise reduction clock signal provided by the second noise reduction clock signal line, control the connection between the second noise reduction node and the second voltage line under the control of the potential of the first node, and control the connection between the second noise reduction clock signal line and the second noise reduction node under the control of the potential of the second noise reduction node.

[0016] Optionally, the first noise reduction control circuit includes a second transistor and a third transistor;

[0017] The gate of the second transistor and the first terminal of the second transistor are electrically connected to the first noise reduction clock signal line, and the second terminal of the second transistor is electrically connected to the first noise reduction node;

[0018] The gate of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the first noise reduction node, and the second electrode of the third transistor is electrically connected to the second voltage line.

[0019] Optionally, the second noise reduction circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;

[0020] The gate of the fourth transistor is electrically connected to the first terminal of the fourth transistor and the second noise reduction clock signal line, and the second terminal of the fourth transistor is electrically connected to the second noise reduction control node.

[0021] The gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the second noise reduction control node, and the second electrode of the fifth transistor is electrically connected to the second voltage line.

[0022] The gate of the sixth transistor is electrically connected to the second noise reduction control node, the first terminal of the sixth transistor is electrically connected to the second noise reduction clock signal line, and the second terminal of the sixth transistor is electrically connected to the second noise reduction node.

[0023] The gate of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the second noise reduction node, and the second electrode of the seventh transistor is electrically connected to the second voltage line.

[0024] Optionally, the second noise reduction circuit includes a fourth transistor and a fifth transistor;

[0025] The gate and the first terminal of the fourth transistor are both electrically connected to the noise reduction control line, and the second terminal of the fourth transistor is electrically connected to the second noise reduction node.

[0026] The gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the second noise reduction node, and the second electrode of the fifth transistor is electrically connected to the second voltage line.

[0027] Optionally, the second noise reduction circuit includes a fourth transistor, a fifth transistor, and a sixth transistor;

[0028] The gate of the fourth transistor is electrically connected to the first terminal of the fourth transistor and the second noise reduction clock signal line, and the second terminal of the fourth transistor is electrically connected to the second noise reduction node;

[0029] The gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the second noise reduction node, and the second electrode of the fifth transistor is electrically connected to the second voltage line.

[0030] The gate and the second terminal of the sixth transistor are both electrically connected to the second noise reduction node, and the first terminal of the sixth transistor is electrically connected to the second noise reduction node.

[0031] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a carry output circuit, a carry reset circuit, and a driving output circuit;

[0032] The carry output circuit is electrically connected to the first node, the output clock signal line, and the carry signal output terminal, respectively, and is used to control the connection between the carry signal output terminal and the output clock signal line under the control of the potential of the first node.

[0033] The carry reset circuit is electrically connected to the first noise reduction node, the second noise reduction node, the carry signal output terminal, and the third voltage line, respectively. It is used to control the connection between the carry signal output terminal and the third voltage line under the control of the potential of the first noise reduction node, and to control the connection between the carry signal output terminal and the third voltage line under the control of the potential of the second noise reduction node.

[0034] The drive output circuit is electrically connected to the first node, the drive signal output terminal, and the output clock signal line, respectively, and is used to control the connection between the drive signal output terminal and the output clock signal line under the control of the potential of the first node.

[0035] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes an energy storage circuit, a first node control circuit, and a noise reduction node control circuit;

[0036] The energy storage circuit is electrically connected to the first node and the drive signal output terminal respectively, and is used to store electrical energy.

[0037] The first node control circuit is electrically connected to the first input terminal, the second input terminal, the first node, the reset terminal, the first noise reduction node, the second noise reduction node, and the second voltage line, respectively. It is used to control the connection between the first node and the second input terminal under the control of the first input signal provided by the first input terminal, control the connection between the first node and the second voltage line under the control of the reset signal provided by the reset terminal, control the connection between the first node and the second voltage line under the control of the potential of the first noise reduction node, and control the connection between the first node and the second voltage line under the control of the potential of the second noise reduction node.

[0038] The noise reduction node control circuit is electrically connected to the first noise reduction node, the second noise reduction node, the first input terminal, and the second voltage line, respectively, and is used to control the connection between the first noise reduction node and the second voltage line, and control the connection between the second noise reduction node and the second voltage line under the control of the first input signal provided by the first input terminal.

[0039] Optionally, the first node control circuit is also electrically connected to the frame reset terminal, and is used to control the connection between the first node and the second voltage line under the control of the frame reset signal provided by the frame reset terminal.

[0040] Optionally, the carry output circuit includes a carry output transistor, the carry reset circuit includes a first carry reset transistor and a second carry reset transistor, the drive output circuit includes a drive output transistor, and the output noise reduction circuit includes a first output noise reduction transistor and a second output noise reduction transistor.

[0041] The gate of the carry output transistor is electrically connected to the first node, the first terminal of the carry output transistor is electrically connected to the output clock signal line, and the second terminal of the carry output transistor is electrically connected to the carry signal output terminal.

[0042] The gate of the first carry reset transistor is electrically connected to the first noise reduction node, the first terminal of the first carry reset transistor is electrically connected to the carry signal output terminal, and the second terminal of the first carry reset transistor is electrically connected to the third voltage line.

[0043] The gate of the second carry reset transistor is electrically connected to the second noise reduction node, the first terminal of the second carry reset transistor is electrically connected to the carry signal output terminal, and the second terminal of the second carry reset transistor is electrically connected to the third voltage line.

[0044] The gate of the drive output transistor is electrically connected to the first node, the first terminal of the drive output transistor is electrically connected to the output clock signal line, and the second terminal of the drive output transistor is electrically connected to the drive signal output terminal.

[0045] The gate of the first output noise reduction transistor is electrically connected to the first noise reduction node, the first terminal of the first output noise reduction transistor is electrically connected to the drive signal output terminal, and the second terminal of the first output noise reduction transistor is electrically connected to the third voltage line.

[0046] The gate of the second output noise reduction transistor is electrically connected to the second noise reduction node, the first terminal of the second output noise reduction transistor is electrically connected to the drive signal output terminal, and the second terminal of the second output noise reduction transistor is electrically connected to the third voltage line.

[0047] Optionally, the first node control circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; the noise reduction node control circuit includes a thirteenth transistor and a fourteenth transistor.

[0048] The gate of the eighth transistor is electrically connected to the first input terminal, the first terminal of the eighth transistor is electrically connected to the second input terminal, and the second terminal of the eighth transistor is electrically connected to the first node.

[0049] The gate of the ninth transistor is electrically connected to the reset terminal, the first terminal of the ninth transistor is electrically connected to the first node, and the second terminal of the ninth transistor is electrically connected to the second voltage line.

[0050] The gate of the tenth transistor is electrically connected to the first noise reduction node, the first electrode of the tenth transistor is electrically connected to the first node, and the second electrode of the tenth transistor is electrically connected to the second voltage line.

[0051] The gate of the eleventh transistor is electrically connected to the second noise reduction node, the first terminal of the eleventh transistor is electrically connected to the first node, and the second terminal of the eleventh transistor is electrically connected to the second voltage line.

[0052] The gate of the twelfth transistor is electrically connected to the frame reset terminal, the first terminal of the twelfth transistor is electrically connected to the first node, and the second terminal of the twelfth transistor is electrically connected to the second voltage line.

[0053] The gate of the thirteenth transistor is electrically connected to the first input terminal, the first terminal of the thirteenth transistor is electrically connected to the first noise reduction node, and the second terminal of the thirteenth transistor is electrically connected to the second voltage line.

[0054] The gate of the fourteenth transistor is electrically connected to the first input terminal, the first terminal of the fourteenth transistor is electrically connected to the second noise reduction node, and the second terminal of the fourteenth transistor is electrically connected to the second voltage line.

[0055] In a second aspect, embodiments of this disclosure provide a drive module including multiple stages of the drive circuits described above.

[0056] Optionally, the drive module includes 2N clock signal lines; N is a positive integer;

[0057] The driving circuit is the a-th stage driving circuit included in the driving module; a is a positive integer.

[0058] The first noise reduction clock signal line is the N+ath clock signal line, and the second noise reduction clock signal line and the output clock signal line are the ath clock signal lines.

[0059] Optionally, the driving circuit includes a carry signal output terminal, a first input terminal, and a reset terminal;

[0060] The first input terminal of the a-th stage driving circuit is electrically connected to the carry signal output terminal of the aN-th stage driving circuit, and the reset terminal of the a-th stage driving circuit is electrically connected to the carry signal output terminal of the a+N-th stage driving circuit.

[0061] Optionally, the driving circuit further includes a second input terminal and a driving signal output terminal;

[0062] The second input terminal of the a-th stage driving circuit is electrically connected to the driving signal output terminal of the aN-th stage driving circuit or the carry signal output terminal of the aN-th stage driving circuit.

[0063] In a third aspect, embodiments of this disclosure provide a display device including the driving module described above. Attached Figure Description

[0064] Figure 1 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0065] Figure 2 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0066] Figure 3 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0067] Figure 4 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0068] Figure 5 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0069] Figure 6 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0070] Figure 7 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0071] Figure 8 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0072] Figure 9 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0073] Figure 10 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0074] Figure 11 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0075] Figure 12 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0076] Figure 13 This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0077] Figure 14This is a timing diagram of the clock signals used in the driving module described in at least one embodiment of this disclosure;

[0078] Figure 15 This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0079] Figure 16 This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0080] Figure 17 This is a structural diagram of the drive module described in at least one embodiment of the present disclosure;

[0081] Figure 18 This is a timing diagram of the operation of the drive module according to at least one embodiment of the present disclosure. Detailed Implementation

[0082] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0083] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0084] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0085] The driving circuit described in this embodiment includes a first noise reduction circuit, a second noise reduction circuit, and an output noise reduction circuit;

[0086] The first noise reduction circuit includes a first noise reduction control circuit and a first transistor;

[0087] The gate and the second terminal of the first transistor are both electrically connected to the first noise reduction node, and the first terminal of the first transistor is electrically connected to the first noise reduction clock signal line.

[0088] The first noise reduction control circuit is electrically connected to the first noise reduction clock signal line, the first noise reduction node and the first node respectively, and is used to control the potential of the first noise reduction node under the control of the first noise reduction clock signal provided by the first noise reduction clock signal line and the potential of the first node.

[0089] The second noise reduction circuit is electrically connected to the noise reduction control line, the first node, and the second noise reduction node, and is used to control the potential of the second noise reduction node under the control of the noise reduction control signal provided by the noise reduction control line and the potential of the first node.

[0090] The output noise reduction circuit is electrically connected to the first noise reduction node, the second noise reduction node and the drive signal output terminal respectively, and is used to reduce the noise of the drive signal provided by the drive signal output terminal under the control of the potential of the first noise reduction node and the potential of the second noise reduction node.

[0091] In the driving circuit of at least one embodiment of this disclosure, the first noise reduction circuit operates under the control of a first noise reduction clock signal provided by a first noise reduction clock signal line, and the second noise reduction circuit operates under the control of a noise reduction control signal provided by a noise reduction control line. The noise reduction control line can be a second noise reduction clock signal line or a first voltage line. The driving circuit of at least one embodiment of this disclosure does not use a first control voltage line VDDO and a second control voltage line VDDE, thereby reducing the number of signal lines used, which is beneficial to reducing the space occupied by the driving module including the driving circuit and to achieving a narrow bezel.

[0092] like Figure 1 As shown, the driving circuit described in at least one embodiment of this disclosure includes a first noise reduction circuit, a second noise reduction circuit 12, and an output noise reduction circuit 13;

[0093] The first noise reduction circuit includes a first noise reduction control circuit 11 and a first transistor M1;

[0094] The gate and source of the first transistor M1 are both electrically connected to the first noise reduction node PD1, and the drain of the first transistor M1 is electrically connected to the first noise reduction clock signal line CK1.

[0095] The first noise reduction control circuit 11 is electrically connected to the first noise reduction clock signal line CK1, the first noise reduction node PD1 and the first node PU respectively, and is used to control the potential of the first noise reduction node PD1 under the control of the first noise reduction clock signal provided by the first noise reduction clock signal line CK1 and the potential of the first node PU.

[0096] The second noise reduction circuit 12 is electrically connected to the noise reduction control line SC, the first node PU, and the second noise reduction node PD2, and is used to control the potential of the second noise reduction node PD2 under the control of the noise reduction control signal provided by the noise reduction control line SC and the potential of the first node PU.

[0097] The output noise reduction circuit 13 is electrically connected to the first noise reduction node PD1, the second noise reduction node PD2 and the drive signal output terminal GT, respectively, and is used to reduce the noise of the drive signal provided by the drive signal output terminal GT under the control of the potential of the first noise reduction node PD1 and the potential of the second noise reduction node PD2.

[0098] This disclosure Figure 1 In at least one embodiment of the driving circuit shown, during operation, the first noise reduction control circuit 11 controls the potential of the first noise reduction node PD1 under the control of the first noise reduction clock signal and the potential of the first node PU; the first transistor M1 controls the connection or disconnection between the first noise reduction node PD1 and the first noise reduction clock signal line CK1 under the control of the potential of the first noise reduction node PD1; the second noise reduction circuit 12 controls the potential of the second noise reduction node PD2 under the control of the noise reduction control signal and the potential of the first node PU; and the output noise reduction circuit 13 performs noise reduction on the driving signal provided by the driving signal output terminal GT under the control of the potential of the first noise reduction node PD1 and the potential of the second noise reduction node PD2.

[0099] Optionally, the noise reduction control line is a second noise reduction clock signal line.

[0100] Optionally, the noise reduction control line is a first voltage line.

[0101] In specific implementation, the noise reduction control line can be a second noise reduction clock signal line or a first voltage line. For example, the first voltage line can be a power supply voltage line; but it is not limited thereto.

[0102] In at least one embodiment of this disclosure, the first noise reduction control circuit is also electrically connected to the second voltage line, and is used to control the connection between the first noise reduction node and the first noise reduction clock signal line under the control of the first noise reduction clock signal, and to control the connection between the first noise reduction node and the second voltage line under the control of the potential of the first node.

[0103] In a specific implementation, the first noise reduction control circuit can also control the connection between the first noise reduction node and the first noise reduction clock signal line under the control of the first noise reduction clock signal, and control the connection between the first noise reduction node and the second voltage line under the control of the potential of the first node.

[0104] Optionally, the second voltage line can be the first low voltage line, but is not limited thereto.

[0105] like Figure 2 As shown, in Figure 1Based on at least one embodiment of the driving circuit shown, the first noise reduction control circuit 11 is also electrically connected to the second voltage line V2, and is used to control the first noise reduction node PD1 to be connected to the first noise reduction clock signal line CK1 under the control of the first noise reduction clock signal, and to control the first noise reduction node PD1 to be connected to the second voltage line V2 under the control of the potential of the first node PU.

[0106] In at least one embodiment of this disclosure, the second noise reduction circuit is further electrically connected to a second noise reduction control node and a second voltage line, respectively, for controlling the connection between the second noise reduction control node and the second noise reduction clock signal line under the control of the first noise reduction clock signal, controlling the connection between the second noise reduction control node and the second voltage line under the control of the potential of the first node, controlling the connection between the second noise reduction node and the second noise reduction clock signal line under the control of the potential of the second noise reduction control node, and controlling the connection between the second noise reduction node and the second voltage line under the control of the potential of the first node.

[0107] In specific implementation, the second noise reduction circuit can control the connection between the second noise reduction control node and the second noise reduction clock signal line under the control of the first noise reduction clock signal, control the connection between the second noise reduction control node and the second voltage line under the control of the potential of the first node, control the connection between the second noise reduction node and the second noise reduction clock signal line under the control of the potential of the second noise reduction control node, and control the connection between the second noise reduction node and the second voltage line under the control of the potential of the first node, so as to control the potential of the second noise reduction node.

[0108] like Figure 3 As shown, in Figure 2 Based on at least one embodiment of the driving circuit shown, the noise reduction control line is a second noise reduction clock signal line CK2;

[0109] The second noise reduction circuit 12 is also electrically connected to the second noise reduction control node PDCN2 and the second voltage line V2, respectively. Under the control of the first noise reduction clock signal, it controls the second noise reduction control node PDCN2 to be connected to the second noise reduction clock signal line CK2. Under the control of the potential of the first node PU, it controls the second noise reduction control node PDCN2 to be connected to the second voltage line V2. Under the control of the potential of the second noise reduction control node PDCN2, it controls the second noise reduction node PD2 to be connected to the second noise reduction clock signal line CK2. Under the control of the potential of the first node PU, it controls the second noise reduction node PD2 to be connected to the second voltage line V2.

[0110] In at least one embodiment of this disclosure, the second noise reduction circuit is also electrically connected to the second voltage line, and is used to control the connection between the noise reduction control line and the second noise reduction node under the control of the noise reduction control signal provided by the noise reduction control line, and to control the connection between the second noise reduction node and the second voltage line under the control of the potential of the first node.

[0111] In a specific implementation, the second noise reduction circuit can control the connection between the noise reduction control line and the second noise reduction node under the control of the noise reduction control signal, and control the connection between the second noise reduction node and the second voltage line under the control of the potential of the first node, so as to control the potential of the second noise reduction node.

[0112] like Figure 4 As shown, in Figure 2 Based on at least one embodiment of the driving circuit shown, the second noise reduction circuit 12 is also electrically connected to the second voltage line V2, and is used to control the noise reduction control line SC to connect with the second noise reduction node PD2 under the control of the noise reduction control signal provided by the noise reduction control line SC, and to control the second noise reduction node PD2 to connect with the second voltage line V2 under the control of the potential of the first node PU.

[0113] In at least one embodiment of this disclosure, the second noise reduction circuit is also electrically connected to the second voltage line, and is used to control the second noise reduction node to be connected to the second noise reduction clock signal line under the control of the second noise reduction clock signal provided by the second noise reduction clock signal line, control the second noise reduction node to be connected to the second voltage line under the control of the potential of the first node, and control the second noise reduction clock signal line to be connected to the second noise reduction node under the control of the potential of the second noise reduction node.

[0114] In a specific implementation, the second noise reduction circuit can control the connection between the second noise reduction node and the second noise reduction clock signal line under the control of the second noise reduction clock signal, control the connection between the second noise reduction node and the second voltage line under the control of the potential of the first node, and control the connection between the second noise reduction clock signal line and the second noise reduction node under the control of the potential of the second noise reduction node.

[0115] like Figure 5 As shown, in Figure 2 Based on at least one embodiment of the driving circuit shown, the noise reduction control line can be a second noise reduction clock signal line CK2;

[0116] The second noise reduction circuit 12 is also electrically connected to the second voltage line V2, and is used to control the second noise reduction node PD2 to be connected to the second noise reduction clock signal line CK2 under the control of the second noise reduction clock signal provided by the second noise reduction clock signal line CK2, control the second noise reduction node PD2 to be connected to the second voltage line V2 under the control of the potential of the first node PU, and control the second noise reduction clock signal line CK2 to be connected to the second noise reduction node PD2 under the control of the potential of the second noise reduction node PD2.

[0117] In at least one embodiment of this disclosure, when the driving module including the above-described driving circuit uses 12 clock signal lines, and the clock signal provided by the clock signal lines has a duty cycle of 1 / 2, a high-level duration of 6H, and a low-level duration of 6H, the first noise reduction clock signal line can be the (a+6)th clock signal line, the second noise reduction signal line can be the ath clock signal line, where a is a positive integer and 1H is a line scan time.

[0118] Optionally, the first noise reduction control circuit includes a second transistor and a third transistor;

[0119] The gate of the second transistor and the first terminal of the second transistor are electrically connected to the first noise reduction clock signal line, and the second terminal of the second transistor is electrically connected to the first noise reduction node;

[0120] The gate of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the first noise reduction node, and the second electrode of the third transistor is electrically connected to the second voltage line.

[0121] Optionally, the second noise reduction circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;

[0122] The gate of the fourth transistor is electrically connected to the first terminal of the fourth transistor and the second noise reduction clock signal line, and the second terminal of the fourth transistor is electrically connected to the second noise reduction control node.

[0123] The gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the second noise reduction control node, and the second electrode of the fifth transistor is electrically connected to the second voltage line.

[0124] The gate of the sixth transistor is electrically connected to the second noise reduction control node, the first terminal of the sixth transistor is electrically connected to the second noise reduction clock signal line, and the second terminal of the sixth transistor is electrically connected to the second noise reduction node.

[0125] The gate of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the second noise reduction node, and the second electrode of the seventh transistor is electrically connected to the second voltage line.

[0126] Optionally, the second noise reduction circuit includes a fourth transistor and a fifth transistor;

[0127] The gate and the first terminal of the fourth transistor are both electrically connected to the noise reduction control line, and the second terminal of the fourth transistor is electrically connected to the second noise reduction node.

[0128] The gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the second noise reduction node, and the second electrode of the fifth transistor is electrically connected to the second voltage line.

[0129] Optionally, the second noise reduction circuit includes a fourth transistor, a fifth transistor, and a sixth transistor;

[0130] The gate of the fourth transistor is electrically connected to the first terminal of the fourth transistor and the second noise reduction clock signal line, and the second terminal of the fourth transistor is electrically connected to the second noise reduction node;

[0131] The gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the second noise reduction node, and the second electrode of the fifth transistor is electrically connected to the second voltage line.

[0132] The gate and the second terminal of the sixth transistor are both electrically connected to the second noise reduction node, and the first terminal of the sixth transistor is electrically connected to the second noise reduction node.

[0133] The driving circuit described in at least one embodiment of this disclosure further includes a carry output circuit, a carry reset circuit, and a driving output circuit;

[0134] The carry output circuit is electrically connected to the first node, the output clock signal line, and the carry signal output terminal, respectively, and is used to control the connection between the carry signal output terminal and the output clock signal line under the control of the potential of the first node.

[0135] The carry reset circuit is electrically connected to the first noise reduction node, the second noise reduction node, the carry signal output terminal, and the third voltage line, respectively. It is used to control the connection between the carry signal output terminal and the third voltage line under the control of the potential of the first noise reduction node, and to control the connection between the carry signal output terminal and the third voltage line under the control of the potential of the second noise reduction node.

[0136] The drive output circuit is electrically connected to the first node, the drive signal output terminal, and the output clock signal line, respectively, and is used to control the connection between the drive signal output terminal and the output clock signal line under the control of the potential of the first node.

[0137] In a specific implementation, the driving circuit may further include a carry output circuit, a carry reset circuit, and a drive output circuit; the carry output circuit, under the control of the potential of the first node, controls the connection between the carry signal output terminal and the output clock signal line; the carry reset circuit, under the control of the potential of the first noise reduction node, controls the connection between the carry signal output terminal and the third voltage line, and under the control of the potential of the second noise reduction node, controls the connection between the carry signal output terminal and the third voltage line; the drive output circuit, under the control of the potential of the first node, controls the connection between the drive signal output terminal and the output clock signal line.

[0138] Optionally, the third voltage line can be a second low voltage line;

[0139] The output clock signal line can be the same clock signal line as the second noise reduction clock signal line to reduce the number of clock signal lines used, which is beneficial for achieving a narrow bezel; however, this is not a limitation.

[0140] like Figure 6 As shown, in Figure 3 Based on at least one embodiment of the driving circuit shown, the driving circuit described in at least one embodiment of this disclosure further includes a carry output circuit 61, a carry reset circuit 62, and a driving output circuit 63;

[0141] The carry output circuit 61 is electrically connected to the first node PU, the output clock signal line CLK and the carry signal output terminal OC respectively, and is used to control the connection between the carry signal output terminal PU and the output clock signal line CLK under the control of the potential of the first node PU.

[0142] The carry reset circuit 62 is electrically connected to the first noise reduction node PD1, the second noise reduction node PD2, the carry signal output terminal OC, and the third voltage line V3, respectively. It is used to control the connection between the carry signal output terminal OC and the third voltage line V3 under the control of the potential of the first noise reduction node PD1, and to control the connection between the carry signal output terminal OC and the third voltage line V3 under the control of the potential of the second noise reduction node PD2.

[0143] The drive output circuit 63 is electrically connected to the first node PU, the drive signal output terminal GT, and the output clock signal line CLK, respectively, and is used to control the connection between the drive signal output terminal GT and the output clock signal line CLK under the control of the potential of the first node PU.

[0144] like Figure 7 As shown, in Figure 4 Based on at least one embodiment of the driving circuit shown, the driving circuit described in at least one embodiment of this disclosure further includes a carry output circuit 61, a carry reset circuit 62, and a driving output circuit 63;

[0145] The carry output circuit 61 is electrically connected to the first node PU, the output clock signal line CLK and the carry signal output terminal OC respectively, and is used to control the connection between the carry signal output terminal PU and the output clock signal line CLK under the control of the potential of the first node PU.

[0146] The carry reset circuit 62 is electrically connected to the first noise reduction node PD1, the second noise reduction node PD2, the carry signal output terminal OC, and the third voltage line V3, respectively. It is used to control the connection between the carry signal output terminal OC and the third voltage line V3 under the control of the potential of the first noise reduction node PD1, and to control the connection between the carry signal output terminal OC and the third voltage line V3 under the control of the potential of the second noise reduction node PD2.

[0147] The drive output circuit 63 is electrically connected to the first node PU, the drive signal output terminal GT, and the output clock signal line CLK, respectively, and is used to control the connection between the drive signal output terminal GT and the output clock signal line CLK under the control of the potential of the first node PU.

[0148] like Figure 8 As shown, in Figure 5 Based on at least one embodiment of the driving circuit shown, the driving circuit described in at least one embodiment of this disclosure further includes a carry output circuit 61, a carry reset circuit 62, and a driving output circuit 63;

[0149] The carry output circuit 61 is electrically connected to the first node PU, the output clock signal line CLK and the carry signal output terminal OC respectively, and is used to control the connection between the carry signal output terminal PU and the output clock signal line CLK under the control of the potential of the first node PU.

[0150] The carry reset circuit 62 is electrically connected to the first noise reduction node PD1, the second noise reduction node PD2, the carry signal output terminal OC, and the third voltage line V3, respectively. It is used to control the connection between the carry signal output terminal OC and the third voltage line V3 under the control of the potential of the first noise reduction node PD1, and to control the connection between the carry signal output terminal OC and the third voltage line V3 under the control of the potential of the second noise reduction node PD2.

[0151] The drive output circuit 63 is electrically connected to the first node PU, the drive signal output terminal GT, and the output clock signal line CLK, respectively, and is used to control the connection between the drive signal output terminal GT and the output clock signal line CLK under the control of the potential of the first node PU.

[0152] The driving circuit described in at least one embodiment of this disclosure further includes an energy storage circuit, a first node control circuit, and a noise reduction node control circuit;

[0153] The energy storage circuit is electrically connected to the first node and the drive signal output terminal respectively, and is used to store electrical energy.

[0154] The first node control circuit is electrically connected to the first input terminal, the second input terminal, the first node, the reset terminal, the first noise reduction node, the second noise reduction node, and the second voltage line, respectively. It is used to control the connection between the first node and the second input terminal under the control of the first input signal provided by the first input terminal, control the connection between the first node and the second voltage line under the control of the reset signal provided by the reset terminal, control the connection between the first node and the second voltage line under the control of the potential of the first noise reduction node, and control the connection between the first node and the second voltage line under the control of the potential of the second noise reduction node.

[0155] The noise reduction node control circuit is electrically connected to the first noise reduction node, the second noise reduction node, the first input terminal, and the second voltage line, respectively, and is used to control the connection between the first noise reduction node and the second voltage line, and control the connection between the second noise reduction node and the second voltage line under the control of the first input signal provided by the first input terminal.

[0156] In a specific implementation, the driving circuit may further include an energy storage circuit, a first node control circuit, and a noise reduction node control circuit; the first node control circuit, under the control of a first input signal, controls the connection between the first node and the second input terminal; under the control of a reset signal, controls the connection between the first node and the second voltage line; under the control of the potential of the first noise reduction node, controls the connection between the first node and the second voltage line; and under the control of the potential of the second noise reduction node, controls the connection between the first node and the second voltage line; the noise reduction node control circuit, under the control of a first input signal, controls the connection between the first noise reduction node and the second voltage line, and controls the connection between the second noise reduction node and the second voltage line.

[0157] In at least one embodiment of this disclosure, the first node control circuit is also electrically connected to the frame reset terminal, and is used to control the connection between the first node and the second voltage line under the control of the frame reset signal provided by the frame reset terminal.

[0158] In a specific implementation, the controllable circuit of the first node can also control the connection between the first node and the second voltage line under the control of the frame reset signal.

[0159] like Figure 9 As shown, in Figure 6 Based on at least one embodiment of the driving circuit shown, the driving circuit described in at least one embodiment of this disclosure further includes an energy storage circuit 91, a first node control circuit 92, and a noise reduction node control circuit 93;

[0160] The energy storage circuit 91 is electrically connected to the first node PU and the drive signal output terminal GT respectively, and is used to store electrical energy.

[0161] The first node control circuit 92 is electrically connected to the first input terminal I1, the second input terminal I2, the first node PU, the reset terminal RST, the first noise reduction node PD1, the second noise reduction node PD2, and the second voltage line V2, respectively. It is used to control the connection between the first node PU and the second input terminal I2 under the control of the first input signal provided by the first input terminal I1, control the connection between the first node PU and the second voltage line V2 under the control of the reset signal provided by the reset terminal RST, control the connection between the first node PU and the second voltage line V2 under the control of the potential of the first noise reduction node PD1, and control the connection between the first node PU and the second voltage line V2 under the control of the potential of the second noise reduction node PD2.

[0162] The noise reduction node control circuit 93 is electrically connected to the first noise reduction node PD1, the second noise reduction node PD2, the first input terminal I1, and the second voltage line V2, respectively. It is used to control the first noise reduction node PD1 to connect with the second voltage line V2 and control the second noise reduction node PD2 to connect with the second voltage line V2 under the control of the first input signal provided by the first input terminal I1.

[0163] The first node control circuit 92 is also electrically connected to the frame reset terminal TRST, and is used to control the connection between the first node PU and the second voltage line V2 under the control of the frame reset signal provided by the frame reset terminal TRST.

[0164] like Figure 10 As shown, in Figure 7 Based on at least one embodiment of the driving circuit shown, the driving circuit described in at least one embodiment of this disclosure further includes an energy storage circuit 91, a first node control circuit 92, and a noise reduction node control circuit 93;

[0165] The energy storage circuit 91 is electrically connected to the first node PU and the drive signal output terminal GT respectively, and is used to store electrical energy.

[0166] The first node control circuit 92 is electrically connected to the first input terminal I1, the second input terminal I2, the first node PU, the reset terminal RST, the first noise reduction node PD1, the second noise reduction node PD2, and the second voltage line V2, respectively. It is used to control the connection between the first node PU and the second input terminal I2 under the control of the first input signal provided by the first input terminal I1, control the connection between the first node PU and the second voltage line V2 under the control of the reset signal provided by the reset terminal RST, control the connection between the first node PU and the second voltage line V2 under the control of the potential of the first noise reduction node PD1, and control the connection between the first node PU and the second voltage line V2 under the control of the potential of the second noise reduction node PD2.

[0167] The noise reduction node control circuit 93 is electrically connected to the first noise reduction node PD1, the second noise reduction node PD2, the first input terminal I1, and the second voltage line V2, respectively. It is used to control the first noise reduction node PD1 to connect with the second voltage line V2 and control the second noise reduction node PD2 to connect with the second voltage line V2 under the control of the first input signal provided by the first input terminal I1.

[0168] The first node control circuit 92 is also electrically connected to the frame reset terminal TRST, and is used to control the connection between the first node PU and the second voltage line V2 under the control of the frame reset signal provided by the frame reset terminal TRST.

[0169] like Figure 11 As shown, in Figure 8 Based on at least one embodiment of the driving circuit shown, the driving circuit described in at least one embodiment of this disclosure further includes an energy storage circuit 91, a first node control circuit 92, and a noise reduction node control circuit 93;

[0170] The energy storage circuit 91 is electrically connected to the first node PU and the drive signal output terminal GT respectively, and is used to store electrical energy.

[0171] The first node control circuit 92 is electrically connected to the first input terminal I1, the second input terminal I2, the first node PU, the reset terminal RST, the first noise reduction node PD1, the second noise reduction node PD2, and the second voltage line V2, respectively. It is used to control the connection between the first node PU and the second input terminal I2 under the control of the first input signal provided by the first input terminal I1, control the connection between the first node PU and the second voltage line V2 under the control of the reset signal provided by the reset terminal RST, control the connection between the first node PU and the second voltage line V2 under the control of the potential of the first noise reduction node PD1, and control the connection between the first node PU and the second voltage line V2 under the control of the potential of the second noise reduction node PD2.

[0172] The noise reduction node control circuit 93 is electrically connected to the first noise reduction node PD1, the second noise reduction node PD2, the first input terminal I1, and the second voltage line V2, respectively. It is used to control the first noise reduction node PD1 to connect with the second voltage line V2 and control the second noise reduction node PD2 to connect with the second voltage line V2 under the control of the first input signal provided by the first input terminal I1.

[0173] The first node control circuit 92 is also electrically connected to the frame reset terminal TRST, and is used to control the connection between the first node PU and the second voltage line V2 under the control of the frame reset signal provided by the frame reset terminal TRST.

[0174] Optionally, the carry output circuit includes a carry output transistor, the carry reset circuit includes a first carry reset transistor and a second carry reset transistor, the drive output circuit includes a drive output transistor, and the output noise reduction circuit includes a first output noise reduction transistor and a second output noise reduction transistor.

[0175] The gate of the carry output transistor is electrically connected to the first node, the first terminal of the carry output transistor is electrically connected to the output clock signal line, and the second terminal of the carry output transistor is electrically connected to the carry signal output terminal.

[0176] The gate of the first carry reset transistor is electrically connected to the first noise reduction node, the first terminal of the first carry reset transistor is electrically connected to the carry signal output terminal, and the second terminal of the first carry reset transistor is electrically connected to the third voltage line.

[0177] The gate of the second carry reset transistor is electrically connected to the second noise reduction node, the first terminal of the second carry reset transistor is electrically connected to the carry signal output terminal, and the second terminal of the second carry reset transistor is electrically connected to the third voltage line.

[0178] The gate of the drive output transistor is electrically connected to the first node, the first terminal of the drive output transistor is electrically connected to the output clock signal line, and the second terminal of the drive output transistor is electrically connected to the drive signal output terminal.

[0179] The gate of the first output noise reduction transistor is electrically connected to the first noise reduction node, the first terminal of the first output noise reduction transistor is electrically connected to the drive signal output terminal, and the second terminal of the first output noise reduction transistor is electrically connected to the third voltage line.

[0180] The gate of the second output noise reduction transistor is electrically connected to the second noise reduction node, the first terminal of the second output noise reduction transistor is electrically connected to the drive signal output terminal, and the second terminal of the second output noise reduction transistor is electrically connected to the third voltage line.

[0181] Optionally, the first node control circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; the noise reduction node control circuit includes a thirteenth transistor and a fourteenth transistor.

[0182] The gate of the eighth transistor is electrically connected to the first input terminal, the first terminal of the eighth transistor is electrically connected to the second input terminal, and the second terminal of the eighth transistor is electrically connected to the first node.

[0183] The gate of the ninth transistor is electrically connected to the reset terminal, the first terminal of the ninth transistor is electrically connected to the first node, and the second terminal of the ninth transistor is electrically connected to the second voltage line.

[0184] The gate of the tenth transistor is electrically connected to the first noise reduction node, the first electrode of the tenth transistor is electrically connected to the first node, and the second electrode of the tenth transistor is electrically connected to the second voltage line.

[0185] The gate of the eleventh transistor is electrically connected to the second noise reduction node, the first terminal of the eleventh transistor is electrically connected to the first node, and the second terminal of the eleventh transistor is electrically connected to the second voltage line.

[0186] The gate of the twelfth transistor is electrically connected to the frame reset terminal, the first terminal of the twelfth transistor is electrically connected to the first node, and the second terminal of the twelfth transistor is electrically connected to the second voltage line.

[0187] The gate of the thirteenth transistor is electrically connected to the first input terminal, the first terminal of the thirteenth transistor is electrically connected to the first noise reduction node, and the second terminal of the thirteenth transistor is electrically connected to the second voltage line.

[0188] The gate of the fourteenth transistor is electrically connected to the first input terminal, the first terminal of the fourteenth transistor is electrically connected to the second noise reduction node, and the second terminal of the fourteenth transistor is electrically connected to the second voltage line.

[0189] like Figure 12 As shown, in Figure 9 Based on at least one embodiment of the driving circuit shown,

[0190] The first noise reduction control circuit includes a second transistor M2 and a third transistor M3;

[0191] The gate and drain of the second transistor M2 are electrically connected to the first noise reduction clock signal line CK1, and the source of the second transistor M2 is electrically connected to the first noise reduction node PD1.

[0192] The gate of the third transistor M3 is electrically connected to the first node PU, the drain of the third transistor M3 is electrically connected to the first noise reduction node PD1, and the source of the third transistor M3 is electrically connected to the first low voltage line LVSS.

[0193] The second noise reduction circuit includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7;

[0194] The gate and drain of the fourth transistor M4 are electrically connected to the second noise reduction clock signal line CK2, and the source of the fourth transistor M4 is electrically connected to the second noise reduction control node PDCN2.

[0195] The gate of the fifth transistor M5 is electrically connected to the first node PU, the drain of the fifth transistor M5 is electrically connected to the second noise reduction control node PDCN2, and the source of the fifth transistor M5 is electrically connected to the first low voltage line LVSS.

[0196] The gate of the sixth transistor M6 is electrically connected to the second noise reduction control node PDCN2, the drain of the sixth transistor M6 is electrically connected to the second noise reduction clock signal line CK2, and the source of the sixth transistor M6 is electrically connected to the second noise reduction node PD2.

[0197] The gate of the seventh transistor M7 is electrically connected to the first node PU, the drain of the seventh transistor M7 is electrically connected to the second noise reduction node PD2, and the source of the seventh transistor M7 is electrically connected to the first low voltage line LVSS.

[0198] The carry output circuit includes a carry output transistor MC, the carry reset circuit includes a first carry reset transistor MR1 and a second carry reset transistor MR2, the drive output circuit includes a drive output transistor MO, and the output noise reduction circuit includes a first output noise reduction transistor MJ1 and a second output noise reduction transistor MJ2.

[0199] The gate of the carry output transistor MC is electrically connected to the first node PU, the drain of the carry output transistor MC is electrically connected to the second noise reduction clock signal line CK2, and the source of the carry output transistor MC is electrically connected to the carry signal output terminal OC.

[0200] The gate of the first carry reset transistor MR1 is electrically connected to the first noise reduction node PD1, the drain of the first carry reset transistor MR1 is electrically connected to the carry signal output terminal OC, and the source of the first carry reset transistor MR1 is electrically connected to the second low voltage line VSS.

[0201] The gate of the second carry reset transistor MR2 is electrically connected to the second noise reduction node PD2, the drain of the second carry reset transistor MR2 is electrically connected to the carry signal output terminal OC, and the source of the second carry reset transistor MR2 is electrically connected to the second low voltage line VSS.

[0202] The gate of the drive output transistor MO is electrically connected to the first node PU, the drain of the drive output transistor MO is electrically connected to the second noise reduction clock signal line CK2, and the source of the drive output transistor MO is electrically connected to the drive signal output terminal GT.

[0203] The gate of the first output noise reduction transistor MJ1 is electrically connected to the first noise reduction node PD1, the drain of the first output noise reduction transistor MJ1 is electrically connected to the drive signal output terminal GT, and the source of the first output noise reduction transistor MJ1 is electrically connected to the second low voltage line VSS.

[0204] The gate of the second output noise reduction transistor MJ2 is electrically connected to the second noise reduction node PD2, the drain of the second output noise reduction transistor MJ2 is electrically connected to the drive signal output terminal GT, and the source of the second output noise reduction transistor MJ2 is electrically connected to the second low voltage line VSS.

[0205] The first node control circuit includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12; the noise reduction node control circuit includes a thirteenth transistor M13 and a fourteenth transistor M14.

[0206] The gate of the eighth transistor M8 is electrically connected to the first input terminal I1, the drain of the eighth transistor M8 is electrically connected to the second input terminal I2, and the source of the eighth transistor M8 is electrically connected to the first node PU.

[0207] The gate of the ninth transistor M9 is electrically connected to the reset terminal RST, the drain of the ninth transistor M9 is electrically connected to the first node PU, and the source of the ninth transistor M9 is electrically connected to the first low voltage line LVSS.

[0208] The gate of the tenth transistor M10 is electrically connected to the first noise reduction node PD1, the drain of the tenth transistor M10 is electrically connected to the first node PU, and the source of the tenth transistor M10 is electrically connected to the first low voltage line LVSS.

[0209] The gate of the eleventh transistor M11 is electrically connected to the second noise reduction node PD2, the drain of the eleventh transistor M11 is electrically connected to the first node PU, and the source of the eleventh transistor M11 is electrically connected to the first low voltage line LVSS.

[0210] The gate of the twelfth transistor M12 is electrically connected to the frame reset terminal TRST, the drain of the twelfth transistor M12 is electrically connected to the first node PU, and the source of the twelfth transistor M12 is electrically connected to the first low voltage line LVSS.

[0211] The gate of the thirteenth transistor M13 is electrically connected to the first input terminal I1, the drain of the thirteenth transistor M13 is electrically connected to the first noise reduction node PD1, and the source of the thirteenth transistor M13 is electrically connected to the first low voltage line LVSS.

[0212] The gate of the fourteenth transistor M14 is electrically connected to the first input terminal I1, the drain of the fourteenth transistor M14 is electrically connected to the second noise reduction node PD2, and the source of the fourteenth transistor M14 is electrically connected to the first low voltage line LVSS.

[0213] The energy storage circuit includes a storage capacitor Cst;

[0214] The first end of Cst is electrically connected to the first node PU, and the second end of Cst is electrically connected to the drive signal output terminal GT.

[0215] In at least one embodiment of this disclosure, the voltage value of the first low voltage signal provided by the LVSS may be less than the voltage value of the second low voltage signal provided by the VSS, but is not limited thereto; in actual operation, the voltage value of the first low voltage signal provided by the LVSS may also be equal to the voltage value of the second low voltage signal provided by the VSS.

[0216] exist Figure 12 In at least one embodiment of the driving circuit shown, all transistors are n-type transistors, but this is not a limitation.

[0217] exist Figure 12 In at least one embodiment of the driving circuit shown, the output clock signal line is the second noise reduction clock signal line CK2, but is not limited thereto.

[0218] This disclosure Figure 12 In at least one embodiment of the driving circuit shown, the first control voltage line and the second control voltage line in the related art are replaced by the first noise reduction clock signal line CK1 and the second noise reduction clock signal line CK2. CK1 and CK2 can be the same clock signal lines as those used in the related art, thereby reducing the number of noise reduction components included in this disclosure. Figure 12 The number of signal lines used in the drive module of at least one embodiment of the drive circuit shown is advantageous for achieving a narrow bezel and reducing the area occupied by the drive module. For example, the bezel size occupied by the drive module can be reduced from 5325μm to 255μm.

[0219] This disclosure Figure 12 In at least one embodiment of the driving circuit shown, when in operation, CK2 can be the first clock signal line CLK1, and CK1 can be the seventh clock signal line CLK7.

[0220] like Figure 13 As shown, the drive module can use twelve clock signal lines: first clock signal line CLK1, second clock signal line CLK2, third clock signal line CLK3, fourth clock signal line CLK4, fifth clock signal line CLK5, sixth clock signal line CLK6, seventh clock signal line CLK7, eighth clock signal line CLK8, ninth clock signal line CLK9, tenth clock signal line CLK10, eleventh clock signal line CLK11 and twelfth clock signal line CLK12;

[0221] The duty cycles of the first clock signal provided by CLK1, the second clock signal provided by CLK2, the third clock signal provided by CLK3, the fourth clock signal provided by CLK4, the fifth clock signal provided by CLK5, the sixth clock signal provided by CLK6, the seventh clock signal provided by CLK7, the eighth clock signal provided by CLK8, the ninth clock signal provided by CLK9, the tenth clock signal provided by CLK10, the eleventh clock signal provided by CLK11, and the twelfth clock signal provided by CLK12 can all be 1 / 2.

[0222] The periods of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth clock signals can all be 12H.

[0223] Where 1H represents the scan time for one line;

[0224] Within one cycle, the time during which the potential of each clock signal remains high can be 6 hours, and the time during which the potential of each clock signal remains low can also be 6 hours.

[0225] The second clock signal can be delayed by 1 hour compared to the first clock signal, the third clock signal can be delayed by 1 hour compared to the second clock signal, the fourth clock signal can be delayed by 1 hour compared to the third clock signal, the fifth clock signal can be delayed by 1 hour compared to the fourth clock signal, the sixth clock signal can be delayed by 1 hour compared to the fifth clock signal, the seventh clock signal can be delayed by 1 hour compared to the sixth clock signal, the eighth clock signal can be delayed by 1 hour compared to the seventh clock signal, the ninth clock signal can be delayed by 1 hour compared to the eighth clock signal, the tenth clock signal can be delayed by 1 hour compared to the ninth clock signal, the eleventh clock signal can be delayed by 1 hour compared to the tenth clock signal, and the twelfth clock signal can be delayed by 1 hour compared to the eleventh clock signal.

[0226] This disclosure Figure 12 In at least one embodiment of the driving circuit shown, during operation, TRST provides a high voltage signal, M12 is turned on, PU and LVSS are connected, and the potential of PU is reset during a portion of the time period at the beginning of a frame and a portion of the time period at the end of a frame.

[0227] A frame of time can include the input phase, output phase, reset phase, and output cutoff phase set sequentially.

[0228] During the input phase, I1 and I2 both provide high voltage signals, M8 is turned on, PU is connected to I2, PU's potential is high voltage, M3 and M5 are turned on, PD1 and PD2's potentials are low voltage, MC and MO are turned on, OC is connected to CK2, and GT is connected to CK2; at this time, CK2 provides a low voltage signal, and OC and GT output low voltage signals.

[0229] During the output phase, CK2 provides a high voltage signal, the potential of PU is boosted by Cst, the potential of PU is high voltage, M3 and M5 are turned on, the potentials of PD1 and PD2 are low voltage, MC and MO are turned on, OC is connected to CK2, and GT is connected to CK2; at this time, CK2 provides a low voltage signal, and OC and GT output low voltage signals.

[0230] During the reset phase, RST provides a high voltage signal, M9 is turned on, PU and LVSS are connected, and the potential of PU is low voltage;

[0231] During the reset phase, PU is at a low voltage; CK1 or CK2 provides a high voltage signal, PD1 or PD2 is at a high voltage, MR1 or MR2 is turned on, MJ1 or MJ2 is turned on, and OC and GT both output low voltage signals.

[0232] During at least a portion of the output cutoff phase, the potential of PU remains low; CK1 or CK2 provides a high voltage signal, the potential of PD1 or PD2 is high, MR1 or MR2 is turned on, MJ1 or MJ2 is turned on, and OC and GT both output low voltage signals.

[0233] During the output cutoff phase, since M1 is in a diode-connected state, PD1 is at a low voltage potential when CK1 provides a low voltage signal.

[0234] In the output cutoff state, when CK2 provides a low voltage signal, since M4 is in diode connection state, the potential of PDCN2 is low voltage. When M6 is turned off, the potential of PD2 can be maintained at high voltage, which can reduce noise for OC and GT through MR2 and MJ2.

[0235] This disclosure Figure 12 In at least one embodiment of the driving circuit shown, when the duty cycle of the clock signal provided by CK1 and the duty cycle of the clock signal provided by CK2 are less than 50%, it can also play a noise reduction role.

[0236] In at least one embodiment of this disclosure, when the driving module uses 2N clock signal lines, N and m are both positive integers;

[0237] The carry signal output terminal of the m-th stage driver circuit is electrically connected to the first input terminal of the (m+N)-th stage driver circuit, and the drive signal output terminal of the m-th stage driver circuit is electrically connected to the second input terminal of the (m+N)-th stage driver circuit; or...

[0238] The carry signal output terminal of the m-th stage driving circuit is electrically connected to the first input terminal of the m+N-th stage driving circuit, and the carry signal output terminal of the m-th stage driving circuit is electrically connected to the second input terminal of the m+N-th stage driving circuit.

[0239] like Figure 14 As shown, in Figure 10 Based on at least one embodiment of the driving circuit shown,

[0240] The first noise reduction control circuit includes a second transistor M2 and a third transistor M3;

[0241] The gate and drain of the second transistor M2 are electrically connected to the first noise reduction clock signal line CK1, and the source of the second transistor M2 is electrically connected to the first noise reduction node PD1.

[0242] The gate of the third transistor M3 is electrically connected to the first node PU, the drain of the third transistor M3 is electrically connected to the first noise reduction node PD1, and the source of the third transistor M3 is electrically connected to the first low voltage line LVSS.

[0243] The second noise reduction circuit includes a fourth transistor M4 and a fifth transistor M5;

[0244] The gate and drain of the fourth transistor M4 are electrically connected to the power supply voltage line VDD, and the source of the fourth transistor M4 is electrically connected to the second noise reduction node PD2.

[0245] The gate of the fifth transistor M5 is electrically connected to the first node PU, the drain of the fifth transistor M5 is electrically connected to the second noise reduction node PD2, and the source of the fifth transistor M5 is electrically connected to the first low voltage line LVSS.

[0246] The carry output circuit includes a carry output transistor MC, the carry reset circuit includes a first carry reset transistor MR1 and a second carry reset transistor MR2, the drive output circuit includes a drive output transistor MO, and the output noise reduction circuit includes a first output noise reduction transistor MJ1 and a second output noise reduction transistor MJ2.

[0247] The gate of the carry output transistor MC is electrically connected to the first node PU, the drain of the carry output transistor MC is electrically connected to the second noise reduction clock signal line CK2, and the source of the carry output transistor MC is electrically connected to the carry signal output terminal OC.

[0248] The gate of the first carry reset transistor MR1 is electrically connected to the first noise reduction node PD1, the drain of the first carry reset transistor MR1 is electrically connected to the carry signal output terminal OC, and the source of the first carry reset transistor MR1 is electrically connected to the second low voltage line VSS.

[0249] The gate of the second carry reset transistor MR2 is electrically connected to the second noise reduction node PD2, the drain of the second carry reset transistor MR2 is electrically connected to the carry signal output terminal OC, and the source of the second carry reset transistor MR2 is electrically connected to the second low voltage line VSS.

[0250] The gate of the drive output transistor MO is electrically connected to the first node PU, the drain of the drive output transistor MO is electrically connected to the second noise reduction clock signal line CK2, and the source of the drive output transistor MO is electrically connected to the drive signal output terminal GT.

[0251] The gate of the first output noise reduction transistor MJ1 is electrically connected to the first noise reduction node PD1, the drain of the first output noise reduction transistor MJ1 is electrically connected to the drive signal output terminal GT, and the source of the first output noise reduction transistor MJ1 is electrically connected to the second low voltage line VSS.

[0252] The gate of the second output noise reduction transistor MJ2 is electrically connected to the second noise reduction node PD2, the drain of the second output noise reduction transistor MJ2 is electrically connected to the drive signal output terminal GT, and the source of the second output noise reduction transistor MJ2 is electrically connected to the second low voltage line VSS.

[0253] The first node control circuit includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12; the noise reduction node control circuit includes a thirteenth transistor M13 and a fourteenth transistor M14.

[0254] The gate of the eighth transistor M8 is electrically connected to the first input terminal I1, the drain of the eighth transistor M8 is electrically connected to the second input terminal I2, and the source of the eighth transistor M8 is electrically connected to the first node PU.

[0255] The gate of the ninth transistor M9 is electrically connected to the reset terminal RST, the drain of the ninth transistor M9 is electrically connected to the first node PU, and the source of the ninth transistor M9 is electrically connected to the first low voltage line LVSS.

[0256] The gate of the tenth transistor M10 is electrically connected to the first noise reduction node PD1, the drain of the tenth transistor M10 is electrically connected to the first node PU, and the source of the tenth transistor M10 is electrically connected to the first low voltage line LVSS.

[0257] The gate of the eleventh transistor M11 is electrically connected to the second noise reduction node PD2, the drain of the eleventh transistor M11 is electrically connected to the first node PU, and the source of the eleventh transistor M11 is electrically connected to the first low voltage line LVSS.

[0258] The gate of the twelfth transistor M12 is electrically connected to the frame reset terminal TRST, the drain of the twelfth transistor M12 is electrically connected to the first node PU, and the source of the twelfth transistor M12 is electrically connected to the first low voltage line LVSS.

[0259] The gate of the thirteenth transistor M13 is electrically connected to the first input terminal I1, the drain of the thirteenth transistor M13 is electrically connected to the first noise reduction node PD1, and the source of the thirteenth transistor M13 is electrically connected to the first low voltage line LVSS.

[0260] The gate of the fourteenth transistor M14 is electrically connected to the first input terminal I1, the drain of the fourteenth transistor M14 is electrically connected to the second noise reduction node PD2, and the source of the fourteenth transistor M14 is electrically connected to the first low voltage line LVSS.

[0261] The energy storage circuit includes a storage capacitor Cst;

[0262] The first end of Cst is electrically connected to the first node PU, and the second end of Cst is electrically connected to the drive signal output terminal GT.

[0263] exist Figure 14 In at least one embodiment of the driving circuit shown, all transistors are n-type transistors, but this is not a limitation.

[0264] exist Figure 14 In at least one embodiment of the driving circuit shown, the output clock signal line is the power supply voltage line VDD, but this is not a limitation.

[0265] This disclosure Figure 14 At least one embodiment of the driving circuit shown, when in operation,

[0266] When the first noise reduction circuit is working, PD1 charges and discharges through M2 and M1 as the clock signal provided by CK1 changes between high and low levels. When the potential of PD1 is low, MR1, MJ1, and M10 do not work, and the working time of MR1, MJ1, and M10 decreases by at least 50%, reducing characteristic drift and improving reliability. The first noise reduction circuit does not work when CK1 provides a low voltage signal. The second noise reduction circuit is controlled by VDD and can control the potential of PD2 to be high when PU is low.

[0267] exist Figure 14 In at least one embodiment of the driving circuit shown, the second noise reduction circuit contains only two transistors. Reducing the number of transistors used can further reduce the space occupied by the driving module, which is beneficial for achieving a narrow bezel.

[0268] This disclosure Figure 14 In at least one embodiment of the driving circuit shown, when in operation, VDD provides a power supply voltage signal, which is a high voltage signal, M4 is turned on, and when the potential of PU is low voltage, the potential of PD2 remains high voltage, controlling MR2 and MJ2 to turn on, thereby reducing noise for OC and GT.

[0269] like Figure 15 As shown, in Figure 10 Based on at least one embodiment of the driving circuit shown,

[0270] The first noise reduction control circuit includes a second transistor M2 and a third transistor M3;

[0271] The gate and drain of the second transistor M2 are electrically connected to the first noise reduction clock signal line CK1, and the source of the second transistor M2 is electrically connected to the first noise reduction node PD1.

[0272] The gate of the third transistor M3 is electrically connected to the first node PU, the drain of the third transistor M3 is electrically connected to the first noise reduction node PD1, and the source of the third transistor M3 is electrically connected to the first low voltage line LVSS.

[0273] The second noise reduction circuit includes a fourth transistor M4 and a fifth transistor M5;

[0274] The gate and drain of the fourth transistor M4 are electrically connected to the second noise reduction clock signal line CK2, and the source of the fourth transistor M4 is electrically connected to the second noise reduction node PD2.

[0275] The gate of the fifth transistor M5 is electrically connected to the first node PU, the drain of the fifth transistor M5 is electrically connected to the second noise reduction node PD2, and the source of the fifth transistor M5 is electrically connected to the first low voltage line LVSS.

[0276] The carry output circuit includes a carry output transistor MC, the carry reset circuit includes a first carry reset transistor MR1 and a second carry reset transistor MR2, the drive output circuit includes a drive output transistor MO, and the output noise reduction circuit includes a first output noise reduction transistor MJ1 and a second output noise reduction transistor MJ2.

[0277] The gate of the carry output transistor MC is electrically connected to the first node PU, the drain of the carry output transistor MC is electrically connected to the second noise reduction clock signal line CK2, and the source of the carry output transistor MC is electrically connected to the carry signal output terminal OC.

[0278] The gate of the first carry reset transistor MR1 is electrically connected to the first noise reduction node PD1, the drain of the first carry reset transistor MR1 is electrically connected to the carry signal output terminal OC, and the source of the first carry reset transistor MR1 is electrically connected to the second low voltage line VSS.

[0279] The gate of the second carry reset transistor MR2 is electrically connected to the second noise reduction node PD2, the drain of the second carry reset transistor MR2 is electrically connected to the carry signal output terminal OC, and the source of the second carry reset transistor MR2 is electrically connected to the second low voltage line VSS.

[0280] The gate of the drive output transistor MO is electrically connected to the first node PU, the drain of the drive output transistor MO is electrically connected to the second noise reduction clock signal line CK2, and the source of the drive output transistor MO is electrically connected to the drive signal output terminal GT.

[0281] The gate of the first output noise reduction transistor MJ1 is electrically connected to the first noise reduction node PD1, the drain of the first output noise reduction transistor MJ1 is electrically connected to the drive signal output terminal GT, and the source of the first output noise reduction transistor MJ1 is electrically connected to the second low voltage line VSS.

[0282] The gate of the second output noise reduction transistor MJ2 is electrically connected to the second noise reduction node PD2, the drain of the second output noise reduction transistor MJ2 is electrically connected to the drive signal output terminal GT, and the source of the second output noise reduction transistor MJ2 is electrically connected to the second low voltage line VSS.

[0283] The first node control circuit includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12; the noise reduction node control circuit includes a thirteenth transistor M13 and a fourteenth transistor M14.

[0284] The gate of the eighth transistor M8 is electrically connected to the first input terminal I1, the drain of the eighth transistor M8 is electrically connected to the second input terminal I2, and the source of the eighth transistor M8 is electrically connected to the first node PU.

[0285] The gate of the ninth transistor M9 is electrically connected to the reset terminal RST, the drain of the ninth transistor M9 is electrically connected to the first node PU, and the source of the ninth transistor M9 is electrically connected to the first low voltage line LVSS.

[0286] The gate of the tenth transistor M10 is electrically connected to the first noise reduction node PD1, the drain of the tenth transistor M10 is electrically connected to the first node PU, and the source of the tenth transistor M10 is electrically connected to the first low voltage line LVSS.

[0287] The gate of the eleventh transistor M11 is electrically connected to the second noise reduction node PD2, the drain of the eleventh transistor M11 is electrically connected to the first node PU, and the source of the eleventh transistor M11 is electrically connected to the first low voltage line LVSS.

[0288] The gate of the twelfth transistor M12 is electrically connected to the frame reset terminal TRST, the drain of the twelfth transistor M12 is electrically connected to the first node PU, and the source of the twelfth transistor M12 is electrically connected to the first low voltage line LVSS.

[0289] The gate of the thirteenth transistor M13 is electrically connected to the first input terminal I1, the drain of the thirteenth transistor M13 is electrically connected to the first noise reduction node PD1, and the source of the thirteenth transistor M13 is electrically connected to the first low voltage line LVSS.

[0290] The gate of the fourteenth transistor M14 is electrically connected to the first input terminal I1, the drain of the fourteenth transistor M14 is electrically connected to the second noise reduction node PD2, and the source of the fourteenth transistor M14 is electrically connected to the first low voltage line LVSS.

[0291] The energy storage circuit includes a storage capacitor Cst;

[0292] The first end of Cst is electrically connected to the first node PU, and the second end of Cst is electrically connected to the drive signal output terminal GT.

[0293] exist Figure 15 In at least one embodiment of the driving circuit shown, all transistors are n-type transistors, but this is not a limitation.

[0294] exist Figure 15 In at least one embodiment of the driving circuit shown, the output clock signal line is the second noise reduction clock signal line CK2.

[0295] This disclosure Figure 15 At least one embodiment of the driving circuit shown is consistent with this disclosure. Figure 14 The difference in at least one embodiment of the driving circuit shown is that:

[0296] The gate and drain of M4 are both electrically connected to the second noise reduction clock signal line CK2.

[0297] This disclosure Figure 15 At least one embodiment of the driving circuit shown is consistent with this disclosure. Figure 14 Compared to at least one embodiment of the driving circuit shown, the use of the power supply voltage line VDD is reduced, which can further reduce the space occupied by the driving module and facilitate the realization of a narrow bezel; for example, the bezel size can be further reduced by 126μm.

[0298] This disclosure Figure 15 In at least one embodiment of the driving circuit shown, when PU has a low potential and CK2 provides a high voltage signal, PD2 has a high potential.

[0299] When the potential of PU is low and CK2 provides a low voltage signal, the potential of PD2 can be maintained at a high voltage, so that MR2 and MJ2 are turned on, and noise reduction is performed for OC and GT.

[0300] like Figure 16 As shown, in Figure 11 Based on at least one embodiment of the driving circuit shown,

[0301] The first noise reduction control circuit includes a second transistor M2 and a third transistor M3;

[0302] The gate and drain of the second transistor M2 are electrically connected to the first noise reduction clock signal line CK1, and the source of the second transistor M2 is electrically connected to the first noise reduction node PD1.

[0303] The gate of the third transistor M3 is electrically connected to the first node PU, the drain of the third transistor M3 is electrically connected to the first noise reduction node PD1, and the source of the third transistor M3 is electrically connected to the first low voltage line LVSS.

[0304] The second noise reduction circuit includes a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6;

[0305] The gate and drain of the fourth transistor M4 are electrically connected to the second noise reduction clock signal line CK2, and the source of the fourth transistor M4 is electrically connected to the second noise reduction node PD2.

[0306] The gate of the fifth transistor M5 is electrically connected to the first node PU, the drain of the fifth transistor M5 is electrically connected to the second noise reduction node PD2, and the source of the fifth transistor M5 is electrically connected to the first low voltage line LVSS.

[0307] The gate of the sixth transistor M6 is electrically connected to the second noise reduction node PD2, the drain of the sixth transistor M6 is electrically connected to the second noise reduction clock signal line CK2, and the source of the sixth transistor M6 is electrically connected to the second noise reduction node PD2.

[0308] The carry output circuit includes a carry output transistor MC, the carry reset circuit includes a first carry reset transistor MR1 and a second carry reset transistor MR2, the drive output circuit includes a drive output transistor MO, and the output noise reduction circuit includes a first output noise reduction transistor MJ1 and a second output noise reduction transistor MJ2.

[0309] The gate of the carry output transistor MC is electrically connected to the first node PU, the drain of the carry output transistor MC is electrically connected to the second noise reduction clock signal line CK2, and the source of the carry output transistor MC is electrically connected to the carry signal output terminal OC.

[0310] The gate of the first carry reset transistor MR1 is electrically connected to the first noise reduction node PD1, the drain of the first carry reset transistor MR1 is electrically connected to the carry signal output terminal OC, and the source of the first carry reset transistor MR1 is electrically connected to the second low voltage line VSS.

[0311] The gate of the second carry reset transistor MR2 is electrically connected to the second noise reduction node PD2, the drain of the second carry reset transistor MR2 is electrically connected to the carry signal output terminal OC, and the source of the second carry reset transistor MR2 is electrically connected to the second low voltage line VSS.

[0312] The gate of the drive output transistor MO is electrically connected to the first node PU, the drain of the drive output transistor MO is electrically connected to the second noise reduction clock signal line CK2, and the source of the drive output transistor MO is electrically connected to the drive signal output terminal GT.

[0313] The gate of the first output noise reduction transistor MJ1 is electrically connected to the first noise reduction node PD1, the drain of the first output noise reduction transistor MJ1 is electrically connected to the drive signal output terminal GT, and the source of the first output noise reduction transistor MJ1 is electrically connected to the second low voltage line VSS.

[0314] The gate of the second output noise reduction transistor MJ2 is electrically connected to the second noise reduction node PD2, the drain of the second output noise reduction transistor MJ2 is electrically connected to the drive signal output terminal GT, and the source of the second output noise reduction transistor MJ2 is electrically connected to the second low voltage line VSS.

[0315] The first node control circuit includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12; the noise reduction node control circuit includes a thirteenth transistor M13 and a fourteenth transistor M14.

[0316] The gate of the eighth transistor M8 is electrically connected to the first input terminal I1, the drain of the eighth transistor M8 is electrically connected to the second input terminal I2, and the source of the eighth transistor M8 is electrically connected to the first node PU.

[0317] The gate of the ninth transistor M9 is electrically connected to the reset terminal RST, the drain of the ninth transistor M9 is electrically connected to the first node PU, and the source of the ninth transistor M9 is electrically connected to the first low voltage line LVSS.

[0318] The gate of the tenth transistor M10 is electrically connected to the first noise reduction node PD1, the drain of the tenth transistor M10 is electrically connected to the first node PU, and the source of the tenth transistor M10 is electrically connected to the first low voltage line LVSS.

[0319] The gate of the eleventh transistor M11 is electrically connected to the second noise reduction node PD2, the drain of the eleventh transistor M11 is electrically connected to the first node PU, and the source of the eleventh transistor M11 is electrically connected to the first low voltage line LVSS.

[0320] The gate of the twelfth transistor M12 is electrically connected to the frame reset terminal TRST, the drain of the twelfth transistor M12 is electrically connected to the first node PU, and the source of the twelfth transistor M12 is electrically connected to the first low voltage line LVSS.

[0321] The gate of the thirteenth transistor M13 is electrically connected to the first input terminal I1, the drain of the thirteenth transistor M13 is electrically connected to the first noise reduction node PD1, and the source of the thirteenth transistor M13 is electrically connected to the first low voltage line LVSS.

[0322] The gate of the fourteenth transistor M14 is electrically connected to the first input terminal I1, the drain of the fourteenth transistor M14 is electrically connected to the second noise reduction node PD2, and the source of the fourteenth transistor M14 is electrically connected to the first low voltage line LVSS.

[0323] The energy storage circuit includes a storage capacitor Cst;

[0324] The first end of Cst is electrically connected to the first node PU, and the second end of Cst is electrically connected to the drive signal output terminal GT.

[0325] exist Figure 16 In at least one embodiment of the driving circuit shown, all transistors are n-type transistors, but this is not a limitation.

[0326] exist Figure 16 In at least one embodiment of the driving circuit shown, the output clock signal line is the second noise reduction clock signal line CK2, but is not limited thereto.

[0327] This disclosure Figure 16 In at least one embodiment of the driving circuit shown, when CK1 provides a high voltage signal and the potential of PU is low, the potential of PD1 is high, and noise reduction is controlled by PD1.

[0328] When CK2 provides a high voltage signal and PU has a low voltage potential, PD2 has a high voltage potential, and noise reduction is controlled by PD2.

[0329] When CK1 provides a low voltage signal, the potential of PD1 leaks to M1 and M2, thus becoming low voltage;

[0330] When CK2 provides a low voltage signal, the potential of PD2 leaks to M4 and M6, thus becoming low voltage.

[0331] This disclosure Figure 16 In at least one embodiment of the driving circuit shown, when the duty cycle of the clock signal provided by CK1 and the duty cycle of the clock signal provided by CK2 are 1 / 2, when the potential of PU is low, the potential of PD1 or the potential of PD2 is high, controlling OC and GT to output low voltage signals. However, when the duty cycle of the clock signal provided by CK1 and the duty cycle of the clock signal provided by CK2 are less than 50%, there will be a period of time when neither the first nor the second noise reduction circuit will work. Therefore, in actual operation, the duty cycle of the clock signal provided by CK1 and the duty cycle of the clock signal provided by CK2 can be set to a larger value.

[0332] The driving module described in this embodiment includes multiple stages of the aforementioned driving circuits.

[0333] Optionally, the drive module includes 2N clock signal lines; N is a positive integer;

[0334] The driving circuit is the a-th stage driving circuit included in the driving module; a is a positive integer.

[0335] The first noise reduction clock signal line is the N+ath clock signal line, and the second noise reduction clock signal line and the output clock signal line are the ath clock signal lines.

[0336] In at least one embodiment of this disclosure, the driving circuit includes a carry signal output terminal, a first input terminal, and a reset terminal;

[0337] The first input terminal of the a-th stage driving circuit is electrically connected to the carry signal output terminal of the aN-th stage driving circuit, and the reset terminal of the a-th stage driving circuit is electrically connected to the carry signal output terminal of the a+N-th stage driving circuit.

[0338] In at least one embodiment of this disclosure, the driving circuit further includes a second input terminal and a driving signal output terminal;

[0339] The second input terminal of the a-th stage driving circuit is electrically connected to the driving signal output terminal of the aN-th stage driving circuit or the carry signal output terminal of the aN-th stage driving circuit.

[0340] like Figure 17 As shown, the driving module described in at least one embodiment of this disclosure uses 12 clock signal lines: a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3, a fourth clock signal line CLK4, a fifth clock signal line CLK5, a sixth clock signal line CLK6, a seventh clock signal line CLK7, an eighth clock signal line CLK8, a ninth clock signal line CLK9, a tenth clock signal line CLK10, an eleventh clock signal line CLK11, and a twelfth clock signal line CLK12.

[0341] exist Figure 17 In the diagram, S1 represents the first-stage drive circuit of the drive module, S2 represents the second-stage drive circuit of the drive module, S3 represents the third-stage drive circuit of the drive module, S4 represents the fourth-stage drive circuit of the drive module, S5 represents the fifth-stage drive circuit of the drive module, S6 represents the sixth-stage drive circuit of the drive module, S7 represents the seventh-stage drive circuit of the drive module, S8 represents the eighth-stage drive circuit of the drive module, S9 represents the ninth-stage drive circuit of the drive module, S10 represents the tenth-stage drive circuit of the drive module, S11 represents the eleventh-stage drive circuit of the drive module, and S12 represents the twelfth-stage drive circuit of the drive module.

[0342] S1 is electrically connected to the first clock signal line CLK1 and the seventh clock signal line CLK7 respectively; S2 is electrically connected to the second clock signal line CLK2 and the eighth clock signal line CLK8 respectively; S3 is electrically connected to the third clock signal line CLK3 and the ninth clock signal line CLK9 respectively; S4 is electrically connected to the fourth clock signal line CLK4 and the tenth clock signal line CLK10 respectively; S5 is electrically connected to the fifth clock signal line CLK5 and the eleventh clock signal line CLK11 respectively; S6 is electrically connected to the sixth clock signal line CLK6 and the twelfth clock signal line CLK12 respectively.

[0343] S7 is electrically connected to the first clock signal line CLK1 and the seventh clock signal line CLK7 respectively; S8 is electrically connected to the second clock signal line CLK2 and the eighth clock signal line CLK8 respectively; S9 is electrically connected to the third clock signal line CLK3 and the ninth clock signal line CLK9 respectively; S10 is electrically connected to the fourth clock signal line CLK4 and the tenth clock signal line CLK10 respectively; S11 is electrically connected to the fifth clock signal line CLK5 and the eleventh clock signal line CLK11 respectively; S12 is electrically connected to the sixth clock signal line CLK6 and the twelfth clock signal line CLK12 respectively.

[0344] The carry signal output terminal of S1 is electrically connected to the first input terminal of S7, and the carry signal output terminal of S7 is electrically connected to the reset terminal of S1.

[0345] The drive signal output terminal of S1 is electrically connected to the second input terminal of S7;

[0346] The carry signal output terminal of S2 is electrically connected to the first input terminal of S8, and the carry signal output terminal of S8 is electrically connected to the reset terminal of S2.

[0347] The drive signal output terminal of S2 is electrically connected to the second input terminal of S8;

[0348] The carry signal output terminal of S3 is electrically connected to the first input terminal of S9, and the carry signal output terminal of S9 is electrically connected to the reset terminal of S2.

[0349] The drive signal output terminal of S3 is electrically connected to the second input terminal of S9;

[0350] The carry signal output terminal of S4 is electrically connected to the first input terminal of S10, and the carry signal output terminal of S10 is electrically connected to the reset terminal of S4.

[0351] The drive signal output terminal of S4 is electrically connected to the second input terminal of S10;

[0352] The carry signal output terminal of S5 is electrically connected to the first input terminal of S11, and the carry signal output terminal of S11 is electrically connected to the reset terminal of S5.

[0353] The drive signal output terminal of S5 is electrically connected to the second input terminal of S11;

[0354] The carry signal output terminal of S6 is electrically connected to the first input terminal of S12, and the carry signal output terminal of S12 is electrically connected to the reset terminal of S6.

[0355] The drive signal output terminal of S6 is electrically connected to the second input terminal of S12;

[0356] The first input terminal of S1, the first input terminal of S3, the first input terminal of S5, the second input terminal of S1, the second input terminal of S3, and the second input terminal of S5 are connected to the first starting voltage STV1;

[0357] The first input terminals of S2, S4, and S6, the second input terminals of S2, S4, and S6 are connected to the second starting voltage STV2.

[0358] In at least one embodiment of this disclosure, the reset terminal of the last six-stage drive circuit of the drive module can be connected to a reset voltage signal.

[0359] Figure 18 This is a timing diagram of the operation of the drive module according to at least one embodiment of the present disclosure.

[0360] exist Figure 18 In the diagram, GT2160 is the output terminal of the 2160th stage drive signal, TZ is the time of one frame, and TB is the blank area.

[0361] Within one cycle, the time during which the potential of each clock signal remains high is 6H, and the time during which the potential of each clock signal remains low is 6H.

[0362] The frame reset signal provided by TRST remains high for 6 hours.

[0363] The potential of the first starting voltage STV1 remains high for 11 hours, and the potential of the second starting voltage STV2 remains high for 11 hours.

[0364] Where 1H represents the scan time for one line.

[0365] The display device described in this disclosure includes the driving module described above.

[0366] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A driving circuit, comprising a first noise reduction circuit, a second noise reduction circuit, and an output noise reduction circuit; The first noise reduction circuit includes a first noise reduction control circuit and a first transistor; The gate and the second terminal of the first transistor are both electrically connected to the first noise reduction node, and the first terminal of the first transistor is electrically connected to the first noise reduction clock signal line. The first noise reduction control circuit is electrically connected to the first noise reduction clock signal line, the first noise reduction node and the first node respectively, and is used to control the potential of the first noise reduction node under the control of the first noise reduction clock signal provided by the first noise reduction clock signal line and the potential of the first node. The second noise reduction circuit is electrically connected to the noise reduction control line, the first node, and the second noise reduction node, and is used to control the potential of the second noise reduction node under the control of the noise reduction control signal provided by the noise reduction control line and the potential of the first node. The output noise reduction circuit is electrically connected to the first noise reduction node, the second noise reduction node and the drive signal output terminal respectively, and is used to reduce the noise of the drive signal provided by the drive signal output terminal under the control of the potential of the first noise reduction node and the potential of the second noise reduction node.

2. The driving circuit as described in claim 1, wherein, The noise reduction control line is the second noise reduction clock signal line.

3. The driving circuit as described in claim 1, wherein, The noise reduction control line is the first voltage line.

4. The driving circuit as described in claim 2, wherein, The first noise reduction control circuit is also electrically connected to the second voltage line, and is used to control the connection between the first noise reduction node and the first noise reduction clock signal line under the control of the first noise reduction clock signal, and to control the connection between the first noise reduction node and the second voltage line under the control of the potential of the first node.

5. The driving circuit as described in claim 2, wherein, The second noise reduction circuit is also electrically connected to the second noise reduction control node and the second voltage line, respectively, and is used to control the connection between the second noise reduction control node and the second noise reduction clock signal line under the control of the second noise reduction clock signal provided by the second noise reduction clock signal line, control the connection between the second noise reduction control node and the second voltage line under the control of the potential of the first node, control the connection between the second noise reduction node and the second noise reduction clock signal line under the control of the potential of the second noise reduction control node, and control the connection between the second noise reduction node and the second voltage line under the control of the potential of the first node.

6. The driving circuit as described in claim 2, wherein, The second noise reduction circuit is also electrically connected to the second voltage line, and is used to control the connection between the noise reduction control line and the second noise reduction node under the control of the noise reduction control signal provided by the noise reduction control line, and to control the connection between the second noise reduction node and the second voltage line under the control of the potential of the first node.

7. The driving circuit as described in claim 2, wherein, The second noise reduction circuit is also electrically connected to the second voltage line, and is used to control the connection between the second noise reduction node and the second noise reduction clock signal line under the control of the second noise reduction clock signal provided by the second noise reduction clock signal line, control the connection between the second noise reduction node and the second voltage line under the control of the potential of the first node, and control the connection between the second noise reduction clock signal line and the second noise reduction node under the control of the potential of the second noise reduction node.

8. The driving circuit as described in claim 4, wherein, The first noise reduction control circuit includes a second transistor and a third transistor; The gate of the second transistor and the first terminal of the second transistor are electrically connected to the first noise reduction clock signal line, and the second terminal of the second transistor is electrically connected to the first noise reduction node; The gate of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the first noise reduction node, and the second electrode of the third transistor is electrically connected to the second voltage line.

9. The driving circuit as described in claim 5, wherein, The second noise reduction circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; The gate of the fourth transistor is electrically connected to the first terminal of the fourth transistor and the second noise reduction clock signal line, and the second terminal of the fourth transistor is electrically connected to the second noise reduction control node. The gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the second noise reduction control node, and the second electrode of the fifth transistor is electrically connected to the second voltage line. The gate of the sixth transistor is electrically connected to the second noise reduction control node, the first terminal of the sixth transistor is electrically connected to the second noise reduction clock signal line, and the second terminal of the sixth transistor is electrically connected to the second noise reduction node. The gate of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the second noise reduction node, and the second electrode of the seventh transistor is electrically connected to the second voltage line.

10. The driving circuit as described in claim 6, wherein, The second noise reduction circuit includes a fourth transistor and a fifth transistor; The gate and the first terminal of the fourth transistor are both electrically connected to the noise reduction control line, and the second terminal of the fourth transistor is electrically connected to the second noise reduction node. The gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the second noise reduction node, and the second electrode of the fifth transistor is electrically connected to the second voltage line.

11. The driving circuit as claimed in claim 7, wherein, The second noise reduction circuit includes a fourth transistor, a fifth transistor, and a sixth transistor; The gate of the fourth transistor is electrically connected to the first terminal of the fourth transistor and the second noise reduction clock signal line, and the second terminal of the fourth transistor is electrically connected to the second noise reduction node; The gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the second noise reduction node, and the second electrode of the fifth transistor is electrically connected to the second voltage line. The gate and the second terminal of the sixth transistor are both electrically connected to the second noise reduction node, and the first terminal of the sixth transistor is electrically connected to the second noise reduction clock signal line.

12. The driving circuit according to any one of claims 1 to 11, wherein, It also includes a carry output circuit, a carry reset circuit, and a drive output circuit; The carry output circuit is electrically connected to the first node, the output clock signal line, and the carry signal output terminal, respectively, and is used to control the connection between the carry signal output terminal and the output clock signal line under the control of the potential of the first node. The carry reset circuit is electrically connected to the first noise reduction node, the second noise reduction node, the carry signal output terminal, and the third voltage line, respectively. It is used to control the connection between the carry signal output terminal and the third voltage line under the control of the potential of the first noise reduction node, and to control the connection between the carry signal output terminal and the third voltage line under the control of the potential of the second noise reduction node. The drive output circuit is electrically connected to the first node, the drive signal output terminal, and the output clock signal line, respectively, and is used to control the connection between the drive signal output terminal and the output clock signal line under the control of the potential of the first node.

13. The driving circuit according to any one of claims 1 to 11, wherein, It also includes an energy storage circuit, a first node control circuit, and a noise reduction node control circuit; The energy storage circuit is electrically connected to the first node and the drive signal output terminal respectively, and is used to store electrical energy. The first node control circuit is electrically connected to the first input terminal, the second input terminal, the first node, the reset terminal, the first noise reduction node, the second noise reduction node, and the second voltage line, respectively. It is used to control the connection between the first node and the second input terminal under the control of the first input signal provided by the first input terminal, control the connection between the first node and the second voltage line under the control of the reset signal provided by the reset terminal, control the connection between the first node and the second voltage line under the control of the potential of the first noise reduction node, and control the connection between the first node and the second voltage line under the control of the potential of the second noise reduction node. The noise reduction node control circuit is electrically connected to the first noise reduction node, the second noise reduction node, the first input terminal, and the second voltage line, respectively, and is used to control the connection between the first noise reduction node and the second voltage line, and control the connection between the second noise reduction node and the second voltage line under the control of the first input signal provided by the first input terminal.

14. The driving circuit as described in claim 13, wherein, The first node control circuit is also electrically connected to the frame reset terminal, and is used to control the connection between the first node and the second voltage line under the control of the frame reset signal provided by the frame reset terminal.

15. The driving circuit as claimed in claim 12, wherein, The carry output circuit includes a carry output transistor, the carry reset circuit includes a first carry reset transistor and a second carry reset transistor, the drive output circuit includes a drive output transistor, and the output noise reduction circuit includes a first output noise reduction transistor and a second output noise reduction transistor. The gate of the carry output transistor is electrically connected to the first node, the first terminal of the carry output transistor is electrically connected to the output clock signal line, and the second terminal of the carry output transistor is electrically connected to the carry signal output terminal. The gate of the first carry reset transistor is electrically connected to the first noise reduction node, the first terminal of the first carry reset transistor is electrically connected to the carry signal output terminal, and the second terminal of the first carry reset transistor is electrically connected to the third voltage line. The gate of the second carry reset transistor is electrically connected to the second noise reduction node, the first terminal of the second carry reset transistor is electrically connected to the carry signal output terminal, and the second terminal of the second carry reset transistor is electrically connected to the third voltage line. The gate of the drive output transistor is electrically connected to the first node, the first terminal of the drive output transistor is electrically connected to the output clock signal line, and the second terminal of the drive output transistor is electrically connected to the drive signal output terminal. The gate of the first output noise reduction transistor is electrically connected to the first noise reduction node, the first terminal of the first output noise reduction transistor is electrically connected to the drive signal output terminal, and the second terminal of the first output noise reduction transistor is electrically connected to the third voltage line. The gate of the second output noise reduction transistor is electrically connected to the second noise reduction node, the first terminal of the second output noise reduction transistor is electrically connected to the drive signal output terminal, and the second terminal of the second output noise reduction transistor is electrically connected to the third voltage line.

16. The driving circuit as claimed in claim 14, wherein, The first node control circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; the noise reduction node control circuit includes a thirteenth transistor and a fourteenth transistor. The gate of the eighth transistor is electrically connected to the first input terminal, the first terminal of the eighth transistor is electrically connected to the second input terminal, and the second terminal of the eighth transistor is electrically connected to the first node. The gate of the ninth transistor is electrically connected to the reset terminal, the first terminal of the ninth transistor is electrically connected to the first node, and the second terminal of the ninth transistor is electrically connected to the second voltage line. The gate of the tenth transistor is electrically connected to the first noise reduction node, the first electrode of the tenth transistor is electrically connected to the first node, and the second electrode of the tenth transistor is electrically connected to the second voltage line. The gate of the eleventh transistor is electrically connected to the second noise reduction node, the first terminal of the eleventh transistor is electrically connected to the first node, and the second terminal of the eleventh transistor is electrically connected to the second voltage line. The gate of the twelfth transistor is electrically connected to the frame reset terminal, the first terminal of the twelfth transistor is electrically connected to the first node, and the second terminal of the twelfth transistor is electrically connected to the second voltage line. The gate of the thirteenth transistor is electrically connected to the first input terminal, the first terminal of the thirteenth transistor is electrically connected to the first noise reduction node, and the second terminal of the thirteenth transistor is electrically connected to the second voltage line. The gate of the fourteenth transistor is electrically connected to the first input terminal, the first terminal of the fourteenth transistor is electrically connected to the second noise reduction node, and the second terminal of the fourteenth transistor is electrically connected to the second voltage line.

17. A drive module comprising multiple stages of drive circuits as described in any one of claims 1, 2, 4-16.

18. The drive module as claimed in claim 17, wherein, The drive module includes 2N clock signal lines; N is a positive integer. The driving circuit is the a-th stage driving circuit included in the driving module; a is a positive integer; The first noise reduction clock signal line is the N+ath clock signal line, and the second noise reduction clock signal line and the output clock signal line are the ath clock signal lines.

19. The drive module as described in claim 18, wherein, The driving circuit includes a carry signal output terminal, a first input terminal, and a reset terminal; The first input terminal of the a-th stage driving circuit is electrically connected to the carry signal output terminal of the aN-th stage driving circuit, and the reset terminal of the a-th stage driving circuit is electrically connected to the carry signal output terminal of the a+N-th stage driving circuit.

20. The drive module as described in claim 19, wherein, The driving circuit also includes a second input terminal and a driving signal output terminal; The second input terminal of the a-th stage driving circuit is electrically connected to the driving signal output terminal of the aN-th stage driving circuit or the carry signal output terminal of the aN-th stage driving circuit.

21. A display device comprising the driving module as described in any one of claims 17 to 20.

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