Method for optimizing clock signal of memory, memory controller and electronic device

Abstract

The application relates to a method for optimizing a clock signal of a memory, a memory controller and an electronic device. The method comprises the following steps: scanning a delay of a clock link where a target clock signal is located, finding a first delay corresponding to a center point of a DQ eye diagram; the target clock signal is a first clock signal or a second clock signal in a DQS clock signal; if the first delay is greater than a target delay, obtaining a skew delay between the clock link where the first clock signal is located and the clock link where the second clock signal is located; the target delay is half of a clock period of the target clock signal; and determining the delay of the clock link where the second clock signal or the first clock signal is located according to the first delay, the target delay and the skew delay. The application can eliminate the influence of skew between the first clock signal and the second clock signal, reduce the delay value that needs to be configured to the clock link, reduce the power consumption of the clock link, and greatly improve the accuracy of data transmission between the memory controller and the memory.

Description

Technical Field

[0001] This application belongs to the field of electronic circuits, and specifically relates to a method for optimizing the clock signal of a memory, a memory controller, and an electronic device. Background Technology

[0002] In memory systems (such as RAM systems), the memory controller (such as the memory controller) interacts with the memory (such as RAM) through a physical layer interface (PHY). The PHY can be built into the memory controller. The PHY and memory interface interact via the DQS (Data Queue Strobe) clock signal and the DQ (Data Queue) data signal. The DQS clock signal is the data sampling clock signal between the PHY and the memory, used to sample the data transmitted by the DQ data signal. The DQS clock signal consists of two differential signals, DQS_t and DQS_c. The reliability of memory interface read / write operations determines the reliability of the memory controller. As the operating frequency of the Central Processing Unit (CPU) increases, the required frequency of the memory interface also increases. Higher frequencies are prone to problems such as signal duty cycle distortion and clock jitter, and the resulting decrease in read / write reliability becomes increasingly significant. Summary of the Invention

[0003] Therefore, the purpose of this application is to provide a method for optimizing the clock signal of a memory, a memory controller, and an electronic device to improve the accuracy of data transmission between the memory controller and the memory.

[0004] The embodiments of this application are implemented as follows: In a first aspect, embodiments of this application provide a method for optimizing a memory clock signal, comprising: scanning the delay of a clock link containing a target clock signal to find a first delay corresponding to the center point of a DQ eye diagram; wherein the DQ eye diagram is the maximum eye diagram obtained by sampling a DQ data signal with the target clock signal; the target clock signal is a first clock signal or a second clock signal in a DQS clock signal; if the first delay is greater than the target delay, obtaining the skew delay between the clock link containing the first clock signal and the clock link containing the second clock signal; wherein the target delay is half the clock period of the target clock signal; and determining the delay of the second clock signal or the clock link containing the first clock signal based on the first delay, the target delay, and the skew delay.

[0005] In the above embodiments, when training the delay of the clock link where the target clock signal is located, if the obtained first delay is greater than the target delay 1UI (UI is half of the clock period of the target clock signal), the skew delay between the clock link where the first clock signal is located and the clock link where the second clock signal is located is further obtained. Then, based on the first delay, the target delay, and the skew delay, the delay of the second clock signal or the clock link where the first clock signal is located is determined to eliminate the influence of the skew between the first clock signal and the second clock signal. At the same time, the delay value that needs to be configured on the clock link is reduced, which can reduce the power consumption of the clock link and significantly improve the accuracy of data transmission between the memory controller and the memory.

[0006] In one possible implementation of the first aspect embodiment, determining the delay of the second clock signal or the clock link where the first clock signal is located based on the first delay, the target delay, and the skew delay includes: determining a second delay based on the first delay, the target delay, and the skew delay; if the second delay is greater than a preset threshold when the target clock signal is the first clock signal, determining the delay of the clock link where the second clock signal is located as the second delay, and using the second clock signal as the sampling clock signal for the starting data.

[0007] In the above embodiments, when the target clock signal is the first clock signal, if the second delay is greater than a preset threshold (such as 0), the delay of the clock link where the second clock signal is located is determined to be the second delay. By switching the differential clock edge of the sampling start data, the delay value that needs to be configured on the clock link is reduced, thereby reducing the power consumption on the clock link and enhancing the pit noise capability of the clock link.

[0008] In one possible implementation of the first aspect embodiment, the method further includes: if the second delay is not greater than the preset threshold, obtaining the jitter error of the clock link where the target clock signal is located; if the jitter error is not less than the absolute value of the second delay, determining the delay of the clock link where the second clock signal is located as the preset threshold, and using the second clock signal as the sampling clock signal for the starting data; if the jitter error is less than the absolute value of the second delay, determining the delay of the clock link where the first clock signal is located as the first delay.

[0009] In the above embodiment, when the second delay (e) is not greater than a preset threshold (e.g., 0), since the delay of the clock link cannot be negative, the jitter error of the clock link (f) also needs to be taken into account. If f ≥ |e|, the delay of the clock link where the second clock signal is located is determined to be the preset threshold, and the sampling start data is changed. If f < |e|, the sampling start data is not changed, and the delay of the clock link where the first clock signal is located is determined to be the first delay. This can minimize the delay value that needs to be configured on the clock link, thereby reducing the power consumption on the clock link and enhancing the pit noise capability of the clock link.

[0010] In one possible implementation of the first aspect embodiment, obtaining the skew delay between the clock link where the first clock signal is located and the clock link where the second clock signal is located includes: scanning the delay of the clock link where the first clock signal is located to find a third delay corresponding to the right boundary of the DQ eye diagram; scanning the delay of the clock link where the second clock signal is located to find a fourth delay corresponding to the right boundary of the DQ eye diagram; and determining the skew delay based on the third delay, the fourth delay, and the target delay.

[0011] In the above embodiment, when obtaining the skew delay, the third and fourth delays corresponding to the right boundary of the same DQ eye diagram are scanned by differential clocks. Then, these two delays are subtracted, and their inherent target delay is subtracted to quickly obtain the skew delay between differential clocks. Since the right boundary of the same DQ eye diagram is scanned by differential clocks, the influence of Skew between differential clocks can be eliminated.

[0012] In one possible implementation of the first aspect embodiment, obtaining the jitter error of the clock link where the target clock signal is located includes: obtaining a first jitter time of the clock signal output when the delay of the clock link where the target clock signal is located is the first fixed delay; obtaining a second jitter time of the clock signal output when the delay of the clock link where the target clock signal is located is the second fixed delay; obtaining the difference between the first jitter time and the second jitter time to obtain the jitter error.

[0013] In the above embodiments, by obtaining the jitter time of the clock signal output by the clock link under different fixed delay values, the jitter error can be obtained according to the different jitter times. For example, jitter error = first jitter time - second jitter time. This allows the required jitter error to be obtained quickly, so that the jitter error can be taken into account in the future, which is beneficial to improving the quality of the clock signal.

[0014] In one possible implementation of the first aspect embodiment, the method further includes: if the first delay is not greater than the target delay, determining the delay of the clock link where the target clock signal is located as the first delay.

[0015] In the above embodiments, when training the delay of the clock link where the target clock signal is located, the delay of the clock link where the target clock signal is located is determined to be the first delay only if the first delay is not greater than the target delay. This can reduce the delay value that needs to be configured on the clock link, thereby reducing the power consumption on the clock link and enhancing the pit noise capability of the clock link.

[0016] Secondly, embodiments of this application also provide a memory controller, including: a delay adjustment module and a control module; the delay adjustment module is located on the clock link where the first clock signal and the second clock signal in the DQS clock signal are located, and is used to adjust the delay of the first clock signal and the second clock signal; the control module is connected to the delay adjustment module and is used to scan the delay of the clock link where the target clock signal is located, and find the first delay corresponding to the center point of the DQ eye diagram; if the first delay is greater than the target delay, obtain the skew delay between the clock link where the first clock signal is located and the clock link where the second clock signal is located; determine the delay of the second clock signal or the clock link where the first clock signal is located based on the first delay, the target delay, and the skew delay; wherein, the DQ eye diagram is the maximum eye diagram obtained by sampling the DQ data signal with the target clock signal; the target clock signal is the first clock signal or the second clock signal in the DQS clock signal; the target delay is half of the clock period of the target clock signal.

[0017] In one possible implementation of the second aspect embodiment, the control module is specifically configured to: determine a second delay based on the first delay, the target delay, and the skew delay; if the target clock signal is the first clock signal, and the second delay is greater than a preset threshold, determine the delay of the clock link where the second clock signal is located as the second delay, and use the second clock signal as the sampling clock signal for the starting data.

[0018] In a possible implementation of the second aspect embodiment, the control module is further specifically configured to: if the second delay is not greater than the preset threshold, obtain the jitter error of the clock link where the target clock signal is located; if the jitter error is not less than the absolute value of the second delay, determine the delay of the clock link where the second clock signal is located as the preset threshold, and use the second clock signal as the sampling clock signal for the starting data; if the jitter error is less than the absolute value of the second delay, determine the delay of the clock link where the first clock signal is located as the first delay.

[0019] Thirdly, embodiments of this application also provide a processor, including: a processor core and a memory controller provided as described in the second aspect embodiments and / or in combination with the second aspect embodiments; the processor core is configured to send training instructions to the memory controller; the memory controller is configured to perform training in response to the training instructions to optimize the transmission signals of the memory.

[0020] Fourthly, embodiments of this application also provide an electronic device, including: a memory and a processor as provided in the third aspect of the embodiments above, wherein the memory is connected to a memory controller in the processor.

[0021] Fifthly, embodiments of this application also provide an electronic device, including: a processor, a memory, and a memory controller as provided in any possible implementation of the second aspect embodiments and / or in combination with the second aspect embodiments, wherein the memory controller is connected to the processor and the memory respectively; the processor is configured to send training instructions to the memory controller; and the memory controller is configured to perform training in response to the training instructions to optimize the clock signal of the memory.

[0022] Other features and advantages of this application will be set forth in the following description. The objectives and other advantages of this application can be realized and obtained through the structures specifically pointed out in the written description and the accompanying drawings. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. The above and other objects, features, and advantages of this application will become clearer through the accompanying drawings.

[0024] Figure 1 This illustration shows a schematic diagram of the connection between a PHY and a DDR memory according to an embodiment of this application.

[0025] Figure 2 A flowchart illustrating a method for optimizing the clock signal of a memory according to an embodiment of this application is shown.

[0026] Figure 3 This illustration shows a schematic diagram of the relationship between a DQS sampling clock and a DQ eye diagram provided in an embodiment of this application.

[0027] Figure 4 A timing diagram of the clkt signal, clkc signal, and DQ data provided in an embodiment of this application is shown.

[0028] Figure 5 The diagram illustrates the principle of a method for optimizing the clock signal of a memory according to an embodiment of this application.

[0029] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. The following embodiments are provided as examples to more clearly illustrate the technical solutions of this application, and should not be used to limit the scope of protection of this application. Those skilled in the art will understand that, without conflict, the following embodiments and features can be combined with each other.

[0031] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0032] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0033] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical term "connection" can be a direct connection or an indirect connection through an intermediate medium.

[0034] For ease of explanation, this application uses DDR (Double Data Rate) memory as an example. It is understood that the memory used in this application includes, but is not limited to, DDR memory, and the method shown in this application can be applied to various memories that interact with the memory controller based on DQS clock signals and DQ data signals. The DQS clock signal and DQ data signal are interaction signals between the memory and the memory controller. The DQS clock signal is the data sampling clock signal between the memory controller and the memory, used to sample the data transmitted by the DQ data signal. The DQ data signal, as the data transmission carrier, is used to transmit the actual data content.

[0035] The connection diagram between the physical layer interface (PHY) and the DDR memory is shown below. Figure 1 As shown, OB (Output Buffer) is the output driver for the clock signal CK and the command signal CA, and IB (Input Buffer) is the receiver for the CK signal and the CA command in the DDR memory. The DDR memory determines the read / write direction by parsing the CA command to control the IO (Input / Output) modules. When the CA command is a read command, the IO modules on the DDR memory side are configured in output drive mode, and the IO modules on the PHY side are configured in input mode. The DDR memory sends the DQS clock signal and the DQ data signal to the PHY. When the CA command is a write command, the IO modules on the DDR memory side are configured in input mode, and the IO modules on the PHY side are configured in output drive mode. The DDR memory receives the DQS clock signal and the DQ data signal from the PHY. In some possible implementations, the DQS clock signal is also called the DQS sampling clock, which includes the DQS_t signal and the DQS_c signal, which are differential signals.

[0036] Figure 1 The diagram only shows the signal flow when the CA command is a read command. After entering the PHY, the DQS_t and DQS_c signals pass through delay adjustment modules S003 (hereinafter referred to as S003 module) and S004 (hereinafter referred to as S004 module), respectively, and are then sent to data samplers S005 and S006 on the DQ link to sample data. The data rates of DQt and DQc are half the DQ data rate. During sampling, the rising edges of the DQS_t and DQS_c signals are used alternately to sample 1 bit of data. For example, the DQS_t signal is used to sample the 1st, 3rd, 5th, and so on bits of data, while the DQS_c signal is used to sample the 2nd, 4th, 6th, and so on bits of data.

[0037] As memory system frequency increases, the DQ eye diagram becomes smaller, and the skew between the DQS_t and DQS_c signals further deteriorates the margin of the DQ eye diagram used for DQS clock signal sampling, resulting in poorer read data stability. The skew between the DQS_t and DQS_c signals mainly originates from the following aspects: 1. The differential duty cycle of the DQS clock signal cannot reach the ideal 50%; 2. The clock links for the DQS_t and DQS_c signals are two completely independent clock links. Inevitably, mismatches exist in the physical implementation and chip manufacturing process, resulting in the clkt and clkc signals sent to the sampler FF (Flip Flop) not being strictly differential signals and exhibiting skew.

[0038] This application provides a method for optimizing the clock signal of a memory, which can eliminate the influence of skew between the DQS_t and DQS_c signals, and at the same time reduce the delay values ​​that need to be configured on the clock link, thus significantly improving the accuracy of data transmission between the memory controller and the memory. Since the delays of modules S003 and S004 are related to whether DQ data can be correctly sampled, training is required (the purpose of training is to adjust the phase of DQS to ensure that DQS can stably sample the correct DQ data). The training process for module S003 is the same as the training process for module S004. This application optimizes the memory clock signal by adjusting the delays of modules S003 and S004. The following describes the method in conjunction with... Figure 2 The method for optimizing the clock signal of a memory provided in the embodiments of this application will be described.

[0039] Step S1: Scan the delay of the clock link where the target clock signal is located, and find the first delay corresponding to the center point of the DQ eye diagram.

[0040] The target clock signal is either the first or second clock signal in the DQS clock signal set. For example, if the first clock signal is DQS_t, then the second clock signal is DQS_c; conversely, if the first clock signal is DQS_c, then the second clock signal is DQS_t. The DQ eye diagram (short for DQ eye diagram data) is the maximum eye diagram obtained by sampling the DQ data signal using the target clock signal. Ideally, the width of the DQ eye diagram is 1UI, where UI is half the clock period of either the DQS_t or DQS_c signal.

[0041] Taking the target clock signal as DQS_t as an example, when scanning the delay of the clock link where the target clock signal is located, the delay is adjusted by... Figure 1The delay of the S003 module in the diagram is adjusted, for example, sequentially in ascending order of delay. Each adjustment involves sampling DQ data until the first delay corresponding to the center point of the DQ eye diagram is found. It is understood that the "delay" in this application may also be referred to as "time delay" in some implementation scenarios.

[0042] The maximum latency supported by modules S003 and S004 is 2 UI. Modules S003 and S004 can include multiple latency units. Latency can be increased by enabling more latency units, or decreased by reducing the number of enabled latency units.

[0043] To quickly obtain the first delay of the center point of the DQ eye diagram, in one possible implementation, the process of scanning the delay of the clock link where the target clock signal is located and finding the first delay corresponding to the center point of the DQ eye diagram may include: scanning the delay of the clock link where the target clock signal is located, finding the delay corresponding to the left boundary of the DQ eye diagram, denoted as a; finding the delay corresponding to the right boundary of the DQ eye diagram, denoted as b; and then determining the first delay based on a and b. If the first delay is represented by c, then c = (a + b) / 2.

[0044] The process of sampling the DQ eye diagram using the DQS clock signal is as follows: Figure 3 As shown, the DQS sampling clock moves from left to right (with the delay gradually increasing) through the delay adjustment module. When the DQS sampling clock is outside the DQ eye diagram, the sampling data is incorrect; when the DQS sampling clock is inside the DQ eye diagram, the sampling data is correct.

[0045] Figure 1 The DQS_t, DQS_c, and DQ data signals are issued simultaneously (e.g., t0) on the DDR memory side. At data samplers S005 or S006, the link delay of the DQS_t or DQS_c signal will be greater than the DQ link delay. The timing diagram is as follows: Figure 4 As shown, the clkt signal or clkc signal will arrive at time td later than the DQ data signal. Figure 4 The DQSpreamble in the code is a DQS preamble used to initialize data transmission. During training, it needs to be... Figure 4 The DQS_t and DQS_c signals are moved forward by one cycle, so that the DQS_t and DQS_c signals are located before the DQ data signals, ensuring that the DQS_t and DQS_c signals can correctly sample the DQ data. Figure 4 The dashed arrows in the diagram represent the process of using the rising edge of the clkt signal to move from left to right to sample the left and right boundaries of the 1st bit of data (the left and right boundaries of the 1st bit of data are the DQ eye diagram).

[0046] In one possible implementation, the DQS clock signal is controlled to be issued before the DQ data signal, rather than at the same time, so that the DQS_t and DQS_c signals precede the DQ data signal. In another possible implementation, the DQS clock signal and DQ data signal are issued simultaneously, using one cycle of the DQS preamble to place the DQS_t and DQS_c signals before the DQ data signal.

[0047] Step S2: Determine whether the first delay is greater than the target delay.

[0048] The target delay is half the clock period of the target clock signal, that is, the target delay is 1UI. After obtaining the first delay, it is determined whether the first delay is greater than the target delay, that is, whether the above c=(a+b) / 2 is greater than 1UI. If the first delay is greater than the target delay, then step S3 is executed. If the first delay is not greater than the target delay, then step S5 is executed.

[0049] Step S3: Obtain the skew delay between the clock link where the first clock signal is located and the clock link where the second clock signal is located.

[0050] When the first delay is greater than the target delay, the skew delay between the clock link containing the first clock signal and the clock link containing the second clock signal is obtained. This skew delay can be obtained and stored in advance for later use, or it can be obtained in real time. For example, the skew delay between the clock link containing the first clock signal and the clock link containing the second clock signal can be obtained directly from a database.

[0051] In some possible implementations, the process of obtaining the skew delay between the clock links containing the first clock signal and the second clock signal may include: scanning the delay of the clock link containing the first clock signal to find the third delay (e.g., denoted by b) corresponding to the right boundary of the DQ eye diagram; scanning the delay of the clock link containing the second clock signal to find the fourth delay (e.g., denoted by h) corresponding to the right boundary of the DQ eye diagram; and determining the skew delay based on the third delay, the fourth delay, and the target delay. Assuming the sampling clock signal uses the first clock signal as the starting data (the 1st bit of data), the phase difference between the rising edges of the first and second clock signals can be calculated as g = bh. If the sampling clock signal uses the second clock signal as the starting data (the 1st bit of data), then g = hb. Since ideally, the phase difference between the rising edges of the first and second clock signals is 1UI, the skew delay skew = g - 1UI. By scanning the sampling boundary of the same DQ eye diagram using differential clocks, the skew effect between differential clocks can be eliminated.

[0052] Step S4: Determine the delay of the second clock signal or the clock link where the first clock signal is located based on the first delay, the target delay, and the skew delay.

[0053] After obtaining the skew delay, the delay of the second clock signal or the clock link where the first clock signal is located can be determined based on the first delay, the target delay, and the skew delay.

[0054] In one possible implementation, the process of determining the delay of the second clock signal or the clock link containing the first clock signal based on the first delay, the target delay, and the skew delay may include: determining the second delay based on the first delay (e.g., denoted by c), the target delay (e.g., 1UI), and the skew delay (e.g., skew); if the target clock signal is the first clock signal, and the second delay is greater than a preset threshold (e.g., 0), then the delay of the clock link containing the second clock signal is determined to be the second delay, and the second clock signal is used as the sampling clock signal for the initial data. For example, if the second delay is denoted by e, then e = c - 1UI - skew. If the target clock signal is the first clock signal, and e is greater than 0, then the delay of the clock link containing the second clock signal is determined to be the second delay, and after training, the second clock signal will be used as the sampling clock signal for the initial data. By switching the differential clock edge of the sampling start data, the delay value that needs to be configured on the clock link is reduced, thereby reducing the power consumption on the clock link and enhancing the pit noise capability of the clock link.

[0055] In one possible implementation, the process of determining the delay of the second clock signal or the clock link where the first clock signal is located based on the first delay, the target delay, and the skew delay further includes: if the second delay is not greater than a preset threshold, obtaining the jitter error (e.g., denoted by f) of the clock link where the target clock signal is located; if the jitter error is not less than the absolute value of the second delay, determining the delay of the clock link where the second clock signal is located as the preset threshold, and using the second clock signal as the sampling clock signal for the initial data; if the jitter error is less than the absolute value of the second delay, determining the delay of the clock link where the first clock signal is located as the first delay. For example, if the target clock signal is the first clock signal, and if e is less than or equal to 0, then f is obtained; if f ≥ |e|, then the delay of the clock link where the second clock signal is located is determined to be 0, and the second clock signal is used as the sampling clock signal for the initial data; conversely, if f < |e|, then the delay of the clock link where the first clock signal is located is determined to be c, and the first clock signal is still used as the sampling clock signal for the initial data thereafter.

[0056] The jitter error can be acquired and stored in advance for later use, or it can be acquired in real time. For example, the jitter error can be retrieved directly from a database.

[0057] In one possible implementation, the process of obtaining the jitter error of the clock link containing the target clock signal may include: obtaining the first jitter time of the clock signal output when the delay of the clock link containing the target clock signal is a first fixed delay; obtaining the second jitter time of the clock signal output when the delay of the clock link containing the target clock signal is a second fixed delay; and obtaining the difference between the first jitter time and the second jitter time to obtain the jitter error. For example, jitter error = first jitter time - second jitter time. The larger the delay of the link, the more susceptible the signal is to noise, and the longer its jitter time. Here, the jitter time is the deviation of the rising edge of the signal from the ideal time position. The first fixed delay is greater than the second fixed delay, and the value range of the first fixed delay and the second fixed delay can be [0, 2UI]. For example, in one possible implementation, the first fixed delay is 1UI, and the second fixed delay is 0 delay.

[0058] The delay training process for the clock link containing the DQS_t signal (the link where the S003 module is located) is the same as the delay training process for the clock link containing the DQS_c signal (the link where the S004 module is located). The jitter error obtained during the delay training process of the DQS_t signal link can be reused. For example, if it is also necessary to obtain the jitter error of the clock link containing the target clock signal during the delay training process of the DQS_c signal link, the jitter error obtained during the delay training process of the DQS_t signal link can be directly reused. Of course, it can also be obtained again using the method described above.

[0059] Step S5: Determine the delay of the clock link where the target clock signal is located as the first delay.

[0060] In this application, the delay of the clock link containing the target clock signal is determined as the first delay only if the first delay is not greater than the target delay; otherwise, step S3 is executed as described above. If the delays of modules S003 and S004 are directly configured as the first delay (greater than 1 UI), it means that more delay units need to be enabled. Due to the increased number of delay units, the power consumption on the clock link will increase. Simultaneously, each delay unit contributes noise to the link; the longer the link delay, the worse the noise performance, and the poorer the noise immunity of the entire clock link. Decreased clock performance leads to decreased stability of the clock sampling data, ultimately reducing the performance of the entire memory system, such as requiring the memory to operate at a lower frequency. Using the method of this application, the delay on the configured clock link can be reduced to decrease clock link power consumption and improve the noise immunity of the clock link, thereby improving the stability and accuracy of data transmission.

[0061] During training, it is necessary to use the target clock signal as both the first and second clock signals. Figure 2The training is illustrated below. To better understand the above principles, an example is provided below, focusing on the delay of the clock link where the DQS_t signal resides (the link where the S003 module is located). Borrowing one cycle from the DQS_t and DQS_c signals, we begin scanning the delay value of the S003 module on the clock link where the DQS_t signal resides. We record the delay values ​​a and b when the left and right boundaries of the DQ eye diagram are found, respectively. Based on the scan results, we calculate the phase shift of the DQS_t signal to the center point of the DQ eye diagram. The delay value that needs to be configured for the S003 module is c = (b + a) / 2. We then determine whether the delay value to be configured for the S003 module is greater than 1UI, i.e., whether d = c - 1UI is greater than 0. If d is less than or equal to 0, the delay of the S003 module is subsequently configured to delay c, and the training ends.

[0062] If d is greater than 0, then start scanning the delay value of the S004 module on the clock link where the DQS_c signal is located, and record the delay value h when the right boundary of the DQ eye diagram is found. Taking the right boundary of the DQ eye diagram as a fixed point, the phase difference g=bh between the rising edges of the DQS_t signal and the DQS_c signal can be calculated. Ideally, the rising edge of the DQS_c signal will be 1UI slower than the DQS_t signal. Therefore, the skew of the rising edges of the DQS_t signal and the DQS_c signal is bh-1UI (this step can also be done earlier). Calculate whether e=c-1UI-skew is greater than 0. If e is greater than 0, then the delay of the S004 module is configured to be delayed by e, and the DQS_c signal is used as the sampling clock signal for the starting data, ending the training.

[0063] If e is less than or equal to 0, since the S004 or S003 module cannot achieve negative delay, further judgment is needed. If f ≥ |e|, then the DQS_c signal is used to sample the starting data in subsequent iterations, and the delay of the S004 module is configured to be 0. At this time, the theoretical margin loss of the DQ eye diagram sampled by the DQS_c signal is |e| (e < 0). If f < |e|, then the starting data is not sampled in a different step, and the DQS_t signal is used to sample the starting data in subsequent iterations. The delay of the S003 module is configured to be c. At this time, the theoretical margin loss of the DQ eye diagram sampled by the DQS_t signal is f, and the training ends.

[0064] The delay training process for the link containing the DQS_c signal is the same as that for the link containing the DQS_t signal. This ensures that the delay values ​​configured for the S003 / S004 modules are relatively small, significantly optimizing power consumption and noise performance on the clock link. Furthermore, it eliminates the skew between the DQS_t and DQS_c signals, further improving the stability of the DQS sampled DQ data.

[0065] It should be noted that the delays of modules S004 or S003, determined during the delay training of the link containing the DQS_t signal, are temporarily stored. After the delay training of the link containing the DQS_c signal is completed, these previously determined delays are then configured for modules S004 and S003, and their delays are not adjusted subsequently. Similarly, the edge-switching sampling described above also only occurs after training is complete and normal operation begins.

[0066] This application also provides a memory controller, which can receive training instructions sent by a processor (or processor core) and execute training in response to the training instructions to optimize the clock signal of the memory. The memory controller includes a delay adjustment module and a control module, which are connected to the delay adjustment module. Delay training is completed through the delay adjustment module and the control module.

[0067] The delay adjustment module can be two, located on the clock links of the first clock signal and the second clock signal in the DQS clock signal, respectively, and is used to adjust the delay of the first clock signal and the second clock signal.

[0068] The control module is used to scan the delay of the clock link where the target clock signal is located, find the first delay corresponding to the center point of the DQ eye diagram; if the first delay is greater than the target delay, obtain the skew delay between the clock link where the first clock signal is located and the clock link where the second clock signal is located; and determine the delay of the second clock signal or the clock link where the first clock signal is located based on the first delay, the target delay, and the skew delay.

[0069] The control module is specifically used to: determine the second delay based on the first delay, the target delay, and the skew delay; if the second delay is greater than a preset threshold when the target clock signal is the first clock signal, determine the delay of the clock link where the second clock signal is located as the second delay, and use the second clock signal as the sampling clock signal for the starting data.

[0070] The control module is also specifically used for: if the second delay is not greater than a preset threshold, obtaining the jitter error of the clock link where the target clock signal is located; if the jitter error is not less than the absolute value of the second delay, determining the delay of the clock link where the second clock signal is located as the preset threshold, and using the second clock signal as the sampling clock signal for the starting data; if the jitter error is less than the absolute value of the second delay, determining the delay of the clock link where the first clock signal is located as the first delay.

[0071] In one possible implementation, when the control module obtains the skew delay between the clock link where the first clock signal is located and the clock link where the second clock signal is located, it specifically performs the following steps: scanning the delay of the clock link where the first clock signal is located to find the third delay corresponding to the right boundary of the DQ eye diagram; scanning the delay of the clock link where the second clock signal is located to find the fourth delay corresponding to the right boundary of the DQ eye diagram; and determining the skew delay based on the third delay, the fourth delay, and the target delay.

[0072] In one possible implementation, when the control module obtains the jitter error of the clock link where the target clock signal is located, it specifically performs the following steps: obtaining the first jitter time of the clock signal output when the delay of the clock link where the target clock signal is located is a first fixed delay; obtaining the second jitter time of the clock signal output when the delay of the clock link where the target clock signal is located is a second fixed delay; and obtaining the difference between the first jitter time and the second jitter time to obtain the jitter error.

[0073] The implementation principle and technical effects provided by the memory controller embodiment are the same as those of the aforementioned method embodiment. For the sake of brevity, any parts not mentioned in the memory controller embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0074] This application also provides a processor, which includes a processor core and the aforementioned memory controller. In this embodiment, the memory controller is integrated into the processor. In some implementations, the processor and the memory controller may be parallel devices rather than being inclusive.

[0075] The processor core is used to send training instructions to the memory controller; the memory controller is used to execute training in response to the training instructions, thereby executing the above-described method for optimizing the clock signals of the memory.

[0076] Based on the same inventive concept, this application also provides an electronic device, which includes a memory and a processor. The memory is connected to a memory controller in the processor. In this case, the processor core in the processor is used to send training instructions to the memory controller; the memory controller is used to execute training in response to the training instructions, thereby executing the above-mentioned method for optimizing the clock signal of the memory.

[0077] In one embodiment, when the memory controller is no longer integrated into the processor, the electronic device includes: a processor, a memory, and the aforementioned memory controller, wherein the memory controller is connected to both the processor and the memory; the processor is configured to send training instructions to the memory controller; and the memory controller is configured to execute training in response to the training instructions, thereby executing the aforementioned method for optimizing the clock signal of the memory.

[0078] In some possible implementations, the memory described above may be RAM, and the memory controller described above may be a memory controller.

[0079] In one implementation, such as Figure 6 As shown, the electronic device includes: a transceiver, a memory, a communication bus, and a processor. The transceiver, memory, and processor are electrically connected directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected through one or more communication buses or signal lines. The transceiver is used to send and receive data. The memory stores computer programs, including at least one software functional module that can be stored in the memory as software or firmware or embedded in the operating system (OS) of the electronic device. The processor executes the software functional module or computer program stored in the memory. For example, the processor executes the aforementioned method for optimizing the clock signals of the memory.

[0080] The memory may be, but is not limited to, Random Access Memory (RAM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), etc.

[0081] The processor may be an integrated circuit chip with signal processing capabilities. The aforementioned processor can be a general-purpose processor, including a Central Processing Unit (CPU), Network Processor (NP), Graphics Processing Unit (GPU), Accelerated Processing Unit (ACCU), Multimedia Application Processor (MAP), microprocessor, etc.; it can also be a Digital Signal Processor (DSP), Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. Alternatively, the processor can be any conventional processor.

[0082] The aforementioned electronic devices include, but are not limited to, smartphones, tablets, servers, base stations, smart cameras, and autonomous vehicles.

[0083] This application also provides a non-volatile computer-readable storage medium (hereinafter referred to as the storage medium) storing a computer program, which, when run by a computer such as the electronic device described above, executes the method described above for optimizing the clock signal of the memory.

[0084] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0085] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0086] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0087] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a computer-readable storage medium and includes several instructions to cause a computer device (which may be a personal computer, laptop, server, or electronic device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned computer-readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0088] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for optimizing the clock signal of a memory, characterized in that, include: Scan the delay of the clock link where the target clock signal is located to find the first delay corresponding to the center point of the DQ eye diagram; wherein, the DQ eye diagram is the maximum eye diagram obtained by sampling the DQ data signal with the target clock signal; the target clock signal is the first clock signal in the DQS clock signal; If the first delay is greater than the target delay, the skew delay between the clock link where the first clock signal is located and the clock link where the second clock signal in the DQS clock signal is located is obtained; wherein, the target delay is half of the clock period of the target clock signal; The delay of the second clock signal or the clock link containing the first clock signal is determined based on the first delay, the target delay, and the skew delay. Determining the delay of the second clock signal or the clock link containing the first clock signal based on the first delay, the target delay, and the skew delay includes: The second delay is determined based on the first delay, the target delay, and the skew delay; If the second delay is greater than a preset threshold, the delay of the clock link where the second clock signal is located is determined to be the second delay, and the second clock signal is used as the sampling clock signal for the starting data.

2. The method according to claim 1, characterized in that, The method further includes: If the second delay is not greater than the preset threshold, the jitter error of the clock link where the target clock signal is located is obtained; If the jitter error is not less than the absolute value of the second delay, the delay of the clock link where the second clock signal is located is determined to be the preset threshold, and the second clock signal is used as the sampling clock signal for the starting data; If the jitter error is less than the absolute value of the second delay, the delay of the clock link where the first clock signal is located is determined to be the first delay.

3. The method according to claim 1, characterized in that, Obtaining the skew delay between the clock link containing the first clock signal and the clock link containing the second clock signal includes: Scan the delay of the clock link where the first clock signal is located to find the third delay corresponding to the right boundary of the DQ eye diagram; Scan the delay of the clock link where the second clock signal is located to find the fourth delay corresponding to the right boundary of the DQ eye diagram; The skew delay is determined based on the third delay, the fourth delay, and the target delay.

4. The method according to claim 2, characterized in that, Obtaining the jitter error of the clock link where the target clock signal is located includes: The first jitter time of the clock signal output when the delay of the clock link where the target clock signal is located is the first fixed delay is obtained; The second jitter time of the clock signal output when the delay of the clock link where the target clock signal is located is the second fixed delay; The difference between the first jitter time and the second jitter time is obtained to obtain the jitter error.

5. The method according to claim 1, characterized in that, The method further includes: If the first delay is not greater than the target delay, the delay of the clock link where the target clock signal is located is determined to be the first delay.

6. A memory controller, characterized in that, include: The delay adjustment module is located on the clock link where the first clock signal and the second clock signal are located in the DQS clock signal, and is used to adjust the delay of the first clock signal and the second clock signal; The control module, connected to the delay adjustment module, is used to scan the delay of the clock link where the target clock signal is located and find the first delay corresponding to the center point of the DQ eye diagram. If the first delay is greater than the target delay, obtain the skew delay between the clock link where the first clock signal is located and the clock link where the second clock signal is located; determine the delay of the second clock signal or the clock link where the first clock signal is located based on the first delay, the target delay, and the skew delay; Wherein, the DQ eye diagram is the maximum eye diagram obtained by sampling the DQ data signal with the target clock signal; The target clock signal is the first clock signal in the DQS clock signal; the target delay is half the clock period of the target clock signal; The control module is specifically used for: The second delay is determined based on the first delay, the target delay, and the skew delay; If the second delay is greater than a preset threshold, the delay of the clock link where the second clock signal is located is determined to be the second delay, and the second clock signal is used as the sampling clock signal for the starting data.

7. The memory controller according to claim 6, characterized in that, The control module is also specifically used for: If the second delay is not greater than the preset threshold, the jitter error of the clock link where the target clock signal is located is obtained; If the jitter error is not less than the absolute value of the second delay, the delay of the clock link where the second clock signal is located is determined to be the preset threshold, and the second clock signal is used as the sampling clock signal for the starting data; If the jitter error is less than the absolute value of the second delay, the delay of the clock link where the first clock signal is located is determined to be the first delay.

8. A processor, characterized in that, include: The processor core and the memory controller as described in any one of claims 6-7; The processor core is used to send training instructions to the memory controller; The memory controller is configured to execute training in response to the training instructions to optimize the transmission signals of the memory.

9. An electronic device, characterized in that, include: The memory and the processor as described in claim 8, wherein the memory is connected to a memory controller in the processor.

10. An electronic device, characterized in that, include: A processor, a memory, and a memory controller as described in any one of claims 6-7, wherein the memory controller is connected to the processor and the memory, respectively. The processor is used to send training instructions to the memory controller; The memory controller is configured to execute training in response to the training instructions to optimize the memory clock signal.

Images