Transistor device and method of manufacturing the same, integrated circuit

Abstract

The application provides a transistor device and a manufacturing method thereof, and an integrated circuit. The transistor device comprises a first substrate 1, a cold field electron emission unit arranged on one side of a first main surface of the first substrate, the cold field electron emission unit comprising an electron acceleration layer 4, a high-potential emitter 7 and a low-potential electrode 12, a gate 10 arranged on the one side of the first main surface, and a back electrode metal film 11 at least partially arranged in a through hole of the first substrate and exposed from a second main surface, in a longitudinal direction perpendicular to the first main surface of the first substrate, the electron acceleration layer 4 is located between the high-potential emitter 7 and the low-potential electrode 12, and the high-potential emitter 7 is located between the gate 10 and the electron acceleration layer 4; a second substrate 20, an electron collector 26 arranged on one side of a first main surface of the second substrate, the electron collector 26 being electrically connected to a wiring 23 arranged on one side of a second main surface of the second substrate through a through hole electrode in the second substrate, and the first main surface of the first substrate 1 being hermetically bonded to the first main surface of the second substrate 20.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a transistor device and its manufacturing method, and an integrated circuit. Background Technology

[0002] The further development of the large-scale integrated circuit industry demands minimizing device feature sizes and improving performance. Currently, transistor feature sizes have reached below 10nm. Such small feature sizes present significant difficulties and challenges to CMOS manufacturing processes. To overcome these limitations of traditional CMOS processes, researchers are continuously improving device structures and exploring new material transistors, such as III-V semiconductor channel transistors, carbon nanotube channel transistors, and graphene channel transistors. Researchers are also actively developing devices based on new operating principles, such as tunneling field-effect transistors, nano-vacuum channel transistors, and spin transistors. Among these, the nano-vacuum transistor is a novel transistor that integrates vacuum tube technology with modern nanoscale semiconductor technology. Traditional vacuum tubes primarily operate through thermionic emission, emitting electrons into the surrounding vacuum by heating the cathode, which often requires extremely high operating voltages and power consumption. Using modern nanofabrication technology, vacuum channel transistors can be made at the nanometer scale. At such a small size, only a small voltage is needed between the cathode and anode to achieve an extremely high electric field. Under this high electric field, cathode electrons fly towards the anode through field emission. Simultaneously, applying a gate voltage near the cathode can regulate the emission current, thus realizing the transistor function.

[0003] Nanoscale vacuum transistors offer performance advantages over other transistors. Firstly, under vacuum conditions, electrons emitted from the cathode reach the anode via ballistic transport, without collisions or scattering, and their maximum velocity is 3 × 10⁻⁶. 10 cm / s, while the highest electron transport rate in semiconductors is 10 cm / s. 7 The speed is on the order of cm / s, so theoretically, nano-vacuum transistors are much faster than silicon nano-semiconductor devices. Secondly, the mean free path of electrons in air is about 200 nm. Therefore, if the distance between the cathode and anode is reduced to below 200 nm, the probability of electrons emitted from the cathode colliding with air molecules decreases. This means that nano-vacuum transistors also hold promise for high-speed operation in air environments. Furthermore, since nano-vacuum transistors operate based on the field emission principle, their performance is very stable in extreme environments, such as high temperatures and high radiation. In contrast, semiconductor devices suffer from threshold voltage drift and leakage current surges in high-temperature environments due to phonon scattering and heat leakage, and can be permanently damaged in high-radiation environments. Therefore, nano-vacuum transistors have great potential applications in the aerospace field.

[0004] Furthermore, in nano-vacuum transistors, the environment for electron emission can be a vacuum or filled with a predetermined gas.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] Existing vacuum transistor structures are divided into, such as Figure 1 The vertical and horizontal structures are shown. In Figure 1 In the diagram: 51 represents the substrate or cathode, 52 represents the tip, 53 represents the insulating layer, 54 represents the metal gate, 55 represents the insulating layer, 56 represents the metal anode, 57 represents the cavity, 61 represents the silicon substrate or back gate, 62 represents the insulating layer, 63 represents silicon or cathode, 64 represents silicon or anode, and 65 represents the gap between the cathode and anode. Figure 1 In this context, 'e' represents an electron.

[0007] like Figure 1 The tip in the needle-type vertical structure shown in (a) can be fabricated using diamond, metal, or silicon. However, it is difficult to fabricate a tip with consistent height and radius of curvature, and it is also difficult to control the distance between the tip and the anode. Furthermore, the needle-tip structure is prone to abnormal discharge, leading to unstable emission current and breakdown damage. Therefore, the performance stability of vertical structure devices is very poor. Although... Figure 1 The back-gate lateral structure shown in (b) is advantageous for integration, but the fabrication and uniformity control of the nanoscale gap between the cathode and anode, as well as the fabrication of the gate surrounding this gap, are difficult to achieve. Furthermore, in the lateral structure, electron emission causes continuous changes in the gap between the cathode and anode, leading to performance degradation. In summary, existing vacuum transistors are still in the research and development stage, and stable device fabrication processes, stable device performance, and practical applications have not yet been achieved.

[0008] Porous silicon prepared using photoelectrochemical etching methods can be applied to the fabrication of electron sources. For example, cold field emission electron sources can be fabricated using single-crystal silicon or columnar polycrystalline silicon materials. Figure 2 It is a porous silicon electron source structure and a voltage V applied across the porous silicon electron source structure. PSThe energy band diagram is shown. When a voltage Vps is applied across the electron source device, hot electrons are injected from the N-type silicon substrate into the broadband porous silicon region. The injected electrons are continuously accelerated by the electric field, reaching the top gold (Au) thin film via a quasi-ballistic transport mechanism, and then tunneling through the Au thin film into the vacuum. This is the cold field electron emission current. Therefore, porous silicon electron source devices have the characteristics of high electron collimation, concentrated energy, and stable emission current.

[0009] The inventors discovered that existing technologies lack the ability to integrate a cold field electron emitter (FEE) unit with a vacuum transistor. Integrating the two would allow for the full utilization of the advantages of both. Therefore, how to integrate the FEE unit with the vacuum transistor became a problem that needed to be solved.

[0010] To address the aforementioned problems or at least similar issues, embodiments of this application provide a transistor device and its manufacturing method, as well as an integrated circuit. A planar cold field electron emission unit, gate, and collector are formed within the same cavity, enabling the integration of the cold field electron emission unit with the structure of a vacuum transistor, fully leveraging the advantages of both. Furthermore, this transistor device is easily manufactured using microelectromechanical systems (MEMS) technology.

[0011] According to one aspect of the embodiments of this application, a transistor device is provided, the transistor device comprising:

[0012] A first substrate (1) has a cold field electron emission unit disposed on one side of a first main surface. The cold field electron emission unit includes an electron acceleration layer (4), a high-potential emitter (7), and a low-potential electrode (12). A gate (10) is also disposed on one side of the first main surface of the first substrate. A back electrode metal film (11) is disposed on one side of a second main surface of the first substrate. In the longitudinal direction perpendicular to the first main surface of the first substrate, the electron acceleration layer (4) is located between the high-potential emitter (7) and the low-potential electrode (12), and the high-potential emitter (7) is located between the gate (10) and the electron acceleration layer (4). The resistivity of the first substrate (1) is higher than a first predetermined value. The low-potential electrode (12) is electrically connected to the back electrode metal film (11) through a through-hole in the first substrate. The back electrode metal film (11) is at least partially disposed in the through-hole and exposed from the second main surface of the first substrate (1).

[0013] The second substrate (20) has an electron collecting electrode (26) disposed on one side of the first main surface of the second substrate. The electron collecting electrode (26) is electrically connected to the wiring (23) disposed on one side of the second main surface of the second substrate through a through-hole electrode in the second substrate.

[0014] The first main surface of the first substrate (1) is hermetically bonded to the first main surface of the second substrate (20).

[0015] In the transverse direction perpendicular to the longitudinal direction, the electron collecting electrode (26) is at least partially opposite to the high-potential emitting electrode (7).

[0016] In the longitudinal direction, a closed cavity (30) is formed between the electron collecting electrode (26) and the high-potential emitting electrode (7), and the gate electrode (10) is at least partially located within the cavity (30).

[0017] According to another aspect of the embodiments of this application, a method for manufacturing a transistor device is provided, the method comprising:

[0018] A cold field electron emission unit and a gate (10) are formed on one side of the first main surface of the first substrate (1). The cold field electron emission unit includes an electron acceleration layer (4), a high-potential emitter (7), and a low-potential electrode (12). A back electrode metal film (11) is disposed on one side of the second main surface of the first substrate. In the longitudinal direction perpendicular to the first main surface of the first substrate, the electron acceleration layer (4) is located between the high-potential emitter (7) and the low-potential electrode (12). The high-potential emitter (7) is located between the gate (10) and the electron acceleration layer (4). The resistivity of the first substrate (1) is higher than a first predetermined value. The low-potential electrode (12) is electrically connected to the back electrode metal film (11) through a through hole in the first substrate. The back electrode metal film (11) is at least partially disposed in the through hole and exposed from the second main surface of the first substrate (1).

[0019] An electron collector (26) is formed on one side of the first main surface of the second substrate (20), and the electron collector (26) is electrically connected to a wiring (23) disposed on one side of the second main surface of the second substrate through a through-hole electrode in the second substrate; and

[0020] The first main surface of the first substrate (1) is hermetically bonded to the first main surface of the second substrate (20).

[0021] In the transverse direction perpendicular to the longitudinal direction, the electron collecting electrode (26) and the high-potential emitting electrode (7) are at least partially opposed to each other. In the longitudinal direction, a closed cavity (30) is formed between the electron collecting electrode (26) and the high-potential emitting electrode (7), and the gate electrode (10) is at least partially located within the cavity (30).

[0022] The advantages of this application are: forming a planar cold field electron emission unit, gate, and collector within the same cavity allows for the integration of the cold field electron emission unit with the structure of a vacuum transistor, fully leveraging the advantages of both. Furthermore, it facilitates the fabrication of this transistor device using microelectromechanical systems (MEMS) technology.

[0023] Specific embodiments of this application are disclosed in detail with reference to the following description and accompanying drawings, indicating how the principles of this application can be adopted. It should be understood that the embodiments of this application are not limited in scope. Within the spirit and scope of the appended claims, embodiments of this application include many changes, modifications, and equivalents.

[0024] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0025] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components. Attached Figure Description

[0026] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without creative effort. In the drawings:

[0027] Figure 1 This is a schematic diagram of an existing vacuum transistor structure;

[0028] Figure 2 It shows the structure of a porous silicon electronic source and the energy band diagram when a voltage is applied across the porous silicon electronic source structure.

[0029] Figure 3 This is a schematic diagram of the transistor device of this application;

[0030] Figure 4 This is a schematic diagram of a method for manufacturing the transistor device of this application;

[0031] Figures 5 to 42 This is a schematic diagram of the device structure for each step of the manufacturing method of transistor device 100. Detailed Implementation

[0032] Referring to the accompanying drawings, the foregoing and other features of this application will become apparent from the following description. Specific embodiments of this application are specifically disclosed in the description and drawings, illustrating partial implementations in which the principles of this application may be employed. It should be understood that this application is not limited to the described embodiments; rather, it includes all modifications, variations, and equivalents falling within the scope of the appended claims.

[0033] In the description of the various embodiments of this application, for ease of description, the direction parallel to the first main surface of the first substrate or the first main surface of the second substrate is referred to as the "lateral direction", and the direction perpendicular to the first main surface of the first substrate or the first main surface of the second substrate is referred to as the "longitudinal direction". The dimension in the "longitudinal direction" can be referred to as the "height" or "thickness". In the "longitudinal direction", the direction from the first main surface of the first substrate to the first main surface of the second substrate is referred to as the "up" direction, and the opposite direction to the "up" direction is referred to as the "down" direction.

[0034] It should be noted that the "up" and "down" directions mentioned above are for illustrative purposes only and do not limit the orientation or posture of the transistor device in this application during manufacturing or use.

[0035] This application provides a transistor device.

[0036] Figure 3 This is a schematic diagram of the transistor device of this application. Figure 3 As shown, the transistor device 100 includes a first substrate 1 and a second substrate 20. The resistivity of the first substrate 1 is higher than a first predetermined value. For example, the resistivity of the first substrate 1 of the transistor device 100 is higher than 5000 Ω*cm. In a specific example, the first substrate 1 of the transistor device 100b is a high-resistivity P-type (100) silicon substrate. The second substrate 20 may be an insulating substrate, such as a glass substrate, a silicon substrate, or other materials.

[0037] A cold field electron emission unit is disposed on one side of the first main surface (e.g., the upper surface) of the first substrate 1. The cold field electron emission unit includes an electron accelerating layer 4, a high-potential emitter 7, and a low-potential electrode 12. The high-potential emitter 7 is a conductive thin film with a thickness of 0.1 nm to 10 nm. The material of the conductive thin film is one or more of metal, conductive compound, and conductive two-dimensional material. The high-potential emitter 7 can also be referred to as a high-potential emitter conductive thin film 7.

[0038] A gate 10 is also disposed on one side of the first main surface of the first substrate 1. The gate 10 can be a metal thin film, so the gate 10 can also be referred to as a gate metal thin film 10. In addition, the gate 10 can also be made of other conductive materials.

[0039] A back electrode metal film 11 is provided on one side of the second main surface (e.g., the lower surface) of the first substrate 1. In the transistor device 100, a low-potential electrode 12 is electrically connected to the back electrode metal film 11 through a through hole in the first substrate 1, wherein the back electrode metal film 11 is at least partially disposed in the through hole and exposed from the second main surface (i.e., the lower surface) of the first substrate 1.

[0040] In the longitudinal direction perpendicular to the first main surface of the first substrate 1, the electron acceleration layer 4 is located between the high-potential emitter 7 and the low-potential electrode 12, and the high-potential emitter 7 is located between the gate 10 and the electron acceleration layer 4.

[0041] An electron collector 26 is disposed on one side of the first main surface (e.g., the lower surface) of the second substrate 20. The electron collector 26 is electrically connected to a wiring 23 disposed on one side of the second main surface (e.g., the upper surface) of the second substrate 20 via a through-hole electrode 21. The electron collector 26 can be a thin film; therefore, it can also be referred to as the bottom electron collector redistribution metal thin film 26. The wiring 23 can also be a metal thin film; therefore, it can also be referred to as the top electron collector redistribution metal thin film 23.

[0042] In the transverse direction perpendicular to this longitudinal direction, the electron collecting electrode 26 is at least partially opposite to the high-potential emitting electrode 7.

[0043] In this application, the first main surface of the first substrate 1 is hermetically bonded to the first main surface of the second substrate 20.

[0044] In the vertical direction, a sealed cavity 30 is formed between the electron collecting electrode 26 and the high-potential emitter 7, and the gate electrode 10 is at least partially located within the cavity 30. The cavity 30 is either a vacuum or filled with a predetermined gas at a predetermined pressure.

[0045] In this application, electrons emitted from the high-potential emitter 7 pass through the cavity 30 and are collected by the electron collecting electrode 26.

[0046] In this application, the distance between the gate 10 and the surface of the high-potential emitter 7 in the vertical direction is 10 nm to 10 μm. In the horizontal direction, the gate 10 has an open structure to form an electron emission path along the vertical direction.

[0047] In this vertical direction, there is a gap between the electron collecting electrode 26 and the gate electrode 10, and the height of the gap is greater than or equal to 2 nm.

[0048] In at least one embodiment of this application, at least one of the high-potential emitter 7, the electron collector 26, and the gate 10 has a patterned structure that forms an electrical signal path between the cavity and the external environment.

[0049] like Figure 3 As shown, the second substrate 20 also has a gate metal contact structure 28 and an emitter metal contact structure 29 on one side of the first main surface.

[0050] The gate metal contact structure 28 is electrically connected to the gate 10. The gate metal contact structure 28 can be elastic and can be compressed and deformed in the longitudinal direction. For example, it can be a spring sheet structure that protrudes downward. Therefore, the gate metal contact structure 28 can be referred to as a miniature spring metal contact for gate bonding.

[0051] The emitter metal contact structure 29 is electrically connected to the high-potential emitter 7. For example, in Figure 3 In the process, the high-potential emitter 7 contacts the emitter lead metal film 6, the emitter lead metal film 6 contacts the emitter metal lead 9, and the emitter metal lead 9 contacts the emitter metal contact structure 29. The emitter metal contact structure 29 can be elastic and can be compressed and deformed in the longitudinal direction. For example, it can be a spring sheet structure with a downward protrusion. Therefore, the emitter metal contact structure 29 can be referred to as a miniature spring metal contact 29 for emitter bonding.

[0052] like Figure 3 As shown, the gate metal contact structure 28 and the emitter metal contact structure 29 are electrically connected to wirings 22 and 24 disposed on one side of the second main surface of the second substrate 20 through through-hole electrodes 21 in the second substrate 20. Wirings 22 and 24 can be metal thin films. Therefore, wiring 22 can also be referred to as top gate redistribution metal thin film 22, and wiring 24 can also be referred to as top emitter redistribution metal thin film 24.

[0053] In addition, such as Figure 3 As shown, the gate metal contact structure 28 can be electrically connected to the via electrode 21 through the bottom gate redistribution metal film 25, and the emitter metal contact structure 29 can be electrically connected to the via electrode 21 through the bottom emitter redistribution metal film 27.

[0054] In addition, Figure 3 In the transistor device 100, there may also be: an undoped columnar polycrystalline silicon thin film 2, a first insulating material (e.g., silicon nitride) thin film 3, an emitter insulating film 5, a second insulating material (e.g., silicon nitride) thin film 8, and a high-resistivity region 13.

[0055] In addition, the transistor device 100 also has an oxide layer 14 and a high-concentration N-type polysilicon 15, with the low-potential electrode 12 located in the high-concentration N-type polysilicon 15.

[0056] The electron accelerator layer 4 will now be explained.

[0057] The thickness of the electron accelerator layer 4 in this application is, for example, 0.1 μm to 5 μm.

[0058] The electron accelerator layer 4 may comprise multiple semiconductor grains (e.g., nano-silicon grains) with a characteristic size of 2 nm to 50 nm. An insulating medium of predetermined thickness is disposed between adjacent semiconductor grains. The insulating medium may be one or more of silicon oxide (e.g., SiO2), compound materials, wide bandgap semiconductors, and voids.

[0059] The predetermined thickness of the insulating medium is 0.3 nm to 8 nm. Under the isolation effect of the insulating medium, the semiconductor grains in the electron accelerating layer 4 exhibit a semiconductor grain chain structure with an insulating layer. The two ends of the semiconductor grain chain structure are close to the low-potential electrode 12 and the high-potential emitter 7, respectively, that is, the semiconductor grain chain extends longitudinally.

[0060] The working principle of the collective tube device 100 in this application is as follows.

[0061] When a voltage V is applied between the top emitter redistribution metal film 24 and the back electrode metal film 11 PS When the top emitter redistribution metal film 24 is connected to a positive voltage and the back electrode metal film 11 is grounded or connected to a negative voltage, electrons e (e.g., hot electrons) are injected from the first substrate 1 into the high-resistivity region 13 through the low-potential electrode 12. Under the influence of the electric field, the electrons are transported to the electron acceleration layer 4, where they are accelerated by the electric field and transported to the high-potential emitter conductive film 7 via a quasi-ballistic transport mechanism. They then tunnel through this conductive film 7 and are emitted into the cavity 30. A voltage V is applied to the gate 10 through the top gate redistribution metal film 22. G This allows control over the number of electrons emitted into cavity 30 that reach the bottom collector rewire metal film 26, thus controlling the collector current.

[0062] Since the transistor device 100 of this application is based on the planar field emission mechanism for ballistic electron emission, the emitted electrons have small color difference in energy, stable performance, and long service life. In addition, the transistor device 100 can be manufactured using MEMS technology, resulting in good uniformity between devices, small size, and integration capability.

[0063] This application also provides an integrated circuit, which may include at least one transistor device 100.

[0064] This application also provides a method for manufacturing a transistor device, for manufacturing a transistor device 100.

[0065] Figure 4 This is a schematic diagram of the manufacturing method of the transistor device, as shown below. Figure 4As shown, the manufacturing method includes:

[0066] 401. A cold field electron emission unit and a gate 10 are formed on one side of the first main surface of the first substrate 1. The cold field electron emission unit includes an electron acceleration layer 4, a high-potential emitter 7, and a low-potential electrode 12. A back electrode metal film 11 is disposed on one side of the second main surface of the first substrate. In the longitudinal direction perpendicular to the first main surface of the first substrate, the electron acceleration layer 4 is located between the high-potential emitter 7 and the low-potential electrode 12. The high-potential emitter 7 is located between the gate 10 and the electron acceleration layer 4. The resistivity of the first substrate 1 is higher than a first predetermined value. The low-potential electrode 12 is electrically connected to the back electrode metal film 11 through a through hole in the first substrate. The back electrode metal film 11 is at least partially disposed in the through hole and exposed from the second main surface of the first substrate 1.

[0067] 402. An electron collecting electrode 26 is formed on one side of the first main surface of the second substrate 20. The electron collecting electrode 26 is electrically connected to a wiring 23 disposed on one side of the second main surface of the second substrate through a through-hole electrode in the second substrate; and

[0068] 403. The first main surface of the first substrate 1 is hermetically bonded to the first main surface of the second substrate 20.

[0069] In the transverse direction perpendicular to the longitudinal direction, the electron collecting electrode 26 and the high-potential emitting electrode 7 are at least partially opposite each other; in the longitudinal direction, a sealed cavity 30 is formed between the electron collecting electrode 26 and the high-potential emitting electrode 7, and the gate electrode 10 is at least partially located within the cavity 30.

[0070] In this application, the first substrate 1 is a substrate with a single material structure or a substrate with a composite material layer structure; the first substrate 1 has a complementary metal-oxide-semiconductor (CMOS) module and / or a microelectromechanical system (MEMS) module.

[0071] In some embodiments of operation 401, the method of forming the electron accelerating layer includes:

[0072] 4011. A polycrystalline semiconductor thin film 2 is formed on the first main surface of the first substrate 1, and the polycrystalline semiconductor thin film is subjected to photoelectrochemical etching to form a porous semiconductor material, or a portion of the first main surface of the first substrate 1 is subjected to photoelectrochemical etching to form a porous semiconductor material; and

[0073] 4012. Passivate the porous semiconductor material to form a semiconductor grain chain structure with an insulating layer in the porous semiconductor material.

[0074] In other embodiments of operation 401, the method of forming the electron accelerating layer includes:

[0075] 4011a. Semiconductor grains and insulating dielectrics encapsulating the semiconductor grains are periodically grown on the first main surface of the first substrate 1 to form a semiconductor grain chain structure with an insulating layer. For example, operation 6011a can be performed using an ultra-high frequency plasma-enhanced chemical vapor deposition (PECVD) growth process; or

[0076] 4012a. A sol containing semiconductor grains is spin-coated onto the first main surface of the first substrate 1 (for example, by spin-coating using a sol-gel method), and a semiconductor grain chain structure with an insulating layer is formed by drying and passivation processes.

[0077] In operation 403, the hermetic bonding can be performed in a vacuum environment or an environment with a predetermined gas.

[0078] like Figure 4 As shown, the manufacturing method further includes:

[0079] 404. After the bonding is performed, the electrode area is opened and / or metal wiring is deposited to achieve electrical signal connection.

[0080] The manufacturing method of the transistor device according to the present application will be described below with reference to specific embodiments. The specific process methods listed in Embodiment 1 are merely examples, and the present application is not limited thereto.

[0081] Figures 5 to 42 This is a schematic diagram of the device structure for each step of the manufacturing process of transistor device 100. For example... Figures 5 to 42 As shown, the manufacturing method of transistor device 100 includes the following steps (1) to (36):

[0082] (1) As Figure 5 As shown, a first substrate 1 is prepared. For example, the first substrate 1 is a high-resistivity P-type (100) silicon substrate, and the first substrate 1 is cleaned by an RCA cleaning process.

[0083] (2) Figure 6 As shown, a pattern 100 with a diameter of 15-20 μm is formed using photolithography, while other areas are protected by photoresist 101.

[0084] (3) Figure 7 As shown, a silicon substrate (first substrate 1) is etched using a deep silicon etching (RIE) method, such as the Bosch process, to form a through silicon via (TSV) 102.

[0085] (4) Figure 8As shown, after removing the photoresist 101 and cleaning the silicon wafer, a SiO2 insulating film 14 with a thickness of 100-200 nm is formed by high-temperature thermal oxidation.

[0086] (5) Figure 9 As shown, high-concentration N-type doped polycrystalline silicon (nc) was deposited using the LPCVD (Low Pressure Chemical Vapor Deposition) method. ++ -doped poly-Si)15, filling through-silicon vias.

[0087] (6) Figure 10 As shown, double-sided polishing and planarization were performed using the Chemical Mechanical Polishing (CMP) method. The thickness of the top polycrystalline silicon 103 was controlled to be 1–2 μm, and the thickness of the back polycrystalline silicon 104 was 10–20 μm.

[0088] (7) Figure 11 As shown, undoped columnar poly-Si films 2 with a thickness of 1–6 μm were deposited using either LPCVD (Low Pressure Chemical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition).

[0089] (8) Figure 12 As shown, the surface is protected with photoresist, and the undoped columnar polysilicon layer on the back is etched using reactive ion etching (RIE) to leave an N-type doped polysilicon layer with a thickness of 10–20 μm.

[0090] (9) such as Figure 13 As shown, a pattern was formed using photolithography, and undoped columnar polysilicon and highly doped N-type polysilicon layers were etched using RIE to form a layer smaller than 20 x 20 μm. 2 The figure is 106. The figure can also be a circle, with a diameter of less than 20 μm.

[0091] (10) such as Figure 14 As shown, a silicon oxide SiO2 thin film 16 with a thickness of 50–100 nm was formed by thermal oxidation. Then, a first silicon nitride Si3N4 thin film 3 with a thickness of 100–150 nm was deposited by LPCVD.

[0092] (11) such as Figure 15As shown, an opening pattern 107 is formed in the columnar polysilicon region using photolithography. A silicon nitride (Si3N4) thin film is etched using RIE (Rinse-Etch), and a silicon oxide thin film is etched using wet etching. The photoresist is then removed. Finally, the surface is protected with photoresist, and the back side silicon nitride and silicon oxide thin films are etched.

[0093] (12) such as Figure 16 As shown, a porous polycrystalline silicon layer 108 is prepared using a photoelectrochemical etching method. The thickness of the porous polycrystalline silicon is 0.1 μm to 5 μm. Below the porous polycrystalline silicon layer 108, an undoped columnar polycrystalline silicon layer with a thickness of 1 μm to 5.9 μm is left to form a high-resistivity layer 13 to prevent abnormal etching of the high-concentration N-type polycrystalline silicon. Below the high-resistivity layer 13, a low-potential electrode 12 is formed in the high-concentration N-type polycrystalline silicon, which provides electrons to the porous polycrystalline silicon layer 108.

[0094] (13) such as Figure 17 As shown, oxidation is performed using thermal oxidation or electrochemical oxidation (ECO) to grow a 0.3–8 nm thick oxide layer (SiO2) (i.e., insulating dielectric) on the surface of the nano-silicon grains (i.e., semiconductor grains) within the porous polycrystalline silicon layer 108. This is followed by high-pressure water vapor annealing (HWA) and supercritical rinsing and drying (SCRD) to form the electron acceleration layer 4. The electron acceleration layer 4 is composed of nano-silicon grain chains (i.e., semiconductor grain chain structure) with a 0.3–8 nm thick oxide film (SiO2) on their surface, with the direction of the nano-silicon grain chains perpendicular to the surface of the silicon substrate (i.e., the first main surface of the first substrate 1). A schematic diagram of the nano-silicon grains in the electron acceleration layer 4 is shown below. Figure 18 As shown.

[0095] (14) such as Figure 19 As shown, an insulating film 5 with a thickness of 0.3–2 nm is deposited on the surface of the electron accelerator layer 4 using atomic layer deposition (ALD). The material of the insulating film 5 is SiO2, ZrO2, Si3N4, HfO2, or Al2O3, etc. Furthermore, if the oxide layer (SiO2) in step (13) is thick enough (for example, the thickness of the oxide layer is about 2 nm), step (14) is not required.

[0096] (15) such as Figure 20 As shown, the surface is protected with photoresist, and the back side is etched with a high concentration of N-type doped polysilicon using the RIE method to form a pit 109 with a depth of 200-400 nm.

[0097] (16) such as Figure 21 As shown, with the surface protected by photoresist, a back metal film 11 is deposited by sputtering. The metal film material is Au / Cr = 300 / 10nm, or Au / Ti = 300 / 10nm, or Al = 300nm, and its thickness is 300-500nm. The surface photoresist is then removed. Finally, back-side CMP is performed for planarization to remove the back oxide layer.

[0098] (17) such as Figure 22 As shown, a metal thin film 6 for electron emitter leads is prepared using photolithography, sputtering (or evaporation), and lift-off processes. The metal thin film material and its thickness are Au / Cr = 200–300 / 10 nm or Au / Ti = 200–300 / 10 nm.

[0099] (18) such as Figure 23 As shown, a high-potential emitter conductive film 7 is prepared using photolithography, sputtering (or evaporation), and lift-off methods. The material and thickness of the high-potential emitter conductive film 7 are Au / Ti≦10 / 1nm, or Au / Cr≦10 / 1nm, or a single-atom-layer graphene film, etc.

[0100] (19) such as Figure 24 As shown, a sacrificial layer 110 with a thickness of 500–600 nm was deposited using LPCVD or plasma-assisted chemical vapor deposition (PECVD), followed by planarization using chemical mechanical polishing (CMP). The sacrificial layer material was tetraethyl orthosilicate-silicon oxide (TEOS-SiO2) or phosphosilicate glass (PSG), etc.

[0101] (20) such as Figure 25 As shown, the sacrificial layer is etched using photolithography and RIE methods to form sacrificial island regions 111. Then, the photoresist is removed.

[0102] (21) such as Figure 26 As shown, the second silicon nitride film 8 is deposited using the LPCVD method, and then planarized using the CMP method to expose the top of the sacrificial layer on the surface.

[0103] (22) such as Figure 27 As shown, the surrounding insulating film and polysilicon film are etched using photolithography and RIE methods to form bare silicon surfaces 112 and 113.

[0104] (23) such as Figure 28 As shown, the surface is protected with photoresist, and the silicon nitride film and sacrificial layer film on the back side are etched using the RIE method to form the bare silicon surface 114 on the back side. Then the surface photoresist is removed.

[0105] (24) such as Figure 29 As shown, emitter contact hole 115 is formed using photolithography and RIE methods. Then, the photoresist is removed.

[0106] (25) such as Figure 30 As shown, the emitter metal lead 9 is fabricated using photolithography, sputtering (or evaporation), and lift-off methods. The material of the emitter metal lead 9 is Au / Cr = 200–300 / 10 nm, or Au / Ti = 200–300 / 10 nm, etc.

[0107] (26) such as Figure 31 As shown, comb-shaped or mesh-shaped gate metal thin films 10 are prepared using photolithography, sputtering (or evaporation), and lift-off methods. The gate metal thin film material is a high-temperature resistant metal material such as Pt = 10–300 nm or W = 10–300 nm. Figure 32 This is a planar schematic diagram of the gate metal thin film 10, as shown below. Figure 32 As shown, in the lateral direction, the gate metal thin film 10 has an opening structure to form an electron emission path in the longitudinal direction.

[0108] (27) such as Figure 33 As shown, an opening 116 is formed using photolithography, and photoresist 117 is used to protect other areas of the surface and the back side.

[0109] (28) such as Figure 34 As shown, the sacrificial layer is etched using a dry or wet etching method to form cavity 30. Then, the photoresist on the surface and back is removed using a dry or wet method.

[0110] (29) such as Figure 35 As shown, a second substrate 20 is prepared, which is, for example, a borosilicate glass substrate (e.g., a Pyrex glass plate). However, this application is not limited to this; the second substrate 20 may also be a silicon substrate. In this case, the following steps can be performed on the second substrate 20 using through-silicon via (TSV) technology.

[0111] (30) such as Figure 36 As shown, a metal mask is prepared using photolithography and etching methods. This metal mask is then used to etch a second substrate 20 using deep reactive ion etching (Deep-RIE) to form feedthroughs 200. The metal mask material is Ni or other high-temperature resistant metals, and its thickness is determined by the etching selectivity.

[0112] (31) such as Figure 37 As shown, metal is filled into the through-hole to form the through-hole electrode 21 by sputtering and electroplating. The sputtering metal material is Cr, and the metal material of the through-hole electrode 21 is Ni, etc.

[0113] (32) such as Figure 38 As shown, the second substrate 20 and the through-hole electrode 21 are photolithographically etched and etched to form a cavity 201.

[0114] (33) such as Figure 39 As shown, a top gate redistribution metal thin film 22, a top collector redistribution metal thin film 23, and a top emitter redistribution metal thin film 24 are prepared by sputtering and photolithography. The metal thin film materials and their thicknesses are Au / Cr = 200–300 / 10 nm or Au / Ti = 200–300 / 10 nm.

[0115] (34) such as Figure 40 As shown, a bottom gate redistribution metal film 25, a bottom collector redistribution metal film 26, and a bottom emitter redistribution metal film 27 are prepared by sputtering or evaporation and photolithography. The metal film materials and their thicknesses are Pt / Ti = 50–200 / 10 nm, Au / Cr = 200–300 / 10 nm, or Au / Ti = 200–300 / 10 nm.

[0116] (35) such as Figure 41 As shown, micro-spring contacts 28 for gate bonding and micro-spring contacts 29 for emitter bonding were fabricated using sputtering, photolithography, and electroplating methods. The micro-spring material and its thickness are Au = 0.5–3 μm.

[0117] (36) such as Figure 42 As shown, after steps (28) and (35) are completed, anodic bonding is performed in a vacuum (or a predetermined gas environment) to form transistor device 100.

[0118] The present application has been described above with reference to specific embodiments. However, those skilled in the art should understand that these descriptions are exemplary and not intended to limit the scope of protection of the present application. Those skilled in the art can make various modifications and variations to the present application based on its spirit and principles, and these modifications and variations are also within the scope of the present application.

Claims

1. A transistor device, characterized in that, The transistor device includes: A first substrate (1) has a cold field electron emission unit disposed on one side of a first main surface. The cold field electron emission unit includes an electron acceleration layer (4), a high-potential emitter (7), and a low-potential electrode (12). A gate (10) is also disposed on one side of the first main surface of the first substrate. A back electrode metal film (11) is disposed on one side of a second main surface of the first substrate. In the longitudinal direction perpendicular to the first main surface of the first substrate, the electron acceleration layer (4) is located between the high-potential emitter (7) and the low-potential electrode (12), and the high-potential emitter (7) is located between the gate (10) and the electron acceleration layer (4). The resistivity of the first substrate (1) is higher than a first predetermined value. The low-potential electrode (12) is electrically connected to the back electrode metal film (11) through a through-hole in the first substrate. The back electrode metal film (11) is at least partially disposed in the through-hole and exposed from the second main surface of the first substrate (1). The second substrate (20) has an electron collecting electrode (26) disposed on one side of the first main surface of the second substrate. The electron collecting electrode (26) is electrically connected to the wiring (23) disposed on one side of the second main surface of the second substrate through a through-hole electrode in the second substrate. The first main surface of the first substrate (1) is hermetically bonded to the first main surface of the second substrate (20). In the transverse direction perpendicular to the longitudinal direction, the electron collecting electrode (26) is at least partially opposite to the high-potential emitting electrode (7). In the longitudinal direction, a closed cavity (30) is formed between the electron collecting electrode (26) and the high-potential emitting electrode (7), and the gate electrode (10) is at least partially located within the cavity (30).

2. The transistor device as claimed in claim 1, characterized in that, The second substrate (20) also has the following on one side of its first main surface: A gate metal contact structure (28) electrically connected to the gate (10); and The emitter metal contact structure (29) is electrically connected to the high-potential emitter (7). The gate metal contact structure (28) and the emitter metal contact structure (29) are electrically connected to wiring (22, 24) provided on one side of the second main surface of the second substrate through through-hole electrodes in the second substrate.

3. The transistor device as claimed in claim 1, characterized in that, The electron acceleration layer (4) contains semiconductor grains, and an insulating medium of a predetermined thickness is disposed between adjacent semiconductor grains.

4. The transistor device as claimed in claim 3, characterized in that, The thickness of the electron acceleration layer is 0.1 μm to 5 μm, and the feature size of the semiconductor grain is 2 nm to 50 nm.

5. The transistor device as claimed in claim 3, characterized in that, The predetermined thickness of the insulating medium is 0.3 nm to 8 nm. Under the isolation effect of the insulating medium, the semiconductor grains in the electron acceleration layer (4) present as semiconductor grain chain structures with insulating layers. The two ends of the semiconductor grain chain structure are close to the low potential electrode (12) and the high potential emitter (7), respectively.

6. The transistor device as claimed in claim 1, characterized in that, The high-potential emitter (7) is a conductive thin film with a thickness of 0.1 nm to 10 nm. The material of the conductive thin film is one or more of metal, conductive compound and conductive two-dimensional material.

7. The transistor device as claimed in claim 1, characterized in that, In the longitudinal direction, the distance between the gate (10) and the surface of the high-potential emitter (7) is 10 nm to 10 μm. In the lateral direction, the gate (10) has an opening structure to form an electron emission path along the longitudinal direction.

8. The transistor device as claimed in claim 1, characterized in that, In the longitudinal direction, there is a gap between the electron collecting electrode (26) and the gate electrode (10), and the gap height is greater than or equal to 2 nm.

9. The transistor device as claimed in claim 1, characterized in that, Electrons emitted from the high-potential emitter (7) pass through the cavity (30) and are collected by the electron collecting electrode (26), the cavity being either a vacuum or containing a predetermined gas.

10. The transistor device as claimed in claim 1, characterized in that, At least one of the high-potential emitter (7), the electron collector (26), and the gate (10) has a patterned structure, which forms an electrical signal path between the cavity and the external environment.

11. An integrated circuit, characterized in that, The integrated circuit includes at least one transistor device as described in any one of claims 1 to 10.

12. A method for manufacturing a transistor device, for manufacturing the transistor device as described in any one of claims 1 to 10, characterized in that, The method includes: A cold field electron emission unit and a gate (10) are formed on one side of the first main surface of the first substrate (1). The cold field electron emission unit includes an electron acceleration layer (4), a high-potential emitter (7), and a low-potential electrode (12). A back electrode metal film (11) is disposed on one side of the second main surface of the first substrate. In the longitudinal direction perpendicular to the first main surface of the first substrate, the electron acceleration layer (4) is located between the high-potential emitter (7) and the low-potential electrode (12). The high-potential emitter (7) is located between the gate (10) and the electron acceleration layer (4). The resistivity of the first substrate (1) is higher than a first predetermined value. The low-potential electrode (12) is electrically connected to the back electrode metal film (11) through a through hole in the first substrate. The back electrode metal film (11) is at least partially disposed in the through hole and exposed from the second main surface of the first substrate (1). An electron collector (26) is formed on one side of the first main surface of the second substrate (20), and the electron collector (26) is electrically connected to a wiring (23) disposed on one side of the second main surface of the second substrate through a through-hole electrode in the second substrate; and The first main surface of the first substrate (1) is hermetically bonded to the first main surface of the second substrate (20). In the transverse direction perpendicular to the longitudinal direction, the electron collecting electrode (26) is at least partially opposite to the high-potential emitting electrode (7). In the longitudinal direction, a closed cavity (30) is formed between the electron collecting electrode (26) and the high-potential emitting electrode (7), and the gate electrode (10) is at least partially located within the cavity (30).

13. The method for manufacturing a transistor device as described in claim 12, characterized in that, The first substrate (1) is a substrate with a single material structure or a substrate with a composite material layer structure. The first substrate (1) has a complementary metal-oxide-semiconductor (CMOS) module and / or a microelectromechanical system (MEMS) module.

14. The method for manufacturing a transistor device as described in claim 12, characterized in that, Forming the electron acceleration layer includes: A polycrystalline semiconductor thin film (2) is formed on the first main surface of the first substrate (1), and the polycrystalline semiconductor thin film is subjected to photoelectrochemical etching to form a porous semiconductor material (101), or a portion of the first main surface of the first substrate (1) is subjected to photoelectrochemical etching to form a porous semiconductor material (101); and The porous semiconductor material is passivated to form a semiconductor grain chain structure with an insulating layer in the porous semiconductor material.

15. A method for manufacturing a transistor device as described in claim 12, characterized in that, Forming the electron acceleration layer includes: Semiconductor grains and insulating dielectrics encapsulating the semiconductor grains are periodically grown on the first main surface of the first substrate (1) to form a semiconductor grain chain structure with an insulating layer; or Sol containing semiconductor grains is spin-coated onto the first main surface of the first substrate (1), and a semiconductor grain chain structure with an insulating layer is formed by drying and passivation processes.

16. The method for manufacturing a transistor device as described in claim 12, characterized in that, The hermetic bonding is performed in a vacuum environment or an environment containing a predetermined gas.

17. The method for manufacturing the transistor device according to claim 12, characterized in that, The manufacturing method further includes: After the bonding is performed, the electrode area is made into openings and / or metal wiring is deposited to achieve electrical signal connection.

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