A method for synchronizing a low-Earth orbit satellite terminal receiver

Abstract

This application provides a method for synchronizing a low-Earth orbit satellite terminal receiver, relating to the field of wireless communication technology. The method includes: using a superframe header sequence and a posterior detection integral algorithm to perform frame header detection on the received baseband signal to obtain a superframe signal; performing digital AGC on the superframe signal; estimating and compensating the frequency offset of the superframe signal after digital AGC; using a local postcode sequence and a posterior detection integral algorithm to perform frame tail detection on the compensated superframe signal to obtain superframe symbols; segmenting the superframe symbols and estimating the timing error of the segmented data; performing symbol segmentation processing based on the timing error; performing symbol interpolation on the segmented data; and performing symbol synchronization output control and superframe length limitation on the interpolated data. This method can solve the problems of frame synchronization, frequency offset estimation and compensation, symbol timing, and symbol synchronization.

Description

Technical Field

[0001] This application relates to the field of wireless communication technology, and more specifically, to a method for synchronizing a low-Earth orbit satellite terminal receiver. Background Technology

[0002] Currently, satellite internet, as an important information infrastructure, is forming a large-scale network based on a certain number of satellites, thereby radiating globally and building a satellite communication system with real-time information processing capabilities, which can provide communication services such as broadband internet access to ground and air application terminals.

[0003] Mega-constellations of low-Earth orbit satellites, exemplified by Starlink, are reshaping the global communications landscape, with satellite-terrestrial converged mobile communication becoming a crucial application scenario for next-generation wireless communication technologies. However, future 6G satellite-terrestrial converged mobile communication will face challenges such as long transmission distances, high latency, and rapidly changing channel links, resulting in an extremely complex channel environment. Simultaneously, satellite terminals will face frequent beam switching and other practical challenges in maintaining broadband access and service communication.

[0004] With the rapid development of the information society, high-quality communication and broadband internet services have become an urgent need in fields such as navigation, aviation, emergency response, and the military. Larger system capacity and higher transmission reliability have become essential requirements for the next generation of satellite communications.

[0005] Synchronization technology is a key technology in satellite communication receivers. Affected by Doppler frequency shift, time delay, beam switching, etc., the receiver synchronization process may "lose synchronization" and cause communication interruption. In order to ensure system recovery, the system needs to have strong reliability and robustness.

[0006] In digital satellite communication, due to the differences in frequency and phase between the receiver's local clock and the transmitter's clock, as well as the existence of channel transmission delay, if the clock generated by the receiver's local oscillator or crystal oscillator is directly used as the timing signal to sample the received signal, the sampling decision cannot be made at the optimal sampling time. This will lead to a decrease in demodulation performance and may even result in incorrect channel decoding.

[0007] The time difference between the actual sampling time and the optimal sampling time at the receiving end is called the timing error. In order to recover the baseband signal from the bandpass signal, timing error estimation is required, and a suitable algorithm is used for compensation. This process is called bit synchronization or symbol synchronization.

[0008] In low-Earth orbit broadband satellite communication, satellite terminals need to overcome adverse factors such as Doppler frequency shift, time offset, and link complexity, depending on communication bandwidth, transmission distance, and mobile speed. They need to design appropriate algorithms for signal processing to improve system performance and stability, and achieve engineering applications through digital circuit design.

[0009] Existing satellite communication systems are mostly narrowband systems operating in medium and high orbits, while broadband low-Earth orbit (LEO) satellites have become a key communication infrastructure for satellite internet applications. 5G-NTN and DVB communication protocols are currently the mainstream satellite communication standards, but for building satellite internet using large LEO satellite constellations, it is still necessary to focus on the impact of satellite channels and high-speed mobility on the performance of modulation and demodulation schemes. Broadband LEO satellite communication systems will use Ka / Ku bands to meet high-throughput communication requirements, and satellite terminals need to adapt to a wide symbol rate range (tens to hundreds of mega-symbols / s) and dynamic channel conditions. However, existing symbol synchronization technologies have shortcomings in the following aspects: Poor dynamic adaptability: In broadband low-Earth orbit satellite communication, Doppler frequency shift (±1MHz) causes traditional phase-locked loop (PLL) to lose lock, increasing symbol timing error.

[0010] Poor performance at low signal-to-noise ratios: Traditional pilot-based synchronization algorithms experience a sharp increase in bit error rate when the signal-to-noise ratio is below 5 dB.

[0011] High computational complexity: Existing time-domain interpolation filtering or frequency-domain FFT methods require a large amount of hardware resources, making it difficult to meet real-time processing requirements.

[0012] Examples of existing technologies: Timing recovery based on Gardner algorithm: relies on symbol transition point detection, but is susceptible to noise interference at low signal-to-noise ratio and has a slow convergence speed.

[0013] Pilot-based symbol synchronization: This method utilizes the PL header pilot in the DVB-S2X frame structure, but the pilots are sparse, limiting the synchronization accuracy. Summary of the Invention

[0014] The embodiments of this application provide a method for synchronizing a low-Earth orbit satellite terminal receiver to solve problems related to frame synchronization, frequency offset estimation and compensation, symbol timing, and symbol synchronization.

[0015] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0016] According to a first aspect of the embodiments of this application, a method for synchronizing a low-Earth orbit satellite terminal receiver is provided, comprising: Using the superframe header sequence, a posterior detection integral algorithm is employed to perform frame header detection on the received baseband signal to obtain the superframe signal; Digital AGC for superframe signals; Frequency offset estimation and compensation are performed on the superframe signal after digital AGC. Using the local postcode sequence, a post-hoc detection integral algorithm is employed to perform frame tail detection on the compensated superframe signal to obtain the superframe symbol; The superframe symbol is segmented, and the timing error of the segmented data is estimated. Perform symbol segmentation processing based on the timing error; Perform symbolic interpolation on the data after symbolic segmentation; The system performs symbol synchronization output control and superframe length limitation on the data after symbol interpolation.

[0017] In some embodiments of this application, based on the foregoing scheme, the step of using a superframe header sequence and employing a posteriori detection integral algorithm to perform frame header detection on the received baseband signal to obtain a superframe signal includes: Block-based coherent integration: using the superframe header sequence as the reference signal, and with length... The signal is divided into several sub-block correlation windows. The baseband signal and the reference signal sub-block correlation windows are convolved with relative sliding. The signal power after convolution of all sub-blocks is accumulated to obtain the convolution power sum. Detection threshold calculation: Remove the beginning and end parts of the convolution power sum to obtain a new convolution power sum; calculate the threshold and perform threshold delay processing; perform pseudo-peak filtering on the delayed threshold and truncate the threshold a second time to obtain a new threshold; calculate the difference between the new convolution power sum and the new threshold to obtain a comparison signal. Synchronization position search: The synchronization position is detected based on the comparison signal and the valid synchronization points are filtered; the precise frame synchronization point is found from the valid synchronization points to obtain the superframe signal.

[0018] In some embodiments of this application, based on the foregoing scheme, the digital AGC of the superframe signal includes: First, the average power is calculated based on a certain length of sampled data. Then, the square root of the power value is taken to obtain the amplitude value. The amplitude value is normalized and its reciprocal is taken to obtain the gain coefficient. Finally, the gain coefficient is multiplied by the superframe signal to adjust the amplitude of the signal.

[0019] In some embodiments of this application, based on the foregoing scheme, the frequency offset estimation and compensation of the superframe signal after digital AGC includes: Synchronize the frame header symbols of the superframe signal after digital AGC to obtain synchronization data; The first and second coarse frequency offset estimates are performed on the synchronized data. The sum of the first coarse frequency offset estimation result and the second coarse frequency offset estimation result is taken as the final frequency offset estimate; Compensation is performed using the final frequency offset estimate.

[0020] In some embodiments of this application, the process of synchronizing frame header symbols based on the aforementioned scheme includes: Define the baseband symbol data used for timing error estimation; Based on the baseband symbol data, the timing error is calculated using the maximum likelihood forward timing estimation method, and the symbol interpolation is performed using the parabolic interpolation method with the Farrow structure.

[0021] In some embodiments of this application, the process of performing the first coarse frequency offset estimation based on the aforementioned scheme includes: The synchronization data is correlated with the frame header reference signal to obtain the signal. ; Based on signal Calculate the autocorrelation function using the baseband symbol rate SRbb and control parameter N. and smoothing coefficient ; Based on autocorrelation function and smoothing coefficient The frequency difference is calculated using weighted phase difference. ; Utilizing frequency difference Frequency offset compensation is performed on the synchronization data to obtain the data symbols. .

[0022] In some embodiments of this application, the process of performing a second coarse frequency offset estimation based on the aforementioned scheme includes: The data symbols are segmented and merged, with a merge length of [length missing]. The merged data is denoted as signal. ; Based on signal Calculate the autocorrelation function using the baseband symbol rate SRbb and control parameter N. and smoothing coefficient ; Based on autocorrelation function and smoothing coefficient The frequency difference is calculated using weighted phase difference. .

[0023] In some embodiments of this application, based on the foregoing scheme, the step of using a local postcode sequence and employing a posteriori detection integral algorithm to perform frame tail detection on the compensated superframe signal to obtain the superframe symbol includes: Using the local postcode sequence as a reference signal, the compensated superframe signal is subjected to block coherent integration, detection threshold calculation, and synchronization position search to form the superframe symbol after frame synchronization.

[0024] In some embodiments of this application, based on the foregoing scheme, the symbol segmentation processing according to the timing error includes: Based on the timing error, calculate the reference sampling points for the segmented data; Symbol segmentation is performed based on the aforementioned benchmark sampling points.

[0025] In some embodiments of this application, based on the foregoing scheme, the step of performing symbol interpolation on the symbol-segmented data includes: Based on the symbol-segmented data, the optimal sampling point interpolation algorithm with the Farrow structure is used to interpolate the optimal sampling point data for a single symbol rate.

[0026] The technical solution of this application has the following beneficial effects: 1. Strong resistance to time deviation: Supports ±30ppm sampling clock deviation jitter at a baseband signal symbol rate of 200MHz, with good synchronization performance.

[0027] 2. Improved synchronization accuracy: Frame synchronization and symbol synchronization technologies suitable for low-Earth orbit broadband satellite forward links are adopted, adapting to signal-to-noise ratios as low as -2.4 dB.

[0028] 3. Supports high-speed mobility: Supports Doppler frequency shift ±3MHz, suitable for low Earth orbit (LEO) satellites and high-speed mobile terminals, providing stable communication while on the move.

[0029] 4. Extended dynamic range: The receiver baseband dynamic range is 72dB, balancing hardware logic resource consumption and receiver performance.

[0030] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0031] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings: Figure 1 A flowchart illustrating a method for synchronizing a low-Earth orbit satellite terminal receiver according to an embodiment of this application is shown. Figure 2 A signal processing flowchart of a low-Earth orbit satellite terminal receiver synchronization implementation method according to an embodiment of this application is shown; Figure 3 A flowchart illustrating the signal processing of the frame synchronization stage according to an embodiment of this application is shown; Figure 4 A flowchart of the signal processing stage of the symbol synchronization phase according to an embodiment of this application is shown; Figure 5 A block diagram of a superframe signal structure according to an embodiment of this application is shown; Figure 6 A block diagram of a low-Earth orbit satellite terminal receiver synchronization implementation apparatus according to one embodiment of this application is shown; Figure 7 A block diagram of an electronic device according to one embodiment of this application is shown; Figure 8 A schematic diagram of the structure of a computer system suitable for implementing the electronic device of the present application is shown. Detailed Implementation

[0032] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0033] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0034] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0035] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0036] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such uses of these terms can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described.

[0037] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0038] The following detailed description of some embodiments of this application will be provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0039] See Figure 1 The diagram shows a flowchart illustrating a method for synchronizing a low-Earth orbit satellite terminal receiver according to an embodiment of this application.

[0040] See Figure 2 The diagram shows a signal processing flowchart for a low-orbit satellite terminal receiver synchronization method.

[0041] according to Figure 2 As shown, this method mainly includes a frame synchronization stage and a symbol synchronization stage.

[0042] See Figure 3 The flowchart of signal processing during the frame synchronization stage is shown.

[0043] See Figure 4 The diagram shows the signal processing flowchart for the symbol synchronization phase.

[0044] It should be noted that hardware settings are required for practical application to implement this method. The specific settings are as follows: Frame synchronization unit: Implemented using FPGA or ASIC logic circuit design, including frame header detection module, frame tail detection module and frequency offset estimation module, and designed with parallel correlator array to calculate the cross-correlation value of multiple symbols simultaneously.

[0045] Symbol synchronization unit: Implemented using FPGA or ASIC logic circuit design, including timing estimation segmentation module, timing estimation module, superframe symbol segmentation module, interpolation module, symbol synchronization output module and frame length limiting module.

[0046] Specifically, such as Figure 1 As shown, a method for synchronizing a low-Earth orbit satellite terminal receiver is illustrated, including steps S100 to S800.

[0047] refer to Figure 1 In step S100, the superframe signal is obtained by using the superframe header sequence and employing a post-hoc detection integral algorithm to perform frame header detection on the received baseband signal.

[0048] In some feasible embodiments, based on the aforementioned scheme, the step of using a superframe header sequence and employing a posterior detection integral algorithm to perform frame header detection on the received baseband signal to obtain a superframe signal includes: Block-based coherent integration: using the superframe header sequence as the reference signal, and with length... The signal is divided into several sub-block correlation windows. The baseband signal and the reference signal sub-block correlation windows are convolved with relative sliding. The signal power after convolution of all sub-blocks is accumulated to obtain the convolution power sum. Detection threshold calculation: Remove the beginning and end parts of the convolution power sum to obtain a new convolution power sum; calculate the threshold and perform threshold delay processing; perform pseudo-peak filtering on the delayed threshold and truncate the threshold a second time to obtain a new threshold; calculate the difference between the new convolution power sum and the new threshold to obtain a comparison signal. Synchronization position search: The synchronization position is detected based on the comparison signal and the valid synchronization points are filtered; the precise frame synchronization point is found from the valid synchronization points to obtain the superframe signal.

[0049] It should be noted that, see Figure 5 The diagram shows the structure of the superframe signal.

[0050] like Figure 5 As shown, the superframe signal is used to transmit service data and control signaling on spot beams. It supports spot beam transmission and consists of a superframe preamble (SOSF), a superframe format indicator (SFFI), a superframe header (SFH), a superframe pilot, a physical layer frame (PLFrame), and a postamble.

[0051] For example, in combination Figure 2 , Figure 3 The specific process of frame header detection is as follows: The frame header detection employs the Post Detection Integration (PDI) algorithm. In scenarios with large frequency offsets (Δf), traditional coherent detection suffers from peak attenuation due to phase rotation, while incoherent detection (such as energy detection), although robust to frequency offset, has low SNR gain. PDI combines the advantages of both, maximizing signal energy within a finite coherence window, and then suppressing the cumulative effect of frequency offset through nonlinear operations (such as modulus taking and differential).

[0052] Step A: Block coherent integration Let the received signal be The reference signal is the superframe header sequence. and will Sequence symbols are divided equally There are 3 sub-blocks, each with a length of 1. .in, The sampling multiple for each symbol.

[0053] 1. No. The received signal sub-block of each sub-block:

[0054] 2. No. Reference signal sub-blocks of each sub-block (inverted and conjugate):

[0055] 3. Perform a relative sliding convolution calculation between the received signal and the reference signal:

[0056] 4. Sum the squared amplitudes of all sub-blocks, i.e., the power:

[0057] Step B: Detection threshold calculation 1. Truncate the convolution result: Remove the sum of convolution power from step A. The beginning and end parts (each with a length of) L = sb _ len × sps ), to obtain new ; 2. Threshold Calculation: A threshold signal is generated using a moving average. Let the moving window length be... T， The normalization factor is ,but

[0058] Where S is a constant with a definable size. '*' represents a vector of all 1s, and '*' represents convolution.

[0059] 3. Threshold delay processing: Shift the threshold sequence to the right by T samples and fill the front end with zeros.

[0060] 4. False peak filtering: If the delayed threshold is higher than the current threshold, the current threshold is replaced to suppress transient interference from false peaks.

[0061] 5. Secondary truncation threshold: Removes the threshold value before... T -1 samples are taken and the tail is truncated to align with the original signal to obtain a new threshold_conv.

[0062] 6. Generate comparison signals: calculate power and sum The difference between pdi_compare and the threshold threshold_conv.

[0063] Step C: Synchronize Location Search 1. Detect synchronization position: Find the index of all comparison signals pdi_compare that are greater than zero. .

[0064] 2. Filtering valid synchronization points: Candidate synchronization positions (minimum interval D) are filtered according to the following rules.

[0065] 3. Precise frame synchronization point: for each candidate position i ,exist[ i,i Search for the maximum value within the range of +5, until the maximum value among the valid synchronization points is reached.

[0066]

[0067] refer to Figure 1 Step S200: Perform digital AGC on the superframe signal.

[0068] For example, refer to Figure 2 and Figure 3 After capturing a valid superframe signal through frame header detection, in order to improve the subsequent symbol synchronization and channel equalization performance, automatic AGC in the digital domain, namely digital AGC, is implemented to adjust the amplitude of the signal.

[0069] In some feasible embodiments, based on the foregoing scheme, the digital AGC of the superframe signal includes: First, the average power is calculated based on a certain length of sampled data. Then, the square root of the power value is taken to obtain the amplitude value. The amplitude value is normalized and its reciprocal is taken to obtain the gain coefficient. Finally, the gain coefficient is multiplied by the superframe signal to adjust the amplitude of the signal.

[0070] refer to Figure 1 Step S300: Frequency offset estimation and compensation are performed on the superframe signal after digital AGC.

[0071] In some feasible embodiments, based on the foregoing scheme, the frequency offset estimation and compensation of the superframe signal after digital AGC includes: Synchronize the frame header symbols of the superframe signal after digital AGC to obtain synchronization data; The first and second coarse frequency offset estimates are performed on the synchronized data. The sum of the first coarse frequency offset estimation result and the second coarse frequency offset estimation result is taken as the final frequency offset estimate; Compensation is performed using the final frequency offset estimate.

[0072] In some feasible embodiments, the process of synchronizing frame header symbols based on the aforementioned scheme includes: Define the baseband symbol data used for timing error estimation; Based on the baseband symbol data, the timing error is calculated using the maximum likelihood forward timing estimation method, and the symbol interpolation is performed using the parabolic interpolation method with the Farrow structure.

[0073] In some feasible embodiments, the process of performing the first coarse frequency offset estimation based on the aforementioned scheme includes: The synchronization data is correlated with the frame header reference signal to obtain the signal. ; Based on signal Calculate the autocorrelation function using the baseband symbol rate SRbb and control parameter N. and smoothing coefficient ; Based on autocorrelation function and smoothing coefficient The frequency difference is calculated using weighted phase difference. ; Utilizing frequency difference Frequency offset compensation is performed on the synchronization data to obtain the data symbols. .

[0074] In some feasible embodiments, the process of performing a second coarse frequency offset estimation based on the aforementioned scheme includes: The data symbols are segmented and merged, with a merge length of [length missing]. The merged data is denoted as signal. ; Based on signal Calculate the autocorrelation function using the baseband symbol rate SRbb and control parameter N. and smoothing coefficient ; Based on autocorrelation function and smoothing coefficient The frequency difference is calculated using weighted phase difference. .

[0075] For example, refer to Figure 2 and Figure 3 The specific steps for frequency offset estimation and compensation are as follows: Step A: Frame header symbol synchronization Define the baseband symbol data segment length as L and the sampling factor as L for timing error estimation. Timing error estimation employs a forward timing estimation method based on maximum likelihood, while sign interpolation uses a parabolic interpolation method with a Farrow structure.

[0076] The specific calculation process is as follows: S1: Calculation length is L, sampling multiple is The magnitude of the sampled signal, i.e., its absolute value; S2: Perform phase rotation on the modulus of each sampling point, with a rotation angle of... ; S3: Summation after rotating sampling points The sum of the real parts of the sampled points is equal to the modulus of the first multiple point minus the modulus of the third multiple point, and then summed. The sum of the imaginary parts of the sampled points is equal to the modulus of the second multiple point minus the modulus of the fourth multiple point, and then summed. S4: Yes The phase is determined from the IQ symbol. .

[0077] S5: Calculate timing error .

[0078] in, The range [-1, 1] represents the offset ratio between the actual sampling and the theoretical optimal sampling point in the time domain.

[0079] S6: Calculate the sampling reference point , The integer part is , The decimal part is , .

[0080] S7: Optimal sampling point interpolation, based on and , cut The total number of symbol points for sampled data X at a sampling multiple of 4 is: The optimal sampling point interpolation is calculated using a parabolic interpolation algorithm based on the Farrow structure, and the final output is... Optimal sampling point data with multiple symbol rates.

[0081] Step B: First coarse frequency offset estimation S1: Based on the frame header symbol synchronization data from step A, perform correlation operations with the frame header reference signal h to obtain... ; S2: Based on The baseband symbol rate SRbb and the control parameter N are calculated as follows: Suppose the observed signal is a complex sinusoidal signal sequence. Its length is .

[0082] 1. Autocorrelation function The calculation is divided into two modes: Precision mode:

[0083] Approximate pattern:

[0084] in, express The phase.

[0085] 2. Smoothing Coefficient Calculation Smoothing coefficient w [ m The expression for ] is:

[0086] 3. Frequency offset estimation Final frequency difference Calculated by weighted phase difference

[0087] S3: Coarse frequency offset compensation. For the frame header signal after symbol synchronization, the frequency offset estimate from step S2 of step B is used. Frequency offset compensation is performed to obtain data symbols. .

[0088] Step C: Second coarse frequency offset estimation S1: To further improve the accuracy of frequency offset estimation, for Perform segment merging, with a merge length of [length missing]. The merged data is z_comb.

[0089] S2: Perform frequency offset estimation on z_comb, using the same method as step S2 in step B, to obtain the second frequency offset estimate. .

[0090] Step D: Frequency Offset Compensation The sum of the results of the first and second frequency offset estimations is the final frequency offset estimate. Use this value to receive the signal Perform frequency offset compensation.

[0091]

[0092] Where t is the sampling time.

[0093] It should be noted that the beneficial effects of this step are as follows: Frequency offset robustness: The effects of large frequency offsets are suppressed by piecewise coherence and differential methods, adapting to high Doppler offset scenarios.

[0094] Low SNR performance: Coherent integration improves the SNR within the segment, while incoherent integration avoids phase sensitivity, resulting in overall performance superior to pure incoherent detection.

[0095] Flexibility: By adjusting the segment length L and control parameters N It can be optimized for different frequency offset and SNR scenarios.

[0096] Applicable scenarios: Continuous Transmission (CTX): In long frame structures, threshold crossover (TC) serial search is used, and PDI reduces the average acquisition time.

[0097] Burst Transmission (BTX): Under single-detection requirements, the ML criterion combined with PDI reduces the frame error rate.

[0098] refer to Figure 1 In step S400, using the local postcode sequence, the frame tail detection algorithm is used to perform frame tail detection on the compensated superframe signal to obtain the superframe symbol.

[0099] In some feasible embodiments, based on the aforementioned scheme, the step of using a local postcode sequence and employing a posteriori detection integral algorithm to perform frame tail detection on the compensated superframe signal to obtain the superframe symbol includes: Using the local postcode sequence as a reference signal, the compensated superframe signal is subjected to block coherent integration, detection threshold calculation, and synchronization position search to form the superframe symbol after frame synchronization.

[0100] For example, refer to Figure 2 , Figure 4 Frame tail detection is used to estimate the position of the postcode of the frame data. It adopts the same method as frame head detection, only the reference signal needs to be changed to the local postcode sequence PostSymbl, and then the start position of the postcode can be calculated, and then the end position of the superframe data can be known.

[0101] After frame header detection, digital AGC, and frequency offset estimation and compensation, the frame-synchronized result is obtained. The baseband superframe signal at the sampling multiple is then treated as a postcode data segment, with the data following the end of the superframe data being considered as the postcode data segment, and the postcode data length is then... The sample is truncated at the sampling rate to form the entire superframe symbol after frame synchronization, denoted as [symbol missing]. The length of the baseband superframe signal is denoted as . The length of the postcode data segment is denoted as . And mark the index of the start signal of the back preamble symbol. Calculation formula:

[0102] refer to Figure 1 In step S500, the superframe symbol is segmented and the timing error of the segmented data is estimated.

[0103] For example, refer to Figure 2 , Figure 4 The specific steps for segmenting the timing error estimation of the superframe signal are as follows: To improve the effectiveness of timing error estimation, the entire superframe symbol is segmented. Simultaneously, resets are performed on a superframe basis to enhance the stability of the functional unit logic circuit design.

[0104] Suppose At the sampling multiple, the segment length is Then the number of segments is The number of signal sampling points used for timing error estimation is .

[0105] Timing error estimation is performed based on segmented data. The processing procedure and frequency offset estimation are the same as steps s1~s5 in step A of the specific compensation steps, and the timing error τ is obtained.

[0106] refer to Figure 1 Step S600: Perform symbol segmentation processing based on the timing error.

[0107] In some feasible embodiments, based on the foregoing scheme, the symbol segmentation processing according to the timing error includes: Based on the timing error, calculate the reference sampling points for the segmented data; Symbol segmentation is performed based on the aforementioned benchmark sampling points.

[0108] For example, refer to Figure 2 , Figure 4 The specific steps for symbol segmentation are as follows: S1: Based on the estimated timing error of the segmented data, calculate the reference sampling points for the data segments. When segmenting the data, for the first segment, its... The calculation and frequency offset estimation are the same as s6 of A in the specific compensation steps, that is... .

[0109] Starting from the second data segment, its The calculation is as follows:

[0110]

[0111] in, Use the data segment number as the sequence number.

[0112] S2: Based on the above calculations Perform data segmentation: based on Index, for superframe symbols By segmenting and extracting numbers, we obtain... .

[0113]

[0114] based on Index, for superframe symbols By segmenting and extracting numbers, we obtain... .

[0115]

[0116] in, This indicates rounding up to the nearest integer.

[0117] After several segmentations, the length of the last segment is insufficient. At that time, the required segmentation The previous segmented calculation will be used. value.

[0118] When implementing segmented data retrieval in engineering, it is necessary to handle superframe symbols. Appropriate caching facilitates the initial timing error estimation followed by data segmentation, resulting in a pipelined circuit structure. Simultaneously, it marks the start of the superframe output signal (sop), the valid data signal (valid), the post-first start signal (post_first), the post-first index (post_first_idx, denoted as PFI), and the last complete segmented data. The remaining number of sampling points at the sampling multiplier is indicated by last_block_remain_point (denoted as LBRP), and the fractional part of the timing error of the last complete segment is also included. .

[0119] refer to Figure 1 Step S700: Perform symbol interpolation on the data after symbol segmentation.

[0120] In some feasible embodiments, based on the foregoing scheme, the step of performing symbol interpolation on the symbol-segmented data includes: Based on the symbol-segmented data, the optimal sampling point interpolation algorithm with the Farrow structure is used to interpolate the optimal sampling point data for a single symbol rate.

[0121] For example, refer to Figure 2 and Figure 4 The segmented data obtained by the S2 process based on the specific steps of symbol segmentation processing. and ,as well as The optimal sampling point interpolation is performed using the parabolic interpolation algorithm with the Farrow structure, and the final output is the optimal sampling point data for a single symbol rate.

[0122] Because the interpolation processing structure is fixed, the clock delay required for its computation is also a fixed value.

[0123] After frame header detection, digital AGC, frequency offset estimation and compensation, frame tail detection, timing error estimation segmentation of superframe signals, timing error estimation, symbol segmentation processing, and symbol interpolation, the following is obtained: The output signal with 2 times the sampling points after frame synchronization and symbol synchronization at the sampling multiple.

[0124] refer to Figure 1 In step S800, symbol synchronization output control and superframe length limitation are applied to the data after symbol interpolation.

[0125] For example, refer to Figure 2 and Figure 4 The specific process of symbol synchronization output control is as follows: To support flexible superframe scheduling with different modulation schemes and meet the diverse service requirements of terminals, it is necessary to control the output of effective symbol synchronization signals.

[0126] When implemented using logic circuits such as FPGAs / ASICs, precise control of signal processing behavior at each clock cycle is required. This necessitates effective symbol length control for synchronized symbol output.

[0127] For different application scenarios, the following two methods can be implemented: Method 1: For resource scheduling where the current superframe uses a fixed modulation scheme, a counter lookup table matching method can be used to accurately mark the end position of the baseband superframe signal and the start position of the post-lead symbol. The specific implementation is as follows: When the superframe uses a fixed modulation scheme, its effective superframe length is a fixed value. Furthermore, the current superframe data exists in two formats: service data and service + signaling data.

[0128] Table 1 Effective Superframe Length Table

[0129] The valid output signals are counted, incrementing by 1 for each valid cycle. The counter is defined as `dout_cnt`. The symbol synchronization superframe start valid signal `sf_symb_first` is obtained by processing the symbol segmentation output `sop` signal and then synchronizing it after interpolation delay. When the counter value equals a valid superframe length value in Table 1 minus 1, and the postlead start signal marker is within the detection window, the superframe signal end signal `sf_symb_data_last` is output, and the postlead start signal `sf_symb_post_start` is generated in the next clock cycle. After detecting the postlead start signal, the postlead symbols are counted. When the count reaches the symbol length, the entire superframe symbol ends, and the marker `sf_symb_last` is output.

[0130] Method 2: For resource scheduling in the current superframe with flexible modulation, a postmark distance detection method can be used to accurately mark the end position of the baseband superframe signal and the start position of the postmark symbol. The specific implementation is as follows: The post-start signal post_first and index are delayed after synchronization via interpolation. Obtain the guide start position indication (denoted as PFP):

[0131] Calculate the distance relative to the first point of the follower:

[0132] in, The value range is [0, 3] integers.

[0133] when When the clock cycle is even, the counter `dout_cnt` is set to an even value, and the valid data signal at this time is marked as `sf_symb_data_last`. Otherwise, the valid data signal for the next clock cycle is marked as `sf_symb_data_last`.

[0134] After generating sf_symb_data_last, a poststart signal sf_symb_post_start is generated in the next clock cycle. The generation of the remaining marker signals is the same as in method 1.

[0135] For example, refer to Figure 2 and Figure 4 The specific process of limiting the superframe length is as follows: Considering the complexity of satellite-to-ground links, wireless communication signals may be subject to various forms of interference and signal truncation caused by beam switching, and there may be missynchronization during receiver synchronization.

[0136] To enhance the robustness of the baseband link processing and prevent missynchronization or synchronization failure caused by interference with the frame tail signal from causing abnormalities in the logic circuit, a frame length limit is specifically imposed on the data length of the symbol synchronization output.

[0137] In actual design, the maximum length of the superframe signal is known. Therefore, the output of each superframe can be limited by using a counter to prevent the data of the two superframes from being connected together due to the failure to detect the start signal of the follower, which would cause abnormalities in the subsequent processing.

[0138] The following describes an embodiment of the apparatus described in this application, which can be used to execute a low-Earth orbit satellite terminal receiver synchronization method as described in the above embodiments of this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method described in the above applications.

[0139] Reference Figure 6 As shown, a low-Earth orbit satellite terminal receiver synchronization implementation apparatus 600 according to an embodiment of this application includes: The frame header detection unit 601 is used to perform frame header detection on the received baseband signal using the superframe header sequence and the posterior detection integral algorithm to obtain the superframe signal. Gain unit 602 is used for digital AGC of superframe signals; The estimation and compensation unit 603 is used to estimate and compensate the frequency offset of the superframe signal after digital AGC. The frame tail detection unit 604 is used to perform frame tail detection on the compensated superframe signal using the local postcode sequence and the a posteriori detection integral algorithm to obtain the superframe symbol. The first segmentation unit 605 is used to segment the superframe symbol; Estimation unit 606 is used to estimate the timing error of segmented data; The second segmentation unit 607 is used to perform symbol segmentation processing based on the timing error; The symbolic interpolation unit 608 is used to perform symbolic interpolation on the data after symbolic segmentation. The synchronization control and length limiting unit 609 is used to control the symbol synchronization output of the data after symbol interpolation and to limit the superframe length.

[0140] like Figure 7 As shown, this application embodiment also provides an electronic device 700, including a memory 710, a processor 720, and a computer program 711 stored in the memory 710 and executable on the processor. When the processor 720 executes the computer program 711, it implements the steps of the above-mentioned low-orbit satellite terminal receiver synchronization method.

[0141] Since the electronic device described in this embodiment is the device used to implement the low-orbit satellite terminal receiver synchronization device in the embodiments of this application, those skilled in the art can understand the specific implementation method and various variations of the electronic device in this embodiment based on the method described in the embodiments of this application. Therefore, how the electronic device implements the method in the embodiments of this application will not be described in detail here. Any device used by those skilled in the art to implement the method in the embodiments of this application falls within the scope of protection of this application.

[0142] In practice, when the computer program 711 is executed by the processor, it can implement any of the embodiments corresponding to the first aspect.

[0143] Figure 8 A schematic diagram of the structure of a computer system suitable for implementing the electronic device of the present application is shown.

[0144] It should be noted that, Figure 8 The computer system 800 of the electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0145] like Figure 8 As shown, the computer system 800 includes a Central Processing Unit (CPU) 801, which can perform various appropriate actions and processes based on programs stored in Read-Only Memory (ROM) 802 or programs loaded from storage portion 808 into Random Access Memory (RAM) 803, such as performing the methods described in the above embodiments. The RAM 803 also stores various programs and data required for system operation. The CPU 801, ROM 802, and RAM 803 are interconnected via a bus 804. An Input / Output (I / O) interface 805 is also connected to the bus 804.

[0146] The following components are connected to I / O interface 805: an input section 806 including a keyboard, mouse, etc.; an output section 807 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 808 including a hard disk, etc.; and a communication section 809 including a network interface card such as a LAN (Local Area Network) card, modem, etc. The communication section 809 performs communication processing via a network such as the Internet. A drive 810 is also connected to I / O interface 805 as needed. A removable medium 811, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on drive 810 as needed so that computer programs read from it can be installed into storage section 808 as needed.

[0147] Specifically, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 809, and / or installed from removable medium 811. When the computer program is executed by central processing unit (CPU) 801, it performs various functions defined in the system of this application.

[0148] It should be noted that the computer-readable medium shown in the embodiments of this application can be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such transmitted data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to wireless, wired, etc., or any suitable combination thereof.

[0149] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. Each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0150] The units described in the embodiments of this application can be implemented in software or hardware, and the described units can also be located in a processor. The names of these units do not necessarily limit the specific unit itself.

[0151] In another aspect, this application also provides a computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the low-Earth orbit satellite terminal receiver synchronization method described in the above embodiments.

[0152] In another aspect, this application also provides a computer-readable medium, which may be included in the electronic device described in the above embodiments; or it may exist independently and not assembled into the electronic device. The computer-readable medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to implement the low-Earth orbit satellite terminal receiver synchronization method described in the above embodiments.

[0153] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to the embodiments of this application, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0154] Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, touch terminal, or network device, etc.) to execute the methods according to the embodiments of this application.

[0155] Other embodiments of this application will readily conceive of by those skilled in the art upon consideration of the specification and practice of the embodiments disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. It should be understood that this application is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A method for synchronizing a low-Earth orbit satellite terminal receiver, characterized in that, include: Using the superframe header sequence, a posterior detection integral algorithm is employed to perform frame header detection on the received baseband signal to obtain the superframe signal; Digital AGC for superframe signals; Frequency offset estimation and compensation are performed on the superframe signal after digital AGC. Using the local postcode sequence, a post-hoc detection integral algorithm is employed to perform frame tail detection on the compensated superframe signal to obtain the superframe symbol; The superframe symbol is segmented, and the timing error of the segmented data is estimated. Perform symbol segmentation processing based on the timing error; Perform symbolic interpolation on the data after symbolic segmentation; Perform symbol synchronization output control and superframe length limitation on the data after symbol interpolation; The symbol segmentation process based on the timing error includes: Based on the timing error, calculate the reference sampling points for the segmented data; Symbol segmentation is performed based on the aforementioned benchmark sampling points.

2. The method according to claim 1, characterized in that, The process of using a superframe header sequence and employing a posterior detection integral algorithm to perform frame header detection on the received baseband signal to obtain the superframe signal includes: Block-based coherent integration: using the superframe header sequence as the reference signal, and with length... The signal is divided into several sub-block correlation windows. The baseband signal is convolved with the sub-block correlation windows in a relatively sliding manner. The signal power after convolution calculation of all sub-block correlation windows is accumulated to obtain the convolution power sum. Detection threshold calculation: Remove the beginning and end parts of the convolution power sum to obtain a new convolution power sum; calculate the threshold and perform threshold delay processing; perform pseudo-peak filtering on the delayed threshold and truncate the threshold a second time to obtain a new threshold; calculate the difference between the new convolution power sum and the new threshold to obtain a comparison signal. Synchronization position search: The synchronization position is detected based on the comparison signal and the valid synchronization points are filtered; the precise frame synchronization point is found from the valid synchronization points to obtain the superframe signal.

3. The method according to claim 1, characterized in that, The digital AGC of the superframe signal includes: First, the average power is calculated based on a certain length of sampled data. Then, the square root of the power value is taken to obtain the amplitude value. The amplitude value is normalized and its reciprocal is taken to obtain the gain coefficient. Finally, the gain coefficient is multiplied by the superframe signal to adjust the amplitude of the signal.

4. The method according to claim 1, characterized in that, The frequency offset estimation and compensation of the superframe signal after digital AGC includes: Synchronize the frame header symbols of the superframe signal after digital AGC to obtain synchronization data; The first and second coarse frequency offset estimates are performed on the synchronized data. The sum of the first coarse frequency offset estimation result and the second coarse frequency offset estimation result is taken as the final frequency offset estimate; Compensation is performed using the final frequency offset estimate.

5. The method according to claim 4, characterized in that, The process of synchronizing frame header symbols includes: Define the baseband symbol data used for timing error estimation; Based on the baseband symbol data, the timing error is calculated using the maximum likelihood forward timing estimation method, and the symbol interpolation is performed using the parabolic interpolation method with the Farrow structure.

6. The method according to claim 4, characterized in that, The process of performing the first coarse frequency offset estimation includes: The synchronization data is correlated with the frame header reference signal to obtain the signal. ; Based on signal Calculate the autocorrelation function using the baseband symbol rate SRbb and control parameter N. and smoothing coefficient ; Based on autocorrelation function and smoothing coefficient The frequency difference is calculated using weighted phase difference. ; Utilizing frequency difference Frequency offset compensation is performed on the synchronization data to obtain the data symbols. .

7. The method according to claim 6, characterized in that, The process of performing the second coarse frequency offset estimation includes: The data symbols are segmented and merged, with a merge length of [length missing]. The merged data is denoted as signal. ; Based on signal Calculate the autocorrelation function using the baseband symbol rate SRbb and control parameter N. and smoothing coefficient ; Based on autocorrelation function and smoothing coefficient The frequency difference is calculated using weighted phase difference. .

8. The method according to claim 1, characterized in that, The step of using a local postcode sequence and employing a post-hoc detection integral algorithm to perform frame tail detection on the compensated superframe signal to obtain the superframe symbol includes: Using the local postcode sequence as a reference signal, the compensated superframe signal is subjected to block coherent integration, detection threshold calculation, and synchronization position search to form the superframe symbol after frame synchronization.

9. The method according to claim 1, characterized in that, The step of performing symbolic interpolation on the symbolically segmented data includes: Based on the symbol-segmented data, the optimal sampling point interpolation algorithm with the Farrow structure is used to interpolate the optimal sampling point data for a single symbol rate.

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