Configurable computing architecture based on subarrays

Abstract

The application discloses a configurable computing architecture based on a subarray, and belongs to the technical field of computing, calculation or counting. First, a hardware architecture capable of dynamically adjusting the size and connection mode of a subarray is designed, so that the utilization rate of a PE array and task adaptability are improved; second, a design space exploration method is designed, which can determine the array size according to the utilization rate and throughput of the PE array, and further improve the computing efficiency. The configurable scheme of the computing architecture proposed in the application is simple to apply, can effectively improve the hardware utilization rate and system throughput, and is suitable for diversified neural network computing tasks.

Description

Technical Field

[0001] This invention relates to integrated circuit technology and discloses a configurable computing architecture based on subarrays, belonging to the technical field of computing, calculation, or counting. Background Technology

[0002] In recent years, wearable smart health monitoring devices have garnered significant attention due to their ability to monitor human health in real time and automatically detect abnormalities. Compared to traditional health monitoring devices, these devices integrate the ability to detect and analyze physiological signals, enabling the detection of abnormalities in biomedical signals such as electrocardiograms (ECG), electroencephalograms (EEG), and electromyograms (EMG), alerting users to potential health problems. ECG, by observing the heart's electrical activity to diagnose heart rate types, can provide crucial information on the progression of myocardial infarction, the presence of various arrhythmias, and the impact of hypertension. EEG, primarily using scalp electrodes to capture electrical activity in the cerebral cortex, detects the functional integrity of the brain, thus helping doctors detect neurological and pathological conditions such as headaches and dizziness, epilepsy, and brain tumors. EMG, by recording and analyzing signals generated by skeletal muscle electrical activity, is widely studied in applied research, physical therapy, and exercise training.

[0003] With the development of deep learning, recognition algorithms based on convolutional neural networks (CNNs) have been widely applied to the detection and classification of physiological signals due to their ability to integrate feature extraction and classification. This has significantly improved accuracy and saved on feature engineering work. However, deep learning neural networks have high computational complexity, making them difficult to apply to edge computing. To address this issue, researchers have conducted research on neural network accelerators to accelerate the computation of neural networks in artificial intelligence applications. However, existing neural network accelerators are customized for specific types of physiological signals and are only suitable for detecting one type of physiological signal, lacking flexibility. To address this problem, configurable accelerators supporting the detection of multiple physiological signals are now available in academia. Compared with traditional deep learning accelerators for physiological signal detection, these accelerators can simultaneously detect and analyze different biomedical signals such as ECG, EEG, and EMG.

[0004] Currently, there is considerable research on configurable accelerators in the industry. Based on supported configuration layers, they can be divided into computational architecture, dataflow, and computational units. The computational architecture layer can improve the resource utilization of different convolutional neural networks by reconfiguring hardware computing resources to support highly scalable and efficient mapping methods. However, current configurable CNN accelerators supporting various physiological signal detection lack in-depth analysis and research on computational architecture configuration strategies, and there is still significant room for optimization in terms of accelerator energy efficiency. Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of the aforementioned background technology by providing a configurable computing architecture based on subarrays. This involves designing a hardware architecture that dynamically adjusts the size and connection method of the subarrays, thereby improving the utilization and task adaptability of the PE array. Furthermore, a spatial exploration method is designed to determine the array size based on the PE array utilization and throughput, further enhancing computational efficiency. Ultimately, this achieves high computational utilization and hardware throughput, solving the technical problem of low computational utilization of PE arrays in neural network accelerators across different scenarios. This fulfills the invention's objective of improving the computational utilization of convolutional neural networks supporting various detection tasks.

[0006] To achieve the above-mentioned objectives, the present invention employs the following technical solution:

[0007] The subarray-based configurable computing architecture includes: R×C subarrays, each containing M×N PE units. The subarrays are interconnected, and the PE units within each subarray are connected. The overall size of the configurable computing architecture, R×C, is determined based on the performance metrics of the undivided configurable computing architecture accelerator. The size of the subarray, M×N, is determined based on the utilization rate of the divided configurable computing architecture accelerator. R, C, M, and N are all positive integers, M≤R, and N≤C.

[0008] As a further optimization of the subarray-based configurable computing architecture, the overall size R×C of the configurable computing architecture is determined based on the performance metrics of the unblocked configurable computing architecture accelerator. Specifically, under given resource constraints, the weighted results of the utilization rate and energy efficiency of the unblocked configurable computing architecture accelerator under different overall size values ​​are calculated as scores for different overall size values, and the overall size value with the highest score is selected as the overall size of the configurable computing architecture.

[0009] As a further optimization of the subarray-based configurable computing architecture, the subarray size M×N is determined based on the accelerator utilization of the partitioned configurable computing architecture, specifically:

[0010] Utilization of configurable computing architecture accelerators after computational partitioning ,in, Here, OX represents the accelerator utilization of the configurable computing architecture after partitioning, R and C represent the length and width of the configurable computing architecture, channel represents the number of output channels for the feature map, and conf represents the partitioning coefficient. This indicates the rounding up operation;

[0011] Select the subarray size that minimizes the partitioning coefficient when the accelerator utilization of the configurable computing architecture reaches a set value.

[0012] As a further optimization of the subarray-based configurable computing architecture, the configurable computing architecture operates in a distributed or centralized mode under the action of configuration instructions. In the distributed mode, the subarrays in the configurable computing architecture are interconnected and work in parallel according to a determined subarray size. In the centralized mode, the PE units in the configurable computing architecture are connected to form a pulsating array and then perform collaborative computing.

[0013] As a further optimization of the subarray-based configurable computing architecture, the subarrays are interconnected via configurable switches in the vertical and horizontal directions.

[0014] As a further optimization of the subarray-based configurable computing architecture, the PE cells within each subarray are connected by configurable vertical and horizontal switches.

[0015] As a further optimization of the subarray-based configurable computing architecture, the subarray transposes the input feature map laterally and transposes the PE cell computation results longitudinally.

[0016] As a further optimization of the subarray-based configurable computing architecture, given the resource constraints, the upper limits of R and C are set to the total number of multipliers on the development board.

[0017] As a further optimization of the subarray-based configurable computing architecture, the weighted expression for calculating the accelerator utilization and energy efficiency of the unpartitioned configurable computing architecture under different overall scale values ​​is as follows: , , , ,in, For accelerator utilization in unblocked configurable computing architectures, The accelerator efficiency is defined by the unblocked configurable computing architecture, where OX is the output feature map size of the configurable computing architecture, R and C are the length and width of the configurable computing architecture, and channel is the number of output feature map channels. The average throughput of the overall configurable computing architecture accelerator without partitioning. Energy consumption for un-blocked configurable computing architecture accelerators. This represents the total number of computational operations required for the accelerator to complete all convolution operations. The time required for the accelerator to complete all convolution operations. This represents the total number of computational operations required for each convolutional layer, i.e., the computational cost of each layer. This represents the number of cycles consumed per round of computation for an unblocked configurable computing architecture accelerator. Calculate the number of computation rounds required for each convolutional layer. For frequency.

[0018] As a further optimization of the subarray-based configurable computing architecture, when the utilization of the configurable computing architecture is less than a set value, the configuration command switches the configurable computing architecture to work in a centralized working mode; otherwise, the configuration command controls the configurable computing architecture to work in a distributed working mode.

[0019] The present invention, by adopting the above technical solution, has the following beneficial effects:

[0020] (1) This invention proposes a configurable computing architecture based on subarrays and designs a hardware architecture that can dynamically adjust the size and connection method of subarrays, which can improve the utilization rate and task adaptability of PE arrays.

[0021] (2) The present invention designs a design space exploration method. First, the overall size of the array is determined based on the utilization rate and throughput of the PE array to further improve the computational efficiency. Then, the size of the subarray is determined based on the utilization rate of the subarray, which can achieve a high computational utilization rate and hardware throughput. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a subarray-based configurable computing architecture provided in one embodiment of the present invention.

[0023] Figure 2 This is a circuit block diagram of a PE unit provided in one embodiment of the present invention.

[0024] Figure 3 This is a schematic diagram of a centralized computing model provided in one embodiment of the present invention.

[0025] Figure 4 This is a schematic diagram of a distributed computing mode provided in one embodiment of the present invention. Detailed Implementation

[0026] Embodiments of the present invention are described in detail below. Examples of the described embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0027] One embodiment of the present invention provides a subarray-based configurable computing architecture as follows: Figure 1 As shown, the architecture comprises R×C subarrays, each a PE set containing M×N PE units. The subarrays are flexibly interconnected via configurable vertical and horizontal switches, and the PE units within each subarray are also flexibly connected via these switches. The overall size of the configurable computing architecture, R×C, is determined based on the utilization and throughput of the unpartitioned configurable computing architecture accelerator. The size of the PE subarrays, M×N, is determined based on the utilization of the partitioned configurable computing architecture.

[0028] In one embodiment of the present invention, a method is provided. Figure 2 The PE unit shown is the smallest execution unit in the subarray, capable of implementing different computational architecture modes according to configuration information. Each PE unit contains a computation unit, three registers, and a multiplexer. The computation unit is primarily responsible for performing multiplication and accumulation operations on the input feature map and weights, and can configure different computational architecture modes for the input feature map and weight data according to control signals. The three registers are used to cache the input feature map, weight data, and intermediate results, respectively. The multiplexer is used to output the final result. The computation unit receives the input feature map and weight data from the convolutional neural network. The input feature map is propagated horizontally in each row of the subarray, meaning the feature map input to the previous PE unit propagates from left to right to the next PE unit. The computation result of the PE unit is propagated vertically in each column of the subarray, meaning the computation result output by the previous PE unit propagates from bottom to top to the next PE unit.

[0029] The overall size (R×C) of the configurable computing architecture is determined based on its utilization and throughput. Specifically, under given resource constraints, the scores of different overall sizes are ranked according to the accelerator evaluation metrics and their importance, and an appropriate overall size for the configurable computing architecture is selected. First, the overall size of the configurable computing architecture needs to be designed. This is done through simulation calculations of the utilization and energy efficiency ratio of the accelerators in the un-segmented configurable computing architecture. The formula for calculating the utilization of the un-segmented configurable computing architecture is: Where OX, R, C, and channel represent the output feature map size of the configurable computing architecture, the length and width of the configurable computing architecture, and the number of output channels for the feature map, respectively. Energy efficiency ratio is the ratio of throughput to energy consumption, where throughput represents the number of computational operations completed per unit time. In the throughput calculation process, it is necessary to first calculate the number of cycles consumed per round of computation in the configurable computing architecture and the number of computation rounds required for each convolutional layer. From this, the throughput of each layer and the average throughput can be calculated. Finally, the formula for calculating the overall average throughput of the unblocked configurable computing architecture accelerator is: ,in, This represents the total number of computational operations required for the accelerator to complete all convolution operations. The time required for the accelerator to complete all convolution operations. This represents the total number of computational operations required for each convolutional layer, i.e., the computational cost of each layer. This represents the number of cycles consumed per round of computation for an unblocked configurable computing architecture accelerator. Calculate the number of computation rounds required for each convolutional layer. For frequency. The final formula for calculating the energy efficiency of the unblocked configurable computing architecture accelerator is: The formula for calculating the score ranking is: ,in, Energy efficiency for accelerators of unpartitioned configurable computing architectures. Energy consumption for unblocked configurable computing architecture accelerators.

[0030] In one embodiment of this invention, under given resource constraints, the upper limit of R and C is set to the total number of multipliers on the development board. This total number needs to be determined based on the development board model; for example, the Xilinx-7 series development board has a total of 220 multipliers. After setting the network parameters and accelerator metrics, a design space exploration is performed. The specific exploration process is as follows: First, the range of values ​​for the number of rows C and columns R of the configurable computing architecture is determined. Second, evaluation metrics such as utilization and throughput of the accelerators in the configurable computing architecture are calculated under different values ​​of R and C. Finally, based on the evaluation metrics of the accelerators and their importance, the scores of the overall size R×C of the configurable computing architecture are ranked, and the overall size with the highest score is selected.

[0031] In one embodiment of the invention, the utilization rate of the configurable computing architecture accelerator after partitioning is provided. The calculation formula is: Where OX, R, C, channel, and conf represent the output feature map size of the configurable computing architecture, the length and width of the configurable computing architecture, the number of output channels for the feature map, and the block coefficient, respectively. This indicates a rounding up operation. The utilization rate of the configurable computing architecture accelerators is calculated for different subarray sizes. The subarray size that minimizes the partitioning coefficient while maintaining accelerator utilization above 90% is selected to ensure power saving in distributed computing architecture operation. The determined subarray size represents the scale of the centralized computing units in the PE (Physical Equipment) module.

[0032] After determining the subarray size M×N, the size and connection method of the subarray are dynamically adjusted by changing the number of centralized computing units in the PE array, based on the computational requirements of the neural network model. The system supports both distributed and centralized operating modes and can switch between them according to the subarray configuration mode signal in the instructions. For ease of explanation, the overall size of the configurable computing architecture is set to 16×8 in this invention. The configurable computing architecture can be divided into four independent 8×4 subarrays working in parallel, or all PE units can be integrated into a unified 16×8 pulsating array for collaborative computation. This scheme effectively balances computational efficiency and resource utilization, thereby reducing resource waste and improving system throughput.

[0033] See Figure 3 and Figure 4 The diagram illustrates the centralized and distributed computing modes within a subarray-based configurable computing architecture. The array employs a 2×2 subarray configuration, comprising four PE sets. Each PE set consists of 8×4 PE units, which are flexibly interconnected via configurable vertical and horizontal switches. The system supports two operating modes: when the configurable computing architecture utilization reaches or exceeds 90%, it switches to centralized computing mode, integrating all PE units into a unified 16×8 pulsating array for collaborative computing, as shown below. Figure 3 As shown; when the utilization rate of the configurable computing architecture is less than 90%, a distributed computing mode is adopted, dividing the configurable computing architecture into four independent 8×4 sub-arrays to work in parallel. Each sub-array independently processes the corresponding feature map data and weight data, such as... Figure 4 As shown in the figure, this scheme effectively balances computational efficiency and resource utilization, thereby reducing resource waste and improving system throughput.

[0034] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the specific embodiments described above. The specific embodiments and descriptions in the specification are merely for further illustrating the principles and preparation effects of the present invention. Various changes and modifications can be made to the present invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the claims and their equivalents.

Claims

1. A configurable computing architecture based on subarrays, characterized in that, include: The system comprises R×C subarrays, each containing M×N PE units. These subarrays are interconnected, and the PE units within each subarray are connected. The overall size of the configurable computing architecture, R×C, is determined based on the performance metrics of the un-blocked configurable computing architecture accelerator. The size of each subarray, M×N, is determined based on the utilization rate of the blocked configurable computing architecture accelerator. Where R, C, M, and N are all positive integers, M ≤ R, and N ≤ C. The overall size R×C of the configurable computing architecture is determined based on the performance metrics of the undivided configurable computing architecture accelerator. Specifically, under given resource constraints, the weighted results of the utilization rate and energy efficiency of the undivided configurable computing architecture accelerator under different overall size values ​​are calculated as scores for different overall size values. The overall size value with the highest score is selected as the overall size of the configurable computing architecture. The expression for calculating the weighted results of the utilization rate and energy efficiency of the undivided configurable computing architecture accelerator under different overall size values ​​is as follows: , , , ,in, For accelerator utilization in unblocked configurable computing architectures, The accelerator efficiency is defined by the unblocked configurable computing architecture, where OX is the output feature map size of the configurable computing architecture, R and C are the length and width of the configurable computing architecture, and channel is the number of output feature map channels. The average throughput of the overall configurable computing architecture accelerator without partitioning. Energy consumption for un-blocked configurable computing architecture accelerators. This represents the total number of computational operations required for the accelerator to complete all convolution operations. The time required for the accelerator to complete all convolution operations. This represents the total number of computational operations required for each convolutional layer, i.e., the computational cost of each layer. This represents the number of cycles consumed per round of computation for an unblocked configurable computing architecture accelerator. Calculate the number of computation rounds required for each convolutional layer. For frequency; The subarray size M×N is determined based on the utilization rate of the configurable computing architecture accelerator after partitioning, specifically: Calculate the utilization of the configurable computing architecture accelerator after the partitioning. ,in, For the accelerator utilization of the configurable computing architecture after partitioning, the conf partitioning factor is used. This indicates the rounding up operation. Select the subarray size that minimizes the partitioning coefficient when the accelerator utilization of the configurable computing architecture reaches a set value.

2. The configurable computing architecture based on subarrays according to claim 1, characterized in that, The configurable computing architecture operates in either a distributed or centralized mode under the influence of configuration instructions. In the distributed mode, the subarrays in the configurable computing architecture are interconnected and work in parallel according to a determined subarray size. In the centralized mode, the PE units in the configurable computing architecture are connected to form a pulsating array and then perform collaborative computing.

3. The configurable computing architecture based on subarrays according to claim 1, characterized in that, The subarrays are interconnected via configurable switches in the vertical and horizontal directions.

4. The configurable computing architecture based on subarrays according to claim 1, characterized in that, The PE units within each subarray are connected via configurable vertical and horizontal switches.

5. The configurable computing architecture based on subarrays according to claim 1, characterized in that, The subarray transduces the input feature map laterally and the PE unit calculation results transduced longitudinally.

6. The configurable computing architecture based on subarrays according to claim 1, characterized in that, The given resource constraint is to set the upper limits of R and C to the total number of multipliers on the development board.

7. The configurable computing architecture based on subarrays according to claim 2, characterized in that, When the utilization rate of the configurable computing architecture is less than a set value, the configuration command switches the configurable computing architecture to work in a centralized working mode; otherwise, the configuration command controls the configurable computing architecture to work in a distributed working mode.

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