A method for modeling and simulating a three-dimensional structure of an interdigital field effect transistor

Abstract

This invention belongs to the field of semiconductor technology and relates to a three-dimensional structural modeling and simulation method for interdigital field-effect transistors (FETs). The method involves starting a virtual machine, opening Sentaurus TCAD, entering the SWB interface, adding the SDE and Sdevice models, and setting simulation parameters. A 3D model structure is constructed, defining interdigital source and drain electrodes on both sides of the channel, performing meshing, and simulation to obtain the basic electrical characteristics of the interdigital FET. Parameters for indium oxide and tantalum oxide are set, along with the physical characteristics and mathematical models of the source, drain, and gate voltages, to obtain the electrical characteristics of the interdigital FET 3D model. Compared to 2D FET models, the simulation method for interdigital FET 3D models provided by this invention can more realistically simulate the manufacturing of interdigital FET 3D devices, saving development time and costs, and facilitating the prediction of the chip's basic performance before prototype fabrication.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a three-dimensional structural modeling and simulation method for interdigitated field-effect transistors. Background Technology

[0002] A field-effect transistor (FET) is a voltage-controlled semiconductor device that uses an electric field to control the current in its conductive channel. Its core structure typically includes three electrodes: a source, a drain, and a gate. By applying a voltage to the gate, charge carriers (electrons or holes) can be induced or depleted in the semiconductor material, effectively modulating the width and resistance of the conductive channel between the source and drain, ultimately achieving precise control over the magnitude of the current flowing from the source to the drain.

[0003] Interdigitated source-drain field-effect transistors (FETs) offer significant advantages over traditional planar source-drain structures. Their unique interlaced comb-like electrode design substantially increases the total length of the channel edges, effectively expanding the effective channel width and thus significantly improving transconductance and current drive capability within the same chip area. The increased electrode-electrolyte contact area significantly enhances signal response sensitivity in biochemical sensing applications (such as ISFETs), making them particularly suitable for trace substance detection. These characteristics make interdigitated structures highly valuable in high-performance, miniaturized, and high-sensitivity sensor integration.

[0004] 2D models, based on axisymmetric or planar simplification assumptions, offer high computational efficiency and are suitable for rapid parameter scanning and preliminary design. However, 2D models cannot accurately capture three-dimensional effects or construct complex polygonal structures, such as interdigitated electrodes, from a single perspective. In contrast, 3D models can fully describe the device geometry and boundary conditions, accurately simulate complex scenarios, and quantify edge effects.

[0005] Using interdigitated electrodes in FET devices and directly constructing conductive channels within their gaps significantly improves sensor performance. However, due to limitations in some semiconductor simulation software, there are still certain restrictions on the parameter settings for some commonly used materials not included in the software library. Sentaurus TCAD, as a semiconductor device simulation platform, has certain advantages in parameter settings for some commonly used materials not included in the software library. By using the material's basic properties and additional calculation formulas, these materials can be input into the simulation platform to simulate them. Summary of the Invention

[0006] This invention addresses the problems existing in the three-dimensional structural modeling of traditional field-effect transistors by proposing a novel three-dimensional structural modeling and simulation method for interdigitated field-effect transistors.

[0007] To achieve the above objectives, the present invention is implemented using the following technical solution: A three-dimensional structural modeling and simulation method for an interdigitated field-effect transistor, wherein the field-effect transistor includes a channel, and a source and a drain are disposed on both sides of the channel, the source and the drain being interdigitated.

[0008] The steps for 3D structural modeling and simulation are as follows: (1) Start the virtual machine VMware Workstation, open Sentaurus TCAD, open the terminal to enter the swb operation interface, add the Sde model and Sdevice model and set the relevant simulation parameters in the jEdit editor.

[0009] (2) Construct a 3D model structure of an interdigitated field-effect transistor, including substrate, bottom oxide layer, channel, top oxide layer, Stern layer, source, drain, gate and electrolyte.

[0010] (3) Define interdigitated source and drain on both sides of the channel, including finger length, finger width and finger spacing, and define contacts on the source and drain, and set the electrode material to metal aluminum or gold.

[0011] (4) In the 3D model, select different regions of the channel, source, drain and substrate and dop them to obtain simulation models of different types of interdigitated FETs, including N-type and P-type.

[0012] (5) Mesh the 3D model of the interdigital field-effect transistor, including setting the geometric model of the substrate, channel and oxide layer, and then save it.

[0013] (6) Start the simulation and view the 3D structure of the interdigitated field-effect transistor in Sentaurus Visual, including the region distribution, grid settings, doping concentration and doping type.

[0014] (7) Obtain the basic electrical characteristics of the interdigital field-effect transistor. Define the channel and top oxide layer materials as indium oxide and tantalum oxide. Set the parameters of indium oxide and tantalum oxide in Sdevice, including the refractive index model, thermal conductivity model, volumetric heat capacity model, band gap model and resistivity model. Then set the physical characteristics and mathematical models of the source, drain and gate voltages to obtain the electrical characteristics of the interdigital FET 3D model.

[0015] The 3D model structure of the interdigitated FET described in step (2) consists of, from bottom to top, a substrate, a bottom oxide layer, a channel, a top oxide layer, a Stern layer, an electrolyte region, and a gate electrode. The source and drain electrodes are located on both sides of the channel. The channel region can use semiconductor materials such as In2O3, CNT, WeS2, and polysilicon; the electrode region can use conductor materials such as Au, Al, and Cu; and the oxide layer can use insulating materials such as SiO2, Y2O3, Ta2O3, GeO2, HfO2, and Al2O3. Its dimensions include the length, height, and width of the substrate, bottom oxide layer, channel, electrical double layer, electrolyte region, gate electrode, and source / drain electrodes. The calculation formula for the electrolyte buffer model is as follows: , In the formula, N C Conduction band density at 300K (cm²) -3 ), N V Valence band density at 300K (cm²) -3 ), N A Avogadro number (mol) -1 E g denoted as the band gap of the semiconductor (eV), k is the Boltzmann constant (J / K), and T is the absolute temperature (K).

[0016] Preferably, the contact between the metal and semiconductor described in step (3) can form a Schottky contact with a potential barrier region or an ohmic contact without a potential barrier. The definitions of the two contact types need to be defined in the Sdevice→Electrode module. Specifying Schottky indicates a Schottky contact, and then the work function of the metal needs to be defined. Here, the metal-semiconductor contact is defined as an ohmic contact, and the source and drain need to be set with finger length, finger width, and finger spacing. The doping of different regions described in step (4) is to simulate the morphology of some wells formed by process steps such as ion implantation, annealing, diffusion, and epitaxy in real semiconductor processes. It mainly includes doping of the substrate, channel, and source and drain. The doping types include P doping (Boron) and N doping (Phosphorus, Arsenic).

[0017] Preferably, the meshing settings in step (5) include defining the mesh by window, by region name, by material name, and by material boundary. The mesh described in step (5) is an important component for Sdevice to perform calculations and generate doping information. The mesh division is also extremely important, as its density determines the simulation speed and accuracy. For the substrate and the bottom oxide layer, a dense mesh is not required; a sparse mesh is sufficient. However, for the semiconductor region and the contact area between the semiconductor region and the insulating layer region, a precise mesh needs to be set to achieve accurate simulation.

[0018] Preferably, Sentaurus Visual, mentioned in step (6), is a post-processing and visualization tool that can graphically present complex simulation data, including material region distribution, mesh settings, doping concentration and type, etc., which helps to quickly understand and analyze the physical characteristics of the device and optimize design and process parameters. In step (6), the region distribution can be viewed in Visibility in Materials or Regions; the mesh settings can be viewed in Mesh in Materials; the doping type can be viewed in ArsenicActiveConcentration, BoronActiveConcentration and PhosphorusActiveConcentration in Scalars; and the doping concentration can be viewed in DopingConcentration in Scalars.

[0019] Preferably, the IV characteristic curve of the FET model described in step (7) is used to calculate the source-drain current, threshold voltage, switching current ratio, subthreshold swing, field-effect mobility, transconductance, and other performance indicators of the model; these performance indicators are used to evaluate the quality of the simulation model. The source-drain current is the response signal of the FET device; the threshold voltage represents the critical gate voltage required for the FET to transition from the off state (subthreshold region) to the on state (strong inversion region). The tangent line is drawn at the point with the largest slope in the transfer characteristic curve of the FET model for electrolytes with different pH values, and the intersection of the tangent line and the x-axis is the threshold voltage. The smaller the threshold voltage, the smaller the gate voltage required to turn on the FET device; the switching current ratio is the ratio of the FET's current in the on state (V0). G >V T ) and off state (V G <V TThe ratio of drain current to switching current is the ratio of the drain current to the switching current. A larger switching current ratio indicates better device performance. Subthreshold swing (SS) refers to the gate voltage required to increase the source-drain current by an order of magnitude in the subthreshold region of the transfer characteristic curve. It reflects the ability of the gate voltage to regulate the source-drain current and the switching rate of the device between turn-on and turn-off. Field-effect mobility represents the average drift velocity of charge carriers in the channel under a unit electric field. It is an effective measure of the actual migration ability of charge carriers in the channel. Transconductance is the differential sensitivity of the drain current to the gate voltage, reflecting the ability of the gate voltage to control the current.

[0020] The calculation formula is as follows: , Where I DS For source and drain current, V GS This refers to the gate voltage. When the subthreshold swing is smaller, the gate voltage regulation capability will be enhanced accordingly, and the switching rate will also be accelerated.

[0021] The formula for calculating field-effect mobility is as follows: , Where I DS For source and drain current, V GS Where L is the gate voltage, C is the channel length, and C is the channel voltage. B It is the gate dielectric capacitance per unit area, V DS It refers to the source-drain voltage. Field-effect mobility determines the conductivity of a semiconductor device; the higher the field-effect mobility, the better the device's performance.

[0022] The formula for calculating transconductance is as follows: .

[0023] Where I DS For source and drain current, V GS This is the gate voltage.

[0024] In step (7), the basic electrical characteristics of the interdigitated field-effect transistor include output characteristics, transfer characteristics, threshold voltage extraction, subthreshold swing, switching current ratio and field-effect mobility; the physical characteristics settings of the source, drain and gate voltages include the determination of the Fermi level, mobility model and recombination mechanism model; the mathematical model settings include starting the extrapolation algorithm, setting the upper limit of the number of iterations, and clarifying the response strategy for solution failure.

[0025] As a preferred option, the refractive index model formula in step (7) is as follows: refractiveindex() = refractiveindex * (1 + alpha * (T-Tpar)).

[0026] Where, refractiveindex() is the final refractive index, refractiveindex is the material's basic refractive index measured at reference temperature Tpar, alpha is the material's refractive index temperature coefficient (1 / K), T is the ambient temperature (K), and Tpar ​​is the reference temperature (K).

[0027] The formula for the thermal conductivity model is as follows: kappa() = kappa + kappa_b * T + kappa_c * T 2 .

[0028] Where kappa() is the final thermal conductivity, kappa is the coefficient of the constant term in the thermal conductivity polynomial (W / (K·cm)), and kappa_b is the coefficient of the first-order temperature term in the thermal conductivity polynomial (W / (K·cm)). 2 ·cm), kappa_c is the coefficient of the second-order temperature term in the thermal conductivity polynomial (W / (K)). 3 ·cm)).

[0029] The formula for the volumetric heat capacity model is as follows: cv() = cv + cv_b * T + cv_c * T 2 + cv_d * T 3 .

[0030] Where cv() is the final volumetric heat capacity, and cv is the coefficient of the constant term in the heat capacity polynomial (J / (K·cm)). 3 ), cv_b(J / (K 2 ·cm 3 ), cv_c (J / (K 3 ·cm 3 ), cv_d (J / (K 4 ·cm 3 )) are the coefficients of the temperature-dependent terms in the heat capacity polynomial, which control the linear, quadratic, and cubic temperature dependencies, respectively; The bandgap model formula is as follows: Eg = Eg0 + dEg0 + alpha * Tpar 2 / (beta + Tpar) - alpha * T 2 / (beta +T).

[0031] Where Eg is the final band gap, Eg0 is the intrinsic band gap width of the material measured at the reference temperature Tpar ​​(eV), dEg0 is the band gap narrowing correction term (eV), and alpha (eV·K) is the band gap narrowing correction term. -1) and beta (K) are the temperature coefficients of the material, and Tpar ​​is the reference temperature (K).

[0032] The formula for the resistivity model is as follows: Resist(T) = Resist0 * ( 1 + TempCoef * ( T - 273 ) ).

[0033] Where Resist(T) is the final resistivity, Resist0 is the basic resistivity of the material measured at the reference temperature (Ω·cm), TempCoef is the temperature coefficient of resistivity of the material (1 / K), and T is a fixed value of 300K.

[0034] Compared with the prior art, the advantages and positive effects of the present invention are as follows: Sentaurus TCAD is a comprehensive toolkit for semiconductor process and device simulation. Compared to the traditional Silvaco TCAD simulation tool, it significantly optimizes algorithm convergence and parallel computing capabilities in 3D modeling and simulation. This invention first defines the substrate, then the bottom oxide layer, followed by the interdigitated source / drain, selecting appropriate finger lengths, widths, and spacing. Finally, it defines the channel layer, bottom oxide layer, Stern layer, electrolyte layer, and gate. First, the electrolyte region is set as a semiconductor material, and then its dielectric constant, electron affinity, band gap, and electron and hole state densities are defined. Next, the channel region is defined as a semiconductor material, and the top oxide layer region is defined as an insulator material. Then, its dielectric constant, refractive index, lattice heat capacity model, thermal conductivity, band gap, electron mobility, and hole mobility are defined to construct a basic interdigitated FET 3D model structure, realizing the simulation of its basic characteristics and electrolytes with different pH values.

[0035] This invention provides a three-dimensional structural modeling and simulation method for interdigital field-effect transistors (FETs). It uses the Sde model to obtain a three-dimensional FET model containing interdigital electrodes. Then, basic simulated voltage conditions are set in the Sdevice model to obtain the output and transfer characteristic curves of the interdigital FET. By comparing the designed 3D model with different material regions (substrate, channel, electrode, and insulating layer dimensions), different doping types (P-doping, N-doping) and concentrations, different mesh optimizations, and different material conditions, the FET performance is observed. Compared to 2D FET models, the simulation method of the interdigital FET 3D model provided by this invention can more realistically simulate the manufacturing of interdigital FET 3D devices, saving development time and costs, and facilitating the prediction of the chip's basic performance before prototype fabrication. Attached Figure Description

[0036] Figure 1This is a structural diagram of the three-dimensional structural modeling and simulation method of the interdigitated field-effect transistor according to an embodiment of the present invention, wherein 1 is the substrate, 2 is the bottom oxide layer, 3 is the source and drain, 4 is the channel, 5 is the top oxide layer, 6 is the Stern layer, 7 is the electrolyte region, and 8 is the gate.

[0037] Figure 2 The output characteristic curve is a result of the three-dimensional structural modeling and simulation method of the interdigitated field-effect transistor according to an embodiment of the present invention.

[0038] Figure 3 The result diagram (transfer characteristic curve) is a three-dimensional structural modeling and simulation method of the interdigitated field-effect transistor according to an embodiment of the present invention. Detailed Implementation

[0039] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described below with reference to specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0040] Numerous specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways than those described herein, and therefore the invention is not limited to the specific embodiments disclosed in the following specification.

[0041] Example 1 This invention provides a specific method for three-dimensional structural modeling and simulation of interdigitated field-effect transistors, including the following steps.

[0042] (1) Start the virtual machine VMware Workstation, open Sentaurus TCAD, open the terminal to enter the Swb operation interface, and add the Sde model and Sdevice model.

[0043] (2) Set the three-dimensional structural parameters of the interdigital FET, wherein the substrate length is 1.2μm, width is 1μm, height is 1μm, bottom oxide layer length is 1.2μm, width is 1μm, height is 0.02μm, channel height is 0.05μm, top oxide layer length is 1.2μm, width is 1μm, height is 0.015μm, Stern layer length is 1.2μm, width is 1μm, height is 0.01μm, electrolyte region length is 1.2μm, width is 1μm, height is 1μm, gate length is 0.4μm, width is 0.4μm, height is 0.05μm; the interdigital electrode finger length is 0.78μm, finger width is 0.048μm, finger pitch is 0.02μm, and finger height is 0.05μm.

[0044] (3) Define contact regions on the source, drain, and gate surfaces. The contact regions are ohmic contacts and no work function needs to be defined.

[0045] Then, the channel region, substrate region, and source / drain region are doped. The doping types are mainly P-doping and N-doping. In this embodiment, N-doping is used in the channel region and source / drain region, and the doping concentration is set to 10%. 16 cm -3 The substrate region is p-doped with Boron, and the doping concentration is set to 10. 16 cm -3 .

[0046] (4) Mesh partitioning for different regions of the interdigitated FET: Defining the mesh by window defines the mesh for the entire device in a holistic manner, which is feasible for devices that do not require precise meshing; dividing the mesh by region name involves partitioning different regions under a custom name (the channel is partitioned by region, first selecting the channel region, then setting the maximum mesh spacing along the X, Y, and Z axes to 0.0025, the minimum mesh spacing along the X, Y, and Z axes to 0.0025, and finally optimizing the mesh at the interface by setting the mesh spacing multiplier to 1); dividing the mesh by material name involves partitioning the mesh for the same material in the entire device (the substrate is partitioned by material region, first setting the partitioned region...). The material name is set first, followed by setting the maximum grid spacing along the X, Y, and Z axes to 0.01 and the minimum grid spacing along the X, Y, and Z axes to 0.005. For the oxide layer, the mesh is divided by material region. First, the material name of the region is set, then the maximum grid spacing along the X, Y, and Z axes to 0.05 and the minimum grid spacing along the X, Y, and Z axes to 0.01. Meshing by material boundary involves selecting two different materials and meshing at their boundaries, defining bilateral spread (first selecting the channel and oxide layer material names, setting the initial grid spacing to 0.002, increasing the grid spacing by 1.5 times, setting the maximum grid spacing to 0.0025, and finally defining the mesh layout on both sides of the interface). This step first meshes different regions, then meshes the channels and oxide layer according to material boundaries.

[0047] (5) Start the SDE simulation, open SentaurusVisual to view the 3D structure and various parameters. For different material regions, view the Visibility in Materials or Regions; for different regions, view the mesh division in Materials; for the same doping type, view the ArsenicActiveConcentration, BoronActiveConcentration and PhosphorusActiveConcentration in Scalars; and for the overall device doping concentration, view the DopingConcentration in Scalars.

[0048] (6) Next, the pH buffer solution is redefined. First, the pH buffer solution is classified as a semiconductor material, and the material name is set to Electrolyte. Then, the material properties of the pH buffer solution are set, including the material's electrical dielectric constant and the conduction band density (cm³) at 300K. -3 )), Nv300 ​​(valence band density at 300K (cm) -3 The parameters include electron affinity (eV), band gap at 300K (eV), etc. In this embodiment, taking pH=5 as an example, the electrolyte region is first defined, with the dielectric constant set to 80, the electron affinity set to 3.9 eV, the band gap at 300K set to 1.5 eV, and the conduction band density at 300K set to 2.33 × 10⁻⁶. 24 The valence band density at 300K was set to 2.33 × 10⁻⁶. 28 The material name for the double layer is Stern, and the material type is semiconductor. The Stern layer is then defined at pH = 5, with a dielectric constant of 22.5, an electron affinity of 3.9 eV, a band gap of 1.5 eV at 300 K, and a conduction band density of 2.33 × 10⁻⁶ at 300 K. 24 The valence band density at 300K was set to 2.33 × 10⁻⁶. 28 Next, different pH buffer solutions were simulated using the Poisson-Boltzmann equation. By changing parameters such as Nc300 and Nv300, different pH buffer materials were obtained. The calculation formula for the electrolyte model is as follows: .

[0049] In the formula, N C Conduction band density at 300K (cm²) -3 ), N V Valence band density at 300K (cm²) -3 ), N A Avogadro number (mol) -1 E g denoted as the band gap of the semiconductor (eV), k is the Boltzmann constant (J / K), and T is the absolute temperature (K).

[0050] Next, based on the existing calculation formulas, materials not found in the software material library for this structure are defined, including refractive index, thermal conductivity, volumetric heat capacity, band gap, and resistivity.

[0051] The formula for the refractive index model is as follows: refractiveindex() = refractiveindex * (1 + alpha * (T-Tpar)).

[0052] Where refractiveindex() is the final refractive index, refractiveindex is the material's basic refractive index measured at reference temperature Tpar, alpha is the material's refractive index temperature coefficient (1 / K), T is the ambient temperature (K), and Tpar ​​is the reference temperature (K). The formula for the thermal conductivity model is as follows: kappa() = kappa + kappa_b * T + kappa_c * T 2 .

[0053] Where kappa() is the final thermal conductivity, kappa is the coefficient of the constant term in the thermal conductivity polynomial (W / (K cm)), kappa_b is the coefficient of the first temperature term in the thermal conductivity polynomial (W / (K^2 cm)), and kappa_c is the coefficient of the second temperature term in the thermal conductivity polynomial (W / (K^3 cm)). The formula for the volumetric heat capacity model is as follows: cv() = cv + cv_b * T + cv_c * T 2 + cv_d * T 3 .

[0054] Where cv() is the final volumetric heat capacity value, cv is the coefficient of the constant term in the heat capacity polynomial (J / (K cm^3)), cv_b (J / (K^2 cm^3)), cv_c (J / (K^3 cm^3)), and cv_d (J / (K^4 cm^3)) are the coefficients of the temperature-dependent terms in the heat capacity polynomial, which control the linear, quadratic, and cubic temperature dependence, respectively. The bandgap model formula is as follows: Eg = Eg0 + dEg0 + alpha * Tpar 2 / (beta + Tpar) - alpha * T 2 / (beta +T).

[0055] Where Eg is the final band gap, Eg0 is the intrinsic band gap width of the material measured at the reference temperature Tpar ​​(eV), dEg0 is the band gap narrowing correction term (eV), alpha (eV K^-1) and beta (K) are the temperature coefficients of the material, and Tpar ​​is the reference temperature (K). The formula for the resistivity model is as follows: Resist(T) = Resist0 * ( 1 + TempCoef * ( T - 273 ) ).

[0056] Where Resist(T) is the final resistivity, Resist0 is the basic resistivity of the material measured at the reference temperature (Ω·cm), TempCoef is the temperature coefficient of resistivity of the material (1 / K), and the value of T is 300K.

[0057] In the indium oxide material parameter settings, the isotropic dielectric constant is set to 9, and the anisotropic dielectric constant is set to 9; in the refractive index model (RefractiveIndex), the reference temperature (Tpar) is set to 300K, the refractive index (refractiveindex) (dimensionless) at the reference temperature is set to 2, and the temperature coefficient of refractive index (alpha) is set to 10. -4 (1 / K), carrier gain coefficient (a0) is 0, reference carrier concentration (N0) is 10 18 (cm -3 In the complex refractive index model, the fundamental real part (n_0) is 2 and the imaginary part (k_0) is 0. All coefficients in the wavelength dependence (Cn_lambda, Dn_lambda, Ck_lambda, Dk_lambda) are 0. The temperature coefficient (Cn_temp) of the real part of the refractive index in the temperature dependence is set to 10. -4 (1 / K); In the thermal conductivity model, the isotropic thermal conductivity is set to 0.1 (W / (K·cm)); In the bandgap model, the bandgap energy (Eg0) is set to 3 (eV), and the electron affinity energy (Chi0) is set to 4.5 (eV); In the resistivity model, the temperature-dependent resistivity (Resist0) is set to 1 (Ω·cm), and the temperature coefficient of resistivity (TempCoef) is set to 10. -3 (1 / K).

[0058] In the tantalum oxide material parameter settings, the static dielectric constant is set to 25, the high-frequency dielectric constant is set to 6.8, the anisotropic dielectric constant is set to 25, and the anisotropic high-frequency dielectric constant is set to 6.8. In the refractive index model (RefractiveIndex), the reference temperature (Tpar) is set to 300K, the refractive index (refractiveindex) (dimensionless) at the reference temperature is set to 2.1, and the temperature coefficient of refractive index (alpha) is set to 10. -4 (1 / K), carrier gain coefficient (a0) is 0, reference carrier concentration (N0) is 10 18 (cm -3 In the complex refractive index model, the fundamental real part (n_0) is 2.1, and the imaginary part (k_0) is 10. -4In the wavelength dependence, all coefficients (Cn_lambda, Dn_lambda, Ck_lambda, Dk_lambda) are 0, and in the temperature dependence, the temperature coefficient (Cn_temp) of the real part of the refractive index is set to 10. -4 (1 / K), Ck_carr is set to 0 (cm 2 Gamma_k_carr is set to 1, Cn_gain is set to 0, and Npar is set to 10. 18 (cm -3 In the thermal conductivity model, the isotropic and anisotropic thermal conductivities (kappa) are set to 0.045 (W / (K·cm)); in the volumetric heat capacity model, the lattice heat capacity (cv) is set to 2.3 (J / (K·cm)). 3 In the bandgap model, the bandgap energy (Eg0) is set to 4.2 eV, and the electron affinity (Chi0) is set to 4.0 eV. In the resistivity model, the temperature-dependent resistivity (Resist0) is set to 10. 12 (Ω·cm), resistivity temperature coefficient (TempCoef) is set to 10. -4 (1 / K).

[0059] (7) Next, set the parameters in Sdevice→Commands. First, define the file format, including Grid, Parameter, Plot, Current and Output.

[0060] Next, define the electrode conditions, setting the initial conditions for the source, drain, and gate voltages to 0 V, and setting the work function, resistance, and other conditions to 0.

[0061] Next, physical conditions are set, including the Fermi level, mobility models (involving the dependence of doping concentration on mobility, the effect of vertical electric field on mobility, and the saturation effect of mobility under high electric field), and recombination mechanism models (covering SRH recombination, Auger recombination, and interband recombination).

[0062] Next, the Plot model is set up, which includes electron / hole concentration, intrinsic carrier concentration, electron / hole mobility, average electron / hole drift velocity, electric field vector, potential distribution, space charge density, Auger recombination rate, radiative recombination rate, electron / hole lifetime, net doping concentration, donor (N-type) / acceptor (P-type) doping concentration, etc.

[0063] Next, define the Math model, set the extrapolation algorithm (Extrapolate), set the upper limit of the number of iterations (Iterations) to 1000, set the failure exit mechanism (ExitOnFailure), set extended numerical precision, and set undefined model check (-CheckUndefinedModels).

[0064] Next, the solution conditions are set, including the Poisson equation conditions (iteration count set to 1000). In the output characteristics, the gate voltage is set to 1 V, and the drain scan voltage to 0-1.5 V. In the transfer characteristics, the drain voltage is set to 0.8 V, and the gate scan voltage to 0-2 V. The minimum step size for voltage amplification is set to 10. -15 The maximum step size is 0.05, the step size increment rate is 1.4, the step size decrease rate is 2, and the initial step size is 10. -10 .

[0065] Next, the Sdevice simulation was started to obtain the IV characteristic curve of the pH buffer solution, and the simulation results of the 3D FET structure were analyzed.

[0066] (8) Finally, the simulation results are obtained by changing different materials or sizes of the 3D FET model region. The above performance indicators are compared. Based on the performance of the simulated 3D FET model, the various structural parameters or doping ion concentrations of the model are further adjusted to continuously optimize the model and obtain a high-performance interdigitated FET device.

[0067] Figure 1 This is a schematic diagram of the structure of a 3D model of an interdigital FET. The bottom part is the substrate 1 of the interdigital field-effect transistor device. Above the substrate is the bottom oxide layer 2. Above the bottom oxide layer 2 are the interdigital source and drain electrodes 3, which are mainly distributed on both sides. The interdigital source and drain electrodes form a channel 4, which fills the interdigital gap. Above the channel is the top oxide layer 5. Above the top oxide layer 5 is the Stern layer 6. Above the Stern layer 6 is the electrolyte region 7. Above the electrolyte region 7 is the gate 8.

[0068] Figure 2 To follow the specific implementation steps of Sdevice in this embodiment, after setting the required parameters, start the Sdevice simulation. After the simulation, open SentaurusVisual, select Drain as the X-axis, and then select Drain as the Y-axis. Combine the output characteristic curves of the interdigitated FET 3D model under optimal conditions with pH=3-9. From... Figure 2As can be seen from the curve, under specific pH conditions, the source-drain current increases with increasing drain voltage, and then saturates. As the pH value increases, the saturation current of the curve decreases, which is consistent with the basic output characteristics of field-effect transistor devices.

[0069] Figure 3 To follow the specific implementation steps of Sdevice in this embodiment, after setting the required parameters, start the Sdevice simulation. After the simulation, open Sentaurus Visual, select Gate as the X-axis, and then select Drain as the Y-axis. The transfer characteristic curves of the interdigitated FET 3D model under optimal conditions, obtained after combining pH=3-9, are then calculated. Figure 3 As can be seen from the curve, under specific pH conditions, the source and drain currents initially level off and then increase as the gate voltage increases. Furthermore, the threshold voltage of the curve increases with increasing pH, consistent with the basic transfer characteristics of field-effect transistor devices.

[0070] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments for application in other fields. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A three-dimensional structural modeling and simulation method for interdigitated field-effect transistors, characterized in that, The field-effect transistor includes a channel, and a source and a drain are disposed on both sides of the channel, wherein the source and the drain are interdigitated. The steps for 3D structural modeling and simulation are as follows: (1) Start the virtual machine VMware Workstation, open Sentaurus TCAD, open the terminal to enter the swb operation interface, add the Sde model and Sdevice model and set the relevant simulation parameters in the jEdit editor; (2) Construct a 3D model structure of an interdigitated field-effect transistor, including substrate, bottom oxide layer, channel, top oxide layer, Stern layer, source, drain, gate and electrolyte; (3) Define interdigitated source and drain on both sides of the channel, including finger length, finger width and finger spacing, and define contacts on the source and drain, and set the electrode material to metal aluminum or gold. (4) In the 3D model, select different regions of the channel, source, drain, and substrate and dope them to obtain simulation models of different types of interdigitated FETs; (5) Mesh the 3D model of the interdigitated field-effect transistor and then save it; (6) Start the simulation and view the 3D structure of the interdigitated field-effect transistor in Sentaurus Visual, including the region distribution, grid settings, doping concentration and doping type; (7) Obtain the basic electrical characteristics of the interdigital field-effect transistor. Define the channel and top oxide layer materials as indium oxide and tantalum oxide. Set the parameters of indium oxide and tantalum oxide in Sdevice, including the refractive index model, thermal conductivity model, volumetric heat capacity model, band gap model and resistivity model. Then set the physical characteristics and mathematical models of the source, drain and gate voltages to obtain the electrical characteristics of the interdigital FET 3D model. The refractive index model formula in step (7) is as follows: refractiveindex() = refractiveindex * (1 + alpha * (T-Tpar)); Where refractiveindex() is the final refractive index, refractiveindex is the material's fundamental refractive index measured at reference temperature Tpar, alpha is the material's refractive index temperature coefficient in 1 / K; T is the ambient temperature in K; and Tpar ​​is the reference temperature in K. The formula for the thermal conductivity model is as follows: kappa() = kappa + kappa_b * T + kappa_c * T 2 ; wherein kappa() is the final thermal conductivity, kappa is the constant term coefficient in the thermal conductivity polynomial, with units of W / (K cm); kappa_b is the first temperature term coefficient in the thermal conductivity polynomial, with units of W / (K 2 cm); kappa_c is the second temperature term coefficient in the thermal conductivity polynomial, with units of W / (K 3 cm); The formula for the volumetric heat capacity model is as follows: cv() = cv + cv_b * T + cv_c * T 2 + cv_d * T 3 ; Where cv() is the final volumetric heat capacity, and cv is the coefficient of the constant term in the heat capacity polynomial, with units of J / (K·cm). 3 ); cv_b is in units of J / (K) 2 ·cm 3 The unit of cv_c is J / (K) 3 ·cm 3 The unit of cv_d is J / (K) 4 ·cm 3 cv_b, cv_c, and cv_d are the coefficients of the temperature-dependent terms in the heat capacity polynomial, which control the linear, quadratic, and cubic temperature dependencies in turn. The bandgap model formula is as follows: Eg = Eg0 + dEg0 + alpha * Tpar 2 / (beta + Tpar) - alpha * T 2 / (beta + T); Where Eg is the final band gap, Eg0 is the intrinsic band gap width of the material measured at the reference temperature Tpar, in eV; dEg0 is the band gap narrowing correction term, in eV; alpha is in eV / K, beta is in K; alpha and beta are the temperature coefficients of the material, and Tpar ​​is the reference temperature, in K; The formula for the resistivity model is as follows: Resist(T) = Resist0 * ( 1 + TempCoef * ( T - 273 ) ); Wherein, Resist is the final resistivity in T; Resist0 is the basic resistivity of the material measured at the reference temperature in Ωcm; TempCoef is the temperature coefficient of resistivity of the material in 1 / K; and T is a fixed value of 300K.

2. The three-dimensional structural modeling and simulation method for interdigitated field-effect transistors according to claim 1, characterized in that, The different types of interdigitated FET simulation models in step (4) include N-type and P-type.

3. The three-dimensional structural modeling and simulation method for interdigitated field-effect transistors according to claim 1, characterized in that: The calculation formula for the electrolyte buffer model in step (2) is as follows: ， In the formula, N C The conduction band density at 300K, in cm³. -3 N V Valence band density at 300K, in cm³ -3 N A Avogadro's number, in mol. -1 E g ν is the band gap of the semiconductor, in eV; k is the Boltzmann constant, in J / K; T is the absolute temperature, in K.

4. The three-dimensional structural modeling and simulation method for interdigitated field-effect transistors according to claim 1, characterized in that: The meshing settings described in step (5) include defining meshes by window, by region name, by material name, and by material boundary.

5. The three-dimensional structural modeling and simulation method for interdigitated field-effect transistors according to claim 4, characterized in that: In step (6), the region distribution can be viewed in Visibility in Materials or Regions; the mesh setting can be viewed in Mesh in Materials; the doping type can be viewed in ArsenicActiveConcentration, BoronActiveConcentration and PhosphorusActiveConcentration in Scalars; and the doping concentration can be viewed in DopingConcentration in Scalars.

6. The three-dimensional structural modeling and simulation method for interdigitated field-effect transistors according to claim 1, characterized in that: In step (7), the basic electrical characteristics of the interdigitated field-effect transistor include output characteristics, transfer characteristics, threshold voltage extraction, subthreshold swing, switching current ratio and field-effect mobility; the physical characteristics of the source, drain and gate voltages include the determination of the Fermi level, mobility model and recombination mechanism model; the mathematical model settings include starting the extrapolation algorithm, setting the upper limit of the number of iterations, and clarifying the response strategy for solution failure.

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