Repairing circuit, display panel repairing method and display device

Abstract

The application provides a repairing circuit, a repairing method of a display panel and a display device. The repairing circuit is used for repairing a driving signal output by a gate driving circuit of the display panel. The repairing circuit comprises a shaping unit, a de-delay unit and an output unit. The shaping unit is connected to a to-be-repaired signal and outputs a square wave signal. The de-delay unit outputs a third signal according to the level state of the square wave signal and a clock signal. The rising edge of the third signal is consistent with the rising edge of the square wave signal, and the falling edge of the third signal is consistent with the falling edge of the clock signal. The output unit outputs a repaired signal according to the level state of the third signal. Through the cooperative work of the shaping unit, the de-delay unit and the output unit, the effective repairing of the output signal of the gate driving circuit of the display panel is realized.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a repair circuit, a repair method for a display panel, and a display device. Background Technology

[0002] In the manufacturing process of display panels, various display defects can occur due to process flaws. Among the many types of defects, GDL (Gate Driver Less) defects account for as much as 30%. GDL defects cause the output of the scan signal for that line to exhibit an abnormal state, which is visually manifested on the screen as dark lines in the horizontal direction. Summary of the Invention

[0003] The main technical problem addressed by this application is to provide a repair method and display device for a repair circuit and display panel, thereby solving the problem of abnormal display screen caused by GDL malfunction in the prior art.

[0004] To address the aforementioned technical problems, the first technical solution provided in this application is: a repair circuit for repairing the drive signal output by the gate drive circuit of a display panel; wherein, it includes: The shaping unit receives a signal to be repaired and outputs a square wave signal; The delay unit outputs a third signal based on the level states of the square wave signal and the clock signal; the rising edge of the third signal coincides with the rising edge of the square wave signal, and the falling edge of the third signal coincides with the falling edge of the clock signal. The output unit outputs a repair signal based on the level of the third signal.

[0005] This includes: The repair circuit also includes a first power supply voltage and a second power supply voltage; a shaping unit is coupled to the first power supply voltage and the second power supply voltage respectively; a delay removal unit is coupled to the first power supply voltage; and an output unit is coupled to the first power supply voltage and the second power supply voltage respectively; the first power supply voltage is used to provide a high-level signal, and the second power supply voltage is used to provide a low-level signal.

[0006] The shaping unit includes a first voltage divider group, a second voltage divider group, a first switch, and a second switch. The first voltage divider group is coupled between the signal to be repaired and the second power supply voltage, and is also coupled to the control terminal of the first switch; The second voltage divider is coupled between the first power supply voltage and the second power supply voltage, and is also coupled to the control terminal of the second switch. The input terminal of the first switch is coupled to the first power supply voltage, and the output terminal of the first switch is coupled to the second power supply voltage. The input terminal of the second switch is coupled to the first power supply voltage, and the output terminal of the second switch is coupled to the second power supply voltage.

[0007] The first voltage divider group includes a first resistor, a first node, and a second resistor connected in series; the second voltage divider group includes a third resistor, a second node, and a fourth resistor connected in series. The first resistor is coupled to the signal to be repaired, the second resistor is coupled to the second power supply voltage, and the first node is coupled to the control terminal of the first switch. The third resistor is coupled to the first power supply voltage, the fourth resistor is coupled to the second power supply voltage, and the second node is coupled to the control terminal of the second switch. The shaping unit also includes a third node, which is connected between the first power supply voltage and the input terminal of the second switch, and outputs a square wave signal.

[0008] The delay removal unit includes a first diode, a second diode, and a third voltage divider group; the third voltage divider group includes a fourth node and is coupled between the first power supply voltage and the second power supply voltage. The input terminal of the first diode is coupled to the first power supply voltage via the fourth node, and the output terminal of the first diode is coupled to the square wave signal. The input terminal of the second diode is coupled to the first power supply voltage via the fourth node, and the output terminal of the second diode is coupled to the clock signal. The fourth node outputs the third signal; The third voltage divider group also includes a fifth resistor and a sixth resistor, with the fifth resistor, the fourth node, and the sixth resistor connected in series.

[0009] The output unit includes a fourth voltage divider group, a fifth voltage divider group, a third switch, a fourth switch, a fifth switch, a sixth switch, and a signal output terminal; The fourth voltage divider group includes a fifth node, and the fourth voltage divider group is coupled between the first power supply voltage and the second power supply voltage; The fifth voltage divider group includes a sixth node, and the fifth voltage divider group is coupled between the first power supply voltage and the second power supply voltage; The control terminal of the third switch is coupled to the third signal, the input terminal of the third switch is coupled to the first power supply voltage via five nodes, and the output terminal of the third switch is coupled to the second power supply voltage. The control terminal of the fourth switch is coupled to the third signal, the input terminal of the fourth switch is coupled to the first power supply voltage via the fifth voltage divider, and the output terminal of the fourth switch is coupled to the second power supply voltage. The control terminal of the fifth switch is coupled to the first power supply voltage via the sixth node, the input terminal of the fifth switch is coupled to the first power supply voltage, and the output terminal of the fifth switch is coupled to the signal output terminal. The control terminal of the sixth switch is coupled to the first power supply voltage via the fifth node, the output terminal of the sixth switch is coupled to the signal output terminal, and the output terminal of the sixth switch is coupled to the second power supply voltage. The signal output terminal outputs a repair signal.

[0010] The fourth voltage divider group includes the seventh resistor and the eighth resistor, with the seventh resistor, the fifth node, and the eighth resistor connected in series. The fifth voltage divider group includes the ninth resistor and the tenth resistor, with the ninth resistor, the sixth node, and the tenth resistor connected in series.

[0011] The output unit also includes an eleventh resistor, a first capacitor, and a second capacitor. One end of the eleventh resistor is coupled to the third signal, and the other end of the eleventh resistor is coupled to the control terminal of the fourth switch and the first terminal of the first capacitor, respectively. The other end of the first capacitor is coupled to the second power supply voltage; The first terminal of the second capacitor is coupled to the first power supply voltage, and the second terminal of the second capacitor is coupled to the control terminal of the sixth switch.

[0012] To solve the above-mentioned technical problems, the second technical solution provided by this application is: to provide a method for repairing a display panel, using the above-mentioned repair circuit for repair; the display panel includes a dual-sided driven gate drive circuit and multiple scan lines; the gate drive circuit includes multiple cascaded gate drive units; one end of the abnormal scan line is electrically connected to the faulty gate drive unit, and the other end is electrically connected to the normally driven gate drive unit, and the drive signal output by the gate drive unit of the normally driven abnormal scan line is used as the signal to be repaired; This includes: Disconnect the electrical connection between the abnormal scan line and the gate drive circuit; The repair circuit repairs the signal to be repaired and transmits the repair signal to both ends of the abnormal scan line.

[0013] To solve the above-mentioned technical problems, the third technical solution provided in this application is: to provide a display device, which includes a display panel and the above-mentioned repair circuit.

[0014] The beneficial effects of this application are as follows: Unlike existing technologies, this application provides a repair circuit, a method for repairing a display panel, and a display device. The repair circuit is used to repair the drive signal output by the gate drive circuit of the display panel. The repair circuit includes a shaping unit, a delay removal unit, and an output unit. The shaping unit receives a signal to be repaired and outputs a square wave signal. The delay removal unit outputs a third signal based on the level states of the square wave signal and the clock signal. The rising edge of the third signal coincides with the rising edge of the square wave signal, and the falling edge of the third signal coincides with the falling edge of the clock signal. The output unit outputs a repair signal based on the level state of the third signal. This application achieves effective repair of the output signal of the gate drive circuit of the display panel through the coordinated operation of the shaping unit, the delay removal unit, and the output unit. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0016] Figure 1 This is a schematic diagram of the compensation circuit in related technologies; Figure 2a These are schematic color drawings illustrating the structure of an embodiment of the display device provided in this application; Figure 2b This is a grayscale schematic diagram of an embodiment of the display device provided in this application; Figure 3 This is a schematic diagram of an embodiment of the repair circuit provided in this application; Figure 4 yes Figure 3 A partially enlarged connection diagram of the shaping unit, the signal to be repaired, and the power supply voltage; Figure 5a This application provides a color illustration of the third node and the waveform of the signal to be repaired. Figure 5b This is a grayscale diagram illustrating the waveform of the third node and the signal to be repaired provided in this application. Figure 6 yes Figure 3 A partially enlarged schematic diagram of the connection between the de-delay unit and the power supply voltage; Figure 7a These are color diagrams illustrating the waveforms of the third node and clock signal provided in this application; Figure 7b This is a grayscale diagram illustrating the waveforms of the third node and clock signal provided in this application; Figure 8 Yes, yes Figure 3A partially enlarged schematic diagram of the connection between the output unit and the power supply voltage; Figure 9a These are color diagrams illustrating the waveforms of the clock signal, the third node, and the fourth node provided in this application. Figure 9b This is a grayscale diagram illustrating the waveforms of the clock signal, the third node, and the fourth node provided in this application; Figure 10a This is a color diagram showing the state of the fifth and sixth switches as a function of time, according to an embodiment provided in this application. Figure 10b This is a grayscale image of the state of the fifth and sixth switches provided in this application as a function of time. Figure 11a This is a color diagram showing the state of the fifth and sixth switches provided in this application over time; Figure 11b This is a grayscale image of the state of the fifth and sixth switches provided in this application as a function of time; Figure 12a These are color diagrams illustrating the waveforms of the clock signal, the third node, and the signal output terminal provided in this application. Figure 12b This is a grayscale diagram illustrating the waveforms of the clock signal, the third node, and the signal output terminal provided in this application. Figure 13 This is a flowchart illustrating one embodiment of the display panel repair method provided in this application.

[0017] Explanation of icon numbers: 100. Repair Circuit; 10. Shaping Unit; 11. First Voltage Divider Group; R1. First Resistor; R2. Second Resistor; 12. Second Voltage Divider Group; R3. Third Resistor; R4. Fourth Resistor; Q1. First Switch; Q2. Second Switch; 20. Delay Removal Unit; D1. First Diode; D2. Second Diode; 21. Third Voltage Divider Group; R5. Fifth Resistor; R6. Sixth Resistor; 30. Output Unit; 31. Fourth Voltage Divider Group; R7. Seventh Resistor; R8. Eighth Resistor; 32. Fifth Voltage Divider Group; R9. Ninth Resistor; R10. Tenth Resistor; Q3. Third Switch; Q4. Fourth Switch; Q5. Fifth Switch; Q6. Sixth Switch; G_out. Signal Output Terminal; V 1. First power supply voltage; V2. Second power supply voltage; R11. Eleventh resistor; C1. First capacitor; C2. Second capacitor; A. First node; B. Second node; C. Third node; D. Fourth node; E. Fifth node; F. Sixth node; 1. Display panel; 200. Gate drive circuit; 211. First gate drive circuit; 212. Second gate drive circuit; Gn. Scan line; 2. Printed circuit board assembly; 3. Display device; OP. Operational amplifier; Ref. Reference voltage; VGH. High-level signal; VGL. Low-level signal; Gn_L / Gn_R / Gout_L / Gout_R. Drive signal; CLK. Clock signal; VGS. Gate-source voltage. Detailed Implementation

[0018] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0019] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0022] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0023] Please see Figure 1 , Figure 1 This is a schematic diagram of the compensation circuit in related technologies.

[0024] In related technologies, such as Figure 1 As shown, the display panel ( Figure 1 (Not shown) is a dual-drive system.

[0025] Gn_L represents the drive signal at the left end of the nth scan line before compensation, and Gn_R represents the drive signal at the right end of the nth scan line before compensation. Gout_L represents the drive signal transmitted to the left end of the scan line after compensation, and Gout_R represents the drive signal transmitted to the right end of the scan line after compensation. When the drive signal Gn_R at the right end of the nth scan line is abnormal, the normal drive signal Gn_L at the left end of the nth scan line is compensated and then transmitted to both ends of the scan line. Specifically, the signal of Gn_L is shaped by the operational amplifier OP and then transmitted to the MOS transistor (Metal-Oxide-Semiconductor Field-Effect Transistor) to achieve waveform delay removal. Then, after being shaped again by the operational amplifier OP, the signal is sent to Gout_L and Gout_R. The reference voltage Ref is used to provide a reference level for the output of the operational amplifier OP. Since the drive signals (Gout_R and Gout_L) and the voltage of the nth scan line Gn are both at the high-level signal VGH and low-level signal VGL levels, and the voltage difference between the high-level signal VGH and the low-level signal VGL in the panel is typically 50V, the selected operational amplifier (OP) must have a power supply voltage greater than 50V, and the gate-source voltage VGS of the MOSFET must also be greater than 50V. Such high-specification operational amplifiers (OPs) are not only expensive and extremely rare, but also exhibit significant input-output delays. Furthermore, there are virtually no available MOSFETs of this specification. Moreover, the circuit exhibits coupling, requiring the addition of capacitors for decoupling, but this further increases the delay.

[0026] To address the aforementioned technical problems, this application provides a repair circuit. The repair circuit is used to repair the drive signal output by the gate drive circuit of a display panel. The repair circuit includes a shaping unit, a delay removal unit, and an output unit. The shaping unit receives a signal to be repaired and outputs a square wave signal. The delay removal unit outputs a third signal based on the level states of the square wave signal and the clock signal. The rising edge of the third signal coincides with the rising edge of the square wave signal, and the falling edge of the third signal coincides with the falling edge of the clock signal. The output unit outputs a repair signal based on the level state of the third signal. This application achieves effective repair of the output signal of the gate drive circuit of the display panel through the coordinated operation of the shaping unit, the delay removal unit, and the output unit.

[0027] Please see Figures 1 to 3 , Figure 2a This is a schematic color drawing illustrating the structure of an embodiment of the display device provided in this application. Figure 2b This is a grayscale schematic diagram of an embodiment of the display device provided in this application. Figure 3This is a schematic diagram of an embodiment of the repair circuit provided in this application.

[0028] Therefore, in order to solve the problems of the prior art, this application provides a repair circuit 100, a repair method for the display panel, and a display device 3. The display device 3 provided in this application embodiment will be described first below.

[0029] The display device 3 includes a display panel 1 and a repair circuit 100.

[0030] The display panel 1 includes a dual-sided driven gate drive circuit 200 and multiple scan lines. The gate drive circuit 200 includes multiple cascaded gate drive units (not shown in the figure). One end of the abnormal scan line is electrically connected to the faulty gate drive unit, and the other end is electrically connected to the normally driven gate drive unit. The drive signal output by the gate drive unit of the normally driven abnormal scan line is used as the signal to be repaired.

[0031] That is, the gate driving circuit 200 simultaneously drives both ends of the same scan line. Specifically, the gate driving circuit 200 includes a first gate driving circuit 211 and a second gate driving circuit 212, which are located on opposite sides of the display area of ​​the display panel 1. The first gate driving circuit 211 is electrically connected to the first end of the scan line, and the second gate driving circuit 212 is connected to the second end of the scan line. During the scanning process, the first gate driving circuit 211 and the second gate driving circuit 212 simultaneously drive the same scan line to achieve bilateral driving.

[0032] When the gate driving circuit 200 in this embodiment malfunctions, only one end of the same scan line is abnormally driven. Specifically, the gate driving unit driving the nth scan line is defined as the nth level gate driving unit. When the nth scan line malfunctions, one of the nth level gate driving units in the first gate driving circuit 211 and the nth level gate driving unit in the second gate driving circuit 212 malfunctions.

[0033] For example, taking the abnormality of the drive signal Gn_R output by the nth stage gate drive unit of the second gate drive circuit 212 connected to the second end of the nth row of scan lines as an example, the drive signal Gn_L output by the nth stage gate drive unit of the first gate drive circuit 211 connected to the first end of the nth row of scan lines is normal and is used as the signal to be repaired. That is, in this embodiment, Gn_L represents the signal to be repaired by the repair circuit 100.

[0034] This application provides a repair circuit 100. The repair circuit 100 is used to repair the drive signal output by the gate drive circuit 200 of the display panel 1. The repair circuit 100 includes a shaping unit 10, a delay removal unit 20, and an output unit 30. The shaping unit 10 receives a signal to be repaired and outputs a square wave signal. The delay removal unit 20 outputs a third signal based on the level states of the square wave signal and the clock signal CLK. The rising edge of the third signal coincides with the rising edge of the square wave signal, and the falling edge of the third signal coincides with the falling edge of the clock signal CLK. The output unit 30 outputs a repair signal based on the level state of the third signal. This application achieves effective repair of the output signal of the gate drive circuit 200 of the display panel 1 through the coordinated operation of the shaping unit 10, the delay removal unit 20, and the output unit 30.

[0035] The repair circuit 100 is electrically connected to the display panel 1. The repair circuit 100 is disposed in the printed circuit board assembly 2 to avoid occupying too much of the bezel area of ​​the display panel 1 and affecting the narrow bezel design.

[0036] Printed circuit board assembly 2 is a PCBA (Printed Circuit Board Assembly).

[0037] In this embodiment, the second end of the abnormal scan line is abnormally driven, meaning the gate driving unit driving the abnormal scan line in the second gate driving circuit 212 is faulty. The first end of the abnormal scan line is normally driven, and the driving signal normally output by the gate driving unit driving the abnormal scan line in the first gate driving unit is used as the signal to be repaired.

[0038] In some embodiments, the repair circuit 100 further includes a first power supply voltage V1 and a second power supply voltage V2. A shaping unit 10 is coupled to both the first power supply voltage V1 and the second power supply voltage V2. A delay removal unit 20 is coupled to the first power supply voltage V1. An output unit 30 is coupled to both the first power supply voltage V1 and the second power supply voltage V2. The first power supply voltage V1 provides a high-level signal VGH, and the second power supply voltage V2 provides a low-level signal VGL.

[0039] For example, the first power supply voltage V1 is 40V and the second power supply voltage V2 is -10V.

[0040] Since the signal to be repaired is transmitted from the display panel 1 to the printed circuit board assembly 2, the waveform of the signal to be repaired transmitted to the repair circuit 100 is non-standard. The shaping unit 20 can be used to shape the waveform of the circuit 100 to obtain a square wave signal.

[0041] Please see Figures 1 to 5b , Figure 4 yes Figure 3A partially enlarged connection diagram of the shaping unit, the signal to be repaired, and the power supply voltage. Figure 5a This application provides a color illustration of the third node and the waveform of the signal to be repaired. Figure 5b This is a grayscale diagram illustrating the waveform of the third node and the signal to be repaired provided in this application.

[0042] In some embodiments, the shaping unit 10 includes a first voltage divider group 11, a second voltage divider group 12, a first switch Q1, and a second switch Q2.

[0043] The first voltage divider group 11 is coupled between the signal to be repaired and the second power supply voltage V2, and is also coupled to the control terminal of the first switch Q1.

[0044] The second voltage divider group 12 is coupled between the first power supply voltage V1 and the second power supply voltage V2, and is also coupled to the control terminal of the second switch Q2.

[0045] The input terminal of the first switch Q1 is coupled to the first power supply voltage V1, and the output terminal of the first switch Q1 is coupled to the second power supply voltage V2.

[0046] The input terminal of the second switch Q2 is coupled to the first power supply voltage V1, and the output terminal of the second switch Q2 is coupled to the second power supply voltage V2.

[0047] The first voltage divider group 11 performs voltage division processing on the input signal to be repaired, and extracts the voltage value suitable for controlling the first switch Q1 to turn on.

[0048] The second voltage divider group 12 divides the input first power supply voltage V1 to extract the voltage value suitable for controlling the second switch Q2 to turn on.

[0049] The high and low level states of the square wave signal are determined by the on / off states of the first switch Q1 and the second switch Q2.

[0050] By setting a first voltage divider group 11 and a second voltage divider group 12 in the shaping unit 10, the appropriate voltage value for turning on the control switch can be extracted, eliminating the need for high-specification operational amplifiers and switches, thereby reducing costs.

[0051] In some embodiments, the first voltage divider group 11 includes a first resistor R1, a first node A, and a second resistor R2 connected in series. The second voltage divider group 12 includes a third resistor R3, a second node B, and a fourth resistor R4 connected in series.

[0052] The first resistor R1 is coupled to the signal to be repaired, the second resistor R2 is coupled to the second power supply voltage V2, and the first node A is coupled to the control terminal of the first switch Q1.

[0053] The third resistor R3 is coupled to the first power supply voltage V1, the fourth resistor R4 is coupled to the second power supply voltage V2, and the second node B is coupled to the control terminal of the second switch Q2.

[0054] The shaping unit 10 also includes a third node C, which is connected between the first power supply voltage V1 and the input terminal of the second switch Q2, and outputs a square wave signal.

[0055] For example, the resistance of the first resistor R1 is 20KΩ and the resistance of the second resistor R2 is 2KΩ.

[0056] The resistance of the third resistor R3 is 20KΩ, and the resistance of the fourth resistor R4 is 2KΩ.

[0057] The resistance values ​​of the first resistor R1 and the second resistor R2 are not restricted here. They can be selected according to actual needs, as long as the first switch Q1 can be opened normally after being divided by the first voltage divider group 11.

[0058] The resistance values ​​of the third resistor R3 and the fourth resistor R4 are not restricted here. They can be selected according to actual needs, as long as the conventional second switch Q2 can be opened normally after being divided by the second voltage divider group 12.

[0059] When the signal to be repaired is a high-level signal VGH, taking an example where the high-level voltage of the signal to be repaired is 40V and the low-level voltage is -10V, the voltage V at the first node A is obtained after voltage division by the first resistor R1 and the second resistor R2. A for: (Formula 1).

[0060] The gate-source voltage VGS of the first switch Q1 reaches 4.55V, causing the first switch Q1 to turn on. With the first switch Q1 on, the voltage at the second node B becomes the second power supply voltage V2, i.e., the voltage at the second node B is -10V. Due to the interconnectivity of the circuit, the gate-source voltage VGS of the second switch Q2 subsequently becomes 0V, causing the second switch Q2 to turn off. Correspondingly, the voltage at the third node C becomes the first power supply voltage V1.

[0061] When the signal to be repaired is a low-level signal VGL, taking an example where the low-level voltage of the current signal to be repaired is -10V, the voltage at the first node A becomes the second power supply voltage V2, causing the first switch Q1 to turn off. The first power supply voltage V1, after being divided by the third resistor R3 and the fourth resistor R4, results in a voltage of -5.45V at the second node B. At this time, the gate-source voltage VGS of the second switch Q2 reaches 4.55V, causing the second switch Q2 to turn on. The turning on of the second switch Q2 causes the voltage at the third node C to become the second power supply voltage V2.

[0062] The shaping unit 10 of this application uses resistors and conventional switches instead of high-specification operational amplifiers. Conventional switches are low in cost and readily available in the market, which avoids the cost problems caused by the high price and scarcity of special-specification components and can significantly reduce component procurement costs.

[0063] Please see Figures 1 to 7b , Figure 6 yes Figure 3 A partially enlarged connection diagram of the de-delay unit and the power supply voltage. Figure 7a This is a color diagram illustrating the waveforms of the third node and clock signal provided in this application. Figure 7b This is a grayscale diagram illustrating the waveforms of the third node and clock signal provided in this application.

[0064] In some embodiments, the delay removal unit 20 includes a first diode D1, a second diode D2, and a third voltage divider group 21. The third voltage divider group 21 includes a fourth node D and is coupled between the first power supply voltage V1 and the second power supply voltage V2.

[0065] The input terminal of the first diode D1 is coupled to the first power supply voltage V1 via the fourth node D, and the output terminal of the first diode D1 is coupled to the square wave signal.

[0066] The input terminal of the second diode D2 is coupled to the first power supply voltage V1 via the fourth node D, and the output terminal of the second diode D2 is coupled to the clock signal CLK.

[0067] The fourth node D outputs the third signal.

[0068] The third voltage divider group 21 also includes a fifth resistor R5 and a sixth resistor R6, with the fifth resistor R5, the fourth node D, and the sixth resistor R6 connected in series.

[0069] The third voltage divider group 21 divides the input first power supply voltage V1 to extract the voltage value suitable for controlling the third switch Q3 to turn on.

[0070] For example, the fifth resistor R5 has a resistance of 20KΩ and the sixth resistor R6 has a resistance of 2KΩ.

[0071] There are no restrictions on the resistance values ​​of the fifth resistor R5 and the sixth resistor R6 here. They can be selected according to actual needs, as long as the conventional third switch Q3 can be opened normally after being divided by the third voltage divider group 21.

[0072] Both the first diode D1 and the second diode D2 are Schottky diodes.

[0073] Because the gate drive circuit 200 itself has a delay, and the in-plane routing also introduces a delay, there is a delay between the shaped waveform and the clock signal CLK output by the current row level conversion chip (not shown in the figure), with a delay time of Δt. If the waveform with the delay is directly transmitted to the scan line, the additional delay of the display panel 1 itself will cause a charging error. However, the drive signal output by the gate drive unit only has one high level in a frame, so the clock signal CLK cannot be simply sent directly. This application sets a delay removal unit 20 after the shaping unit 10 to achieve the delay removal function.

[0074] Specifically, when both the third node C and the clock signal CLK are high, both the first diode D1 and the second diode D2 are turned off. The first power supply voltage V1 is divided by the fifth resistor R5 and the sixth resistor R6, resulting in a voltage of -5.45V at the fourth node D.

[0075] When the third node C is low, causing the first diode D1 to conduct, and / or when the clock signal CLK is low, causing the second diode D2 to conduct, the voltage of the fourth node D becomes the second power supply voltage V2. That is, when either the third node C or the clock signal CLK is low (VGL), the voltage of the fourth node D becomes the second power supply voltage V2.

[0076] This method ensures that the rising edge of the fourth node D coincides with the rising edge of the third node C, and the falling edge of the fourth node D coincides with the falling edge of the clock signal CLK, thus achieving the function of delay removal.

[0077] The delay removal unit 20 of this application uses a conventional Schottky diode to replace the high-specification transistor in the existing circuit, which helps to save costs.

[0078] Please see Figures 1 to 9b , Figure 8 Yes, yes Figure 3 A partially enlarged connection diagram of the output unit and the power supply voltage. Figure 9a These are color diagrams illustrating the waveforms of the clock signal, the third node, and the fourth node provided in this application. Figure 9b This is a grayscale diagram illustrating the waveforms of the clock signal, the third node, and the fourth node provided in this application.

[0079] In some embodiments, the output unit 30 includes a fourth voltage divider group 31, a fifth voltage divider group 32, a third switch Q3, a fourth switch Q4, a fifth switch Q5, a sixth switch Q6, and a signal output terminal G_out.

[0080] The fourth voltage divider group 31 includes a fifth node E, and the fourth voltage divider group 31 is coupled between the first power supply voltage V1 and the second power supply voltage V2.

[0081] The fifth voltage divider group 32 includes a sixth node F, and the fifth voltage divider group 32 is coupled between the first power supply voltage V1 and the second power supply voltage V2.

[0082] The control terminal of the third switch Q3 is coupled to the third signal, the input terminal of the third switch Q3 is coupled to the first power supply voltage V1 via five nodes, and the output terminal of the third switch Q3 is coupled to the second power supply voltage V2.

[0083] The control terminal of the fourth switch Q4 is coupled to the third signal, the input terminal of the fourth switch Q4 is coupled to the first power supply voltage V1 via the fifth voltage divider group 32, and the output terminal of the fourth switch Q4 is coupled to the second power supply voltage V2.

[0084] The control terminal of the fifth switch Q5 is coupled to the first power supply voltage V1 via the sixth node F. The input terminal of the fifth switch Q5 is coupled to the first power supply voltage V1. The output terminal of the fifth switch Q5 is coupled to the signal output terminal G_out.

[0085] The control terminal of the sixth switch Q6 is coupled to the first power supply voltage V1 via the fifth node E. The output terminal of the sixth switch Q6 is coupled to the signal output terminal G_out. The output terminal of the sixth switch Q6 is coupled to the second power supply voltage V2.

[0086] The signal output terminal G_out outputs the repair signal.

[0087] That is, the control terminal of the third switch Q3 is coupled to the fourth node D, and the control terminal of the fourth switch Q4 is coupled to the fourth node D.

[0088] The fourth voltage divider group 31 divides the input first power supply voltage V1 to extract the voltage value suitable for controlling the sixth switch Q6 to turn on.

[0089] The fifth voltage divider group 32 divides the input first power supply voltage V1 to extract the voltage value suitable for controlling the fifth switch Q5 to turn on.

[0090] This application reduces costs by setting a fourth voltage divider group 31 and a fifth voltage divider group 32 in the output unit 30 to extract the appropriate voltage value for turning on the control switch, without the need for high-specification operational amplifiers and switches.

[0091] In some embodiments, the fourth voltage divider group 31 includes a seventh resistor R7 and an eighth resistor R8, with the seventh resistor R7, the fifth node E, and the eighth resistor R8 connected in series.

[0092] The fifth voltage divider group 32 includes a ninth resistor R9 and a tenth resistor R10, which are connected in series with the ninth resistor R9, the sixth node F and the tenth resistor R10.

[0093] For example, the resistance of the seventh resistor R7 is 20KΩ, and the resistance of the eighth resistor R8 is 2KΩ.

[0094] The resistance of the ninth resistor R9 is 2KΩ, and the resistance of the tenth resistor R10 is 20KΩ.

[0095] There are no restrictions on the resistance values ​​of the seventh resistor R7 and the eighth resistor R8 here. They can be selected according to actual needs, as long as the conventional sixth switch Q6 can be opened normally after being divided by the fourth voltage divider group 31.

[0096] There are no restrictions on the resistance values ​​of the ninth resistor R9 and the tenth resistor R10 here. They can be selected according to actual needs, as long as the conventional fifth switch Q5 can be opened normally after being divided by the fifth voltage divider group 32.

[0097] Specifically, when the voltage at the fourth node D is -5.45V and in a high-level state, both the third switch Q3 and the sixth switch Q6 are turned on. Turning on the third switch Q3 causes the gate-source voltage VGS of the fifth switch Q5 to become 0V, thus causing the fifth switch Q5 to turn off. Meanwhile, when the sixth switch Q6 is turned on, the first power supply voltage V1 is divided by the ninth resistor R9 and the tenth resistor R10, making the gate-source voltage VGS of the fifth switch Q5 -5.45V, thus causing the fifth switch Q5 to turn on. The signal output terminal G_out outputs the second power supply voltage V2.

[0098] When the voltage at the fourth node D is the second power supply voltage V2 and is in a low-level state, both the third switch Q3 and the sixth switch Q6 are turned off. The sixth switch Q6 being turned off makes the gate-source voltage VGS of the fifth switch Q5 0V, causing the fifth switch Q5 to turn off. The first power supply voltage V1 is divided by the seventh resistor R7 and the eighth resistor R8, causing the sixth switch Q6 to turn on, and the signal output terminal G_out outputs the first power supply voltage V1.

[0099] The output unit 30 of this application uses resistors and conventional switches instead of high-specification operational amplifiers. Conventional switches are low in cost and readily available in the market, which avoids the cost problems caused by the high price and scarcity of special-specification components and can significantly reduce component procurement costs.

[0100] Please see Figures 1 to 12b , Figure 10a This is a color diagram showing the state of the fifth and sixth switches provided in this application over time, according to an embodiment. Figure 10b This is a grayscale image showing the state changes of the fifth and sixth switches provided in this application over time. Figure 11a This is a color diagram showing the state of the fifth and sixth switches provided in this application over time, according to another embodiment. Figure 11b This is a grayscale image of the state of the fifth and sixth switches provided in this application as a function of time; Figure 12aThese are color diagrams illustrating the waveforms of the clock signal, the third node, and the signal output terminal provided in this application. Figure 12b This is a grayscale diagram illustrating the waveforms of the clock signal, the third node, and the signal output terminal provided in this application.

[0101] In some embodiments, the output unit 30 further includes an eleventh resistor R11, a first capacitor C1, and a second capacitor C2.

[0102] One end of the eleventh resistor R11 is coupled to the third signal, and the other end of the eleventh resistor R11 is coupled to the control terminal of the fourth switch Q4 and the first terminal of the first capacitor C1, respectively.

[0103] The other end of the first capacitor C1 is coupled to the second power supply voltage V2.

[0104] The first terminal of the second capacitor C2 is coupled to the first power supply voltage V1, and the second terminal of the second capacitor C2 is coupled to the control terminal of the sixth switch Q6.

[0105] For example, the resistance of the eleventh resistor R11 is 2KΩ.

[0106] Specifically, such as Figure 10a and Figure 10b As shown, when the fourth node D is high, the third switch Q3 will be turned on, while the fourth switch Q4 needs to charge the first capacitor C1 to the turn-on voltage before it will be turned on. This ensures that the fifth switch Q5 will be turned on when the sixth switch Q6 is in the off state.

[0107] like Figure 11a and Figure 11b As shown, when the fourth node D is low, the third switch Q3 and the fourth switch Q4 are both closed, and the fifth switch Q5 is open. The fourth switch Q4 will only open after the second capacitor C2 discharges to the opening voltage. This ensures that the sixth switch Q6 will only open when the fifth switch Q5 is closed.

[0108] This application increases the dead time by setting an eleventh resistor R11, a first capacitor C1, and a second capacitor C2 in the output unit 30, thus ensuring that the fifth switch Q5 and the sixth switch Q6 will not be turned on simultaneously.

[0109] In this embodiment, the first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the sixth switch Q6 are all MOSFETs, and the gate-source breakdown voltage of the MOSFETs is 20V.

[0110] Gate-source breakdown voltage refers to the maximum voltage that a MOSFET can withstand between its gate and source. When the gate-source voltage VGS exceeds 20V, the gate oxide layer of the MOSFET may be broken down, causing the MOSFET to lose its normal control function.

[0111] In this embodiment, the first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4 and the sixth switch Q6 are all N-type MOSFETs, and the fifth switch Q5 is a P-type MOSFET.

[0112] The repair circuit 100 of this application repairs the drive signal by sequentially setting a shaping unit 10, a delay removal unit 20 and an output unit 30, and the repair waveform delay is about 100ns, that is, it reduces the delay signal transmission of the drive signal, and the delay can reach the nanosecond level.

[0113] Please see Figures 1 to 13 , Figure 13 This is a flowchart illustrating one embodiment of the display panel repair method provided in this application.

[0114] This application provides a method for repairing a display panel. The repair is performed using the aforementioned repair circuit 100. The display panel 1 includes a dual-sided driven gate drive circuit 200 and multiple scan lines. The gate drive circuit 200 includes multiple cascaded gate drive units. One end of the abnormal scan line is electrically connected to the faulty gate drive unit, and the other end is electrically connected to a normally driven gate drive unit. The drive signal output by the gate drive unit driving the abnormal scan line is used as the signal to be repaired.

[0115] Display panel 1 is the same as the display panel 1 described above.

[0116] The specific methods for repairing the display panel include: S10: Disconnect the electrical connection between the abnormal scan line and the gate drive circuit.

[0117] Specifically, the electrical connection between the abnormal scan line and the gate drive circuit is cut off in the border area.

[0118] That is, in the border area, the electrical connection between the first end of the abnormal scan line and the first gate drive circuit 211 is cut off, and the electrical connection between the second end of the abnormal scan line and the second gate drive circuit 212 is cut off, so that the abnormal drive signal does not enter the scan line of the display area.

[0119] In this embodiment, only one end of the abnormal scan line is abnormally driven, and the second end of the abnormal scan line is also abnormally driven. That is, the driving signal output by the gate driving unit of the first gate driving circuit 211 that drives the first end of the abnormal scan line is the signal to be repaired.

[0120] For example, the second end of the nth scan line is abnormally driven.

[0121] S20: The repair circuit repairs the signal to be repaired and transmits the repair signal to both ends of the abnormal scan line.

[0122] Connecting leads are provided in the border area to electrically connect the repair circuit 100 to the signal to be repaired. A first repair line and a second repair line are also provided in the border area. The repair signal is transmitted to the first end of the abnormal scan line via the first repair line, and the repair signal is also transmitted to the second end of the abnormal scan line via the second repair line, so that the charging display effect of the abnormal scan line is consistent with that of the adjacent row scan line, thus achieving the repair effect.

[0123] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0124] The above are merely embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A repair circuit for repairing the drive signal output by the gate drive circuit of a display panel; characterized in that, include: The shaping unit receives a signal to be repaired and outputs a square wave signal; The delay unit outputs a third signal based on the level states of the square wave signal and the clock signal; the rising edge of the third signal coincides with the rising edge of the square wave signal, and the falling edge of the third signal coincides with the falling edge of the clock signal. The output unit outputs a repair signal based on the level state of the third signal; The repair circuit further includes a first power supply voltage and a second power supply voltage; the shaping unit is coupled to the first power supply voltage and the second power supply voltage respectively; the delay removal unit is coupled to the first power supply voltage; the output unit is coupled to the first power supply voltage and the second power supply voltage respectively; the first power supply voltage is used to provide a high-level signal, and the second power supply voltage is used to provide a low-level signal; The delay removal unit includes a first diode, a second diode, and a third voltage divider group; the third voltage divider group includes a fourth node, and the third voltage divider group is coupled between the first power supply voltage and the second power supply voltage. The input terminal of the first diode is coupled to the first power supply voltage via the fourth node, and the output terminal of the first diode is coupled to the square wave signal. The input terminal of the second diode is coupled to the first power supply voltage via the fourth node, and the output terminal of the second diode is coupled to the clock signal; The fourth node outputs the third signal; The third voltage divider group also includes a fifth resistor and a sixth resistor, and the fifth resistor, the fourth node, and the sixth resistor are connected in series.

2. The repair circuit according to claim 1, characterized in that, The shaping unit includes a first voltage divider group, a second voltage divider group, a first switch, and a second switch; The first voltage divider group is coupled between the signal to be repaired and the second power supply voltage, and is also coupled to the control terminal of the first switch; The second voltage divider is coupled between the first power supply voltage and the second power supply voltage, and is also coupled to the control terminal of the second switch; The input terminal of the first switch is coupled to the first power supply voltage, and the output terminal of the first switch is coupled to the second power supply voltage. The input terminal of the second switch is coupled to the first power supply voltage, and the output terminal of the second switch is coupled to the second power supply voltage.

3. The repair circuit according to claim 2, characterized in that, The first voltage divider group includes a first resistor, a first node, and a second resistor connected in series; the second voltage divider group includes a third resistor, a second node, and a fourth resistor connected in series. The first resistor is coupled to the signal to be repaired, the second resistor is coupled to the second power supply voltage, and the first node is coupled to the control terminal of the first switch; The third resistor is coupled to the first power supply voltage, the fourth resistor is coupled to the second power supply voltage, and the second node is coupled to the control terminal of the second switch. The shaping unit further includes a third node, which is connected between the first power supply voltage and the input terminal of the second switch, and outputs the square wave signal.

4. The repair circuit according to claim 1, characterized in that, The output unit includes a fourth voltage divider group, a fifth voltage divider group, a third switch, a fourth switch, a fifth switch, a sixth switch, and a signal output terminal; The fourth voltage divider group includes a fifth node, and the fourth voltage divider group is coupled between the first power supply voltage and the second power supply voltage; The fifth voltage divider group includes a sixth node, and the fifth voltage divider group is coupled between the first power supply voltage and the second power supply voltage; The control terminal of the third switch is coupled to the third signal, the input terminal of the third switch is coupled to the first power supply voltage via the five nodes, and the output terminal of the third switch is coupled to the second power supply voltage. The control terminal of the fourth switch is coupled to the third signal, the input terminal of the fourth switch is coupled to the first power supply voltage via the fifth voltage divider group, and the output terminal of the fourth switch is coupled to the second power supply voltage. The control terminal of the fifth switch is coupled to the first power supply voltage via the sixth node, the input terminal of the fifth switch is coupled to the first power supply voltage, and the output terminal of the fifth switch is coupled to the signal output terminal. The control terminal of the sixth switch is coupled to the first power supply voltage via the fifth node, the output terminal of the sixth switch is coupled to the signal output terminal, and the output terminal of the sixth switch is coupled to the second power supply voltage. The repair signal is output from the signal output terminal.

5. The repair circuit according to claim 4, characterized in that, The fourth voltage divider group includes a seventh resistor and an eighth resistor, and the seventh resistor, the fifth node, and the eighth resistor are connected in series. The fifth voltage divider group includes a ninth resistor and a tenth resistor, and the ninth resistor, the sixth node, and the tenth resistor are connected in series.

6. The repair circuit according to claim 4, characterized in that, The output unit also includes an eleventh resistor, a first capacitor, and a second capacitor; One end of the eleventh resistor is coupled to the third signal, and the other end of the eleventh resistor is coupled to the control terminal of the fourth switch and the first terminal of the first capacitor, respectively. The other end of the first capacitor is coupled to the second power supply voltage; The first terminal of the second capacitor is coupled to the first power supply voltage, and the second terminal of the second capacitor is coupled to the control terminal of the sixth switch.

7. A method for repairing a display panel, comprising using the repair circuit described in any one of claims 1 to 6; the display panel includes a dual-sided driven gate drive circuit and multiple scan lines; the gate drive circuit includes multiple cascaded gate drive units; one end of the abnormal scan line is electrically connected to a faulty gate drive unit, and the other end is electrically connected to a normally driven gate drive unit, wherein the drive signal output by the gate drive unit normally driving the abnormal scan line is used as the signal to be repaired; Its features are, include: Disconnect the electrical connection between the abnormal scan line and the gate drive circuit; The repair circuit repairs the signal to be repaired and transmits the repaired signal to both ends of the abnormal scan line.

8. A display device, characterized in that, It includes a display panel and the repair circuit as described in any one of claims 1 to 6.

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