Display driving method and display apparatus

Abstract

The application discloses a display driving method and a display device. The method can include: obtaining a first time point of a data signal, a second time point of the data signal, and a third time point of a clock signal in a first period of an eye diagram based on current eye diagram data of a display; calculating a first phase difference between the data signal and the clock signal and a second phase difference between the data signal and the clock signal based on the first time point, the second time point, and the third time point; and performing signal output control on a driving module of the display based on the first phase difference and the second phase difference. In the eye diagram data, the first time point is a negative intersection time point of the data signal and a horizontal axis in the first period, the second time point is a positive intersection time point of the data signal and the horizontal axis in the first period, and the third time point is an intersection time point of the clock signal and the horizontal axis in the first period. Through the application, automatic signal output control can be performed based on the eye diagram.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display driving method and a display device. Background Technology

[0002] As display products have evolved, more and more customers demand larger-sized products. Simultaneously, the larger the product size, the higher the data transmission rate required, and the higher the requirements for the quality of data signal transmission. Therefore, ensuring the stability, consistency, and accuracy of data transmission in large-size display products is a crucial control point. Since larger display products require more data transmission and have a faster transmission rate per unit time, the quality of high-speed transmission signals is usually measured using an eye diagram. An eye diagram reflects signal quality; a poor eye diagram indicates potential problems such as inter-symbol interference, voltage noise, excessive duty cycle, and signal jitter. While the eye diagram itself does not affect the display effect, it can reveal some display issues. Currently, eye diagram quality can be improved by manually controlling the signal output. When the eye diagram quality meets requirements, the current display effect is considered satisfactory. However, this method is time-consuming, labor-intensive, and inefficient. Summary of the Invention

[0003] This application provides a display driving method and a display device that can perform automated signal output control based on an eye diagram.

[0004] In a first aspect, this application provides a display driving method, the method comprising: obtaining a first time point and a second time point of a data signal in a first cycle of the eye diagram based on the current eye diagram data of the display, and a third time point of a clock signal in the first cycle of the eye diagram; calculating a first phase difference and a second phase difference between the data signal and the clock signal based on the first time point, the second time point and the third time point; and performing signal output control on the driving module of the display based on the first phase difference and the second phase difference; wherein, in the eye diagram data, the negative boundary time point of the data signal and the horizontal axis in the first cycle is the first time point, the positive boundary time point of the data signal and the horizontal axis in the first cycle is the second time point, and the boundary time point of the clock signal and the horizontal axis in the first cycle is the third time point.

[0005] As can be seen, by detecting the current eye diagram data of the display, the first, second, and third time points in the eye diagram can be obtained. Based on the first, second, and third time points, the first and second phase differences between the data signal and the clock signal can be calculated. Automated signal output control of the display's drive module is then performed using these first and second phase differences, thereby improving the quality of the eye diagram and ultimately enhancing the product's display effect.

[0006] In one possible implementation, the driving module includes a driving chip, and the signal output control of the driving module for the display based on the first phase difference and the second phase difference may include: determining the output time of the data signal based on the first phase difference and the second phase difference; and outputting the data signal to the driving chip based on the output time of the data signal.

[0007] It is evident that the output time of the data signal can be automatically controlled by obtaining the first phase difference and the second phase difference.

[0008] In one possible implementation, determining the output time of the data signal based on the first phase difference and the second phase difference may include: determining the output time of the data signal based on the first phase difference and the first threshold when the first phase difference is less than a first threshold; or determining the output time of the data signal based on the second phase difference and the second threshold when the second phase difference is less than the second threshold.

[0009] It can be seen that the output time of the data signal can be determined based on the first phase difference and the first threshold.

[0010] In one possible implementation, the above-mentioned signal output control of the display driving module based on the first phase difference and the second phase difference may include: when the first phase difference is less than a first threshold, determining the delay time information of the data signal and performing delayed output processing on the data signal based on the delay time information; or when the second phase difference is less than a second threshold, determining the advance time information of the data signal and performing advance output processing on the data signal based on the advance time information.

[0011] It is evident that, if the first phase difference does not meet the threshold, the data signal should be processed by automated delayed output; if the second phase difference does not meet the threshold, the data signal should be processed by automated early output.

[0012] In one possible implementation, before obtaining the first time point of the data signal and the second time point of the data signal in the first cycle of the eye diagram based on the current eye diagram data of the display, and the third time point of the clock signal in the first cycle of the eye diagram, the method may further include: sending a start signal to the driver chip, the start signal being used to instruct the driver chip to drive the display to show the target image; and generating the current eye diagram data of the display upon receiving an end signal from the driver chip.

[0013] As can be seen, after the driver chip completes the display of the target image, it can generate the current eye diagram data of the display so that the timing control chip can analyze the current eye diagram data of the display and perform automated signal output control based on the eye diagram.

[0014] In one possible implementation, the driving module includes a driving chip. The signal output control of the driving module for the display based on the first phase difference and the second phase difference may include: when the first phase difference or the second phase difference meets the control conditions, sending an output adjustment signal to the driving chip, the output adjustment signal being used to control the driving chip to adjust the output time of the data signal according to the register parameters.

[0015] As can be seen, the timing control chip can also send an output adjustment signal to the driver chip when the first phase difference or the second phase difference meets the control conditions. The output adjustment signal is used to control the driver chip to automatically adjust the output time of the data signal according to the register parameters, thereby reducing the computing power required by the timing control chip and reducing the cost of the timing control chip.

[0016] In one possible implementation, the above method may further include: setting the control pin to a low level when the first phase difference and the second phase difference do not meet the control conditions.

[0017] It can be seen that if the first phase difference or the second phase difference does not meet the control conditions, the timing control chip can set the control pin to a low level, thereby stopping the driver chip from controlling the signal output of the display's driver module.

[0018] Secondly, embodiments of this application provide a display device, which includes a driving module and a display unit. The driving module includes a timing control chip and a driving chip. The driving chip is used to display an image through the display unit in response to the control of the timing control chip. The timing control chip obtains a first time point and a second time point of the data signal in the first cycle of the eye diagram, and a third time point of the clock signal in the first cycle of the eye diagram, based on the current eye diagram data of the display device. The timing control chip is also used to calculate a first phase difference and a second phase difference between the data signal and the clock signal based on the first time point, the second time point, and the third time point. The timing control chip is also used to perform signal output control on the driving module of the display device based on the first phase difference and the second phase difference. In the eye diagram data, the negative boundary time point of the data signal and the horizontal axis in the first cycle is the first time point, the positive boundary time point of the data signal and the horizontal axis in the first cycle is the second time point, and the boundary time point of the clock signal and the horizontal axis in the first cycle is the third time point.

[0019] In one possible implementation, the timing control chip is further configured to send an output adjustment signal to the driver chip when the first phase difference or the second phase difference meets the control conditions. The output adjustment signal is used to control the driver chip to adjust the output time of the data signal according to the register parameters.

[0020] In one possible implementation, the timing control chip is also used to set the control pin to a low level when the first phase difference and the second phase difference do not meet the control conditions.

[0021] Thirdly, embodiments of this application provide an electronic device, which includes: a memory for storing a program; and a processor for executing the program stored in the memory. When the program is executed by the processor, the processor executes a method as described in any of the possible implementations of the first aspect.

[0022] Fourthly, embodiments of this application provide a computer storage medium storing a computer program, the computer program including program instructions, and when the program instructions are executed by a processor, the processor performs a method as described in the first aspect and any possible implementation thereof.

[0023] Fifthly, embodiments of this application provide a computer program product, which includes: instructions or a computer program; when the instructions or the computer program are executed, the method in the first aspect and any possible implementation of the first aspect is implemented.

[0024] Sixthly, embodiments of this application provide a chip including a processor. The processor executes instructions, which, when executed, cause the chip to perform the methods described in the first aspect and any possible implementation thereof. Optionally, the chip further includes an input / output interface for receiving or transmitting signals. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the structure of a display device provided in an embodiment of this application; Figure 2 A flowchart illustrating a display driving method provided in an embodiment of this application; Figure 3 A schematic diagram of an eye diagram provided for an embodiment of this application; Figure 4This is a schematic flowchart illustrating signal output control of a timing control chip, provided as an embodiment of this application. Figure 5 This is a schematic diagram of the structure of a timing control chip provided in an embodiment of this application; Figure 6 This is a schematic flowchart illustrating signal output control of a driver chip, provided as an embodiment of this application. Figure 7 This is a schematic diagram of the structure of a timing control chip and a driver chip provided in an embodiment of this application; Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0027] Explanation of reference numerals in the attached figures: 110 - Driver module, 111 - Timing control chip, 112 - First driver chip, 113 - Second driver chip, 114 - Third driver chip, 115 - Nth driver chip, 120 - Display unit, 510 - Data detection module, 520 - Data analysis module, 530 - Differential signal output module, 710 - Data detection module, 720 - Data analysis module, 730 - Signal receiving module, 740 - Register control module, 750 - Differential signal output module, 810 - Processor, 820 - Communication interface, 830 - Memory, 840 - Bus. Detailed Implementation

[0028] The embodiments of this application will now be described with reference to the accompanying drawings.

[0029] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0030] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0031] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0032] As used in this specification, the terms "component," "module," "system," etc., are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0033] The following describes a display device to which this application embodiment applies.

[0034] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 1As shown, the display device includes a driving module 110 and a display unit 120. The display device can be a monitor. Taking the driving module 110 as an example, where N is a positive integer, the driving module 110 includes a timing control chip 111, a first driving chip 112, a second driving chip 113, a third driving chip 114, ..., an Nth driving chip 115. The number of timing control chips 111 and the number of driving chips are for illustrative purposes only and do not constitute a limitation on the embodiments of this application.

[0035] The timing control chip 111 generates data signals and clock signals, and sends them to each driver chip. The driver chip converts the received data signals and clock signals into signals that the display unit 120 can understand, and displays the image through the display unit 120.

[0036] It should be added that, Figure 1 The A-shaped line in the diagram represents the data feedback path. Figure 1 The b-shaped line in the diagram represents the control command path. Figure 1 The C-shaped line in the diagram represents the data transmission path.

[0037] The timing control chip 111 can send a first start signal to the first driver chip 112 via a control command path. The first start signal instructs the first driver chip 112 to drive the display unit 120 to display the first target image via the data transmission path. After the first driver chip 112 completes the output of the first target image, it can send a second start signal to the second driver chip 113 via a control command path. The second start signal instructs the second driver chip 113 to drive the display unit 120 to display the second target image via the data transmission path. After the second driver chip 113 completes the output of the second target image, it can send a third start signal to the third driver chip 114 via a control command path. The target image is output sequentially from the first driver chip 112 to the Nth driver chip 115. A cascaded structure is formed between the timing control chip 111, the first driver chip 112, the second driver chip 113, the third driver chip 114, ..., the Nth driver chip 115 via start signals.

[0038] After each driver chip completes the output of the target image, it can also send an end signal to the timing control chip 111 through the data feedback path. For example, after the first driver chip 112 completes the output of the first target image, the first driver chip 112 can send a first end signal to the timing control chip 111 through the data feedback path. When the timing control chip 111 receives the first end signal from the first driver chip 112, it generates the current eye diagram data of the display device.

[0039] The following describes the display driver method provided in the embodiments of this application.

[0040] Please see Figure 2 , Figure 2 This is a flowchart illustrating a display driving method provided in an embodiment of this application. Figure 2 As shown, the display driving method may include, but is not limited to, the following steps: S201, based on the current eye diagram data of the display, obtain the first time point of the data signal and the second time point of the data signal in the first cycle of the eye diagram, as well as the third time point of the clock signal in the first cycle of the eye diagram.

[0041] An eye diagram is a statistical distribution diagram naturally formed by superimposing data bits at different positions in a high-speed digital signal according to time intervals. It reflects the overall characteristics of all digital signals in the entire data signal transmission link. An eye diagram can also be described as the result of superimposing a series of different binary codes of a digital signal according to a certain rule. In the mini protocol, the eye diagram is composed of a clock signal and a data signal superimposed, and the eye width directly corresponds to the clock skew value from the clock signal to the data signal. Eye width is a core parameter in high-speed serial communication and signal integrity analysis, used to quantify the stability window of a digital signal in the time domain, directly reflecting the signal's anti-interference capability and system reliability. The wider the eye width, the higher the system's tolerance to clock jitter, data skew, and inter-symbol interference. Therefore, by adjusting the phase relationship between the clock signal and the data signal, the clock skew value from the clock signal to the data signal can be dynamically corrected, thereby improving the eye width and quality of the eye diagram.

[0042] In this system, both clock and data signals are transmitted using differential signals. Differential signals transmit a pair of signals with equal amplitude but opposite phase through two wires. The receiving end extracts the useful information by comparing the difference between the two signals. This method is beneficial for resisting common-mode noise and reducing crosstalk, among other benefits.

[0043] Based on the current eye diagram data of the display, the timing control chip can obtain the first time point of the data signal and the second time point of the data signal in the first cycle of the eye diagram, as well as the third time point of the clock signal in the first cycle of the eye diagram.

[0044] In the eye diagram data, the first cycle can be any cycle within the eye diagram. The first time point is the point where the data signal crosses the horizontal axis from the negative voltage region (zero voltage level) into the positive voltage region within the first cycle. The second time point is the point where the data signal crosses the horizontal axis from the positive voltage region into the negative voltage region within the first cycle. The third time point is the point where the clock signal crosses the horizontal axis (usually the rising edge) within the first cycle.

[0045] In one possible implementation, the timing control chip can automatically identify the negative boundary time point between the data signal and the horizontal axis in the first cycle of the eye diagram based on the current eye diagram data of the display, and determine this negative boundary time point as the first time point. The timing control chip can also automatically identify the positive boundary time point between the data signal and the horizontal axis in the first cycle of the eye diagram based on the current eye diagram data of the display, and determine this positive boundary time point as the second time point. Finally, the timing control chip can automatically identify the boundary time point between the clock signal and the horizontal axis in the first cycle of the eye diagram based on the current eye diagram data of the display, and determine this boundary time point as the third time point.

[0046] like Figure 3 As shown, Figure 3 This is a schematic diagram of an eye diagram provided in an embodiment of this application. The eye diagram is composed of a clock signal and a data signal superimposed on each other. Figure 3 In the diagram, solid lines represent data signals, and dashed lines represent clock signals. The area enclosed by the rectangle represents the first cycle; optionally, the first cycle can also be any other cycle in the eye diagram.

[0047] The timing control chip can automatically identify the current eye diagram of the display, and identify the negative intersection point between the data signal and the horizontal axis in the first cycle, i.e. Figure 3 T1 is defined as the first time point. The orthogonal boundary time point between the data signal and the horizontal axis in the first cycle is identified, i.e. Figure 3 T2 in the time frame is determined as the second time point. The intersection point between the clock signal and the horizontal axis in the first cycle is identified, i.e. Figure 3 T3 in the time frame is determined as the third time point.

[0048] S202, based on the first time point, the second time point and the third time point, calculate the first phase difference between the data signal and the clock signal, and the second phase difference between the data signal and the clock signal.

[0049] In one possible implementation, a first phase difference between the data signal and the clock signal can be calculated based on a first time point and a third time point; a second phase difference between the data signal and the clock signal can be calculated based on a second time point and a third time point. That is, the time difference between the first time point and the third time point is the first phase difference, and the time difference between the second time point and the third time point is the second phase difference.

[0050] The clock offset from the clock signal to the data signal is the sum of the first phase difference and the second phase difference; that is, the eye width is the sum of the first phase difference and the second phase difference. The larger the sum of the first phase difference and the second phase difference, the larger the eye width, the higher the system's tolerance to non-ideal factors such as clock jitter and transmission delay, the more reliable the signal quality, and the better the final display effect.

[0051] like Figure 3 As shown, the first phase difference is T3-T1, and the second phase difference is T2-T3. The eye width is T2-T1.

[0052] The first phase difference is the setup time of the data signal, and the second phase difference is the hold time of the data signal. The setup time is the minimum time the data signal must remain stable before the arrival of the valid edge of the clock signal (such as a rising or falling edge). This ensures that the data is completely stable when the clock is sampled, avoiding sampling errors caused by data changes. The hold time is the minimum time the data signal must remain stable after the arrival of the valid edge of the clock signal. This prevents rapid data changes after clock sampling, which could lead to unstable sampling results.

[0053] The mini protocol explicitly specifies the minimum setup and hold times. When the driver chip transmits data and clock signals to external devices (such as receiver chips, buses, or other modules), it must ensure that the time difference between the actual transmitted data and clock signals meets the minimum setup and hold times. If the setup time is insufficient, the clock may sample unstable data in a transitional state; if the hold time is insufficient, the data may change immediately after sampling, leading to incorrect latch values ​​at the receiver.

[0054] In one possible implementation, the timing control chip includes an algorithm controller, which can be used to calculate a first phase difference between the data signal and the clock signal, and a second phase difference between the data signal and the clock signal, based on a first time point, a second time point, and a third time point.

[0055] S203, based on the first phase difference and the second phase difference, performs signal output control on the display's driving module.

[0056] The display's driving module includes a timing control chip and a driving chip, which can control the signal output of the timing control chip or the driving chip based on a first phase difference and a second phase difference.

[0057] like Figure 4 As shown, Figure 4 This is a schematic diagram illustrating a signal output control process for a timing control chip, provided as an embodiment of this application.

[0058] S401, the timing control chip sends a start signal to the driver chip. Correspondingly, the driver chip receives the start signal from the timing control chip.

[0059] The start signal is used to instruct the driver chip to drive the display to show the target image.

[0060] In this embodiment of the application, the driver chip is Figure 1 The first driver chip in the process.

[0061] Understandably, the driver chip can also be Figure 1 This refers to any one of the driver chips other than the first driver chip. At this time, the start signal will be sent by the preceding driver chip. For example, in this case, the driver chip is... Figure 1 When the second driver chip is shown, a start signal is sent from the first driver chip to the second driver chip. This start signal is used to instruct the second driver chip to drive the display to show the target image. In this driver chip... Figure 1 When the Nth driver chip is shown, the start signal is sent from the (N-1)th driver chip to the Nth driver chip. This start signal is used to instruct the Nth driver chip to drive the display to show the target image.

[0062] S402, the driver chip drives the display to show the target image.

[0063] In this embodiment, upon receiving the start signal, the driver chip immediately activates the driver stage circuits of channels 1 to 966. Each channel sequentially outputs a pulse width modulation (PWM) signal or analog voltage according to a preset line scanning timing (such as line-by-line illumination or partitioned refresh), driving the corresponding display unit to display the target image. The target image is a blank screen, such as a black screen or a blank screen, to avoid any abnormal image display caused by interference during initial data transmission.

[0064] S403, the driver chip sends a stop signal to the timing control chip. Correspondingly, the timing control chip receives the stop signal from the driver chip.

[0065] In this embodiment, after the driver chip completes the output of the target image, it sends an end signal to the timing control chip. The end signal is used to indicate that the driver chip has completed the output of the target image.

[0066] Understandably, in the driver chip is Figure 1 When any of the other driver chips besides the first driver chip is used, after the driver chip has completed the output of the target image, it also sends an end signal to the timing control chip.

[0067] For example, in the driver chip for Figure 1 When the second driver chip is shown, after completing the output of the target image, it sends an end signal to the timing control chip. This end signal is used to indicate that the second driver chip has completed the output of the target image. In this driver chip... Figure 1 When the Nth driver chip is shown, after the Nth driver chip completes the output of the target image, it sends an end signal to the timing control chip. This end signal is used to instruct the Nth driver chip to complete the output of the target image.

[0068] In one possible implementation, the timing control chip includes a signal controller for receiving a termination signal from the driver chip.

[0069] S404, the timing control chip, generates the current eye diagram data of the display.

[0070] In one possible implementation, the timing control chip generates the current eye diagram data of the display when it receives an end signal from the driver chip.

[0071] In one possible implementation, the timing control chip also receives data signals and clock signals from the driver chip. When the timing control chip receives the end signal from the driver chip, it generates the current eye diagram data of the display based on the data signals and clock signals.

[0072] The S405 timing control chip obtains the first time point of the data signal and the second time point of the data signal in the first cycle of the eye diagram based on the current eye diagram data of the display, as well as the third time point of the clock signal in the first cycle of the eye diagram.

[0073] The S406 timing control chip calculates the first phase difference between the data signal and the clock signal, and the second phase difference between the data signal and the clock signal, based on the first time point, the second time point, and the third time point.

[0074] The specific implementation methods of steps S405-S406 can be found above. Figure 2 Steps S201-S202 in the process will not be described again here.

[0075] S407, the timing control chip, determines the output time of the data signal based on the first phase difference and the second phase difference.

[0076] In this embodiment of the application, when the first phase difference is less than the first threshold, the output time of the data signal can be determined based on the first phase difference and the first threshold; or when the second phase difference is less than the second threshold, the output time of the data signal can be determined based on the second phase difference and the second threshold.

[0077] The first threshold is the minimum setup time of the data signal, and the second threshold is the minimum hold time of the data signal. When the first phase difference between the data signal and the clock signal meets the first threshold (i.e., the first phase difference is greater than or equal to the first threshold), and the second phase difference between the data signal and the clock signal meets the second threshold (i.e., the second phase difference is greater than or equal to the second threshold), the data signal can maintain a clear eye diagram shape, and there is no risk of display abnormalities.

[0078] For example, the first threshold is set to 400 ps, ​​and the second threshold is also set to 400 ps. Taking a first phase difference of 300 ps and a second phase difference of 500 ps as an example, the first phase difference is less than the first threshold, and the second phase difference is greater than the second threshold. Therefore, the output time of the data signal can be determined based on the first phase difference and the first threshold. That is, based on the first phase difference of 300 ps and the first threshold of 400 ps, ​​the output time of the data signal is adjusted by 100 ps.

[0079] The S408 timing control chip outputs data signals to the driver chip based on the output time of the data signals.

[0080] In this embodiment of the application, the timing control chip can output a data signal to the driver chip based on the redefined output time of the data signal when transmitting the data signal and clock signal corresponding to the next frame of the image, and output a clock signal to the driver chip based on the original output time of the clock signal.

[0081] The timing control chip adjusts the first or second phase difference between the data signal and the clock signal by controlling the output time of the data signal to the driver chip, until the first phase difference between the data signal and the clock signal meets a first threshold, and the second phase difference between the data signal and the clock signal meets a second threshold. This ensures that the data signal and the clock signal maintain a clear eye diagram within the maximum allowable clock offset range, thereby avoiding abnormal screen display issues such as flickering, screen distortion, and data corruption.

[0082] S409, when the first phase difference is less than the first threshold, the timing control chip determines the delay time information of the data signal and performs delayed output processing on the data signal based on the delay time information; or when the second phase difference is less than the second threshold, it determines the advance time information of the data signal and performs advance output processing on the data signal based on the advance time information.

[0083] In this embodiment, the timing control chip can determine the delay time information of the data signal when the first phase difference is less than a first threshold, and perform delayed output processing on the data signal based on the delay time information when transmitting the data signal and clock signal corresponding to the next frame image. Simultaneously, the clock signal is output according to the originally planned clock signal output time. The delay time information includes the time that the data signal needs to be delayed for output, and the timing control chip performs delayed output processing on the data signal based on this required delay time.

[0084] The timing control chip can determine the advance time information of the data signal when the second phase difference is less than the second threshold. When transmitting the data signal and clock signal corresponding to the next frame of the image, it performs advance output processing on the data signal based on the advance time information. Simultaneously, the clock signal is output according to the originally planned clock signal output time. The advance time information includes the time by which the data signal needs to be output in advance, and the timing control chip performs advance output processing on the data signal based on this required advance output time.

[0085] The timing control chip adjusts the first phase difference or the second phase difference between the data signal and the clock signal by performing delayed output processing or advanced output processing on the data signal, until the first phase difference between the data signal and the clock signal meets the first threshold and the second phase difference between the data signal and the clock signal meets the second threshold.

[0086] It should be noted that steps S407 and S408 are one implementation method, while step S409 is another implementation method.

[0087] Through the embodiments of this application, the timing control chip can control the timing of the data signal output to the driver chip by detecting and analyzing the data signal and the clock signal, thereby ensuring that the first phase difference between the data signal and the clock signal meets the first threshold and the second phase between the data signal and the clock signal meets the second threshold, thus improving the quality of the eye diagram and improving the display effect of the display.

[0088] like Figure 5 As shown, Figure 5 This is a schematic diagram of the structure of a timing control chip provided in an embodiment of this application.

[0089] The timing control chip includes a data detection module 510, a data analysis module 520, and a differential signal output module 530.

[0090] The data detection module 510 can be used to obtain the first time point of the data signal and the second time point of the data signal in the first cycle of the eye diagram, as well as the third time point of the clock signal in the first cycle of the eye diagram, based on the current eye diagram data of the display.

[0091] The data analysis module 520 can be used to calculate the first phase difference between the data signal and the clock signal, and the second phase difference between the data signal and the clock signal, based on the first time point, the second time point, and the third time point.

[0092] In one possible implementation, the differential signal output module 530 can be used to determine the output time of the data signal based on the first phase difference and the second phase difference; and to output the data signal to the driver chip based on the output time of the data signal.

[0093] In one possible implementation, the differential signal output module 530 can be used to determine the output time of the data signal based on the first phase difference and the first threshold when the first phase difference is less than the first threshold; or to determine the output time of the data signal based on the second phase difference and the second threshold when the second phase difference is less than the second threshold.

[0094] In another possible implementation, the differential signal output module 530 can be used to determine the delay time information of the data signal when the first phase difference is less than a first threshold, and perform delayed output processing on the data signal based on the delay time information; or to determine the advance time information of the data signal when the second phase difference is less than a second threshold, and perform advance output processing on the data signal based on the advance time information.

[0095] like Figure 6 As shown, Figure 6 This is a schematic diagram of a signal output control process for a driver chip, provided as an embodiment of this application.

[0096] S601, the timing control chip sends a start signal to the driver chip. Correspondingly, the driver chip receives the start signal from the timing control chip.

[0097] S602, the driver chip drives the display to show the target image.

[0098] S603, the driver chip sends a stop signal to the timing control chip. Correspondingly, the timing control chip receives the stop signal from the driver chip.

[0099] S604, the timing control chip, generates the current eye diagram data of the display.

[0100] The S605 timing control chip obtains the first time point and the second time point of the data signal in the first cycle of the eye diagram based on the current eye diagram data of the display, as well as the third time point of the clock signal in the first cycle of the eye diagram.

[0101] The S606 timing control chip calculates the first phase difference between the data signal and the clock signal, and the second phase difference between the data signal and the clock signal, based on the first time point, the second time point, and the third time point.

[0102] The specific implementation methods of steps S601-S606 can be found above. Figure 4 Steps S401-S406 in the process will not be repeated here.

[0103] S607: When the first phase difference or the second phase difference meets the control condition, the timing control chip sends an output adjustment signal to the driver chip. Correspondingly, the driver chip receives the output adjustment signal from the timing control chip.

[0104] The control conditions are that the first phase difference is less than a first threshold and the second phase difference is less than a second threshold. Either the first phase difference or the second phase difference satisfies the control condition, i.e., the first phase difference is less than the first threshold, or the second phase difference is less than the second threshold. The output adjustment signal is used to control the driver chip to adjust the output time of the data signal according to the register parameters.

[0105] In this embodiment, when the first phase difference is less than the first threshold or the second phase difference is less than the second threshold, the timing control chip will send an output adjustment signal to the driver chip.

[0106] In one possible implementation, the timing control chip includes a control pin. When the first phase difference is less than a first threshold or the second phase difference is less than a second threshold, the timing control chip sets the control pin to a high level. At this time, the timing control chip will send a high-level signal to the driver chip, which is the output adjustment signal.

[0107] The S608 driver chip adjusts the output time of the data signal according to the register parameters.

[0108] The register parameter consists of 8 binary bits, each of which can represent 0 or 1, so the register parameter can include 256 levels (0-255).

[0109] In one possible implementation, each level can correspond to a different adjustment time of the data signal, and high-precision output adjustment of the data signal can be achieved through different register parameters.

[0110] In one possible implementation, when the first phase difference is less than a first threshold, the driver chip adjusts the output time of the data signal by delaying the output according to the register parameters. When the second phase difference is less than a second threshold, the driver chip adjusts the output time of the data signal by advancing the output according to the register parameters.

[0111] For example, the adjustment time for the data signals corresponding to register parameters of level 0 to level 255 is 1ps to 256ps respectively.

[0112] When the first phase difference is less than the first threshold and the register parameter level is 0, the driver chip delays the output time of the data signal to the display unit by 1 ps. When the second phase difference is less than the second threshold and the register parameter level is 0, the driver chip advances the output time of the data signal to the display unit by 1 ps. When the first phase difference is less than the first threshold and the register parameter level is 20, the driver chip delays the output time of the data signal to the display unit by 21 ps. When the second phase difference is less than the second threshold and the register parameter level is 20, the driver chip advances the output time of the data signal to the display unit by 21 ps.

[0113] In another possible implementation, each level corresponds to a different output time of the data signal. The output time of the data signal is directly determined by different register parameters.

[0114] For example, the output time of the data signal corresponding to register parameters from level 0 to level 255 increases progressively. The lower the level of the register parameter, the earlier the driver chip outputs the data signal. Conversely, the higher the level of the register parameter, the later the driver chip outputs the data signal.

[0115] The timing control chip's output time of the data signal corresponds to register parameters at level 125. When the first phase difference is less than a first threshold, the driver chip can adjust the register parameters in progressively decreasing steps starting from level 125, thereby delaying the output time of the data signal. When the second phase difference is less than a second threshold, the driver chip can adjust the register parameters in progressively increasing steps starting from level 125, thereby advancing the output time of the data signal.

[0116] In one possible implementation, the driver chip can adjust the output time of the data signal to the display unit of the monitor according to register parameters while transmitting the data signal and clock signal corresponding to the current frame image. Optionally, the driver chip can also adjust the output time of the data signal to the display unit of the monitor according to register parameters while transmitting the data signal and clock signal corresponding to the next frame image.

[0117] S609, the timing control chip sets the control pin to a low level when the first phase difference and the second phase difference do not meet the control conditions.

[0118] In one possible implementation, when the timing control chip detects that the first phase difference and the second phase difference do not meet the control conditions, it sets the control pin to a low level. At this time, the timing control chip will send a low-level signal to the driver chip. This low-level signal is used to instruct the driver chip not to adjust the output time of the data signal according to the register parameters, but to output the data signal according to the original data signal output time.

[0119] Through the embodiments of this application, the timing control chip can detect and analyze data signals and clock signals, and when the first phase difference or the second phase difference meets the control conditions, send an output adjustment signal to the driver chip. The driver chip then controls the signal output of the display's driving module. This reduces the computing power required by the timing control chip, lowers its cost, and improves the quality of the eye diagram, thereby enhancing the display effect.

[0120] Simultaneously, a dynamic image quality optimization function interface can be opened to users. When the signal integrity of the user-end product deteriorates due to environmental factors such as component aging, temperature drift, or external power fluctuations during long-term use (e.g., deterioration of eye diagram opening or increased jitter), users can enable the intelligent compensation mode by calling the open dynamic image quality optimization function interface. After activation, the system's built-in timing control chip will initiate real-time eye diagram detection and analysis. When the first phase difference or second phase difference of the eye diagram meets the control conditions, it sends an output adjustment signal to the driver chip, which then controls the signal output of the user-end product's drive module. This achieves dynamic recovery of eye diagram quality without manual intervention, ensuring that the displayed image always maintains the design standard signal-to-noise ratio and bit error rate performance.

[0121] like Figure 7 As shown, Figure 7 This is a schematic diagram of the structure of a timing control chip and a driver chip provided in an embodiment of this application.

[0122] The timing control chip includes a data detection module 710 and a data analysis module 720. The driver chip includes a signal receiving module 730, a register control module 740, and a differential signal output module 750.

[0123] The data detection module 710 can be used to obtain the first time point of the data signal and the second time point of the data signal in the first cycle of the eye diagram, as well as the third time point of the clock signal in the first cycle of the eye diagram, based on the current eye diagram data of the display.

[0124] The data analysis module 720 can be used to calculate the first phase difference between the data signal and the clock signal, and the second phase difference between the data signal and the clock signal, based on the first time point, the second time point, and the third time point.

[0125] The signal receiving module 730 can be used to receive output adjustment signals from the timing control chip.

[0126] The register control module 740 can be used to cache register parameters.

[0127] The differential signal output module 750 can be used to adjust the output time of the data signal according to the register parameters.

[0128] This application also provides an electronic device; please refer to [link / reference]. Figure 8 , Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0129] like Figure 8 As shown, the electronic device may include: one or more processors 810, one or more memories 830, one or more communication interfaces 820, and a bus 840, wherein the processors 810, memories 830, and communication interfaces 820 are connected via the bus 840.

[0130] The memory 830 is used to store a program; the processor 810 is used to execute the program stored in the memory. When the program is executed, the processor 810 performs the method as described in any possible implementation of the display driving method.

[0131] It should be understood that, in the embodiments of this application, the memory 830 mentioned above includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or compact disc read-only memory (CDROM), as well as external memory other than computer memory and processor cache. A portion of the memory 830 may also include non-volatile random access memory. For example, the memory 830 may also store device type information.

[0132] The processor 810 described above can be one or more central processing units (CPUs). If the processor 810 is a CPU, it can be a single-core CPU or a multi-core CPU. The processor 810 can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0133] The steps performed in the foregoing embodiments can be based on the above. Figure 8 The illustrated electronic device is implemented such that processor 810 can execute any of the optional embodiments of the display driving method provided in this application. Memory 830 can provide a cache when processor 810 executes the method in any of the possible implementations of the display driving method described above, and can also store the computer programs required by processor 810 to execute the method in any of the possible implementations of the display driving method described above.

[0134] In one possible implementation, the electronic device can be connected to the display device via wired or wireless means, and the display device includes a timing control chip and a driver chip. When the electronic device is connected to the display device, the timing control chip and driver chip in the display device can achieve the above-mentioned functionality. Figure 2 , Figure 4 or Figure 6 The method shown.

[0135] This application also provides a computer storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor, enable the processor to implement the above-mentioned functions. Figure 2 , Figure 4 or Figure 6 The method shown.

[0136] This application also provides a computer program product, which includes: instructions or a computer program; when the instructions or the computer program are executed, the above-mentioned functions can be achieved. Figure 2 , Figure 4 or Figure 6 The method shown.

[0137] This application also provides a chip, which includes a processor. The processor executes instructions, enabling the chip to achieve the aforementioned... Figure 2 , Figure 4 or Figure 6 The method shown is described above. Optionally, the chip also includes a communication interface for receiving or transmitting signals.

[0138] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by hardware related to computer programs. The computer programs can be stored in computer storage media, and when executed, they can implement the processes of the above method embodiments. The aforementioned computer storage media include various media capable of storing computer program code, such as read-only memory (ROM) or random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A display driving method, characterized in that, include: Based on the current eye diagram data of the display, the first time point of the data signal and the second time point of the data signal in the first cycle of the eye diagram are obtained, as well as the third time point of the clock signal in the first cycle of the eye diagram. Based on the first time point, the second time point, and the third time point, calculate the first phase difference between the data signal and the clock signal, and the second phase difference between the data signal and the clock signal; The signal output control of the display's driving module is based on the first phase difference and the second phase difference; In the eye diagram data, the negative intersection point of the data signal and the horizontal axis in the first cycle is the first time point, the positive intersection point of the data signal and the horizontal axis in the first cycle is the second time point, and the intersection point of the clock signal and the horizontal axis in the first cycle is the third time point.

2. The method as described in claim 1, characterized in that, The driving module includes a driving chip, and the signal output control of the driving module for the display based on the first phase difference and the second phase difference includes: The output time of the data signal is determined based on the first phase difference and the second phase difference; Based on the output time of the data signal, the data signal is output to the driver chip.

3. The method as described in claim 2, characterized in that, Determining the output time of the data signal based on the first phase difference and the second phase difference includes: If the first phase difference is less than a first threshold, the output time of the data signal is determined based on the first phase difference and the first threshold; or If the second phase difference is less than the second threshold, the output time of the data signal is determined based on the second phase difference and the second threshold.

4. The method as described in claim 1, characterized in that, The step of controlling the signal output of the display's driving module based on the first phase difference and the second phase difference includes: If the first phase difference is less than a first threshold, determine the delay time information of the data signal, and perform delay output processing on the data signal based on the delay time information; or If the second phase difference is less than the second threshold, the advance time information of the data signal is determined, and advance output processing is performed on the data signal based on the advance time information.

5. The method according to any one of claims 2-4, characterized in that, Before obtaining the first time point of the data signal in the first cycle of the eye diagram and the second time point of the data signal, and the third time point of the clock signal in the first cycle of the eye diagram based on the current eye diagram data of the display, the method further includes: A start signal is sent to the driver chip, the start signal being used to instruct the driver chip to drive the display to show the target image; Upon receiving a termination signal from the driver chip, the current eye diagram data of the display is generated.

6. The method according to any one of claims 1-4, characterized in that, The driving module includes a driving chip, and the signal output control of the driving module for the display based on the first phase difference and the second phase difference includes: When the first phase difference or the second phase difference meets the control conditions, an output adjustment signal is sent to the driver chip. The output adjustment signal is used to control the driver chip to adjust the output time of the data signal according to the register parameters.

7. The method as described in claim 6, characterized in that, The method further includes: If the first phase difference and the second phase difference do not meet the control conditions, the control pin is set to a low level.

8. A display device, characterized in that, The display device includes a driving module and a display unit. The driving module includes a timing control chip and a driving chip. The driving chip is used to display an image through the display unit in response to the control of the timing control chip. The timing control chip is used to obtain, based on the current eye diagram data of the display device, a first time point of the data signal in the first cycle of the eye diagram and a second time point of the data signal, as well as a third time point of the clock signal in the first cycle of the eye diagram. The timing control chip is further configured to calculate, based on the first time point, the second time point, and the third time point, a first phase difference between the data signal and the clock signal, and a second phase difference between the data signal and the clock signal; The timing control chip is also used to control the signal output of the driving module of the display device based on the first phase difference and the second phase difference; In the eye diagram data, the negative intersection point of the data signal and the horizontal axis in the first cycle is the first time point, the positive intersection point of the data signal and the horizontal axis in the first cycle is the second time point, and the intersection point of the clock signal and the horizontal axis in the first cycle is the third time point.

9. The display device as claimed in claim 8, characterized in that, The timing control chip is further configured to send an output adjustment signal to the driver chip when the first phase difference or the second phase difference meets the control conditions. The output adjustment signal is used to control the driver chip to adjust the output time of the data signal according to the register parameters.

10. The display device as claimed in claim 8, characterized in that, The timing control chip is also used to set the control pin to a low level when the first phase difference and the second phase difference do not meet the control conditions.

Images