A spaceborne ultra-large-scale digital phased array system based on JESD204B clock synchronization network

Abstract

This application relates to a spaceborne ultra-large-scale digital phased array system based on a JESD204B clock synchronization network. It includes a radio frequency antenna layer for receiving and transmitting electromagnetic waves in space, and for converting between radio frequency signals and space electromagnetic waves; a sub-array baseband layer for sampling, transmitting, and digitally multi-beamforming in the transceiver link of 64-channel S-band intermediate frequency signals, and for data transmission with the motherboard clock layer. It also performs reconfiguration of the baseband module signal processing FPGA via a low-speed interface; the motherboard clock layer handles data aggregation and distribution, and performs task scheduling and management for the entire digital phased array system. An on-board JESD204B clock tree network is designed to distribute clocks to each baseband module to synchronize the target signal for synchronous sampling and transmission output. This system enables access for massive numbers of ground users and provides efficient tracking and precise pointing.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a spaceborne ultra-large-scale digital phased array system based on the JESD204B clock synchronization network. Background Technology

[0002] With the continuous upgrading of communication technologies and the needs of national strategies, the future communication field will inevitably develop towards a combination of satellite communication and terrestrial mobile communication. Among these, digital phased array systems in satellite communication are the core technology supporting modern and future integrated space-air information networks. Their application background mainly stems from the deep integration of accelerated global digitalization and upgraded communication demands. Firstly, low Earth orbit can only accommodate approximately 60,000 satellites. With the accelerated construction of national constellations such as Starlink and GW constellations, orbital and communication frequency band resources are becoming increasingly saturated, necessitating the use of phased array systems to achieve higher spectrum reuse and dynamic resource allocation. Traditional spaceborne phased array systems using static single-beam, fixed multi-beam, and uniform power distribution technologies are no longer able to meet the traffic demands of users in different regions and time periods, resulting in uneven distribution of communication resources and an inability to achieve optimal allocation. However, using DBF technology can dynamically adjust beam direction, coverage, and transmission power, thereby improving network service quality. Secondly, with the large-scale application of direct satellite connection technology for mobile phones, low-Earth orbit satellites will serve a massive number of ground users simultaneously. This requires phased array antennas to generate several independent beams simultaneously. Using DBF technology combined with digital channel partitioning technology, broadband signals are decomposed into several parallel sub-channels to achieve real-time processing of different frequency bands. This allows for a larger number of users and adapts to the on-demand allocation of network bandwidth by different users, greatly improving flexibility. Each beam can independently control its phase and amplitude to achieve precise pointing and network signal coverage for ground users. Multi-channel synchronization technology plays a crucial role in this, directly determining the quality of beamforming and communication capacity. Thirdly, satellite communication in scenarios such as military command and emergency disaster relief requires millisecond-level response. If there is clock deviation in the multi-channel synchronization of a digital phased array system, it will lead to inconsistent signal transmission delays, reducing communication reliability and failing to meet the requirement of rapid emergency link reconstruction through synchronized multi-beams in the event of communication interruption. Since each antenna element in a digital phased array system is equipped with an independent ADC / DAC and RF link, errors introduced by clock deviations or cables affect beam pointing accuracy and signal gain, making the synchronization process more complex and difficult.

[0003] Satellite communication technology can solve the problems of high cost and difficulty in deploying terrestrial base stations on a large scale in remote mountainous areas, oceans, deserts, and other geographically complex or sparsely populated areas, which are inherent to terrestrial 5G mobile communication. The combination of satellite communication and multi-channel synchronization technology in digital phased arrays can provide terrestrial users with higher-quality network services, supporting a larger number of users while maintaining low latency transmission. In the future, it can be widely used in scenarios such as military communications and rapid reconstruction of communication networks during natural disasters.

[0004] Currently, 5G technology employs key technologies such as millimeter wave, massive MIMO, and dense networking. Ground base stations utilize antenna arrays composed of hundreds of antenna elements to serve multiple users and improve network service quality. With the application of antenna arrays, ground base stations can flexibly employ multi-beamforming technology to achieve comprehensive network coverage within a cell. Existing multi-beam array implementations mainly employ analog multi-beam, hybrid multi-beam, and all-digital multi-beam architectures. Analog multi-beam synthesizes beams directly in the RF link by introducing phase shifters and variable gain amplifiers (VGAs). Its advantages include reducing the burden on digital signal processing, eliminating the need for ADC sampling and digital filtering, and offering high real-time performance. However, for large-scale array applications, it cannot reconstruct beams in real-time via software, resulting in a lack of flexibility. Hybrid multi-beaming divides a large-scale antenna array into multiple subarrays in a hierarchical manner. Within a single subarray, the phase and amplitude of the signal are controlled by phase shifters and VGAs to form a relatively wide primary beam. Then, the analog-to-digital signals are converted between each channel through independent ADCs and DACs. The signals from each channel are weighted and summed by FPGAs / DSPs to generate multiple independent high-gain narrow beams to support multi-user scheduling. The advantages are lower hardware complexity and cost, higher flexibility and real-time performance, and the ability to meet microsecond-level beam switching requirements. The disadvantages are that the effective aperture is reduced due to subarray division, the beam gain decreases, and the width of the analog beam limits the maximum scanning range. The all-digital multi-beam architecture places the DBF (Digital Baseband Array) function entirely in the digital domain. The antenna array consists of numerous independent elements, each corresponding to a separate RF transceiver channel, including a low-noise amplifier, power amplifier, and ADC / DAC. The signal received by each element is converted into a digital baseband signal by the ADC and transmitted to the signal processing unit. Transmission is achieved by the DAC unit, which converts the digital signal into an analog RF signal. By weighting the signal of each element in the digital domain with amplitude and phase, independent beams with different directions are generated. The weights are calculated in real-time and dynamically adjusted by the beamforming algorithm. The core advantage of all-digital multi-beam architecture is that the beam direction, shape, and number can be reconstructed in real-time via software, with beam switching time below microseconds, providing extremely high flexibility, faster target detection, and shorter user tracking time. Furthermore, each antenna element is equipped with an independent RF transceiver channel, resulting in higher system reliability and reducing the risk of single-point failures. The disadvantages are that in large-scale antenna array applications, the increased number of channels makes phase synchronization of the transceiver channels more difficult, leading to higher array costs and greater power consumption. Summary of the Invention

[0005] Therefore, it is necessary to provide a spaceborne ultra-large-scale digital phased array system that can achieve massive terrestrial user access, efficient tracking, and precise pointing, thus overcoming the problems of small coverage and high deployment costs of terrestrial 5G communication.

[0006] A spaceborne ultra-large-scale digital phased array system based on the JESD204B clock synchronization network, the system comprising a radio frequency antenna layer, a subarray baseband layer, a motherboard clock layer, and a power management layer; The radio frequency antenna layer is an array composed of multiple patch antennas and corresponding radio frequency links, used to receive and transmit electromagnetic waves in space, and to complete the mutual conversion between radio frequency signals and spatial electromagnetic waves. The subarray baseband layer consists of multiple baseband modules. The baseband modules are used to implement the sampling, transmission and digital domain multi-beam synthesis of 64 intermediate frequency signals in the S-band and the transceiver link. The main external data interface is realized through the 10G optical module that integrates transceiver to realize data transmission with the motherboard clock layer, and the reconstructing function of the baseband module signal processing FPGA is completed through the low-speed interface. The motherboard clock layer is used to realize data exchange between the satellite platform and each baseband module, and plays the role of data aggregation and distribution. It also performs task scheduling and management of the entire digital phased array system, and designs the JESD204B clock tree network and distributes it to each baseband module to synchronize the clock to indicate the target signal to complete synchronous sampling and transmission output. The power management layer distributes power to the RF antenna layer, subarray baseband layer, and motherboard clock layer.

[0007] The aforementioned spaceborne ultra-large-scale digital phased array system based on the JESD204B clock synchronization network, this application takes digital multi-beam technology as its starting point and designs the clock synchronization network of the entire digital phased array data link based on the synchronization of 512 transceiver channels. It uses the JESD204B interface of the RF transceiver and DBF chip to realize the synchronization function of the on-board transceiver channels. Simultaneously, it receives the same clock and SYNC synchronization trigger signal from the motherboard to achieve phase consistency between the transceiver channels of each baseband module, solving the problems caused by differences in power-on cycles, clock skew, and external cable errors among the baseband modules. The introduction of the JESD204B synchronization protocol greatly reduces the requirements for data transmission bus and equal-length clock pair design, simplifies PCB routing, and allows for dynamic compensation of clock skew between different channels through a dedicated clock chip to achieve synchronous sampling and transmission functions. Expanding with 64T64R baseband modules to form a 512T512R digital phased array is very suitable for large-scale applications such as multi-user mobile phone direct satellite connections. To reduce overall system power consumption, the baseband module is designed based on the maximum logic resources and supported channel number of a single DBF chip, combined with eight zero-IF (zero intermediate frequency) RF transceivers. Each transceiver channel supports 64 channels and 64 beamforming, with independent enable control for each channel. The number of channels and beams can be flexibly adjusted to reduce power consumption for different application scenarios. After calibration, the phase difference between the RF transceiver channels is within 2°, demonstrating excellent synchronization performance. This application primarily utilizes the S-band, laying the foundation for the large-scale application of 5G / 6G NTN technology in integrated terrestrial and ground-based network architectures. It enables massive terrestrial user access and efficient tracking and precise pointing, overcoming the limitations of limited coverage and high deployment costs in terrestrial 5G communication. Attached Figure Description

[0008] Figure 1 This is a structural diagram of a spaceborne ultra-large-scale digital phased array system based on a JESD204B clock synchronization network in one embodiment. Figure 2 This is a schematic diagram of a multi-channel synchronous clock network design in one embodiment. Detailed Implementation

[0009] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0010] In one embodiment, such as Figure 1 As shown, a spaceborne ultra-large-scale digital phased array system based on the JESD204B clock synchronization network is provided. The system includes an RF antenna layer, a subarray baseband layer, a motherboard clock layer, and a power management layer. The radio frequency antenna layer is an array composed of multiple patch antennas and corresponding radio frequency links, used to receive and transmit electromagnetic waves in space, and to complete the mutual conversion between radio frequency signals and spatial electromagnetic waves. The subarray baseband layer consists of multiple baseband modules. The baseband modules are used to implement the sampling, transmission and digital domain multi-beam synthesis of 64 intermediate frequency signals in the S-band and the transceiver link. The main external data interface is realized through the 10G optical module that integrates transceiver to realize data transmission with the motherboard clock layer, and the reconstructing function of the baseband module signal processing FPGA is completed through the low-speed interface. The motherboard clock layer is used to realize data exchange between the satellite platform and each baseband module, and plays the role of data aggregation and distribution. It also performs task scheduling and management of the entire digital phased array system, and designs the JESD204B clock tree network and distributes it to each baseband module to synchronize the clock to indicate the target signal to complete synchronous sampling and transmission output. The power management layer distributes power to the RF antenna layer, subarray baseband layer, and motherboard clock layer.

[0011] like Figure 1As shown, the entire digital phased array system consists of four parts: an RF antenna layer, a subarray baseband layer, a motherboard clock layer, and a power management layer. The RF antenna layer is an array composed of multiple patch antennas and corresponding RF links, primarily responsible for receiving and transmitting electromagnetic waves in space, and converting between RF signals and spatial electromagnetic waves. Each antenna element has an independent RF channel and an ADC / DAC unit. The subarray baseband layer controls the amplitude and phase of the RF signals in the RF antenna layer, causing the radiated signals to coherently superimpose in space to form a beam with a specific direction, shape, and radiation pattern. The subarray baseband layer consists of eight baseband modules. Each baseband module primarily implements the sampling, transmission, and digital domain multi-beamforming of 64 intermediate frequency signals in the S-band, and its main external data interface is a 10G transceiver module that transmits data to the motherboard clock layer. It can also perform signal processing FPGA reconfiguration functions through a low-speed interface. Furthermore, to ensure the reliability of the baseband module operating in aerospace irradiation environments, the signal processing FPGA's operating software requires a triple-mode redundancy design. An irradiation-immune control FPGA is used to load, refresh, and monitor the signal processing FPGA's program. Data exchange between the motherboard clock layer and the satellite platform is achieved through the CPRI interface. The motherboard signal processing FPGA packages and classifies the data, and the transceiver optical module distributes the user data to each baseband module for further processing. The motherboard can receive reconstructed data from the satellite platform via a low-speed interface to complete the reconstruction function of the motherboard FPGA. Again, to ensure the motherboard's reliability in aerospace irradiation environments, the signal processing FPGA's operating software also requires a triple-mode redundancy design. An irradiation-immune control FPGA is used to load, refresh, and monitor the signal processing FPGA's program. Another important function of the motherboard clock layer is to distribute the JESD204B clock network to each baseband module and achieve synchronous reception and transmission of 512 RF transceiver channels through the clock tree network of each baseband module. The power management layer primarily distributes power to the RF antenna layer, subarray baseband layer, and motherboard clock layer, and also possesses functions such as self-testing, OC command switching, and status reporting. As can be seen from the hierarchical division, this device employs fully digital multi-beamforming technology. Beamforming no longer relies on phase shifters and VGA units; the synchronization of the 512 RF transceiver channels is mainly implemented and completed within each baseband module.

[0012] This application introduces a fully digital multi-beam architecture, enabling beamforming to be performed in the digital domain. This significantly reduces the pressure on the signal processing FPGA logic resources. The FPGA can flexibly control the DBF chip through multiple parallel interfaces to dynamically adjust the beam direction, shape, and number in real time. Beam switching time is below microseconds, providing extremely high flexibility, resulting in faster target detection and shorter user tracking time. Simultaneously, the 512 transceiver channels support access for a larger number of terrestrial users, addressing the limitations of terrestrial 5G mobile communication such as limited coverage and high deployment costs in remote areas. The fully digital multi-beam architecture ensures a one-to-one correspondence between the antenna, RF, and ADC / DAC channels, resulting in higher system reliability and reducing the risk of single-point failures. Furthermore, the digital phased array allows for independent enable control of each RF transceiver channel to flexibly adjust the number of channels and beams to reduce system power consumption, tailored to different geographical locations and user scenarios. Additionally, the introduction of fully digital multi-beam architecture requires synchronous sampling and processing of data streams from analog to digital ends across the 512 RF receiving channels, as well as synchronous transmission of RF signals from digital to analog ends across the 512 transmitting channels. Relying on the RF transceiver and DBF chip's JESD204B synchronization interface, a two-level clock tree architecture is designed on the motherboard and each baseband module based on this interface characteristic to complete the clock synchronization of the entire array. The clocks at each level are cascaded through the SCLK clock and SYNC synchronization trigger signal. The motherboard signal processing FPGA triggers the clock chip 0 through the SPI interface. Each clock chip responds to the synchronization trigger signal and outputs the edge-aligned SYNC / SYSREF signal to realize the RF transceiver synchronization sampling and data refresh function. The FPGA also uses the sampled SYSREF edge to complete the serial-to-parallel conversion and alignment of the data before forwarding the data synchronously through the 10G optical module. The JESD204B synchronization protocol, combined with an automatic amplitude and phase calibration algorithm, solves the problem of multi-channel synchronization difficulties caused by differences in power-on cycles, clock skew, aging, and temperature and humidity among baseband modules. In particular, the characteristics of the JESD204B protocol greatly reduce the requirements for strict equal-length design of the data transmission bus and clock pairs on the PCB. The dedicated clock chip supports picosecond-level step adjustment accuracy and can dynamically compensate for clock skew between different channels, improving synchronization performance. After calibration, the phase difference of the RF transceiver channels is within 2°, resulting in excellent synchronization performance.

[0013] In one embodiment, the patch antenna unit has an independent radio frequency channel and an ADC / DAC unit. The amplitude and phase of the radio frequency signal of the radio frequency antenna layer are controlled by the subarray baseband layer so that the radiated signals are coherently superimposed in space to form a beam with a specific direction, shape and radiation beam.

[0014] In one embodiment, the operating software of the signal processing FPGA is designed with triple redundancy, and the program loading, refreshing and monitoring functions of the signal processing FPGA are realized through the irradiation-immune control FPGA.

[0015] In one embodiment, the motherboard clock layer is used to exchange data with the satellite platform through the CPRI interface. The data is packaged and classified by the motherboard signal processing FPGA, and the user data is distributed to each baseband module by the transceiver optical module for further processing. The motherboard FPGA completes the reconstruction function by receiving the satellite platform reconstruction data through the low-speed interface.

[0016] In one embodiment, the JESD204B clock tree network is a two-stage pipelined architecture. The high-frequency clock SCLK and synchronization signal SYNC fan out from the motherboard clock chip 1 / 2 and are distributed to the motherboard clock chip 0 of each sub-array baseband. The motherboard clock chip 0 is a clock chip with an internal dual phase-locked loop structure. After frequency multiplication by VCO, it is distributed to clock chip 1 / 2. The SPI pin of the motherboard clock chip 0 is connected to the FPGA to solve the skew or phase reversal problem of each output clock channel under different power-on cycles. The motherboard clock chip 1 / 2 is a clock chip with frequency division function. The baseband module uses two stages of clock chips without PLL to avoid clock frequency deviation and phase ambiguity problems.

[0017] In a specific embodiment, such as Figure 2 As shown, the JESD204B clock synchronization network for both the motherboard and each baseband module adopts a two-stage pipelined architecture. The high-frequency clock SCLK and synchronization signal SYNC, fanned out by the motherboard clock chip 1 / 2, are distributed to the clock chips 0 of each sub-array baseband. Clock chip 0 is designed with an internal dual phase-locked loop (PLL) structure, and the VCO multiplies the frequency before distributing it to clock chips 1 / 2. The advantage of the two-stage PLL structure is that PLL1 has an extremely narrow loop bandwidth, typically tens of Hz, used to clear clock jitter and suppress and filter out spurious high-frequency phase noise from the input clock. PLL2 has a wider loop bandwidth, used to improve the phase noise performance of the output high-frequency clock SCLK and synchronization signal SYNC at the receiving end. The SPI pin of the motherboard clock chip 0 is connected to the FPGA to solve the skew or phase reversal problems of the output clock channels under different power-on cycles. The motherboard clock chip 1 / 2 is designed with a clock chip with frequency division function, and the baseband module is also designed with two-stage clock chips without PLL to avoid clock frequency deviation and phase ambiguity problems.

[0018] In one embodiment, the clock tree network achieves clock synchronization by including: The externally input single-ended clock is converted into a differential clock by a balun and then sent to the CLKIN port of the motherboard clock chip 0 to enter PLL1 as the main clock of the JESD204B clock network. The clock input channel is switched through the internal switch of the chip. A VC-TCXO is selected for the design between the two PLL stages. The output of the VC-TCXO is connected to OSC_FREF as the reference clock input of PLL2. The charge pump output pin CP_OUT of PLL1 is connected to the VC pin of the VC-TCXO to control the voltage-controlled voltage to adjust the frequency deviation of the output clock across the entire temperature range, perform real-time clock calibration, and improve phase noise performance. The motherboard clock chip 0 outputs 3 pairs of reference clock SCLK and SYNC synchronous trigger signals. Two pairs of SCLK clock and SYNC signals are given to the CLKIN and SYNCIN pins of the motherboard clock chip 1 / 2 as input clock and synchronous trigger signals, respectively. The remaining pair of SCLK and SYNC signals are connected to the signal processing FPGA of the motherboard for data stream processing. The motherboard clock chip 0 outputs one pair of GT_CLK clocks, which are connected to the GT Bank of the FPGA for data transmission clocks of the 10G optical module, using the CPRI protocol for communication with the satellite platform. At the same time, it outputs one pair of SCLK clocks, which are then divided into eight pairs of GT_CLK clocks after passing through the clock buffer and sent to the GT Bank of the FPGA for use as the 10G optical module interface for data interaction between various baseband modules.

[0019] In a specific embodiment, the motherboard clock chip 1 / 2 only divides the input clock SCLK. Since the digital phased array system has a total of 8 baseband modules, each clock chip 1 / 2 outputs 4 pairs of SCLK clocks and SYNC synchronization trigger signals to manage and synchronize the JESD204B clocks of the 4 baseband modules. When synchronizing, the motherboard clock chip 1 / 2 needs to respond to the SYNC trigger signal output by clock chip 0 to complete the edge alignment of the output signal SYNC. Considering factors such as anti-interference and testing convenience, RF connectors are used for clock routing between the motherboard and the baseband modules. The differential signal output by the clock is converted into a single-ended signal by a balun, sent to each baseband module via RF cable, and then converted back into a differential signal by a balun before being fed into the input terminal of the baseband module clock chip 0.

[0020] In one embodiment, the baseband module has a two-level clock tree architecture. The clock chip 0 of each baseband module receives the SCLK clock and SYNC synchronization trigger signal output from the motherboard clock chip 1 / 2 as input. After internal frequency division, it outputs two pairs of SCLK clocks and SYNC synchronization signals. These two pairs of clock signals serve as the input reference clock and synchronization trigger signal of the baseband module's clock chip 1 / 2, respectively. Synchronization of the clock chips 0 of each baseband module is achieved by responding to the SYNC trigger signal output by the motherboard clock chip 1 / 2. The clock chip 0 of the baseband module also outputs two pairs of SCLK clocks and SYSREF signals to the signal processing FPGA for use by the JESD204B IP. The clock chip 0 of the baseband module also outputs one pair of GT_CLK clocks to the GTBank of the FPGA for data transmission clock of the 10G optical module. The clocks of the baseband module and the 10G optical module of the motherboard clock layer are designed from the same source. After the clock chip 0 of the baseband module outputs one pair of SCLK clocks into the clock buffer, it splits into eight pairs of GT_CLK clocks and sends them to the GTBank of the FPGA for data transmission with the DBF chip.

[0021] In one embodiment, the clock chip 0 of the baseband module outputs a pair of SCLK clock and SYSREF signals to the DBF chip and provides them to the JESD204B IP core as a data link clock reference. The clock chips 1 and 2 of the baseband module divide the SCLK clock input from the clock chip 0 of the baseband module. Since a single baseband module has 8 RF transceivers, each of the clock chips 1 and 2 outputs 4 pairs of SCLK clocks and SYSREF reference signals to manage and synchronize the clocks of the 4 RF transceivers JESD204B. When synchronizing, the clock chips 1 and 2 of the baseband module respond to the SYNC trigger signal output by the clock chip 0 of the baseband module to complete the edge alignment of the output SYSREF signal. The SCLK clock of the RF transceiver completes the multi-channel synchronous sampling process by capturing the edge-aligned SYSREF signal. The data link is synchronized through the elastic buffer and deterministic delay characteristics of the JESD204B. The synchronization reference is still the edge-aligned SYSREF signal.

[0022] In one embodiment, the baseband module's RF transceiver, DBF chip, and signal processing FPGA are cascaded via JESD204B interfaces. First, JESD204B synchronization between the DBF chip and the FPGA is completed. Then, the FPGA controls the DBF chip to complete the JESD204B interface synchronization process with the RF transceiver.

[0023] In one embodiment, since the synchronization methods of the receiving and transmitting channels are similar, the present invention will describe the data link synchronization process between the DBF chip and the FPGA in the receiving link as an example.

[0024] The clock synchronization process is as follows: The baseband module's signal processing FPGA configures clock chips 0 / 1 / 2. Clock chip 0 receives the SCLK clock and SYNC synchronization signal output from motherboard clock chips 1 / 2, and provides the device clock SCLK and reference clock SYSREF signals to the DBF chip and FPGA chip. The baseband module clock chips 1 / 2 output the device clock SCLK and reference clock SYSREF signals to the RF transceiver. The SCLK clock of each device is divided to obtain the frame clock and multi-frame clock LMFC. The LMFC uses the edge of the captured SYSREF signal for frame data alignment. The deterministic delay is closely related to the edge of the captured LMFC. The edges of the LMFC at both ends of the transmission and reception must be strictly aligned to ensure that the transmission delay between the transmitting and receiving ends of the data is fixed, so as to calculate and compensate for the deterministic delay of the link. The SYSREF signal and SCLK clock must meet timing requirements. The edge of SYSREF is captured by the edge of SCLK clock to complete the leading edge alignment of the frame and LMFC, and the data in BRD is released with the aligned LMFC edge as a reference. When the timing of the two does not meet the setup and hold time requirements, the channel delay can be adjusted separately by the clock chip.

[0025] Finally, due to amplitude and phase errors introduced by passive components and cables, and amplitude and phase deviations caused by aging, temperature, humidity, and other environmental factors in analog components, a calibration algorithm provided by the signal processing FPGA is needed to compensate for amplitude and phase errors between receiving channels and to periodically calibrate each receiving / transmitting channel. This invention employs a specific radiation and phase self-calibration algorithm for a 512-channel digital phased array system. The general process involves multiplexing the working channel as a calibration channel, continuously calculating the gain and phase error of each receiving / transmitting channel in real time using new input / output signal characteristics in a recursive manner, and adjusting the radiation and phase of different channels using the QEC quadrature error calibration module and DC error calibration module built into the RF transceiver. Channel calibration is completed by the configuration parameters sent from the signal processing FPGA to each calibration module of the RF transceiver. The calibration is achieved through electromagnetic wave spatial coupling. This calibration scheme is highly suitable for integrated antenna RF channel design, reducing the size and power consumption of the digital phased array. Multiplexing the working channel as a self-calibration channel provides greater design flexibility; theoretically, any channel can be used as a self-calibration channel or a working channel, thus increasing the overall antenna reliability. The digital phased array receiving channel disclosed this time has a single-tone phase error that can be controlled within 2° after calibration, and the channel phase consistency performance is excellent.

[0026] It should be understood that, although Figure 1The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0027] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0028] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A spaceborne ultra-large-scale digital phased array system based on a JESD204B clock synchronization network, characterized in that, The system includes a radio frequency antenna layer, a subarray baseband layer, a motherboard clock layer, and a power management layer; The radio frequency antenna layer is an array composed of multiple patch antennas and corresponding radio frequency links, used to receive and transmit electromagnetic waves in space, and to complete the mutual conversion between radio frequency signals and spatial electromagnetic waves. The subarray baseband layer consists of multiple baseband modules. These modules are used to implement digital domain multi-beamforming in the sampling, transmission, and transceiver links of 64 intermediate frequency (IF) signals in the S-band. The main external data interface uses a 10G optical transceiver module to transmit data to the motherboard clock layer, and a low-speed interface to reconstruct the signal processing FPGA of the baseband module. The baseband data link of the baseband module includes eight zero-IF architecture RF transceivers, one DBF chip, and one signal processing FPGA. The RF transceivers, DBF chip, and signal processing FPGA of the baseband module are cascaded via JESD204B interfaces. First, JESD204B synchronization between the DBF chip and the FPGA is completed, and then the FPGA controls the DBF chip to complete JESD204B interface synchronization between it and the RF transceivers. The motherboard clock layer is used to realize data exchange between the satellite platform and each baseband module, and plays the role of data aggregation and distribution. It also performs task scheduling and management of the entire digital phased array system, and designs the JESD204B clock tree network and distributes the synchronization clock to each baseband module to indicate the target signal to complete synchronous sampling and transmission output. The JESD204B clock tree network is a two-stage pipeline architecture. The high-frequency clock SCLK and the synchronization trigger signal SYNC fan out by the motherboard clock chips 1 and 2 are distributed to the clock chip 0 of each sub-array baseband. The motherboard clock chip 0 is a clock chip with an internal dual phase-locked loop structure. After frequency multiplication by VCO, it is distributed to the motherboard clock chips 1 and 2. The SPI pin of the motherboard clock chip 0 is connected to the FPGA to solve the skew or phase reversal problem of each output clock channel under different power-on cycles. The motherboard clock chips 1 and 2 are selected as clock chips with frequency division function; The baseband module uses a two-stage clock chip without a PLL to avoid clock frequency offset and phase ambiguity problems. The baseband module adopts a two-level clock tree architecture. The clock chip 0 of each baseband module receives the SCLK clock and SYNC synchronization trigger signal output from the motherboard clock chips 1 and 2 as input. After internal frequency division, it outputs two pairs of SCLK clock and SYNC synchronization trigger signals. These two pairs of clock signals serve as the input reference clock and synchronization trigger signal for the clock chips 1 and 2 of the baseband module, respectively. Synchronization of the clock chips 0 of each baseband module is achieved by responding to the SYNC trigger signal output by the motherboard clock chips 1 and 2. The clock chip 0 of the baseband module also outputs two pairs of SCLK clock and SYSREF signals to the signal processing FPGA for use by the JESD204B IP. The power management layer is a power distribution network for the radio frequency antenna layer, the subarray baseband layer, and the motherboard clock layer.

2. The system according to claim 1, characterized in that, The patch antenna has independent radio frequency channels, ADC and DAC units. The amplitude and phase of the radio frequency signal of the radio frequency antenna layer are controlled by the subarray baseband layer so that the radiated signals are coherently superimposed in space to form a beam with a specific direction, shape and radiation beam.

3. The system according to claim 1, characterized in that, The operating software of the signal processing FPGA is designed with triple redundancy, and the program loading, refreshing and monitoring functions of the signal processing FPGA are realized through the irradiation-immune control FPGA.

4. The system according to claim 1, characterized in that, The motherboard clock layer is used to exchange data with the satellite platform through the CPRI interface. The motherboard signal processing FPGA packages and classifies the data, and the transceiver optical module distributes the user data to each baseband module for further processing. It also receives the satellite platform's reconstructed data through the low-speed interface to complete the reconstructing function of the motherboard signal processing FPGA.

5. The system according to claim 1, characterized in that, The clock tree network achieves clock synchronization through the following processes: The externally input single-ended clock is converted into a differential clock by a balun and then sent to the CLKIN port of the motherboard clock chip 0 to enter PLL1 as the main clock of the JESD204B clock network. The clock input channel is switched through the internal switch of the chip. A VC-TCXO is selected for the design between the two PLL stages. The output of the VC-TCXO is connected to OSC_FREF as the reference clock input of PLL2. The charge pump output pin CP_OUT of PLL1 is connected to the VC pin of the VC-TCXO to control the voltage-controlled voltage to adjust the frequency deviation of the output clock across the entire temperature range and to perform real-time clock calibration. The motherboard clock chip 0 outputs three pairs of reference clock SCLK and SYNC synchronous trigger signals. Two pairs of SCLK clock and SYNC signals are given to the CLKIN and SYNCIN pins of the motherboard clock chips 1 and 2, respectively, as input clock and synchronous trigger signals. The remaining pair of SCLK and SYNC signals are connected to the signal processing FPGA of the motherboard for data stream processing. The motherboard clock chip 0 outputs one pair of GT_CLK clocks, which are connected to the GT Bank of the FPGA for data transmission clocks of the 10G optical module, using the CPRI protocol for communication with the satellite platform. At the same time, it outputs one pair of SCLK clocks, which are then divided into eight pairs of GT_CLK clocks after passing through the clock buffer and sent to the GT Bank of the FPGA for use as the 10G optical module interface for data interaction between various baseband modules.

6. The system according to claim 1, characterized in that, The clock chip 0 of the baseband module also outputs a pair of GT_CLK clocks to the GT Bank of the FPGA for data transmission clocks of the 10G optical module; the clocks of the baseband module and the 10G optical module of the motherboard clock layer are designed from the same source; the clock chip 0 of the baseband module outputs a pair of SCLK clocks, which enter the clock buffer and then splits into 8 pairs of GT_CLK clocks to be sent to the GT Bank of the FPGA for data transmission with the DBF chip.

7. The system according to claim 6, characterized in that, The clock chip 0 of the baseband module outputs a pair of SCLK clock and SYSREF signals, which are connected to the DBF chip and provided to the JESD204B IP core as a data link clock reference. The clock chips 1 and 2 of the baseband module divide the clock SCLK input from the clock chip 0 of the baseband module and each outputs 4 pairs of SCLK clocks and SYSREF reference signals to manage and synchronize the clocks of the 4 JESD204B RF transceivers. When the clock chips 1 and 2 of the baseband module are synchronized, they complete the edge alignment of the output SYSREF signal by responding to the SYNC trigger signal output by the clock chip 0 of the baseband module. The SCLK clock of the RF transceiver completes the multi-channel synchronous sampling process by capturing the edge-aligned SYSREF signal. The data link is synchronized by the elastic buffer and deterministic delay characteristics of the JESD204B. The synchronization reference is still the edge-aligned SYSREF signal.

8. The system according to claim 7, characterized in that, The signal processing FPGA of the baseband module configures the clock chips 0, 1, and 2 of the baseband module. Clock chip 0 receives the SCLK clock and SYNC synchronization trigger signal output from the motherboard clock chips 1 and 2, and provides the device clock SCLK and reference clock SYSREF signals to the DBF chip and FPGA chip. Clock chips 1 and 2 output the device clock SCLK and reference clock SYSREF signals to the RF transceiver. The SCLK clock of each device is divided to obtain the frame clock and multi-frame clock LMFC, where the LMFC captures... The edges of the SYSREF signal are used for frame data alignment. The edges of the LMFC at both the transmitting and receiving ends must be strictly aligned to ensure that the transmission delay between the transmitting and receiving ends is fixed, so as to calculate and compensate for the deterministic delay of the link. The SYSREF signal and the SCLK clock must meet the timing requirements. The edge of the SYSREF signal is captured by the edge of the SCLK clock to complete the leading edge alignment of the frame and the LMFC. The data in the RBD is released with the aligned LMFC edge as a reference. When the timing of the two does not meet the setup and hold time requirements, the channel delay is adjusted separately by the clock chip of the baseband module.

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