Infrared readout circuit and infrared detector

Abstract

An infrared readout circuit and an infrared detector are disclosed. The infrared readout circuit includes a bias unit, a compensation unit, and an integration unit. The bias unit is adapted to output an output signal for one row of pixels. The compensation unit is adapted to compensate the output signal of the target pixel based on the output signals of adjacent pixels, and output a compensation signal. The integration unit is adapted to integrate the compensation signal and output the integration result. This solution can reduce the impact of inconsistent substrate temperature and self-heating effects of the bias circuit on the output signal of the target pixel, thereby improving image quality.

Description

Technical Field

[0001] This invention relates to the field of image processing technology, and in particular to an infrared readout circuit and an infrared detector. Background Technology

[0002] Infrared detectors can detect the infrared radiation from external objects, which is then processed by readout circuits and converted into an image. They have wide applications in both military and civilian fields. Uncooled infrared detectors, in particular, have advantages such as light weight, low power consumption, and low cost because they do not require cooling components, making them a hot topic in infrared imaging research.

[0003] Traditional uncooled infrared detectors suffer from non-ideal factors such as target radiation temperature rise, bias self-heating effect, and inconsistent substrate temperature, which cause non-ideal components in the signal read out by the readout circuit, resulting in poor image quality. Summary of the Invention

[0004] The objective of this invention is at least to provide an infrared readout circuit that can improve image quality.

[0005] In a first aspect, the present invention provides an infrared readout circuit, comprising: a bias unit, a compensation unit, and an integration unit, wherein: the bias unit is adapted to provide an output signal of a pixel; the compensation unit is adapted to compensate the output signal of the target pixel based on the output signals of neighboring pixels of the target pixel, and output a compensation signal; the integration unit is adapted to integrate the signal output by the compensation unit and output the integration result.

[0006] A compensation unit is set up to compensate the output signal of the target pixel based on the output signals of its neighboring pixels, and outputs a compensated signal. The compensation unit integrates the compensated signal and outputs the integration result. This reduces the impact of substrate temperature inconsistencies, bias circuit self-heating effects, and other factors on the output signal of the target pixel, thereby improving image quality.

[0007] Optionally, the adjacent pixels include at least one of the following: m pixels to the left of the target pixel; or n pixels to the right of the target pixel; where n and m are both positive integers.

[0008] Optionally, the compensation unit includes at least one of the following: a first compensation module and a second compensation module; the first compensation module is used to amplify the output signal of the m adjacent pixels to the left of the target pixel by a first coefficient; the second compensation module is used to amplify the output signal of the n adjacent pixels to the right of the target pixel by a second coefficient.

[0009] Optionally, the first compensation module includes: m first multiplication units; wherein, the input terminal of the i-th first multiplication unit is coupled to the output terminal of the i-th pixel among the m adjacent pixels to the left of the target pixel, and its output terminal is coupled to the input terminal of the integration unit, and the amplification factor of the i-th first multiplication unit is the i-th first coefficient; i and n are both positive integers and 1≤i≤m.

[0010] Optionally, the second compensation module includes: n second multiplication units; wherein, the input terminal of the i-th second multiplication unit is coupled to the output terminal of the i-th pixel among the n adjacent pixels to the right of the target pixel, and its output terminal is coupled to the input terminal of the integration unit, and the amplification factor of the i-th second multiplication unit is the i-th second coefficient; i and n are both positive integers and 0≤i≤n.

[0011] Optionally, the compensation unit further includes: a third compensation module; the third compensation module includes: a third operational amplifier, a third feedback resistor, and a third resistor, wherein: the third operational amplifier has a first input terminal receiving a reference voltage, a second input terminal coupled to the output terminal of the target pixel, and an output terminal coupled to the first terminal of the third resistor; the third feedback resistor is coupled between the second input terminal and the output terminal of the third operational amplifier; and the second terminal of the third resistor is coupled to the input terminal of the integration unit.

[0012] Optionally, the first compensation module includes: m first compensation sub-modules, wherein the i-th first compensation sub-module includes: a first operational amplifier, a first feedback resistor, and a first resistor, wherein: the first operational amplifier has a reference voltage input at its first input terminal, its second input terminal is coupled to the output terminal of the i-th pixel among the n adjacent pixels to the left of the target pixel, and its output terminal is coupled to the first terminal of the first resistor; the first feedback resistor is coupled between the second input terminal and the output terminal of the first operational amplifier; the second terminal of the first resistor is coupled to the input terminal of the integration unit; the first coefficient corresponding to the i-th first compensation sub-module is: the quotient of the resistance value of the third resistor and the resistance value of the first resistor of the i-th first compensation sub-module.

[0013] Optionally, the second compensation module further includes: n second compensation sub-modules; the i-th second compensation sub-module includes: a second operational amplifier, a second feedback resistor, and a second resistor, wherein: the second operational amplifier has a reference voltage input at its first input terminal, its second input terminal is coupled to the output terminal of the i-th pixel among the n adjacent pixels to the right of the target pixel, and its output terminal is coupled to the first terminal of the second resistor; the second feedback resistor is coupled between the second input terminal and the output terminal of the second operational amplifier; the second resistor has its second terminal coupled to the input terminal of the integration unit; the second coefficient corresponding to the i-th second compensation sub-module is: the quotient of the resistance value of the third resistor and the resistance value of the second resistor of the i-th second compensation sub-module.

[0014] Optionally, the compensation unit further includes at least one of the following: a first inverting module and a second inverting module; wherein the first inverting module is coupled between the output terminal of the first compensation module and the input terminal of the integrator; and the second inverting module is coupled between the output terminal of the second compensation module and the input terminal of the integrator.

[0015] Optionally, the compensation unit further includes the third compensation module, which further includes: a storage unit for storing a first output signal of a pixel in the previous row that is in the same column as the target pixel; and outputting the first output signal when a control signal is received; a fourth resistor, the first end of which is coupled to the output terminal of the storage unit, and the second end of which is coupled to the input terminal of the third inverting module; the quotient of the resistance value of the third resistor and the resistance value of the fourth resistor is a third coefficient; and a third inverting module, the input terminal of which is coupled to the output terminal of the storage unit, and the output terminal of which is coupled to the input terminal of the integration unit.

[0016] The compensation unit also includes a storage unit that stores the first output signal of the previous row of pixels in the same column as the target pixel. The first output signal is multiplied by a third coefficient to compensate for the output signal of the currently read target pixel. This reduces the impact of bias circuit self-effects and further improves image quality.

[0017] Optionally, the compensation unit includes: a storage unit and a fourth multiplication unit, wherein: the storage unit is used to store the first output signal of the previous row of pixels in the same column as the target pixel; and, when a control signal is received, to output the first output signal; the fourth multiplication unit has its input terminal coupled to the storage unit and its output terminal coupled to the input terminal of the integration unit, and is adapted to amplify the first output signal by a third coefficient and output it.

[0018] The storage unit stores the first output signal of the previous row of pixels in the same column as the target pixel. This first output signal is then multiplied by a third coefficient as compensation for the output signal of the currently read target pixel. This reduces the impact of bias circuit self-effects and improves image quality.

[0019] Optionally, the storage unit includes: a first storage capacitor, a second storage capacitor, a first switching unit, a second switching unit, a third switching unit, and a fourth switching unit, wherein: the first switching unit has a first terminal coupled to the output terminal of the target pixel and a second terminal coupled to the first terminal of the first storage capacitor; the second switching unit has a first terminal coupled to the output terminal of the target pixel and a second terminal coupled to the first terminal of the second storage capacitor; the third switching unit has a first terminal coupled to the second terminal of the first switching unit and a second terminal coupled to the first terminal of the fourth resistor; the fourth switching unit has a first terminal coupled to the second terminal of the second switching unit and a second terminal coupled to the first terminal of the fourth resistor.

[0020] Secondly, the present invention also provides an infrared detector, including the infrared readout circuit provided in any of the above embodiments. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of an infrared readout circuit according to an embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram of pixel distribution in a pixel array according to an embodiment of the present invention;

[0023] Figure 3 This is a schematic diagram of pixel distribution in another pixel array according to an embodiment of the present invention;

[0024] Figure 4 This is a schematic diagram of another infrared readout circuit in an embodiment of the present invention;

[0025] Figure 5 This is a schematic diagram of another infrared readout circuit in an embodiment of the present invention;

[0026] Figure 6 This is a schematic diagram of another infrared readout circuit in an embodiment of the present invention;

[0027] Figure 7 This is a schematic diagram of another infrared readout circuit in an embodiment of the present invention;

[0028] Figure 8 This is a schematic diagram of another infrared readout circuit in an embodiment of the present invention. Detailed Implementation

[0029] As described in the background section, traditional uncooled infrared detectors suffer from non-ideal factors such as target radiation temperature rise, bias self-heating effect, and inconsistent substrate temperature, which cause non-ideal components in the signal read out by the readout circuit, resulting in poor image quality in the final acquisition.

[0030] In this embodiment of the invention, a compensation unit is provided to compensate the output signal of the target pixel based on the output signals of its neighboring pixels, and output a compensation signal. The compensation signal is then integrated by the compensation unit, and the integration result is output. This reduces the impact of substrate temperature inconsistencies, bias circuit self-heating effects, and other factors on the output signal of the target pixel, thereby improving image quality.

[0031] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0032] This invention provides an infrared readout circuit, referring to... Figure 1 The following will provide a detailed explanation through specific steps.

[0033] In this embodiment of the invention, the infrared readout circuit may include: a bias unit 101, a compensation unit 102, and an integration unit 103, wherein:

[0034] Bias unit 101 is adapted to provide the output signal of the pixel;

[0035] The compensation unit 102 is adapted to compensate the output signal of the target pixel based on the output signals of the neighboring pixels of the target pixel, and output a compensation signal.

[0036] The integration unit 103 is adapted to integrate the compensation signal output by the compensation unit 102 and output the integration result.

[0037] In this embodiment of the invention, the output signal of a pixel can refer to either the output current or the output voltage of the pixel. In the following description, the output signal of a pixel will be defined as the output current of the pixel.

[0038] In practical implementation, the infrared readout circuit can output the output signal of a pixel in each clock cycle, with one row of pixels as the unit.

[0039] In this embodiment of the invention, adjacent pixels can be the m pixels to the left of the target pixel; or, adjacent pixels can be the n pixels to the right of the target pixel; or, adjacent pixels can include the m pixels to the left of the target pixel and the n pixels to the right of the target pixel. The values ​​of n and m are both positive integers, and the values ​​of n and m can be equal or unequal.

[0040] like Figure 2 The diagram shows a pixel distribution in a pixel array according to an embodiment of the present invention.

[0041] Figure 2 In this array, the pixel array consists of N rows and M columns of pixels. N and M are both positive integers, and the values ​​of N and M are related to the specific model of the uncooled infrared sensor, the arrangement of the pixels, etc.

[0042] In some embodiments, n and m are both 1, and adjacent pixels are the pixel to the left and the pixel to the right of the target pixel. For example... Figure 2 As shown, the adjacent pixels are the pixel An to the left of the target pixel Bn and the pixel Cn to the right.

[0043] In other embodiments, m is 0, meaning adjacent pixels do not include pixels to the left of the target pixel; and n is 1, meaning adjacent pixels include pixels to the right of the target pixel. For example... Figure 2 As shown, adjacent pixels can also include only pixel Cn.

[0044] In some other embodiments, m is 1 and n is 0, meaning that adjacent pixels only include the target pixel An.

[0045] In this embodiment of the invention, the compensation unit 102 may include at least one of the following: a first compensation module and a second compensation module. Specifically, the first compensation module is used to generate a first compensation component; the second compensation module is used to generate a second compensation component.

[0046] In specific implementation, the first compensation component can be the sum of the products of the output signals of the m adjacent pixels to the left of the target pixel and the first coefficient; the second compensation component can be the sum of the products of the output signals of the n adjacent pixels to the right of the target pixel and the second coefficient.

[0047] If the adjacent units are the m pixels to the left of the target pixel, the compensation unit 102 can generate a first compensation component to compensate the output signal of the target pixel. Therefore, the compensation signal output by the compensation unit 102 is the sum of the output signal of the target pixel and the first compensation component.

[0048] If m is 1, then the first compensation component is the product of the output signal of the pixel adjacent to the left of the target pixel and the first coefficient.

[0049] by Figure 2 For example, the neighboring pixels of the target pixel are pixels An. The compensation signal output by the compensation unit 102 is: α×IAn+IBn, where α is the first coefficient, IAn is the output signal corresponding to pixel An, and IBn is the output signal corresponding to the target pixel Bn.

[0050] If m is 2 or a larger value, then the first compensation component is the sum of the products of the output signals of the m pixels and their respective first coefficients. The first coefficients corresponding to the m pixels can be unequal, partially equal, or all equal.

[0051] For example, adjacent pixels include the two pixels to the left of the target pixel, namely pixel a and pixel b. The first coefficient corresponding to pixel a is α1, and the first coefficient corresponding to pixel b is α2, where α1 ≠ α2. The first compensation component is: α1 × Ia + α2 × Ib. Ia is the output signal of pixel a, and Ib is the output signal of pixel b.

[0052] If the adjacent units are the n pixels to the right of the target pixel, the compensation unit 102 can generate a second compensation component to compensate the output signal of the target pixel. Therefore, the compensation signal output by the compensation unit 102 is the sum of the output signal of the target pixel and the second compensation component.

[0053] If n is 1, then the second compensation component is the product of the output signal of the pixel adjacent to the right of the target pixel and the second coefficient.

[0054] by Figure 2 For example, the neighboring pixels of the target pixel are pixels Cn. The compensation signal output by the compensation unit 102 is: β×ICn+IBn, where β is the second coefficient, ICn is the output signal corresponding to pixel Cn, and IBn is the output signal corresponding to the target pixel Bn.

[0055] If n is 2 or greater, then the second compensation component is the sum of the products of the output signals of the n pixels and their respective second coefficients. The second coefficients corresponding to the n pixels can be unequal, partially equal, or all equal.

[0056] For example, adjacent pixels include the two pixels to the right of the target pixel, namely pixel c and pixel d. The second coefficient corresponding to pixel c is β1, and the second coefficient corresponding to pixel d is β2, where β1 ≠ β2. The first compensation component is: β1 × Ic + β2 × Id. Ic is the output signal of pixel c, and Id is the output signal of pixel d.

[0057] If the adjacent unit includes m pixels to the left and n pixels to the right of the target pixel, then the compensation unit 102 can generate a first compensation component and a second compensation component to compensate the output signal of the target pixel. Therefore, the compensation signal output by the compensation unit 102 is the sum of the output signal of the target pixel, the first compensation component, and the second compensation component.

[0058] by Figure 2For example, the compensation signal output by compensation unit 102 is: α×IAn+IBn+β×ICn.

[0059] In embodiments of the present invention, to achieve compensation for the first row of pixels, the first column of pixels in the pixel array, and the last column of pixels, it is also possible to... Figure 2 In the pixel array shown, one or two rows of blind cells are added, and / or one or two columns of blind cells are added. By setting blind cells, a first compensation component and / or a second compensation component can be provided when the target pixel is a first column of pixels or a first row of pixels.

[0060] like Figure 3 As shown, a schematic diagram of pixel distribution in another pixel array according to an embodiment of the present invention is presented. Figure 3 It can be in Figure 2 Based on this, the first row blind cell, the first column blind cell, the last row blind cell, and the last column blind cell have been added.

[0061] Understandably, it is also possible to... Figure 2 Based on this, only the first row blind cell, the last row blind cell, and the last column blind cell are added. Therefore, no compensation operation is required for the output signal of the first row pixels.

[0062] In this embodiment of the invention, the first compensation module may include m first multiplication units, wherein the input terminal of the i-th first multiplication unit is coupled to the output terminal of the i-th pixel among the m adjacent pixels to the left of the target pixel, and its output terminal is coupled to the input terminal of the integration unit 103; the amplification factor of the i-th first multiplication unit is the i-th first coefficient, 1≤i≤m.

[0063] Combination Figure 2 If the value of m is 1, then the first compensation module includes one first multiplication unit. The input terminal of the first multiplication unit is IAn, and the output of the first multiplication unit is α×IAn.

[0064] The second compensation module may include n second multiplication units, wherein the input terminal of the i-th second multiplication unit is coupled to the output terminal of the i-th pixel among the n adjacent pixels to the right of the target pixel, and its output terminal is coupled to the input terminal of the integration unit 103; the amplification factor of the i-th second multiplication unit is the i-th second coefficient, 1≤i≤n.

[0065] Combination Figure 2 If n is 1, the first compensation module includes one second multiplication unit. The input of the second multiplication unit is ICn, and the output of the second multiplication unit is β×ICn.

[0066] In specific implementation, the aforementioned first multiplication unit and second multiplication unit can be multipliers, current mirrors, or other circuits or components capable of performing multiplication.

[0067] Reference Figure 4 The present invention provides a schematic diagram of another infrared readout circuit in an embodiment of the present invention.

[0068] Figure 4 In the compensation unit 102, there are a first compensation module and a second compensation module. The first compensation module includes a first multiplication unit, the amplification factor of which is a first coefficient. The second compensation module includes a second multiplication unit, the amplification factor of which is a second coefficient.

[0069] like Figure 4 As shown, if the compensation unit 102 only includes the first compensation module, then... Figure 4 The second compensation module shown is removed; if the compensation unit 102 only includes the second compensation module, then it can be removed. Figure 4 The first compensation module shown is removed.

[0070] In some embodiments, the output signal of the target pixel can also be output to the integration unit 103 after passing through the third multiplication unit. Specifically, the output signal of the target pixel is input to the third multiplication unit with an amplification factor of 1. The output terminal of the third multiplication unit is coupled to the input terminal of the integration unit 103, thereby realizing that the output signal input to the integration unit 103 is the same as the output signal input to the multiplication unit.

[0071] like Figure 4 As shown, the compensation unit 102 also includes a third compensation module, which includes a third multiplication unit with an amplification factor of 1.

[0072] It is understandable that if the number of adjacent pixels to the left / right of the target pixel is 2 or more, then a corresponding multiplication unit can be added at the output of the corresponding adjacent pixels, and the amplification factor of the multiplication unit is the corresponding first coefficient / second coefficient.

[0073] For example, if there are two adjacent pixels to the left of the target pixel, then two first multiplication units are set. The first first multiplication unit is coupled to the output of the first adjacent pixel to the left, and the second first multiplication unit is coupled to the output of the second adjacent pixel to the left. The first coefficient of the first first multiplication unit is not equal to the first coefficient of the second first multiplication unit.

[0074] In this embodiment of the invention, the i-th first compensation submodule in the first compensation module may also include: a first operational amplifier, a first feedback resistor, and a first resistor, wherein:

[0075] The first input terminal of the first operational amplifier is input with a reference voltage. The second input terminal of the first operational amplifier is coupled to the output terminal of the i-th pixel among the m adjacent pixels to the left of the target pixel. The output terminal of the first operational amplifier is coupled to the first terminal of the first resistor.

[0076] The first feedback resistor is coupled between the second input terminal and the output terminal of the first operational amplifier.

[0077] The second end of the first resistor is coupled to the input of the integrator 103.

[0078] The i-th second compensation submodule in the second compensation module may also include: a second operational amplifier, a second feedback resistor, and a second resistor, wherein:

[0079] The first input terminal of the second operational amplifier is input with a reference voltage. The second input terminal of the second operational amplifier is coupled to the output terminal of the i-th pixel among the m adjacent pixels to the right of the target pixel. The output terminal of the second operational amplifier is coupled to the first terminal of the second resistor.

[0080] The second feedback resistor is coupled between the second input terminal and the output terminal of the second operational amplifier.

[0081] The second end of the second resistor is coupled to the input of the integrator 103.

[0082] In a specific implementation, the compensation unit 102 may further include a third compensation module, comprising: a third operational amplifier, a third feedback resistor, and a third resistor, wherein:

[0083] The first input terminal of the third operational amplifier is connected to the reference voltage, the second input terminal of the third operational amplifier is coupled to the output terminal of the target pixel, and the output terminal of the third operational amplifier is coupled to the first terminal of the third resistor.

[0084] The third feedback resistor is coupled between the second input terminal and the output terminal of the third operational amplifier.

[0085] The second end of the third resistor is coupled to the input of the integrator 103.

[0086] In specific implementation, the ratio of the resistance value of the third resistor R3 to the resistance value of the first resistor R1 is the first coefficient; the ratio of the resistance value of the third resistor R3 to the resistance value of the second resistor is the second coefficient.

[0087] In specific implementation, the first input terminal of the first operational amplifier A1, the second operational amplifier A2, and the third amplifier A3 can all refer to the positive input terminal of the corresponding operational amplifier, and the second input terminal can all refer to the inverted input terminal of the corresponding operational amplifier.

[0088] Reference Figure 5 The present invention provides a schematic diagram of another infrared readout circuit in an embodiment of the present invention.

[0089] Figure 5 In the compensation unit 102, there are a first compensation module, a second compensation module and a third compensation module.

[0090] Reference Figure 5 The first compensation module includes a first compensation submodule, which includes: a first operational amplifier A1, a first feedback resistor Rf1, and a first resistor R1, wherein:

[0091] The first input terminal of the first operational amplifier A1 is connected to the reference voltage, the second input terminal of the first operational amplifier A1 is coupled to the output terminal of the pixel An, and the output terminal of the first operational amplifier A1 is coupled to the first terminal of the first resistor R1.

[0092] The first feedback resistor Rf1 is coupled between the second input terminal and the output terminal of the first operational amplifier A1;

[0093] The second end of the first resistor R1 is coupled to the input end of the integrator 103.

[0094] The second compensation module includes a second compensation submodule, which comprises: a second operational amplifier A2, a second feedback resistor Rf2, and a second resistor R2, wherein:

[0095] The first input terminal of the second operational amplifier A2 is connected to the reference voltage, the second input terminal of the second operational amplifier A2 is coupled to the output terminal of the pixel Cn, and the output terminal of the second operational amplifier A2 is coupled to the first terminal of the second resistor R2.

[0096] The second feedback resistor Rf2 is coupled between the second input terminal and the output terminal of the second operational amplifier A2.

[0097] The second end of the second resistor R2 is coupled to the input end of the integrator 103.

[0098] The third compensation module includes: a third operational amplifier A3, a third feedback resistor Rf3, and a third resistor R3, wherein:

[0099] The first input terminal of the third operational amplifier A3 is connected to the reference voltage, the second input terminal of the third operational amplifier A3 is coupled to the output terminal of the pixel Bn, and the output terminal of the third operational amplifier A3 is coupled to the first terminal of the third resistor R3.

[0100] The third feedback resistor Rf3 is coupled between the second input terminal and the output terminal of the third operational amplifier A3.

[0101] The second terminal of the third resistor R3 is coupled to the input terminal of the integrator 103. The resistance of the third resistor R3 is R, the resistance of the first resistor is R / α, and the resistance of the second resistor R2 is R / β.

[0102] like Figure 5 As shown, if the compensation unit 102 only includes the first compensation module, then... Figure 5 The second compensation module shown is removed; if the compensation unit 102 only includes the second compensation module, then it can be removed. Figure 5 The first compensation module shown is removed.

[0103] Understandably, if the target pixel has two or more adjacent pixels to its left, a corresponding first compensation submodule can be added to the output of that pixel. The structure of the added first compensation submodule can be referenced. Figure 5 The structure of the first compensation submodule corresponding to the middle pixel An.

[0104] Accordingly, if the number of adjacent pixels to the right of the target pixel is two or more, a corresponding second compensation submodule can be added to the output of the corresponding pixel. The structure of the added second compensation submodule can be referred to Figure 5 The structure of the second compensation submodule corresponding to the middle pixel Cn.

[0105] Reference Figure 6 The present invention provides a schematic diagram of another infrared readout circuit in an embodiment of the present invention.

[0106] In this embodiment of the invention, the compensation unit 102 may further include: a first inverting module 601 coupled to the first compensation module, and / or a second inverting module 602 coupled to the second compensation module. Obviously, when the compensation unit 102 includes only the first compensation module, the compensation unit 102 may also include the first inverting module 601. When the compensation unit 102 includes only the second compensation module, the compensation unit 102 may also include the second inverting module 602.

[0107] In a specific implementation, the input terminal of the first inverting module 601 can be coupled to the output terminal of the first compensation module, and the output terminal of the first inverting module 601 is coupled to the input terminal of the integrating unit 103. The input terminal of the second inverting module 602 can be coupled to the output terminal of the second compensation module, and the output terminal of the second inverting module 602 is coupled to the input terminal of the integrating unit 103.

[0108] In this embodiment of the invention, the third compensation module may further include: a storage unit 603, a fourth resistor R4, and a third inverting module 604, wherein:

[0109] The storage unit 603 is used to store the first output signal of the previous row of pixels in the same column as the target pixel; and to output the first output signal when a control signal is received.

[0110] The fourth resistor R4 has its first end coupled to the output terminal of the storage unit 603 and its second end coupled to the input terminal of the third inverting module 604; the quotient of the resistance value of the third resistor R3 and the resistance value of the fourth resistor R4 is the third coefficient.

[0111] The third inverting module 604 has its output terminal coupled to the input terminal of the integrating unit 103.

[0112] In a specific implementation, the storage unit 603 may include: a first storage capacitor C1, a second storage capacitor C2, a first switching unit S1, a second switching unit S2, a third switching unit S3, and a fourth switching unit S4, wherein:

[0113] The first terminal of the first switching unit S1 can be coupled to the output terminal of the target pixel Bn, and the second terminal of the first switching unit S1 is coupled to the first terminal of the first storage capacitor C1.

[0114] The first end of the second switching unit S2 can be coupled to the output end of the target pixel Bn, and the second end of the second switching unit S2 is coupled to the first end of the second storage capacitor C2.

[0115] The first end of the third switching unit S3 is coupled to the second end of the first switching unit S1 and the first end of the first storage capacitor C1, and the second end of the third switching unit S3 is coupled to the input end of the third inverting module 603.

[0116] The first terminal of the fourth switching unit S4 is coupled to the second terminal of the second switch S2 and the first terminal of the second storage capacitor C2. The second terminal of the fourth switching unit S4 is coupled to the input terminal of the third inverting module 603.

[0117] The second terminal of the first storage capacitor C1 is coupled to the second terminal of the second storage capacitor C2.

[0118] By setting the fourth resistor R4, the first output signal IBn-1 is multiplied with the third coefficient.

[0119] In specific implementation, the first inverting module 601, the second inverting module 602, and the third inverting module 604 mentioned above can be made from existing electronic devices that can achieve the inverting function.

[0120] In some embodiments, refer to Figure 7 The present invention provides a schematic diagram of another infrared readout circuit in an embodiment of the present invention.

[0121] Figure 7 In this configuration, the first inverting module 601 may include a feedback resistor, an operational amplifier, and a resistor. The structures of the second inverting module 602 and the third inverting module 604 may be the same as those of the first inverting module.

[0122] Taking the first inverting module 601 as an example, in the first inverting module 601:

[0123] The first input terminal of the operational amplifier receives the first reference voltage VREFA, the second input terminal of the operational amplifier is coupled to the first terminal of the feedback resistor, and the output terminal of the operational amplifier is coupled to the first terminal of the resistor; the second input terminal of the operational amplifier is the input terminal of the first inverting module.

[0124] The second end of the resistor is coupled to the input of the integrator unit;

[0125] The feedback resistor is coupled between the second input terminal and the output terminal of the operational amplifier.

[0126] For the second inverting module 602, the first input terminal of the operational amplifier therein is input to the second reference voltage VREFB; for the third inverting module 604, the first input terminal of the operational amplifier therein is input to the third reference voltage VREFC.

[0127] The first coefficient can be adjusted by adjusting the first reference voltage VREFA. Correspondingly, the second coefficient can be adjusted by adjusting the second reference voltage VREFB. The third coefficient can be adjusted by adjusting the third reference voltage VREFC.

[0128] for Figure 6 and Figure 7 The infrared readout circuit shown outputs the following signal to the integration unit: α×IAn+IBn+β×ICn+γ×IBn-1, where γ is the third coefficient and IBn-1 is the output signal of pixel Bn-1.

[0129] For the first inverting module 601, the second inverting module 602, and the third inverting module 604, the feedback resistor and the resistance value of the resistor are equal, thereby realizing the inverting function.

[0130] In this embodiment of the invention, the integration unit 103 can be a common circuit or device capable of performing integration functions.

[0131] For example, such as Figure 6 As shown, a typical integration unit 103 may include: a switching unit S, a capacitor C, and a comparator A, wherein:

[0132] The first input terminal of comparator A is the input of the reference voltage, the second input terminal of comparator A is the input terminal of the integration unit, and the output terminal of comparator A is the output terminal of the integration unit.

[0133] The first terminal of the switching unit S is coupled to the second input terminal of the comparator A, and the second terminal of the switching unit S is coupled to the output terminal of the comparator A.

[0134] The first terminal of capacitor C is coupled to the second input terminal of comparator A, and the second terminal of capacitor C is coupled to the output terminal of comparator A.

[0135] The first input of comparator A can be a positive input, and the second input of comparator A can be a negative input.

[0136] In this embodiment of the invention, the compensation unit may also include only a storage unit and a fourth multiplication unit, wherein:

[0137] The storage unit is used to store the first output signal of the previous row of pixels in the same column as the target pixel; and to output the first output signal when a control signal is received.

[0138] The fourth multiplication unit has its input terminal coupled to the storage unit and its output terminal coupled to the input terminal of the integration unit. It is suitable for amplifying the third coefficient of the first output signal and outputting it.

[0139] In practical implementation, the specific structure of the storage unit can be referred to Figure 6 and Figure 7 The provided storage unit.

[0140] By multiplying the first output signal of the pixel in the row above the target pixel by the third coefficient, the resulting product is used as a compensation amount to compensate the output signal of the target pixel. This reduces the influence of the bias circuit self-effect and improves image quality.

[0141] Reference Figure 8 The present invention provides a schematic diagram of another infrared readout circuit in an embodiment of the present invention.

[0142] Figure 8In the compensation unit 102, there are a storage unit 801 and a fourth multiplication unit 802. The storage unit 801 can store the first output signal mentioned above, and the amplification factor of the fourth multiplication unit 802 is the third coefficient. When a control signal is received, the fourth multiplication unit 802 outputs the product of the third coefficient and the first output signal to compensate the output signal of the target pixel.

[0143] for Figure 8 The infrared readout circuit shown outputs the signal to the integration unit as: IBn + γ × IBn-1, where γ is the third coefficient and IBn-1 is the output signal of pixel Bn-1.

[0144] In the above embodiments of the present invention, the specific values ​​of the first coefficient, the second coefficient, and the third coefficient can all be preset. The first coefficient, the second coefficient, and the third coefficient can be empirical values ​​or obtained through certain experimental methods and calculations.

[0145] In some embodiments, the infrared detector can be operated as a baffle in the initial state, and powered on after the ambient temperature and substrate temperature have stabilized. The first coefficient, the second coefficient, and the third coefficient are all set to 0, that is, the compensation unit 102 can be regarded as not participating in the operation. The output signal is cyclically output, the bias voltage of the bias unit 101 is adjusted, and the initial state is corrected so that the output signal of each pixel in the pixel array is consistent.

[0146] The baffle operation is disabled, allowing the pixel array to receive radiation uniformly. The radiation intensity is adjusted at different times, and the output signals of the first / last column pixels and the first / last column blind pixels at each time are recorded. First and second coefficients are calculated from the data to ensure that the output signals of the first / last column blind pixels are consistent with those when the baffle operation is in place. The obtained first and second coefficients are saved. The first and second coefficients obtained in this way can effectively reduce the impact of inconsistent substrate temperature on the output signal.

[0147] After acquiring the first and second coefficients, the system can re-enter the initial state. A baffle operation is performed on the infrared detector, and power is applied after the ambient and substrate temperatures have stabilized. The first, second, and third coefficients are all set to 0, and the output signal is cycled. The bias voltage of the bias unit 101 is adjusted to correct the initial state so that the output signal of each pixel in the pixel array is consistent.

[0148] The baffle operation is cancelled, allowing the pixel array to receive radiation uniformly. The radiation intensity is adjusted at different times, and the output signal of each pixel and the tail-end blind pixel at each time is recorded. A third coefficient is calculated from the data to ensure that the output signal of the tail-end blind pixel is consistent with the output signal when the baffle operation is present. The obtained third coefficient is saved. The third coefficient obtained in the above manner can effectively reduce the impact of the bias self-heating effect on the output signal.

[0149] Ideally, the pixel substrate temperature is uniform, and radiation to a pixel will not cause changes in the temperature of the pixel's location or the surrounding substrate, thus preventing thermal interference to adjacent pixels. However, in practical applications, it is known that due to process fluctuations, the substrate temperature is difficult to maintain stability. Furthermore, poor heat transfer after a pixel is irradiated can cause localized substrate temperature changes, which further lead to deviations in the pixel's output signal. Therefore, the output signals of adjacent pixels can be used to compensate for the output signal of the target pixel, thereby reducing the impact of temperature fluctuations on the pixel's output signal.

[0150] For example, if pixel An receives a large amount of radiation, its output signal IAn will be large. Whether it is radiative heat dissipation or Joule heating due to its own current resistance (IR), it will cause the temperature of the surrounding substrate to increase, which will in turn cause a change in the output signal of pixel Bn. By transferring the first coefficient multiple component of IAn to pixel Bn, the output signal of pixel Bn is compensated, thereby achieving image correction.

[0151] In this embodiment of the invention, as described in the above embodiments, adjacent pixels can be adjacent pixels to the left of the target pixel, adjacent pixels to the right of the target pixel, or adjacent pixels to both the left and right of the target pixel. The number of adjacent pixels can be one, two, or more.

[0152] In practical implementation, the bias self-heating effect refers to the fact that the bias current generates some heat, causing changes in the pixel parameters. Furthermore, since the pixels in the pixel array are read out column by column, each column of pixels shares the same bias circuit. Therefore, in this embodiment of the invention, by subtracting the self-heating compensation component from the output signal of the currently read target pixel, the deviation in the output signal caused by the bias self-heating effect can be eliminated. The aforementioned self-heating compensation component is the product of the previous output signal of the target pixel and the third coefficient.

[0153] In this embodiment of the invention, if the image sensor's manufacturing process is ideal and the mismatch between the pixel array and the infrared readout circuit is small, the self-heating component of adjacent pixels can be approximated as the self-heating compensation component of the target pixel. The aforementioned self-heating component of adjacent pixels is the product of the output signal of the adjacent pixels and the third coefficient.

[0154] For example, replacing the product of the third coefficient and IAn with the product of the third coefficient and IBn-1 can compensate for the output signal of the target pixel, thereby compensating for the bias self-heating effect and reducing timing control and additional layout overhead.

[0155] In summary, by employing the infrared compensation circuit provided in this embodiment of the invention, and setting up a compensation unit, the output signal of the target pixel is compensated based on the output signals of adjacent pixels, and a compensation signal is output. The compensation unit integrates the compensation signal and outputs the integration result. Therefore, the influence of substrate temperature inconsistency, bias circuit self-heating effect, etc., on the output signal of the target pixel can be reduced, thus improving image quality.

[0156] The present invention also provides an infrared detector, including the infrared readout circuit provided in any of the above embodiments.

[0157] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An infrared readout circuit, characterized in that, include: The bias unit, compensation unit, and integration unit are as follows: The bias unit is adapted to provide the output signal of the pixel; The compensation unit is adapted to compensate the output signal of the target pixel based on the output signals of its neighboring pixels, and output a compensation signal; the neighboring pixels include at least one of the following: m pixels adjacent to the left of the target pixel; n pixels adjacent to the right of the target pixel; n and m are both positive integers; the compensation unit includes at least one of the following: a first compensation module and a second compensation module; the first compensation module is used to amplify the output signal of the m pixels adjacent to the left of the target pixel by a first coefficient; the second compensation module is used to amplify the output signal of the n pixels adjacent to the right of the target pixel by a second coefficient; The integrator unit is adapted to integrate the compensation signal and output the integration result.

2. The infrared readout circuit as described in claim 1, characterized in that, The first compensation module includes: m first multiplication units; wherein, the input terminal of the i-th first multiplication unit is coupled to the output terminal of the i-th pixel among the m adjacent pixels to the left of the target pixel, and its output terminal is coupled to the input terminal of the integration unit, and the amplification factor of the i-th first multiplication unit is the i-th first coefficient; i and n are both positive integers and 1≤i≤m.

3. The infrared readout circuit as described in claim 1, characterized in that, The second compensation module includes: n second multiplication units; wherein, the input terminal of the i-th second multiplication unit is coupled to the output terminal of the i-th pixel among the n adjacent pixels to the right of the target pixel, and its output terminal is coupled to the input terminal of the integration unit, and the amplification factor of the i-th second multiplication unit is the i-th second coefficient; i and n are both positive integers and 0≤i≤n.

4. The infrared readout circuit as described in claim 1, characterized in that, The compensation unit further includes: a third compensation module; the third compensation module includes: a third operational amplifier, a third feedback resistor, and a third resistor, wherein: The third operational amplifier has a reference voltage input at its first input terminal, a second input terminal coupled to the output terminal of the target pixel, and an output terminal coupled to the first terminal of the third resistor. The third feedback resistor is coupled between the second input terminal and the output terminal of the third operational amplifier; The second end of the third resistor is coupled to the input end of the integrator.

5. The infrared readout circuit as described in claim 4, characterized in that, The first compensation module includes: m first compensation sub-modules, wherein the i-th first compensation sub-module includes: a first operational amplifier, a first feedback resistor, and a first resistor, wherein: The first operational amplifier has a reference voltage input at its first input terminal, a second input terminal coupled to the output terminal of the i-th pixel among the n adjacent pixels to the left of the target pixel, and an output terminal coupled to the first terminal of the first resistor. The first feedback resistor is coupled between the second input terminal of the first operational amplifier and the output terminal of the first operational amplifier; The second end of the first resistor is coupled to the input terminal of the integrator unit; The first coefficient corresponding to the i-th first compensation submodule is the quotient of the resistance value of the third resistor and the resistance value of the first resistor of the i-th first compensation submodule.

6. The infrared readout circuit as described in claim 4 or 5, characterized in that, The second compensation module further includes: n second compensation sub-modules; the i-th second compensation sub-module includes: a second operational amplifier, a second feedback resistor, and a second resistor, wherein: The second operational amplifier has a reference voltage input at its first input terminal, its second input terminal coupled to the output terminal of the i-th pixel among the n adjacent pixels to the right of the target pixel, and its output terminal coupled to the first terminal of the second resistor. The second feedback resistor is coupled between the second input terminal and the output terminal of the second operational amplifier; The second resistor has its second end coupled to the input terminal of the integrator unit; The second coefficient corresponding to the i-th second compensation submodule is the quotient of the resistance value of the third resistor and the resistance value of the second resistor of the i-th second compensation submodule.

7. The infrared readout circuit as described in claim 6, characterized in that, The compensation unit further includes at least one of the following: a first inverting module and a second inverting module; wherein the first inverting module is coupled between the output terminal of the first compensation module and the input terminal of the integrator; and the second inverting module is coupled between the output terminal of the second compensation module and the input terminal of the integrator.

8. The infrared readout circuit as described in claim 7, characterized in that, The third compensation module also includes: A storage unit is configured to store the first output signal of the previous row of pixels in the same column as the target pixel; and to output the first output signal when a control signal is received. The fourth resistor has its first end coupled to the output terminal of the memory cell and its second end coupled to the input terminal of the third inverting module; the quotient of the resistance value of the third resistor and the resistance value of the fourth resistor is the third coefficient. The third inverting module has its output terminal coupled to the input terminal of the integrator unit.

9. The infrared readout circuit as described in claim 8, characterized in that, The storage unit includes: a first storage capacitor, a second storage capacitor, a first switching unit, a second switching unit, a third switching unit, and a fourth switching unit, wherein: The first switching unit has a first end coupled to the output end of the target pixel and a second end coupled to the first end of the first storage capacitor. The second switching unit has a first end coupled to the output end of the target pixel and a second end coupled to the first end of the second storage capacitor. The third switching unit has a first end coupled to the second end of the first switching unit, and its second end coupled to the first end of the fourth resistor. The first end of the fourth switching unit is coupled to the second end of the second switching unit, and the second end of the fourth resistor is coupled to the first end of the fourth resistor.

10. The infrared readout circuit as described in claim 1, characterized in that, The compensation unit includes: a storage unit and a fourth multiplication unit, wherein: The storage unit is used to store the first output signal of the previous row of pixels in the same column as the target pixel; and to output the first output signal when a control signal is received. The fourth multiplication unit has its input terminal coupled to the storage unit and its output terminal coupled to the input terminal of the integration unit, and is adapted to amplify the first output signal by a third coefficient and output it.

11. An infrared detector, characterized in that, Includes the infrared readout circuit as described in any one of claims 1 to 10.

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