An FPGA netlist-level hardware Trojan detection method based on a large language model

Abstract

The application discloses a FPGA netlist level hardware Trojan detection method based on a large language model, relates to the technical field of integrated circuit security and hardware Trojan detection, and comprises the following steps: constructing an original FPGA netlist into a text attribute graph containing text attributes, generating a path text sequence through bidirectional random walk, and constructing a corpus to pre-train a large language model; subsequently, a local neighborhood is demarcated with each node as the center and a path text set is generated, a pre-training model is used to extract a semantic vector representation, and a node level training sample set is further constructed; on the basis, a classifier and CB-Focal Loss are combined for supervised fine-tuning to obtain a final model; in the reasoning stage, a to-be-detected node is represented, constructed and discriminated to realize node level hardware Trojan detection. The application can simultaneously retain circuit topology and semantic information, realize node level hardware Trojan positioning, improve detection precision and generalization ability, and improve the degree of automation.

Description

Technical Field

[0001] This invention relates to the fields of integrated circuit security and hardware Trojan detection technology, and in particular to an FPGA netlist-level hardware Trojan detection method based on a large language model. Background Technology

[0002] With the widespread application of FPGAs in security-critical fields such as communications and aerospace, hardware trojans (HT) have become a significant threat to chip supply chain security. Hardware trojans are typically hidden in the original circuit with extremely small area and power consumption. They can be triggered under specific conditions, causing information leakage or functional failure, and are difficult to detect by traditional verification methods.

[0003] Traditional detection methods and their shortcomings: (1) Functional testing: It relies on high coverage test vectors, which are difficult to exhaustively test in large designs, and the conditions for triggering Trojans are often overlooked.

[0004] (2) Formal verification: The state space grows exponentially with the size of the circuit and cannot be extended to a million-gate FPGA netlist.

[0005] (3) Reverse engineering and side-channel analysis: requires expensive equipment and expert experience, is sensitive to environmental noise, and has poor repeatability.

[0006] In recent years, researchers have attempted to introduce deep learning into netlist Trojan detection, resulting in two main technical approaches: (1) Graph structure modeling: The netlist is converted into a graph, and the node representation is learned end-to-end using a graph neural network (GNN). This type of method can capture topological information, but ignores the rich gate-level semantic attributes inside the nodes and is difficult to generalize to unknown Trojan types.

[0007] (2) Text sequence modeling: The netlist nodes and their connections are linearized into text, and then traditional NLP models (TextCNN, LSTM, etc.) are used for binary classification. Although textualization preserves some semantics, it severs the circuit topology, resulting in a large loss of structural information.

[0008] Large Language Models (LLMs) have demonstrated powerful cross-domain semantic understanding capabilities. However, two major challenges remain in hardware netlist scenarios: (1) Graph-text mapping is missing: Existing methods lack a mechanism to completely convert graph structure information into natural language sequences, and cannot simultaneously preserve topological and attribute semantics.

[0009] (2) Task adaptation gap: There is no publicly available work that connects pre-trained LLM with node-level Trojan detection task system, and there is a lack of a pre-training-fine-tuning framework from "general circuit understanding" to "precise Trojan location".

[0010] In summary, existing technologies still cannot simultaneously meet the four major requirements of "high detection accuracy, strong generalization ability, node-level localization, large-scale scalability and automated implementation", and there is an urgent need for a new detection method that can unify structural modeling and semantic understanding. Summary of the Invention

[0011] The technical problem to be solved by this invention is to address the shortcomings of existing technologies, specifically by providing an FPGA netlist-level hardware Trojan detection method based on a large language model, as detailed below: 1) In a first aspect, the present invention provides a method for detecting hardware Trojans at the FPGA netlist level based on a large language model, the specific technical solution of which is as follows: Based on the original FPGA netlist, a text attribute graph is constructed. The text attribute graph includes at least two logic unit nodes, at least one directed edge for signal connection relationship, and textual attributes corresponding to each logic unit node. Based on the text attribute graph, starting from any logical unit node, a node sequence corresponding to each starting point is obtained through bidirectional random walk. Then, according to the arrangement order of the logical unit nodes in the node sequence, the textual attributes corresponding to the logical unit nodes are concatenated to form the text path corresponding to each starting point. After merging and deduplicating all text paths, a corpus file is generated. Based on the corpus file, a pre-trained large language model is obtained to obtain a target large language model. In the text attribute graph, any number of logical unit nodes are selected as target nodes. Combined with a preset hop count threshold, sampling operations are performed along the forward and backward directions with each target node as the center and the preset hop count threshold as the constraint condition. The target text path corresponding to each target node is recorded, and all target text paths are merged to generate a path text set. The target large language model is used to analyze and process each target text path in the path text set to obtain the semantic vector matrix corresponding to each target node. The semantic vector matrix is ​​then processed by a classifier, and the target large language model is supervised and fine-tuned in conjunction with a loss function to obtain the final model. For any node to be detected in any FPGA netlist, construct the corresponding target path text set, and input it into the final model for judgment to obtain the label and probability value of whether the node contains a Trojan.

[0012] The beneficial effects of the FPGA netlist-level hardware Trojan detection method based on a large language model provided by this invention are as follows: By abstracting the FPGA netlist into a unified text attribute graph and using bidirectional random walks to generate natural language paths, the large language model can simultaneously capture the circuit's topology and semantic attributes during the pre-training stage, thus overcoming the information gap bottleneck of traditional graph neural networks or pure text modeling. Subsequently, a node-centric local sampling and semantic vector aggregation mechanism achieves high-precision localization of node-level Trojans, significantly reducing false negatives and false positives. Class-balanced Focal Loss fine-tuning further alleviates the class imbalance problem caused by scarce Trojan nodes, improving the model's discrimination ability on complex boundaries. The entire framework is decoupled from specific large language models, possessing strong generalization capabilities and rapid transfer characteristics across processes and design scales. It can be deployed directly on new netlists with zero or a small number of samples, significantly reducing reliance on expert experience and manual annotation costs, improving automation, and supporting online detection of large-scale FPGA designs.

[0013] Based on the above solution, the present invention can be further improved as follows.

[0014] Furthermore, the process of constructing the text attribute graph is as follows: The original FPGA netlist is parsed line by line to identify lookup tables, inverters, multiplexers, flip-flops, carry units, and buffer logic units. A logic unit node is generated for each logic unit, and the logic unit node is associated with textual attributes. Based on the input and output signals corresponding to each logic unit node, a mapping index table between logic unit nodes is constructed. For each logical unit node, perform reverse matching on the input signal to determine the source node corresponding to each logical unit node, and based on the source node, determine the directed edges of the signal connection relationship; Virtual nodes and relay nodes are defined, and a text attribute graph is constructed based on logical unit nodes, textual attributes, mapping index table, directed edges of signal connection relationships, virtual nodes, and relay nodes.

[0015] The beneficial effects of the above-mentioned further solutions are as follows: By directly extracting key units such as LUT, INV, MUX, FDCE, FDRE, FDPE, CARRY4, BUFG, IBUF, and OBUF from the netlist line by line and generating textual attributes in real time, nodes carry complete logical unit-level semantics from the beginning of creation, thereby reducing redundancy and deviation in the subsequent feature transformation process. The mapping index table established with the output signal as the key and the reverse matching mechanism with the input signal can complete the batch construction of directed edges in one scan, significantly reducing the graph construction time. Virtual nodes process constant signals to ensure the integrity of the graph structure and the absence of broken edges. The automatic merging of relay nodes eliminates non-logical functional units such as assign, BUFG, IBUF, and OBUF, reducing the number of redundant nodes and path length, thereby reducing the computational load of subsequent random walks and language model inference. The above design makes the text attribute graph more compact and efficient while maintaining complete structure and semantics, directly improving the path sampling quality, pre-training convergence speed, and the accuracy and generalization ability of node-level Trojan detection.

[0016] Furthermore, the process of obtaining the node sequence corresponding to each starting point through bidirectional random walks is as follows: According to the uniform distribution sampling method, multiple logical unit nodes are determined, and each logical unit node is used as the starting point for sampling in turn. Path acquisition is performed using a bidirectional random walk method, which includes forward walk and backward walk; Using adjacency constraints, repetition constraints, and length constraints as combined constraints, the node sequence corresponding to each starting point is determined. The adjacency constraint is as follows: when collecting paths through bidirectional random walks, the adjacent logical unit nodes of the current logical unit node are taken as the next path collection node. The repetition constraint is as follows: set a maximum number of accesses for each logical unit node, and prohibit access when the number of accesses for any logical unit node reaches the maximum number of accesses; The length constraint is as follows: set the maximum path length for path acquisition, and when the path length corresponding to the node sequence of any starting point reaches the maximum path length, directly output the node sequence.

[0017] The beneficial effects of the above-mentioned further solutions are as follows: Uniform sampling ensures that nodes in different regions have the opportunity to become starting points, enhancing corpus diversity. Forward and backward bidirectional traversal simultaneously captures signal-driven and dependency relationships, ensuring the path includes upstream and downstream structural information. Adjacency constraints guarantee that sampling always follows actual circuit connections, avoiding invalid jumps. Repetition constraints prevent repeated loop traversal, reducing redundant computation and preventing the model from overfitting local patterns. Length constraints strike a balance between structural coverage and semantic integrity, preventing excessively long paths from diluting key features. These combined constraints result in a node sequence that is topologically representative, semantically coherent, and computationally efficient, significantly enhancing the large language model's understanding of local circuit behavior and improving the generalization performance and localization accuracy of subsequent Trojan detection.

[0018] Furthermore, the process of obtaining the semantic vector matrix corresponding to each target node is as follows: Extract the embedding representation of each token from the last hidden layer of the target large language model; Using the same target text path as a unit, the embedded representations of all tokens are aggregated through average pooling; Aggregate the embedded representations of all target text paths to generate a semantic vector matrix corresponding to any target node.

[0019] The beneficial effects of the above-mentioned further solutions are as follows: By directly extracting the last hidden state of the large language model as a token-level embedding, the richest contextual semantics are preserved while avoiding extra parameters. Average pooling is performed on the same path as a unit, which compresses the sequence length while balancing and integrating node type, connection order and key attributes to form a path-level representation with high signal-to-noise ratio. Then, the average of all path representations is taken to steadily aggregate the multi-view local structural information into a node-level semantic vector matrix, so that the vector of each target node has topological integrity, semantic consistency and dimensional uniformity, which significantly improves the accuracy and robustness of the subsequent classifier in identifying Trojan nodes.

[0020] 2) Secondly, the present invention also provides an FPGA netlist-level hardware Trojan detection system based on a large language model, the specific technical solution of which is as follows: The building module is used to: construct a text attribute graph based on the original FPGA netlist. The text attribute graph includes at least two logic unit nodes, at least one directed edge for signal connection, and textual attributes corresponding to each logic unit node. The generation module is used to: based on the text attribute graph, take any logical unit node as the starting point, obtain the node sequence corresponding to each starting point through bidirectional random walk, and concatenate the textual attributes corresponding to the logical unit nodes according to the arrangement order of the logical unit nodes in the node sequence to form the text path corresponding to each starting point, and generate a corpus file after merging and deduplicating all text paths. The training module is used to: pre-train a large language model based on the corpus file to obtain a target large language model; select any number of logical unit nodes as target nodes in the text attribute graph; combine a preset hop count threshold; take each target node as the center and the preset hop count threshold as the constraint; perform sampling operations along the forward and backward directions respectively; record the target text path corresponding to each target node; and merge all target text paths to generate a path text set. The optimization module is used to: analyze and process each target text path in the path text set through the target large language model to obtain the semantic vector matrix corresponding to each target node; process the semantic vector matrix through a classifier; and perform supervised fine-tuning of the target large language model in combination with a loss function to obtain the final model. The detection module is used to: construct a corresponding target path text set for any node to be detected in any FPGA netlist, and input it into the final model for judgment to obtain the label and probability value of whether the node contains a Trojan.

[0021] Based on the above solution, the present invention can be further improved as follows.

[0022] Furthermore, the process of constructing the text attribute graph is as follows: The original FPGA netlist is parsed line by line to identify lookup tables, inverters, multiplexers, flip-flops, carry units, and buffer logic units. A logic unit node is generated for each logic unit, and the logic unit node is associated with textual attributes. Based on the input and output signals corresponding to each logic unit node, a mapping index table between logic unit nodes is constructed. For each logical unit node, perform reverse matching on the input signal to determine the source node corresponding to each logical unit node, and based on the source node, determine the directed edges of the signal connection relationship; Virtual nodes and relay nodes are defined, and a text attribute graph is constructed based on logical unit nodes, textual attributes, mapping index table, directed edges of signal connection relationships, virtual nodes, and relay nodes.

[0023] Furthermore, the process of obtaining the node sequence corresponding to each starting point through bidirectional random walks is as follows: According to the uniform distribution sampling method, multiple logical unit nodes are determined, and each logical unit node is used as the starting point for sampling in turn. Path acquisition is performed using a bidirectional random walk method, which includes forward walk and backward walk; Using adjacency constraints, repetition constraints, and length constraints as combined constraints, the node sequence corresponding to each starting point is determined. The adjacency constraint is as follows: when collecting paths through bidirectional random walks, the adjacent logical unit nodes of the current logical unit node are taken as the next path collection node. The repetition constraint is as follows: set a maximum number of accesses for each logical unit node, and prohibit access when the number of accesses for any logical unit node reaches the maximum number of accesses; The length constraint is as follows: set the maximum path length for path acquisition, and when the path length corresponding to the node sequence of any starting point reaches the maximum path length, directly output the node sequence.

[0024] Furthermore, the process of obtaining the semantic vector matrix corresponding to each target node is as follows: Extract the embedding representation of each token from the last hidden layer of the target large language model; Using the same target text path as a unit, the embedded representations of all tokens are aggregated through average pooling; Aggregate the embedded representations of all target text paths to generate a semantic vector matrix corresponding to any target node.

[0025] 3) In a third aspect, the present invention also provides an electronic device, the electronic device including a processor coupled to a memory, the memory storing at least one computer program, the at least one computer program being loaded and executed by the processor to enable the electronic device to perform any of the above methods.

[0026] 4) In a fourth aspect, the present invention also provides a computer-readable storage medium storing at least one computer program, which is loaded and executed by a processor to enable a computer to implement any of the above methods.

[0027] It should be noted that the beneficial effects of the technical solutions of the second to fourth aspects of the present invention and their corresponding possible implementations can be found in the above description of the technical effects of the first aspect and its corresponding possible implementations, and will not be repeated here. Attached Figure Description

[0028] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a flowchart illustrating an FPGA netlist-level hardware Trojan detection method based on a large language model, according to an embodiment of the present invention. Figure 2 This is a schematic diagram of the model architecture of an FPGA netlist-level hardware Trojan detection method based on a large language model according to an embodiment of the present invention. Figure 3This is a schematic diagram illustrating the text attribute graph construction process of an FPGA netlist-level hardware Trojan detection method based on a large language model, according to an embodiment of the present invention. Figure 4 This is a schematic diagram of path sampling and text generation for an FPGA netlist-level hardware Trojan detection method based on a large language model, according to an embodiment of the present invention. Figure 5 This is a structural framework diagram of an electronic device according to the present invention. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0030] like Figure 1 As shown in the figure, an FPGA netlist-level hardware Trojan detection method based on a large language model according to an embodiment of the present invention includes the following steps: S1. Based on the original FPGA netlist, construct a text attribute graph. The text attribute graph includes at least two logic unit nodes, at least one directed edge for signal connection relationship, and textual attributes corresponding to each logic unit node. S2, based on the text attribute graph, uniformly sample multiple logical unit nodes, and sequentially obtain the node sequence corresponding to each starting point through a bidirectional random walk, taking each node as the starting point. Then, according to the arrangement order of the logical unit nodes in the node sequence, concatenate the textual attributes corresponding to the logical unit nodes to form the text path corresponding to each starting point. After merging and deduplicating all text paths, generate a corpus file. S3. Based on the corpus file, pre-train a large language model to obtain a target large language model. Select any number of logical unit nodes as target nodes in the text attribute graph. Combined with a preset hop count threshold, take each target node as the center and the preset hop count threshold as the constraint condition, perform sampling operations along the forward and backward directions respectively, record the target text path corresponding to each target node, and merge all target text paths to generate a path text set. S4, each target text path in the path text set is analyzed and processed by the target large language model to obtain the semantic vector matrix corresponding to each target node. The semantic vector matrix is ​​processed by a classifier and combined with a loss function to supervise and fine-tune the target large language model to obtain the final model. S5: For any node to be detected in any FPGA netlist, construct the corresponding target path text set and input it into the final model for judgment to obtain the label and probability value of whether the node contains a Trojan.

[0031] The beneficial effects of the FPGA netlist-level hardware Trojan detection method based on a large language model provided by this invention are as follows: By abstracting the FPGA netlist into a unified text attribute graph and using bidirectional random walks to generate natural language paths, the large language model can simultaneously capture the circuit's topology and semantic attributes during the pre-training stage, thus overcoming the information gap bottleneck of traditional graph neural networks or pure text modeling. Subsequently, a node-centric local sampling and semantic vector aggregation mechanism achieves high-precision localization of node-level Trojans, significantly reducing false negatives and false positives. Class-balanced Focal Loss fine-tuning further alleviates the class imbalance problem caused by scarce Trojan nodes, improving the model's discrimination ability on complex boundaries. The entire framework is decoupled from specific large language models, possessing strong generalization capabilities and rapid transfer characteristics across processes and design scales. It can be deployed directly on new netlists with zero or a small number of samples, significantly reducing reliance on expert experience and manual annotation costs, improving automation, and supporting online detection of large-scale FPGA designs.

[0032] It should be noted that the original FPGA netlist refers to the gate-level netlist file generated during the FPGA design flow after the RTL description (Verilog / VHDL) is synthesized by synthesis tools (such as Vivado, Quartus, Yosys, etc.). It is typically saved in text format (.v, .edif, .vqm, etc.) and includes the following content: Instantiation of all basic logic units (LUT, FF, MUX, CARRY, BRAM, DSP, etc.); The type, parameters (such as the INIT value of the LUT, the initial state of the FF), and input / output port connections of each instance; Connection information between all signal lines (net) and ports; It does not include physical coordinates, timing constraints, or bitstream information after placement and routing; it only describes the logical-level "cell-port-connection" topology.

[0033] In another embodiment of this solution, the original FPGA netlist file is used as the sole input source. The system scans line by line, character by character, using regular expressions or a lexical analyzer to identify instance declaration lines beginning with keywords such as LUT, INV, MUX, FDCE, FDRE, FDPE, CARRY4, BUFG, IBUF, and OBUF. The instance name is extracted as the node identifier. Simultaneously, the parameter list within parentheses is parsed to obtain key attributes such as INIT, which are immediately converted into key-value pairs. Then, within the same line, port declarations such as .I(), .O(), .CLK(), .D(), and .S() are matched, and port names and connection names are collected and temporarily stored as a dictionary structure. After all instances are parsed, a signal-node index table is built, with the signal name as the primary key and the value being the node identifier driving the signal. Then, each instance is scanned in reverse order. For example, the input port list is used to locate the source node by looking up a table, thereby generating a directed edge from the source node to the current node. If a constant signal 1'h0 or 1'h1 is encountered, a uniquely numbered virtual node is immediately inserted into the graph, with its textual attribute set to "Node_virtual_0" or "Node_virtual_1", and this virtual node is connected as the driving source. Then, all nodes are traversed. If a node is of type assign, IBUF, OBUF, or BUFG and only a single-point pass-through is performed, the node is deleted, and its incoming edge is directly pointed to the outgoing edge target node, thus merging relay nodes. Finally, the instance name, type string, INIT parameter strings of each node, as well as the input port list and output port list, are concatenated into a natural language description according to a fixed template, such as "name=Node_100". TYPE=LUT6 INIT=64'h0123456789ABCDEF inputs=[a,b,c,d,e,f] outputs=[o]”, which serves as the textual attribute of this node, and is output together with the node set and the directed edge set as a text attribute graph structure.

[0034] In another embodiment of this solution, the specific implementation process of S2 includes: Initialize a global empty corpus file. Using a uniform random strategy, cyclically extract starting nodes from the node set until a preset number of starting nodes is reached or the entire graph is covered. For each starting node, perform a random walk to generate a path. Each walk randomly selects a forward or backward node from the current node. If the node's visit count has reached a preset limit or there are no valid successor nodes, the walk terminates. The walk length is randomly generated within a preset minimum and maximum range to control the path length. After obtaining each node sequence, extract the textual attribute strings corresponding to each node in sequence, concatenate them sequentially separated by spaces, and insert direction markers "from" or "to" between adjacent node attributes to preserve the propagation direction semantics, forming a complete natural language text path. Write this text path into the corpus file. After all forward and backward walks of all starting nodes are completed, deduplication is performed to obtain a large-scale unlabeled corpus file containing all bidirectional text paths for subsequent language model pre-training.

[0035] In another embodiment of this solution, the specific implementation process of S3 includes: Using a corpus file as the data source, the original word segmenter is first dynamically expanded according to the standard autoregressive language model process: hardware unit types, parameter keywords, and direction markers appearing in all text paths are scanned and added to the vocabulary. Then, the corpus file is split into training and validation sets at an 8:2 ratio. The AdamW optimizer is used with an initial learning rate of 1e-4 and a cosine decay learning rate scheduling strategy to dynamically adjust the learning rate. The batch size is 16, and training is performed for 3 epochs. At each step, the next token is predicted given a prefix token sequence, minimizing the cross-entropy loss. After training, the model weights are saved to obtain the target large language model. Subsequently, preparations are made for node-level detection on the text attribute graph: First, a global data structure is initialized for each circuit diagram to be processed, and all logical unit nodes are traversed, skipping virtual nodes of type '1'h0' or '1'h1'. For each valid node, as the target node, a restricted depth-first search (DFS) is performed from it along the forward and reverse adjacency lists of the graph to generate all possible paths, with the path length not exceeding the preset maximum number of hops. During the Depth-First Search (DFS) traversal, a backtracking strategy is employed to prevent duplicate node visits. When generating each path, the textual attributes of the node are extracted on the fly, including its type and initialization value (the initial value information is retained for LUT nodes). Direction markers "to" or "from" are inserted between adjacent nodes to form a complete text path. All generated paths are summarized into a list of the target node. This process is repeated until all target nodes are covered. Finally, the generated set of text paths is saved as a JSON file for subsequent semantic vector extraction and classification fine-tuning training.

[0036] In another embodiment of this solution, S4 is specifically implemented as follows: For the pre-trained target large language model, a learnable multilayer perceptron classifier is inserted at its end. The structure is as follows: Linear(d→512)→LayerNorm→GELU→Dropout(0.5)→Linear(512→256)→LayerNorm→GELU→Dropout(0.5)→Linear(256→2), where d is the dimension of the hidden layer of the language model. Then, the target text path is read one by one as the input stream, first converted into a token sequence by a token segmenter and then fed into the language model to obtain the last hidden state matrix. K is the number of paths, L is the number of tokens along that path, and the path-level vector is obtained by average pooling H along the token dimension. Then, average pooling is performed along the path number K dimension to obtain the node-level vector. The vector and the corresponding node label (0 / 1) are fed into the classifier to obtain logits, and then softmax is used to obtain the Trojan probability. During the training phase, CB-Focal Loss with class balance factor α_t and Focal modulation factor γ=2 is used. After calculating the batch loss, backpropagation is performed and the classifier weights are updated with a learning rate of 1e-5. The language model parameters are fine-tuned with a learning rate of 1e-6. The AdamW optimizer, batch_size=4, gradient clipping norm 1.0 are used. The training is performed for 30 epochs and early stopping on the validation set with patience=5. After fine-tuning, the language model and classifier weights are frozen and the overall checkpoint is saved, which is the complete model that can be directly used for Trojan detection of new nodes.

[0037] Furthermore, the process of constructing the text attribute graph is as follows: The original FPGA netlist is parsed line by line to identify LUT, INV, MUX, FDCE, FDRE, FDPE, CARRY4, BUFG, IBUF, and OBUF logic units, and a logic unit node is generated for each logic unit. At the same time, the logic unit node is associated with textual attributes. Based on the output signal corresponding to each logical unit node, a mapping index table between logical unit nodes is constructed. For each logical unit node, perform reverse matching on the input signal to determine the source node corresponding to each logical unit node, and based on the source node, determine the directed edges of the signal connection relationship; Virtual nodes and relay nodes are defined, and a text attribute graph is constructed based on logical unit nodes, textual attributes, mapping index table, directed edges of signal connection relationships, virtual nodes, and relay nodes.

[0038] It should be noted that a logic unit refers to the smallest functional entity in the programmable logic array inside an FPGA chip, including LUTs, MUXs, FDREs, CARRY4s, etc., which can characterize the specific logic function and resource usage of a circuit at the gate level.

[0039] Textual attributes refer to readable strings that are constructed by concatenating the instance name, type, INIT parameters, and input / output port list of a logical unit according to a natural language template. These strings can represent all the static semantic information of the unit and can be directly understood by the language model.

[0040] A directed edge is a unidirectional connection from the output port of a source logic unit to the input port of a target logic unit. It corresponds to the signal connection relationship in the netlist and can characterize the actual propagation direction and data dependency of the signal in the circuit.

[0041] Furthermore, the process of obtaining the node sequence corresponding to each starting point through bidirectional random walks is as follows: According to the uniform distribution sampling method, multiple logical unit nodes are determined, and each logical unit node is used as the starting point for sampling in turn. Path acquisition is performed using a bidirectional random walk method, which includes forward walk and backward walk; Using adjacency constraints, repetition constraints, and length constraints as combined constraints, the node sequence corresponding to each starting point is determined. The adjacency constraint is as follows: when collecting paths through bidirectional random walks, the adjacent logical unit nodes of the current logical unit node are taken as the next path collection node. The repetition constraint is as follows: set a maximum number of accesses for each logical unit node, and prohibit access when the number of accesses for any logical unit node reaches the maximum number of accesses; The length constraint is as follows: set the maximum path length for path acquisition, and when the path length corresponding to the node sequence of any starting point reaches the maximum path length, directly output the node sequence.

[0042] Furthermore, the process of obtaining the semantic vector matrix corresponding to each target node is as follows: Extract the embedding representation of each token from the last hidden layer of the target large language model; Using the same target text path as a unit, the embedded representations of all tokens are aggregated through average pooling; Aggregate the embedded representations of all target text paths to generate a semantic vector matrix corresponding to any target node.

[0043] Example 1, such as Figures 2 to 4As shown, 1. To achieve unified modeling of the structural and semantic information in the FPGA circuit netlist, it is first formally abstracted into a text attribute graph. This structure is used to capture the connection relationships between various logic elements in the circuit, while retaining the multi-dimensional attribute information of the nodes themselves, thus laying the foundation for subsequent path modeling and semantic learning. The text attribute graph is defined as a triple: ,in: : A set of nodes, each node in the graph This represents a logical unit in the netlist, such as LUT, MUX, FDRE, CARRY4, etc. : Used to describe the attribute information attached to each node. For each node Extract the following five key attributes: in, This serves as a unique identifier for the logical unit. Indicates the logical function type (such as LUT6, FDRE, etc.); Key parameters representing elements, such as the INIT value of a LUT, are used. It should be noted that during netlist generation, some elements are assigned the INIT value of 1'hx, indicating an unknown initial state. To avoid semantic ambiguity, these indeterminate INIT parameters are filtered during the path generation phase. and The input and output signals of the node are described separately, and all these attributes are mapped to... ; A set of directed edges, representing the signal connection relationships between logic elements, based on attribute information. The input and output signals in the middle construct directed edges, that is, when The output signal and When matching the input signal, a directed edge is established. .

[0044] Figure 3 The process of constructing a text property graph is shown, including the following key operations: (1) Logic unit parsing and node construction: The FPGA netlist is parsed line by line to identify various logic units (such as LUT, MUX, FDRE, etc.), extract their node attributes, and add them as nodes in the graph structure.

[0045] (2) Signal mapping and edge establishment: A mapping index table from the output signal of the node is established. Then, all input signals are matched in reverse to determine their source nodes, thereby establishing a complete set of directed edges that reflect the signal propagation path.

[0046] (3) Virtual node mechanism: In order to ensure the integrity of the graph structure, a virtual node mechanism is introduced to handle the situation where there are undefined signals or special signals (such as 1'h0, 1'h1, etc.). By creating a uniquely numbered virtual node, a special node is simulated and connected to the graph to ensure the integrity of the graph structure.

[0047] (4) Relay Node Merging: To improve the quality of graph construction and the simplicity of the graph structure, some relay-type non-functional nodes (such as "assign", "BUFG", "IBUF", "OBUF", etc.) were merged. These nodes usually do not have actual logical functions and only serve as signal relays. By analyzing their input and output signals, they are removed from the graph, and the source node of their input signal is directly connected to the target node of their output signal, thereby bypassing the relay nodes to establish a simpler connection. For example, if the following connection exists: Then, after merging, construct directly: This approach effectively avoids interference from invalid paths, reduces redundant structures, and also helps improve the extraction of important information for subsequent path semantic modeling.

[0048] The text attribute graph constructed in this way not only preserves the circuit's topology but also fully expresses the semantic information of the logic units, providing a unified structural and attribute modeling foundation for subsequent path generation and semantic modeling.

[0049] 2. Path Sampling and Text Generation Traditionally, language models typically use natural language text sequences as input, and cannot directly process graph-structured data. To address the mapping problem from graph structure to language sequence, a path-level textual modeling framework that integrates graph structure and textual semantic representation is proposed, such as... Figure 4 As shown, this method maps structural paths in the FPGA circuit netlist into a structured path text sequence with natural language syntax. This process preserves the original topology and key semantic information while transforming circuit information into a language sequence that can be efficiently processed by a large language model, providing the model with suitable pre-training data and thus enabling the model to capture local semantic patterns in the circuit.

[0050] 2.1 Path Sampling To obtain high-quality path corpus during the pre-training phase, a bidirectional covering random walk strategy based on the constructed text attribute graph is designed to systematically extract local structural paths representing signal propagation behavior in circuits. This strategy maintains semantic context integrity while covering potential topological variations in the graph as much as possible, effectively improving the diversity and generalization ability of the corpus. Specifically, the sampling process is performed on the pre-constructed text attribute graph... Execute on, where the node set Represents logical units, edge sets Indicates the signal connection relationship. Include The node attributes.

[0051] For each valid node Execute the following path generation process: Random starting point selection: Sample nodes from the entire graph using a uniform distribution as the starting point. ; Direction setting: Perform forward walk and backward walk separately to capture signal-driven and dependent paths; Adjacency constraint: Each traversal selects the neighboring nodes of the current node, and the direction depends on... or ; Duplicate limit: Set a maximum number of visits for each node within each path. To prevent getting stuck in a local loop; Length limit: The maximum path length is limited to [value missing]. The number of hops is usually set between 3 and 10 to balance structural coverage and semantic integrity. Termination condition: The current path sampling terminates if the path reaches the specified length or if there are no feasible neighbors to extend it.

[0052] Each sampling path is ultimately represented as a sequence of nodes. All paths will be further fed into the path text function. (See Section 2.2 for details) It is transformed into a structured language sequence and used to build a large-scale pre-trained corpus.

[0053] 2.2 Text Generation To achieve the conversion from graph structures to natural language sequences, this paper defines a path text function. This function will assign any directed path in the graph to the graph. Mapped to natural language sequences that a language model can process: in: Represents a node The type attributes (such as LUT6, FDRE, etc.) are concatenated after the type to form a node description fragment if there are key parameters (such as the INIT value of LUT). The `connector` directive indicates the path direction between adjacent nodes, representing forward or backward propagation of the signal. The function's final output is an unambiguous textual representation of the path described in natural language. This text sequence fully conforms to natural language syntax, transforming the logical relationships between nodes into the contextual information of the text. This allows for semantic modeling of the text using language models, similar to processing general language text. For example, the forward propagation path could be "FDCE from LUT2 4'h4 from LUT664'h80000000000000000", and the backward path could be "FDCE to FDCE". This function bridges the gap between graph structures and natural language.

[0054] 3. Large Language Model Pre-training To integrate graph structure information with the deep semantic modeling capabilities of large language models, an unsupervised pre-training task is constructed based on the path text sequence established in Section 2, so as to achieve the learning of graph structure in the form of text sequence.

[0055] According to the path text function in Section 2.2 All paths Mapped to an ordered sequence of text Each token Representing graph node attributes or connection semantics (e.g., "FDRE toLUT6") naturally carries structural order and semantic information; that is, the order of nodes in the graph naturally corresponds to the order of text tokens. To address the sparsity of hardware domain terminology in large models, dynamic vocabulary expansion was performed, extracting specific hardware unit types and expanding the segmenter vocabulary to improve the model's ability to model circuit semantics. Then, training was conducted with a standard autoregressive language modeling objective: given a prefix at each step... Predict the next token The probability of occurrence. The training process can be formally represented as minimizing the following loss function: in Represents a sequence Length, Is a given prefix Predict the next token The probability of occurrence.

[0056] In this way, while learning the token order, LLM also implicitly learns the topological order and semantic dependencies of path nodes in the graph, thereby gaining an understanding of the local circuit structure. Through this process, the graph structure information between nodes is combined with the deep semantic features of LLM to generate a more expressive semantic representation of the graph structure.

[0057] 4. Node Neighborhood Partitioning and Path Sampling To further support node-level hardware Trojan identification tasks, a node-centric local structure modeling method was designed based on the constructed text attribute graph. By extracting its forward and backward paths, multiple semantically rich structured path texts are generated as input representations for subsequent classification models.

[0058] For each node to be detected in the graph Set a hop count threshold centered on it. The number of jumps performed along the forward and backward directions in the TAG graph shall not exceed [a certain number]. This involves a path sampling operation. During the sampling process, all paths originating from that node are acquired and recorded to ensure comprehensive information coverage and semantic coherence.

[0059] Each path in the sampling results This is further transformed into structured text in natural language form. This is done using the pathtext function. Structured encoding is performed, preserving the type, initialization parameters, and connection order of each node in the path. Each node is ultimately represented as a corpus of path sets consisting of several structured path texts. It covers its upstream and downstream connection information and local topology.

[0060] 5. Semantic Embedding Generation and Node Representation The path set corpus of each node is input into a pre-trained language model to generate semantic embeddings and aggregate them into node representations to support subsequent detection tasks.

[0061] For each target node, its neighborhood paths have been transformed into several structured natural language text sequences. These path texts are then fed into a pre-trained large language model for semantic encoding. First, for each path text... Embedding generation involves extracting the embedding representation of each token from the last hidden layer of the model. ,in, Given a fixed embedding dimension, for the same path, all token embeddings are aggregated using average pooling to generate a path-level embedding vector. This path-level encoding method not only captures topological features such as node types and connection relationships within the path, but also preserves the sequence dependencies of the semantic context. Because each node... Represented as multiple path texts Therefore, by aggregating the representations of all path texts, node-level representations are obtained. If each node contains Path, path embedding as The final node representation is obtained using the following formula: This mean pooling operation takes into account the structural semantic information of all paths and can stably reflect the functional characteristics of a node in its local structure.

[0062] 6. Fine-tuning of node classification After obtaining the semantic representation of nodes based on a language model, an MLP layer is added as a classifier, and the semantic understanding capability of FPGA netlist node paths is transferred to specific hardware Trojan detection tasks through supervised fine-tuning. This stage aims to build an end-to-end trainable framework to achieve closed-loop optimization from semantic representation to task classification.

[0063] Unlike traditional supervised training, to better address the problem of severe class imbalance (i.e., far fewer malicious nodes than normal nodes), Class-Balanced Focal Loss (CB-Focal Loss) was used as the optimization objective function during training. CB-Focal Loss combines two mechanisms: first, the class balance factor is adjusted based on the frequency of each class in the training set, alleviating the problem of minority class samples being ignored in gradient updates; second, a modulation term from Focal Loss is introduced, making the model pay more attention to marginal samples that are difficult to classify, thereby improving the model's discriminative ability on complex boundaries. The formula for calculating the loss function is as follows: in, For batch size, For the number of categories, For the first The sample at the th Model output for each category For the first The sample at the th Labels on each category For category The number of samples in the training set, For the focus loss parameter, This is a category balancing factor that controls the smoothness of the weights. For category The balance weight, For the first The sample at the th Predicted probabilities for each category.

[0064] This fine-tuning process effectively transfers the specific task from graph path semantic modeling to hardware Trojan detection, enabling the model to not only understand the full graph structure but also effectively capture hardware Trojan nodes in circuit design.

[0065] The effects that can be achieved through this solution include: Dataset Based on publicly available hardware trojan benchmarks on Trust-Hub and GitHub, a total of 39 circuits containing hardware trojans were collected, including AES, DES, and RS232 circuit types. These circuits were all provided in RTL Verilog code form, and therefore were synthesized into a Xilinx gate-level netlist using Yosys tools. During synthesis, optimization options were disabled to preserve the original circuit's logic structure as much as possible and avoid interfering with the trojan's behavior.

[0066] 2. Experimental Setup The model is implemented and trained using the PyTorch framework. During pre-training, the number of training epochs is set to 3, the batch size to 16, and the initial learning rate to 1e-4. The AdamW optimizer is used for parameter updates. During training, a cosinedecay learning rate scheduling strategy is employed to mitigate oscillations in the later stages of training and improve convergence. In the fine-tuning stage, an MLP classifier is designed and implemented for binary classification prediction of node representations. This model consists of a three-layer fully connected structure, with LayerNorm, GELU activation function, and Dropout mechanism introduced between layers to enhance model stability and generalization ability. The Dropout rate is 0.5. Specifically, the input feature dimension is consistent with the output dimension of the large model used, the hidden layer dimensions are set to 512 and 256, and the output is a 2D class representation. Model parameters are initialized using Xavier, and the AdamW optimizer is used. The overall architecture balances discriminative ability with computational efficiency and overfit suppression. A node-level dataset is constructed and divided into training and validation sets in an 8:2 ratio, with 30 training epochs. Furthermore, a grid search was performed on the key hyperparameters of the model to achieve a good balance between generalization performance and training stability. The specific parameter search range and final selection results are summarized in the table below. In addition, to prevent overfitting, an early stopping mechanism was introduced during the fine-tuning stage to terminate training early when the validation set performance no longer improves, further enhancing the model's generalization ability, as shown in Table 1.

[0067] Table 1 The experiment employs leave-one-out cross-validation, where one circuit is used as the test set and the remaining circuits are used as the training set each time. To prevent information leakage, a rigorous check is performed before training begins to ensure there are no overlapping samples between the test and training sets. If overlap is found, the corresponding samples are removed from the training set, guaranteeing complete independence between the training and test datasets.

[0068] To comprehensively evaluate the performance of the proposed model in hardware Trojan detection tasks, the following classic metrics are used: Accuracy represents the proportion of samples correctly predicted by the model out of the total number of samples, and is defined as: Wherein, TP (True Positive) is the number of true positives, that is, the number of samples correctly predicted as positive; TN (True Negative) is the number of true negatives, that is, the number of samples correctly predicted as negative; FP (False Positive) is the number of false positives, that is, the number of negative samples incorrectly predicted as positive; and FN (False Negative) is the number of false negatives, that is, the number of positive samples incorrectly predicted as negative.

[0069] Precision measures the proportion of samples that are actually predicted as positive out of all samples predicted as positive. The formula is: Recall measures the proportion of samples that are actually positive that are correctly identified. The formula is: The F1 score is the harmonic average of precision and recall, used to comprehensively consider the trade-off between the two, and is defined as follows: The True Negative Rate (TNR) measures the proportion of samples that are actually negative (i.e., normal nodes) but are correctly identified as negative. It reflects the model's ability to distinguish "normal circuits," and its calculation formula is as follows: The above metrics reflect the classification performance of the model from different perspectives. Among them, the F1 score, as the harmonic mean of precision and recall, can comprehensively measure the accuracy and coverage of the model, and is of great significance for evaluating the actual application effect of the model.

[0070] 3. Experimental Results First, the high-performance large language model Qwen2.5 was selected as the backbone model for semantic modeling, and experiments were conducted on a node-level hardware Trojan detection task. To fully cover the node context information and capture the mesoscale semantic features in the local structure, the path length was fixed at 4, meaning that each forward and backward path contained a maximum of 5 nodes. Under this setting, all 39 collected hardware Trojan circuits were trained and tested, and the accuracy, precision, recall, and F1 score of each circuit in the node-level classification task were statistically analyzed. The experimental results are shown in the table, indicating that the proposed method exhibits stable and superior detection performance on most circuits, verifying the effectiveness of the proposed method.

[0071] Table 2 After experiments on 39 hardware Trojan benchmark circuits, the model demonstrated stable and excellent detection performance. Overall, the model achieved an average accuracy of 95.59%, an average precision of 86.35%, an average recall of 90.93%, an average TNR of 96.44%, and an average F1 score of 88.10%, fully demonstrating the model's effectiveness in locating hardware Trojan nodes.

[0072] In the above embodiments, although the steps are numbered S1, S2, etc., they are only specific embodiments given by the present invention. Those skilled in the art can adjust the execution order of S1, S2, etc. according to the actual situation, which is also within the protection scope of the present invention. It can be understood that in some embodiments, some or all of the above embodiments may be included.

[0073] This invention also provides an FPGA netlist-level hardware Trojan detection system based on a large language model, the specific technical solution of which is as follows: The building module is used to: construct a text attribute graph based on the original FPGA netlist. The text attribute graph includes at least two logic unit nodes, at least one directed edge for signal connection, and textual attributes corresponding to each logic unit node. The generation module is used to: based on the text attribute graph, take any logical unit node as the starting point, obtain the node sequence corresponding to each starting point through bidirectional random walk, and according to the arrangement order of the logical unit nodes in the node sequence, concatenate the textual attributes corresponding to the logical unit nodes to form the text path corresponding to each starting point, and generate a corpus file after merging and deduplicating all text paths. The training module is used to: pre-train a large language model based on the corpus file to obtain a target large language model; select any number of logical unit nodes as target nodes in the text attribute graph; combine a preset hop count threshold; take each target node as the center and the preset hop count threshold as the constraint; perform sampling operations along the forward and backward directions respectively; record the target text path corresponding to each target node; and merge all target text paths to generate a path text set. The optimization module is used to: analyze and process each target text path in the path text set through the target large language model to obtain the semantic vector matrix corresponding to each target node; process the semantic vector matrix through a classifier; and perform supervised fine-tuning of the target large language model in combination with a loss function to obtain the final model. The detection module is used to: construct a corresponding target path text set for any node to be detected in any FPGA netlist, and input it into the final model for judgment to obtain the label and probability value of whether the node contains a Trojan.

[0074] It should be noted that the beneficial effects of the FPGA netlist-level hardware Trojan detection system based on a large language model provided in the above embodiments are the same as those of the FPGA netlist-level hardware Trojan detection method based on a large language model, and will not be repeated here. Furthermore, the system provided in the above embodiments is only illustrated by the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the system can be divided into different functional modules according to the actual situation to complete all or part of the functions described above. In addition, the system and method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiments, and will not be repeated here.

[0075] like Figure 5 As shown, an electronic device 300 according to an embodiment of the present invention includes a processor 320 coupled to a memory 310. The memory 310 stores at least one computer program 330, which is loaded and executed by the processor 320 to enable the electronic device 300 to implement any of the above-mentioned methods. Specifically: The electronic device 300 can vary considerably due to differences in configuration or performance. It may include one or more processors 320 (Central Processing Units, CPUs) and one or more memories 310. The memories 310 store at least one computer program 330, which is loaded and executed by the processors 320 to enable the electronic device 300 to implement the FPGA netlist-level hardware Trojan detection method based on a large language model provided in the above embodiments. Of course, the electronic device 300 may also have wired or wireless network interfaces, a keyboard, and input / output interfaces for input and output. It may also include other components for implementing device functions, which will not be elaborated upon here.

[0076] An embodiment of the present invention provides a computer-readable storage medium storing at least one computer program, which is loaded and executed by a processor to enable a computer to implement any of the above-described methods.

[0077] Alternatively, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, a floppy disk, and an optical data storage device, etc.

[0078] In an exemplary embodiment, a computer program product or computer program is also provided, which includes computer instructions stored in a computer-readable storage medium. A processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device to perform any of the methods described above.

[0079] It should be noted that the terms "first" and "second" in the specification and claims of this application are used to distinguish similar objects and represent a limitation on a specific order or sequence. Where appropriate, the order of use for similar objects can be interchanged so that the embodiments of this application described herein can be implemented in an order other than that shown or described.

[0080] Those skilled in the art will recognize that this invention can be implemented as a system, method, or computer program product. Therefore, this disclosure can be specifically implemented in the following forms: it can be entirely hardware, entirely software (including firmware, resident software, microcode, etc.), or a combination of hardware and software, generally referred to herein as a "circuit," "module," or "system." Furthermore, in some embodiments, the invention can also be implemented as a computer program product contained in one or more computer-readable media, which includes computer-readable program code.

[0081] Any combination of one or more computer-readable media may be used. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in connection with an instruction execution system, apparatus, or device.

[0082] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for detecting hardware Trojans at the FPGA netlist level based on a large language model, characterized in that, include: Based on the original FPGA netlist, a text attribute graph is constructed, which includes at least two logic unit nodes, at least one directed edge for signal connection, and textual attributes corresponding to each logic unit node. Based on the text attribute graph, starting from any logical unit node, a node sequence corresponding to each starting point is obtained through bidirectional random walk. Then, according to the arrangement order of the logical unit nodes in the node sequence, the textual attributes corresponding to the logical unit nodes are concatenated to form the text path corresponding to each starting point. After merging and deduplicating all text paths, a corpus file is generated. Based on the corpus file, a pre-trained large language model is obtained to obtain a target large language model. In the text attribute graph, any number of logical unit nodes are selected as target nodes. Combined with a preset hop count threshold, sampling operations are performed along the forward and backward directions with each target node as the center and the preset hop count threshold as the constraint condition. The target text path corresponding to each target node is recorded, and all target text paths are merged to generate a path text set. The target large language model is used to analyze and process each target text path in the path text set to obtain the semantic vector matrix corresponding to each target node. The semantic vector matrix is ​​then processed by a classifier, and the target large language model is supervised and fine-tuned in conjunction with a loss function to obtain the final model. For any node to be detected in any FPGA netlist, construct the corresponding target path text set, and input it into the final model for judgment to obtain the label and probability value of whether the node contains a Trojan. The text attribute graph is defined as a triple: ,in: : Node set : Used to describe the attribute information attached to each node. Extract the following five key attributes: in, A unique identifier for a logical unit; Indicates the logical function type; The key parameters of the element are represented. During the netlist generation process, the INIT value of some elements is assigned as 1'hx, indicating that the initial state is unknown. To avoid introducing semantic ambiguity, this type of uncertain INIT parameter is filtered during the path generation stage. and The input and output signals of the node are described separately, and all these attributes are mapped to... ; A set of directed edges, representing the signal connection relationships between logic elements, based on attribute information. The input and output signals in the middle construct directed edges, that is, when The output signal and When matching the input signal, a directed edge is established. ; The process of constructing a text attribute graph includes the following steps: (1) Logic unit parsing and node construction: The FPGA netlist is parsed line by line to identify different types of logic units, extract their node attributes, and add them as nodes in the graph structure; (2) Signal mapping and edge establishment: A signal-to-node mapping index table is established through the output signal of the node. All input signals are reverse matched to determine their source nodes, thereby establishing a complete set of directed edges to reflect the signal propagation path; (3) Virtual node mechanism: In order to ensure the integrity of the graph structure, a virtual node mechanism is introduced to handle the situation where there are undefined signals or special signals. By creating a uniquely numbered virtual node to simulate a special node, and connecting it to the graph, the integrity of the graph structure is ensured. (4) Relay node merging: In order to improve the quality of graph construction and the simplicity of graph structure, node merging was performed on relay non-functional nodes; relay non-functional nodes do not have actual logical functions and only serve as signal transfer; by analyzing the input and output signals, they are removed from the graph and directly connected to the source node of the input signal and the target node of the output signal, thereby bypassing the relay nodes to establish a simpler connection. The process of constructing the text attribute graph is as follows: The original FPGA netlist is parsed line by line to identify lookup tables, inverters, multiplexers, flip-flops, carry units, and buffer logic units, and a logic unit node is generated for each logic unit. At the same time, the logic unit node is associated with textual attributes. Based on the input and output signals corresponding to each logic unit node, a mapping index table between logic unit nodes is constructed. For each logical unit node, perform reverse matching on the input signal to determine the source node corresponding to each logical unit node, and based on the source node, determine the directed edges of the signal connection relationship; Virtual nodes and relay nodes are set up, and the text attribute graph is constructed based on logical unit nodes, textual attributes, mapping index table, directed edges of signal connection relationships, virtual nodes, and relay nodes. The process of obtaining the node sequence corresponding to each starting point through bidirectional random walk is as follows: According to the uniform distribution sampling method, multiple logical unit nodes are determined, and each logical unit node is used as the starting point for sampling in turn. Path acquisition is performed using a bidirectional random walk method, which includes forward walk and backward walk; Using adjacency constraints, repetition constraints, and length constraints as combined constraints, the node sequence corresponding to each starting point is determined. The adjacency constraint is as follows: when collecting paths through bidirectional random walks, the adjacent logical unit nodes of the current logical unit node are taken as the next path collection node. The repetition constraint is as follows: a maximum number of accesses is set for each logical unit node, and access is prohibited when the number of accesses for any logical unit node reaches the maximum number of accesses; The length constraint is as follows: set the maximum path length for path acquisition, and when the path length corresponding to the node sequence of any starting point reaches the maximum path length, directly output the node sequence.

2. The method for detecting FPGA netlist-level hardware Trojans based on a large language model according to claim 1, characterized in that, The process of obtaining the semantic vector matrix corresponding to each target node is as follows: Extract the embedding representation of each token from the last hidden layer of the target large language model; Using the same target text path as a unit, the embedded representations of all tokens are aggregated through average pooling; Aggregate the embedded representations of all target text paths to generate a semantic vector matrix corresponding to any target node.

3. A hardware Trojan detection system for FPGA netlist level based on a large language model, employing the hardware Trojan detection method for FPGA netlist level based on a large language model as described in claim 1, characterized in that... include: The construction module is used to: build a text attribute graph based on the original FPGA netlist, wherein the text attribute graph includes at least two logic unit nodes, at least one directed edge for signal connection relationship, and textual attributes corresponding to each logic unit node; The generation module is used to: based on the text attribute graph, take any logical unit node as the starting point, obtain the node sequence corresponding to each starting point through bidirectional random walk, and according to the arrangement order of the logical unit nodes in the node sequence, concatenate the textual attributes corresponding to the logical unit nodes to form the text path corresponding to each starting point, and generate a corpus file after merging and deduplicating all text paths. The training module is used to: pre-train a large language model based on the corpus file to obtain a target large language model; select any number of logical unit nodes as target nodes in the text attribute graph; combine a preset hop count threshold; take each target node as the center and the preset hop count threshold as the constraint; perform sampling operations along the forward and backward directions respectively; record the target text path corresponding to each target node; and merge all target text paths to generate a path text set. The optimization module is used to: analyze and process each target text path in the path text set through the target large language model to obtain the semantic vector matrix corresponding to each target node; process the semantic vector matrix through a classifier; and perform supervised fine-tuning of the target large language model in combination with a loss function to obtain the final model. The detection module is used to: construct a corresponding target path text set for any node to be detected in any FPGA netlist, and input it into the final model for judgment to obtain the label and probability value of whether the node contains a Trojan.

4. The FPGA netlist-level hardware Trojan detection system based on a large language model according to claim 3, characterized in that, The process of obtaining the semantic vector matrix corresponding to each target node is as follows: Extract the embedding representation of each token from the last hidden layer of the target large language model; Using the same target text path as a unit, the embedded representations of all tokens are aggregated through average pooling; Aggregate the embedded representations of all target text paths to generate a semantic vector matrix corresponding to any target node.

5. An electronic device, characterized in that, The electronic device includes a processor coupled to a memory storing at least one computer program, which is loaded and executed by the processor to enable the electronic device to perform the method as described in claim 1 or 2.

6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores at least one computer program, which is loaded and executed by a processor to enable the computer to perform the method as described in claim 1 or 2.

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