Model adaptive AI computing chip implementation method

Abstract

This invention discloses a model-adaptive AI computing chip implementation method, belonging to the field of integrated circuits. Utilizing the technical characteristics of reconfigurable hardware, it deeply integrates model features with the characteristics of heterogeneous hardware. By maintaining compatibility with traditional AI computing designs, this invention achieves a certain balance between computational efficiency and accuracy. Furthermore, based on the integration and driving of reconfigurable hardware, it enhances the model's adaptability, better adapting to new hardware requirements arising from future AI model development. Within a system time limit, without altering the model implementation, this invention optimizes computation by iteratively optimizing dynamically reconfigurable hardware units and optimizing the distribution of computational tasks across tensor-specific units, vector computation units, and dynamically reconfigurable hardware units, thereby improving the overall optimization capability of the dynamically reconfigurable hardware units. This invention can also achieve joint optimization of the model and hardware by changing the model's implementation structure within a certain range.

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