Display panel and display device

Abstract

This application provides a display panel and display device, including multiple pixel units. Each pixel unit includes a driving module, a pre-charge control module, a frequency control module, a storage module, and a light-emitting module. The driving module is electrically connected to the pre-charge control module, the storage module, the frequency control module, and the light-emitting module. The driving module receives data signals and transmits them to the storage module for storage through the pre-charge control module. The driving module drives the light-emitting module to emit light according to the data signals to perform image display. The frequency control module is electrically connected to the pre-charge control module and is used to control the pre-charge control module to receive or stop receiving data signals transmitted to the storage module. When the pre-charge control module receives data signals, the pixel unit performs image display at a first refresh rate. When the pre-charge control module stops receiving data signals, it performs image display at a second refresh rate, thereby controlling the display area to achieve multi-frequency partitioned display and enabling vertical multi-frequency partitioned display.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to display panels and display devices. Background Technology

[0002] With the development of display technology, the application scenarios of display panels are increasing, and users' display needs are becoming more diversified. Users often use split-screen displays in various scenarios when using terminal products, such as watching videos while playing mobile games or reading novels simultaneously. Moreover, the required frequency varies depending on the specific split-screen scenario. Therefore, researchers have begun studying multi-frequency partitioned display technology. However, current multi-frequency partitioned displays typically divide the display area horizontally. In different scenarios, vertical partitioning is also necessary to save power. Therefore, how to achieve vertical partitioning so that each partition can display multiple frequencies is a problem that urgently needs to be solved. Summary of the Invention

[0003] To address the aforementioned technical problems, embodiments of this application provide a display panel and display device that can effectively achieve vertically partitioned multi-frequency display.

[0004] In a first aspect, embodiments of this application provide a display panel, including a display area comprising a plurality of pixel units arranged in an array. Each pixel unit is used to perform image display based on received data signals. Each pixel unit includes a driving module, a pre-charge control module, a frequency control module, a storage module, and a light-emitting module. The driving module is electrically connected to the pre-charge control module, the storage module, the frequency control module, and the light-emitting module. During a signal pre-charge phase within a frame image display period, the driving module receives the data signal and transmits it to the storage module for storage via the pre-charge control module. During an image display phase within a frame image display period, the driving module drives the light-emitting module to emit light based on the data signal to perform image display. The frequency control module is electrically connected to the pre-charge control module and is used to control the pre-charge control module to receive or stop receiving data signals transmitted to the storage module. When the pre-charge control module receives the data signal, the pixel unit performs image display at a first refresh rate; when the pre-charge control module stops receiving the data signal, it performs image display at a second refresh rate. The signal pre-charge phase and the display phase are two consecutive phases during image display by the pixel unit.

[0005] The frequency control module controls the pixel unit to receive data signals when displaying an image at the first refresh rate and to stop receiving signals when displaying an image at the second refresh rate. This allows the display area to be divided into multiple display areas that execute different refresh rates, thereby achieving multi-frequency partitioned display. Since it is possible to control the pixel unit connected to the same data line to receive data signals at the first refresh rate and to stop receiving data signals at the second refresh rate, vertical multi-frequency partitioned display can be achieved.

[0006] Optionally, the display area includes at least one preset area. When the preset area executes the first refresh rate, the pre-charge control module in the pixel unit receives the data signal during each frame of image display. When the preset area executes the second refresh rate, the pre-charge control module in the pixel unit stops receiving the data signal during the continuous display of multiple frames of images.

[0007] By controlling the pixel units in the preset area to receive data signals for each frame of image display when displaying images at a first refresh rate, and stopping receiving data signals when displaying images in areas outside the preset area at a second refresh rate, multi-frequency display in zones can be achieved.

[0008] Optionally, the pixel unit further includes a first reset module, a second reset module, a first light emission control module, and a second light emission control module. The first reset module is electrically connected to the driving module and is used to reset the driving module before the driving module receives the data signal. The second reset module is electrically connected to the light emission module and is used to reset the light emission module before the driving module drives the light emission module. The first light emission control module is electrically connected to the driving module and the power supply voltage terminal. The second light emission control module is electrically connected between the driving module and the light emission module. The first light emission control module and the second light emission control module are used to cooperate with the driving module to drive the light emission module to emit light during the light emission phase.

[0009] Optionally, the driving module includes a first switching transistor and a driving switching transistor. The control terminal of the first switching transistor is electrically connected to the scan line, the first terminal of the first switching transistor is electrically connected to the data line, the second terminal of the first switching transistor is electrically connected to the first terminal of the driving switching transistor, the control terminal of the driving switching transistor is electrically connected to a first node, and the second terminal of the driving switching transistor is electrically connected to a second node. The first switching transistor is used to conduct under the control of the scan signal to receive the data signal and transmit it to the driving switching transistor. When the first node receives a first level signal, the driving switching transistor is turned on to transmit the data signal to the second node.

[0010] Optionally, the pre-charge control module includes a second switch, a third switch, a first capacitor, and a second capacitor; the storage module includes a storage capacitor; wherein the control terminal of the second switch is electrically connected to the frequency control module; the first terminal of the second switch is electrically connected to a reference voltage terminal; the second terminal of the second switch is electrically connected to the first node; the control terminal of the third switch is electrically connected to the frequency control module; the first terminal of the third switch is electrically connected to the second node; the second terminal of the third switch is electrically connected to the first node; the second terminal of the third switch is electrically connected to the first node and then electrically connected to the first terminal of the storage capacitor; the second terminal of the storage capacitor is electrically connected to a power supply voltage terminal; the first terminal of the first capacitor is electrically connected to the control terminal of the second switch; the second terminal of the first capacitor is electrically connected to the power supply voltage terminal; the first terminal of the second capacitor is electrically connected to the control terminal of the third switch; and the second terminal of the second capacitor is electrically connected to the power supply voltage terminal. When the area where the pixel unit is located displays an image at the first refresh rate, the frequency control module controls the second switch and the third switch to be turned on. When the second switch is turned on, the reference voltage terminal outputs a first level signal to the first node to control the driving switch to be turned on. The data signal is transmitted to the storage capacitor for storage via the driving switch, the second node, and the third switch. When the area where the pixel unit is located displays an image at the second refresh rate, the frequency control module controls the second switch and the third switch to be turned off to control the storage capacitor to stop receiving the data signal of the current frame image display.

[0011] By controlling the on and off states of the second and third switching transistors, the pixel unit can be effectively controlled to receive or not receive data signals for image display. This allows the pixel unit to receive data signals for image display when the first refresh rate is executed, and to stop receiving data signals when the second refresh rate is executed, thereby maintaining the previous frame image.

[0012] Optionally, the frequency control module includes a fourth switch, a fifth switch, and a third capacitor. The control terminal of the fourth switch is electrically connected to the frequency control terminal, the first terminal of the fourth switch is electrically connected to the first signal terminal, the second terminal of the fourth switch is electrically connected to the control terminal of the second switch, the control terminal of the fifth switch is electrically connected to the frequency control terminal, the first terminal of the fifth switch is electrically connected to the second signal terminal, the second terminal of the fifth switch is electrically connected to the control terminal of the third switch, the first terminal of the third capacitor is electrically connected to the frequency control terminal, and the second terminal of the third capacitor is electrically connected to the power supply voltage terminal. When the area where the pixel unit is located displays an image at the first refresh rate, the frequency control terminal controls the fourth and fifth switches to be turned on, so as to control the first and second signal terminals to output a second level signal to the control terminals of the second and third switches, so as to control the second and third switches to be turned on. When the area where the pixel unit is located displays an image at the second refresh rate, the frequency control module controls the fourth and fifth switches to be turned off, so as to control the second and third switches to be turned off.

[0013] Optionally, the first reset module includes a sixth switch, and the second reset module includes a seventh switch. The control terminal of the sixth switch is electrically connected to a third signal terminal, the first terminal of the sixth switch is electrically connected to a first reset terminal, the second terminal of the sixth switch is electrically connected to a first terminal of the driving switch, the control terminal of the seventh switch is electrically connected to a fourth signal terminal, the first terminal of the seventh switch is electrically connected to a second reset terminal, and the second terminal of the seventh switch is electrically connected to the light-emitting module. The sixth switch is turned on under the control of the third signal terminal to control the first reset terminal to output a reset signal to reset the driving switch, and the seventh switch is turned on under the control of the fourth signal terminal to control the second reset terminal to reset the light-emitting module.

[0014] Optionally, the first light-emitting control module includes an eighth switch, and the second light-emitting control module includes a ninth switch. The control terminal of the eighth switch is electrically connected to a fifth signal terminal, the first terminal of the eighth switch is electrically connected to a first terminal of a driving switch, and the second terminal of the eighth switch is electrically connected to a power supply voltage terminal. The control terminal of the ninth switch is electrically connected to a sixth signal terminal, the first terminal of the ninth switch is electrically connected to the second node, and the second terminal of the ninth switch is electrically connected to the light-emitting module. During the image display stage, the eighth switch is turned on under the control of the fifth signal terminal, the ninth switch is turned on under the control of the sixth signal terminal, the driving switch is turned on under the control of the data signal, and the power supply voltage output from the power supply voltage terminal passes through the eighth switch, the driving switch, and the ninth switch to output a power supply voltage to drive the light-emitting module to emit light.

[0015] Optionally, when the area where the pixel unit is located displays an image at the first refresh rate, the pixel unit performs image display in a series of periods: a first period, a second period, a third period, a fourth period, a fifth period, and a sixth period. In the first period, the fifth signal terminal outputs a second level signal to control the eighth switch to turn off, thereby controlling the power supply voltage terminal to stop outputting power supply voltage to the driving switch. In the second period, the frequency control terminal controls the fourth and fifth switches to turn on, the second signal terminal controls the third switch to turn on, and simultaneously the third signal terminal controls the sixth switch to turn on, thereby controlling the first reset terminal to reset the driving switch. In the third period, the first signal terminal controls the second switch to turn on, thereby controlling the reference voltage terminal to output a first level signal to the first node to control the driving switch to turn on. In the fourth time period, the scanning signal controls the first switch to turn on, and the data signal is transmitted to the storage capacitor via the driving switch and the third switch. In the fifth time period, the second signal terminal controls the point switch to turn off, and the third signal terminal controls the sixth switch to turn on, so as to control the first reset terminal to reset the driving switch. In the sixth time period, the fifth signal terminal controls the seventh and eighth switches to turn on, the data signal controls the driving switch to turn on, and the power supply voltage terminal outputs the power supply voltage to the light-emitting module through the eighth switch, the driving switch, and the ninth switch, so as to control the light-emitting module to emit light. When the area where the pixel unit is located displays an image at the second refresh rate, in the second and third time periods, the frequency control terminal outputs a second frequency control signal to control the fourth and fifth switches to turn off, so as to control the second and third switches to turn off, so as to control the storage capacitor to stop receiving the data signal.

[0016] Optionally, the display panel further includes a data driving circuit, a selection circuit, and a conversion circuit. The selection circuit is electrically connected to the data driving circuit, the conversion circuit, and the pixel unit. The conversion circuit is electrically connected to the frequency control terminal. The data driving circuit is used to output the data signal and the initial signal to the selection circuit simultaneously. The selection circuit is used to transmit the data signal to the pixel unit and the initial signal to the conversion circuit. The conversion circuit is used to identify the rising edge and falling edge of the initial signal. When the conversion circuit outputs the first frequency control signal to the frequency control terminal based on the rising edge of the initial signal, the area where the pixel unit is located displays the image at the first refresh rate. When the conversion circuit outputs the second frequency control signal to the frequency control terminal based on the falling edge of the initial signal, the area where the pixel unit is located displays the image at the second refresh rate.

[0017] By setting the selection circuit to control the data drive circuit to output data signals to the pixel unit and output initial signals to the conversion circuit, the timeliness and accuracy of the signal output can be effectively guaranteed, avoiding display failures caused by erroneous signals.

[0018] Optionally, the selection circuit includes a first control transistor and a second control transistor. The control terminal of the first control transistor is electrically connected to the selection signal terminal, the first terminal of the first control transistor is electrically connected to the data driving circuit, and the second terminal of the first control transistor is electrically connected to the pixel unit. The control terminal of the second control transistor is electrically connected to the selection signal terminal, the first terminal of the second control transistor is electrically connected to the data driving circuit, and the second terminal of the second control transistor is electrically connected to the conversion circuit. When the selection signal terminal outputs a first level signal, the first control transistor is turned on, and the data driving circuit outputs the data signal to the pixel unit via the first control transistor. When the selection signal terminal outputs a second level signal, the second control transistor is turned on, and the data driving circuit outputs the initial signal to the conversion circuit via the second control transistor.

[0019] Optionally, the conversion circuit includes an adjustment module, an output module, and a sustaining module. The adjustment module is electrically connected to the data driving circuit and the output module. The adjustment module is used to identify the rising edge and falling edge of the initial signal. When the adjustment module identifies the rising edge of the initial signal, the adjustment module outputs a first control signal to the output module. When the adjustment module identifies the falling edge of the initial signal, the adjustment module outputs a second control signal. The output module outputs a first frequency control signal to the frequency control terminal based on the first control signal. The output module outputs a second frequency control signal to the frequency control terminal based on the second control signal. The sustaining module is electrically connected to the adjustment module and is used to maintain the stability of the voltage in the adjustment module when the adjustment module performs voltage adjustment.

[0020] The conversion circuit outputs high-level and low-level signals based on the rising and falling edges of the initial signal, respectively, thus avoiding the voltage limitation of the data drive circuit output voltage and enabling the conversion circuit to output effective level control signals.

[0021] Optionally, the adjustment module includes a third control transistor, a fourth control transistor, a fourth capacitor, and a fifth capacitor. The first terminal of the fourth capacitor is electrically connected to the input terminal, the second terminal of the fourth capacitor is electrically connected to the control terminal of the third control transistor, the first terminal of the third control transistor is electrically connected to the off voltage terminal, the second terminal of the third control transistor is electrically connected to the control node, the control terminal of the fourth control transistor is electrically connected to the input terminal, the first terminal of the fourth control transistor is electrically connected to the on voltage terminal, and the second terminal of the fourth control transistor is electrically connected to the control node. The first terminal of the fifth capacitor is electrically connected to the input terminal, and the second terminal of the fifth capacitor is electrically connected to the second terminal of the fourth control transistor. The three control transistors are used to turn on based on the rising edge of the initial signal to control the off voltage terminal to output a first-level signal to the control node, and the fourth control transistor is used to turn on based on the falling edge of the initial signal to control the on voltage terminal to output a second-level signal to the control node.

[0022] Optionally, the output module includes a fifth control transistor and a sixth control transistor, and the sustaining module includes a seventh control transistor. The control terminal of the fifth control transistor is electrically connected to the control node, the first terminal of the fifth control transistor is electrically connected to the turn-on voltage terminal, and the second terminal of the fifth control transistor is electrically connected to the output terminal. The control terminal of the sixth control transistor is electrically connected to the control node, the first terminal of the sixth control transistor is electrically connected to the turn-off voltage terminal, and the second terminal of the sixth control transistor is electrically connected to the output terminal. The control terminal of the seventh control transistor is electrically connected to the input terminal, and the first terminal of the seventh control transistor is electrically connected to the turn-off voltage terminal. The second terminal of the seventh control transistor is electrically connected to the control terminal of the third control transistor; the fifth control transistor is turned on according to the first level signal to control the turn-on voltage terminal to output the first frequency control signal to the frequency control terminal via the output terminal; the sixth control transistor is turned on according to the second level signal to control the turn-off voltage terminal to output the second frequency control signal to the frequency control terminal via the output terminal; the seventh control transistor is turned on when the initial signal is at the first level to control the turn-off voltage terminal to output the first level signal to the control terminal of the third control transistor to control the third control transistor to remain in the off state.

[0023] Secondly, embodiments of this application also provide a display device, including a power module and a display panel as described above, wherein the power module is used to provide driving current to the display panel to drive the display panel to perform image display.

[0024] Compared to the problems of existing technologies, the embodiments of this application, by setting a frequency control module in the pixel unit to control the pixel unit to receive data signals when displaying an image at the first refresh rate and to stop receiving data signals when displaying an image at the second refresh rate, can divide the display area into multiple display areas that execute different refresh rates, thereby enabling multi-frequency display with partitioned display. Furthermore, by precisely controlling whether the pixel unit receives or does not receive data signals, the refresh rate of any range of display areas can be controlled, enabling both horizontal and vertical partitioned display.

[0025] It should be understood that the beneficial effects achieved by the second aspect of the technical solution of this application can be referred to the above-described technical effects of the first aspect and its corresponding possible implementations, and will not be repeated here. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the structure of a display device 100 provided in the first embodiment of this application;

[0028] Figure 2 for Figure 1 A schematic diagram of the floor plan layout of the central display panel;

[0029] Figure 3 for Figure 2 A schematic diagram illustrating the refresh rate control of the central display area;

[0030] Figure 4 for Figure 2 A schematic diagram of the equivalent circuit of a mid-pixel unit;

[0031] Figure 5 for Figure 4 Timing diagram of the output signal;

[0032] Figure 6 This is a schematic diagram of the conversion circuit layout;

[0033] Figure 7 for Figure 6 Equivalent circuit diagram of the intermediate conversion circuit;

[0034] Figure 8 for Figure 7 Schematic diagram of voltage changes at the input and output terminals;

[0035] Figure 9 This is a timing diagram of signal output for a pixel unit during the display of multiple consecutive image frames. Detailed Implementation

[0036] To better understand the technical solutions provided in the embodiments of this application, the relevant embodiments of this application are described below.

[0037] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a display device 100 provided in the first embodiment of this application.

[0038] like Figure 1As shown, the display device 100 includes a display panel 10 and a power module 20, which is located on the back of the display panel 10, i.e., the non-display surface of the display panel 10. The power module 20 is used to provide driving current for the display panel 10 to display images.

[0039] Please see Figure 2 , Figure 2 for Figure 1 A schematic diagram of the floor plan layout of the central display panel.

[0040] like Figure 2 As shown, the display area of ​​the display panel 10 includes multiple pixel units P arranged in a matrix, m data lines S1 to Sm and n scan lines G1 to Gn, where m and n are natural numbers greater than 1.

[0041] The n scan lines G1 to Gn extend along the first direction F1 and are mutually insulated and arranged in parallel along the second direction F2. The m data lines S1 to Sm extend along the second direction F2 and are mutually insulated and arranged in parallel along the first direction F1. The first direction F1 and the second direction F2 are perpendicular to each other.

[0042] The non-display area of ​​the display panel 10 includes a timing control circuit 11 for driving pixel units to display images, a data driving circuit 12, and a scanning driving circuit 13 disposed on the array substrate 10c.

[0043] The timing control circuit 11 is electrically connected to the data driving circuit 12 and the scan driving circuit 13. It is used to control the working timing of the data driving circuit 12 and the scan driving circuit 13, that is, to output the corresponding timing light emission signal to the data driving circuit 12 and the scan driving circuit 13, so as to control when to output the corresponding scan signal and data signal.

[0044] The data driving circuit 12 is electrically connected to the m data lines S1 to Sm, and is used to transmit the data signal (Data) to be displayed to the plurality of pixel units P in the form of data voltage through the m data lines S1 to Sm.

[0045] The scan driving circuit 13 is electrically connected to the n scan lines G1 to Gn, and outputs scan signals through the n scan lines G1 to Gn to control when the pixel unit P receives data signals. Specifically, the scan driving circuit 13 outputs scan signals from the n scan lines G1 to Gn in sequence according to their positional arrangement and in accordance with the scan cycle.

[0046] Please see Figure 3 , Figure 3 for Figure 2 A schematic diagram showing the refresh rate control of area 10a in the display.

[0047] like Figure 3 As shown, the display area 10a includes a first display area A and a second display area B. The first display area A can be a preset area, and its size range can be set according to specific settings. The first display area A is the area overlapping between the a-th scan line Ga to the b-th scan line and the a-th data line Sa to the b-th data line Sb. The second display area B is the display area other than the first display area A.

[0048] The display panel 10 includes a first display mode, a second display mode, and a third display mode. When the display panel 10 executes the first display mode, the first display area A and the second display area B display images at the same refresh rate. When the display panel 10 executes the second display mode, the refresh rate of the first display area A is greater than the refresh rate of the second display area B. When the display panel executes the third display mode, the refresh rate of the first display area A is less than the refresh rate of the second display area B. Here, refresh rate refers to the number of frames displayed per unit time.

[0049] When the first display mode is executed, n scan lines Ga-Gn output scan signals at the same frequency to control the first display area A and the second display area B to display images at the same refresh rate.

[0050] When the second display mode is executed, scan lines Ga to Gb sequentially output scan signals at a first frequency (high refresh rate), while pixel units in the first display area A receive data signals at the first frequency for image display, so that the first display area A displays images at the first refresh rate. Scan lines G1 to a-1 and b+1 to n output scan signals at either a first frequency or a second frequency (low refresh rate), while pixel units P in the second display area B receive data signals at the second frequency for image display, so that the second display area B displays images at the second refresh rate. The first frequency is greater than the second frequency.

[0051] When the third display mode is executed, scan lines Ga from a to b output scan signals at a first or second frequency, while the pixel units in the first display area A receive data signals at the second frequency for image display. Scan lines G1 to a-1 and b+1 to n output scan signals at the first frequency, while the pixel units P in the second display area B receive data signals at the first frequency for image display.

[0052] It is understandable that, since the same column of pixel units P is connected to the same data line S, when pixel unit P in the first display area A refreshes at the first frequency, or displays an image at the first refresh rate, and pixel unit P in the second display area B refreshes at the second frequency, or displays an image at the second refresh rate, during the continuous display of a frames of images, it is possible to control pixel unit P in the first display area A to receive data signals and display images in each frame of image display. At the same time, it is possible to control pixel unit P in the second display area B to stop receiving data signals in the continuous c frames of images, that is, to maintain the current screen unchanged. Thus, it is possible to control pixel units connected to the same data line S to display images at different frequencies, where c is an integer greater than or equal to 1.

[0053] In an exemplary embodiment, c can be set according to specific needs, such as 10, 20, 30, etc., that is, the pixel unit that controls the second frequency refresh stops receiving data signal refresh when displaying images for 10, 20, or 30 consecutive frames. Of course, c can also be set to other quantities as needed, and this application does not limit this.

[0054] Please see Figure 4 , Figure 4 for Figure 2 A schematic diagram of the equivalent circuit of a mid-pixel unit.

[0055] like Figure 4 As shown, the pixel unit P includes a pixel circuit 15. The pixel circuit 15 receives data signals and controls the pixel unit P to emit light. The pixel circuit 15 includes a driving module 151, a pre-charge control module 152, a storage module 153, a frequency control module 154, and a light-emitting module 155. The driving module 151 is electrically connected to the pre-charge control module 152, the storage module 153, and the light-emitting module 155. During the signal pre-charge stage, the driving module 151 receives data signals and transmits them to the pre-charge control module 152, which then transmits them to the storage module 153 for storage. During the display stage, the storage module 153 transmits data signals to the driving module 151 to control the driving module 151 to drive the light-emitting module 155 to emit light. The frequency control module 154 is electrically connected to the pre-charge control module 152 and controls whether the pre-charge control module 152 transmits data signals to the storage module 153 for storage. When the display area where pixel unit P is located displays an image at the first refresh rate, the frequency control module 154 controls the precharge control module 152 to transmit data signals to the storage module 153 during the display of multiple consecutive frames of images. When the display area where pixel unit P is located displays an image at the second refresh rate, the frequency control module 154 controls the precharge control module 152 to stop transmitting data signals to the storage module 153 during the display of c consecutive frames of images.

[0056] For example, when the display panel 10 executes the second display mode, the frequency control module 154 in the pixel unit of the first display area A controls the precharge control module 152 to receive data signals and transmit them to the storage module 153, so as to control the driving module 151 to drive the light-emitting module 155 to emit light during each frame of image display. Meanwhile, the frequency control module 154 in the pixel unit of the second display area B controls the precharge control module 152 to stop receiving data signals, so as to control the driving module 151 to stop driving the light-emitting module 155 to emit light, that is, to control the pixel unit P to maintain the brightness of the previous frame, thereby controlling the first display area A to maintain a high refresh rate state and controlling the second display area B to maintain a low refresh rate state.

[0057] Similarly, when the display panel 10 executes the third display mode, the frequency control module 154 in the pixel unit P in the first display area A controls the precharge control module 152 to stop transmitting the received data signal to the storage module 153, so as to control the drive module 151 to stop driving the light-emitting module 155 to emit light, that is, to control the pixel unit P to maintain the brightness of the previous frame. The frequency control module 154 in the pixel unit P in the second display area B controls the precharge control module 152 to receive the data signal and transmit it to the storage module 153, so as to control the drive module 151 to drive the light-emitting module 155 to emit light in each frame of image display, thereby controlling the first display area A to maintain a low refresh rate state and controlling the second display area B to maintain a high refresh rate state.

[0058] The pixel circuit 15 also includes a first reset module 156, a second reset module 157, a first light emission control module 158, and a second light emission control module 159. The first reset module 156 is electrically connected to the driving module 151 and is used to reset the driving module 151 before it receives a data signal. The second reset module 157 is electrically connected to the light emission module 155 and is used to reset the light emission module 155 before the driving module 151 drives it to emit light. The first light emission control module 158 is electrically connected to the driving module 151 and the power supply voltage terminal VDD. The second light emission control module 159 is electrically connected between the driving module 151 and the light emission module 155. The first light emission control module 158 and the second light emission control module 159 are used to cooperate with the driving module 151 to drive the light emission module 155 to emit light during the light emission stage.

[0059] Specifically, the driving module 151 includes a first switching transistor T1 and a driving switching transistor DT. The control terminal of the first switching transistor T1 is electrically connected to the scan line G, the first terminal of the first switching transistor T1 is electrically connected to the data line S, and the second terminal of the first switching transistor T1 is electrically connected to the first terminal of the driving switching transistor DT. The control terminal of the driving switching transistor DT is electrically connected to the first node N1, and the second terminal of the driving switching transistor DT is electrically connected to the second node N2. When the control terminal of the first switching transistor T1 receives a scan signal from the scan line G, the first switching transistor T1 is turned on, and the data signal is transmitted to the first terminal of the driving switching transistor DT through the first switching transistor T1. When the first node N1 is at the first potential, the driving switching transistor DT is turned on to transmit the data signal to the second node N2.

[0060] The pre-charge control module 152 includes a second switch T2, a third switch T3, a first capacitor C1, and a second capacitor C2. The storage module 153 includes a storage capacitor Cst. The control terminal of the second switch T2 is electrically connected to the frequency control module 154. The first terminal of the second switch T2 is electrically connected to the reference voltage terminal Vref. The second terminal of the second switch T2 is electrically connected to the first node N1 and is connected to the first terminal of the storage capacitor Cst through the first node N1. The second switch T2 is used to be turned on under the control of the frequency control module 154 during the signal pre-charge stage, so that the reference voltage terminal Vref charges the first node N1 to the first potential.

[0061] The control terminal of the third switch T3 is electrically connected to the frequency control module 154. The first terminal of the third switch T3 is electrically connected to the second node N2, and the second terminal of the third switch T3 is electrically connected to the first node N1, and through the first node N1, it is electrically connected to the first terminal of the storage capacitor Cst. The second terminal of the storage capacitor Cst is electrically connected to the power supply voltage terminal VDD. The third switch T3 is used to conduct under the control of the frequency control module 154 during the signal pre-charge phase, receiving data signals from the second node N2 and transmitting them to the storage capacitor Cst for storage. The first terminal of the first capacitor C1 is electrically connected to the control terminal of the second switch T2, and the second terminal of the first capacitor C1 is electrically connected to the power supply voltage terminal VDD. The first terminal of the second capacitor C2 is electrically connected to the control terminal of the third switch T3, and the second terminal of the second capacitor C2 is electrically connected to the power supply voltage terminal VDD.

[0062] When the display area where pixel unit P is located is refreshed at the first frequency, during the signal pre-charging phase, the frequency control module 154 controls the second switch T2 to turn on so that the first node N1 is charged to the first potential, thereby controlling the drive switch TD to turn on, so that the data signal is transmitted to the storage capacitor Cst for storage via the drive switch TD, the second node N2, the third switch T3, and the first node N1. When the display area where pixel unit P is located is refreshed at the second frequency, the frequency control module 154 controls the second switch T2 and the third switch T3 to turn off so that the storage capacitor Cst stops receiving the data signal for the next frame of image display, that is, controls pixel unit P not to refresh the image when the next frame of image is displayed. Here, the first capacitor C1 is used to maintain the stability of the voltage at the control terminal of the second switch T2, and the second capacitor C2 is used to maintain the stability of the voltage at the control terminal of the third switch T3.

[0063] The frequency control module 154 includes a fourth switch T4, a fifth switch T5, and a third capacitor C3. The control terminal of the fourth switch T4 is electrically connected to the frequency control terminal Vc, the first terminal of the fourth switch T4 is electrically connected to the first signal terminal SC1, and the second terminal of the fourth switch T4 is electrically connected to the control terminal of the second switch T2. The fourth switch T4 is turned on under the control of the frequency control terminal Vc, so that the first signal terminal SC1 outputs a second level signal (high level) to the control terminal of the second switch T2 to control the second switch T2 to turn on.

[0064] The control terminal of the fifth switch T5 is electrically connected to the frequency control terminal Vc. The first terminal of the fifth switch T5 is electrically connected to the second signal terminal SC2. The second terminal of the fifth switch T5 is electrically connected to the control terminal of the third switch T3. The fifth switch T5 is used to conduct under the control of the frequency control terminal Vc, so that the second signal terminal SC2 outputs a second level signal to the control terminal of the second switch T2 to control the second switch T2 to conduct.

[0065] The first terminal of the third capacitor C3 is electrically connected to the frequency control terminal Vc, which is also electrically connected to the control terminal of the fourth switch T4 and the fifth switch T5. The second terminal of the third capacitor C3 is electrically connected to the power supply voltage terminal VDD. The third capacitor C3 is used to maintain the stability of the control terminal voltage of the fourth switch T4 and the fifth switch T5.

[0066] When the area where pixel unit P is located is refreshed at the first frequency, the frequency control terminal Vc outputs the first frequency control signal to control the fourth switch T4 and the fifth switch T5 to turn on, and to control the first signal terminal SC1 and the second signal terminal SC2 to output the second level signal to the second switch T2 and the third switch T3 to turn on. When the area where pixel unit P is located is refreshed at the second frequency, the frequency control terminal Vc outputs the second frequency control signal to control the second and fourth switches T4 and the fifth switch T5 to turn off, and then control the second switch T2 and the third switch T3 to turn off.

[0067] The light-emitting module 155 includes a light-emitting element D, the anode of which is electrically connected to the second reset module 157, and the cathode of which is electrically connected to the low-voltage terminal VSS. The light-emitting element D can be an organic light-emitting diode (OLED).

[0068] The first reset module 156 includes a sixth switch transistor T6, and the second reset module 157 includes a seventh switch transistor T7. The control terminal of the sixth switch transistor T6 is electrically connected to the third signal terminal SC3, the first terminal of the sixth switch transistor T6 is electrically connected to the first reset terminal VR1, and the second terminal of the sixth switch transistor T6 is electrically connected to the first terminal of the driving switch transistor TD. The sixth switch transistor T6 is turned on under the control of the first level signal (low level) output from the third signal terminal SC3, so that the first reset terminal VR1 outputs a reset signal to the driving switch transistor TD to reset the driving switch transistor TD.

[0069] The control terminal of the seventh switch T7 is electrically connected to the fourth signal terminal SC4, the first terminal of the seventh switch T7 is electrically connected to the second reset terminal VR2, and the second terminal of the seventh switch T7 is electrically connected to the anode of the light-emitting element D. The seventh switch T7 is used to conduct under the control of the first level signal output from the fourth signal terminal SC4, so that the second reset terminal VR2 resets the light-emitting element D.

[0070] The first light-emitting control module 158 includes an eighth switch transistor T8, and the second light-emitting control module 159 includes a ninth switch transistor T9. The control terminal of the eighth switch transistor T8 is electrically connected to the fifth signal terminal SC5, the first terminal of the eighth switch transistor T8 is electrically connected to the power supply voltage terminal VDD, and the second terminal of the eighth switch transistor T8 is electrically connected to the first terminal of the driving switch transistor DT. The eighth switch transistor T8 is turned on under the control of a first-level signal output from the fifth signal terminal SC5, so that the power supply voltage terminal VDD outputs a power supply voltage to the first terminal of the driving switch transistor DT. The control terminal of the ninth switch transistor T9 is electrically connected to the sixth signal terminal SC6, the first terminal of the ninth switch transistor T9 is electrically connected to the second node N2, and the second terminal of the ninth switch transistor T9 is electrically connected to the anode of the light-emitting element D. The ninth switch transistor T9 is turned on under the control of the first-level signal output from the sixth signal terminal SC6, so that the power supply voltage transmitted from the switch transistor DT to the second node N2 is transmitted to the anode of the light-emitting element D, thereby driving the light-emitting element D to emit light. That is, when the eighth switch T8, the ninth switch T9 and the driving switch DT are turned on at the same time, the power supply voltage terminal VDD outputs the power supply voltage to the anode of the light-emitting element D to drive the light-emitting element D to emit light.

[0071] In this embodiment, the driving switch DT, the first switch T1, the sixth switch T6, the seventh switch T7, the eighth switch T8, and the ninth switch T9 are P-type thin-film transistors (TFTs), and the second switch T2, the third switch T3, the fourth switch T4, and the fifth switch T5 are N-type TFTs. Of course, the first switch T1 to the ninth switch T9 can be configured according to specific needs, and this application does not impose any limitations on this. The control terminal of the switch can be the gate, the first terminal of the switch can be the source, and the second terminal of the switch can be the drain.

[0072] Please see Figure 5 , Figure 5 for Figure 4 Timing diagram of the signal output.

[0073] like Figure 5 As shown, when the area where pixel unit P is located refreshes the image at the first frequency, the pixel unit P displays the image in a series of time periods including the first time period t1, the second time period t2, the third time period t3, the fourth time period t4, the fifth time period t5, and the sixth time period t6. In the first time period t1, the fifth signal terminal SC5 outputs a second level signal (high level) to control the eighth switch T8 to turn off, so as to control the power supply voltage terminal VDD to stop outputting power supply voltage to the driving switch DT.

[0074] During the second time period t2, the frequency control terminal Vc outputs a first frequency control signal to control the fifth switch T5 to turn on, the second signal terminal SC2 outputs a second level signal to control the third switch T3 to turn on, and at the same time, the third signal terminal SC3 outputs a first level signal to control the sixth switch T6 to turn on, so that the first reset terminal VR1 resets the driving switch DT.

[0075] During the third time period t3, the first signal terminal SC1 outputs a second level signal through the fourth switch T4 to control the second switch T2 to turn on, thereby causing the reference voltage terminal Vref to output a first level signal through the second switch T2 and the first node N1 to the drive switch DT to control the drive switch DT to turn on.

[0076] During the fourth time period t4, the scan line G outputs a scan signal to control the first switch T1 to turn on, so that the data signal is transmitted through the first switch T1 to the drive switch DT, and through the drive switch DT to the second node N2, and through the third switch T3 and the first node N1 to the storage capacitor Cst for storage.

[0077] During the fifth time period t5, the second signal terminal SC2 outputs a first level signal to control the third switch T3 to be turned off, and at the same time, the third signal terminal SC3 outputs a first level signal to control the sixth switch T6 to be turned on, so as to reset the drive switch DT.

[0078] During the sixth time period t6, the fifth signal terminal SC5 outputs a first level signal to control the seventh switch T7 and the eighth switch T8 to turn on. The data signal in the storage capacitor Cst controls the drive switch DT to turn on. The power supply voltage terminal VDD outputs the power supply voltage, which is transmitted to the anode of the light-emitting element D through the eighth switch T8, the drive switch DT and the seventh switch T7 to drive the light-emitting element D to emit light.

[0079] When the area where pixel unit P is located is refreshed at the second frequency, the frequency control terminal Vc outputs the second frequency control signal to the control terminals of the fourth switch T4 and the fifth switch T5 to control the fourth switch T4 and the fifth switch T5 to be in the off state, thereby controlling the second switch T2 and the third switch T3 to be in the off state during the second time period t2 and the third time period t3, thereby controlling the storage capacitor Cst to stop receiving the data signal of the current frame, so as to control pixel unit P to maintain the image of the previous frame, that is, not refresh the image of the current frame.

[0080] Please see Figure 6 , Figure 6 This is a schematic diagram of the conversion circuit layout.

[0081] like Figure 6As shown, the display panel 10 also includes a selection circuit 16 and a conversion circuit 17. The selection circuit 16 is electrically connected to the data driving circuit 12, the conversion circuit 17, and the pixel circuit 15 in the display area 10a. The conversion circuit 17 is electrically connected to the frequency control terminal Vc in the pixel circuit 15. The data driving circuit 12 is used to output data signals and initial signals to the selection circuit 16 at different times. The selection circuit 16 is used to transmit data signals to the pixel circuit 15 and transmit initial signals to the conversion circuit 17.

[0082] The conversion circuit 17 outputs a first frequency control signal or a second frequency control signal based on the initial signal and transmits it to the frequency control terminal Vc. When the area where pixel unit P is located is refreshed at the first frequency, the conversion circuit 17 outputs the first frequency control signal to the frequency control terminal Vc. When the area where pixel unit P is located is refreshed at the second frequency, the conversion circuit 17 outputs the second frequency control signal to the frequency control terminal Vc. The first frequency control signal is a high-level signal, and the second frequency control signal is a low-level signal. The first frequency control signal is transmitted to the control terminals of the fourth switch transistor T4 and the fifth switch transistor T5 to control the fourth switch transistor T4 and the fifth switch transistor T5 to be turned on. This controls pixel unit P to display the image based on the received data signal. The second frequency control signal is transmitted to the control terminals of the fourth switch transistor T4 and the fifth switch transistor T5 to control the fourth switch transistor T4 and the fifth switch transistor T5 to be turned off, thus controlling pixel unit P not to receive the current frame data signal, thereby continuing to display the previous frame image, i.e., not refreshing the image.

[0083] Specifically, the selection circuit 16 includes a first control transistor M1 and a second control transistor M2. The control terminal of the first control transistor M1 is electrically connected to the selection signal terminal K, the first terminal of the first control transistor M1 is electrically connected to the data driving circuit 12, and the second terminal of the first control transistor M1 is electrically connected to the pixel circuit 15. The control terminal of the second control transistor M2 is electrically connected to the selection signal terminal K, the first terminal of the second control transistor M2 is electrically connected to the data driving circuit 12, and the second terminal of the second control transistor M2 is electrically connected to the conversion circuit 17. When the selection signal terminal K outputs a first-level signal, the first control transistor M1 is turned on, and the data driving circuit 12 transmits the output data signal to the pixel circuit 15 via the first switching transistor M1, so that the pixel circuit 15 controls the pixel unit P to emit light according to the data signal. When the selection signal terminal K outputs a second-level signal, the second control transistor M2 is turned on, and the data driving circuit 12 outputs an initial signal, which is transmitted to the conversion circuit 17 via the second control transistor M2. The selection signal terminal K can be electrically connected to the timing control circuit 11, that is, the timing control circuit 11 can control the conduction and cutoff of the first control transistor M1 and the second control transistor M2.

[0084] In this embodiment, the first control transistor M1 is an N-type transistor, which is turned on under the control of a high-level signal, and the second control transistor M2 is a P-type transistor, which is turned on under the control of a low-level signal. The control terminal of the control transistor can be the gate, the first terminal of the control transistor can be the source, and the second terminal of the control transistor can be the drain. Of course, the first control transistor M1 and the second control transistor M2 can be set to other types of transistors as needed, and this application does not limit this.

[0085] Since the data driving circuit 12 can only output voltages from 0V to 7V, and controlling the fourth switch T4 and the fifth switch T5 to turn on and off requires high-level signals and low-level signals, which are (-7)V to 7V voltages, the conversion circuit 17 is used to identify the rising and falling edges of the initial signal output by the data driving circuit 12, and outputs a first frequency control signal to the pixel circuit 15 based on the rising edge of the initial signal, and outputs a second frequency control signal to the pixel circuit 15 based on the falling edge of the initial signal.

[0086] Please refer to the following: Figure 7 and Figure 8 , Figure 7 for Figure 6 The equivalent circuit diagram of the intermediate conversion circuit. Figure 8 for Figure 7 A schematic diagram showing the voltage changes at the input and output terminals.

[0087] like Figure 7 and Figure 8 As shown, the conversion circuit 17 includes an adjustment module 171, an output module 172, and a sustaining module 173. The adjustment module 171 is electrically connected to the data driving circuit 12 and the output module 172. It is used to receive the initial signal input from the data driving circuit 12 and identify the rising or falling edge of the initial signal. When the adjustment module 171 identifies the rising edge of the initial signal, the adjustment module 171 outputs a first control signal to the output module 172. When the adjustment module 171 identifies the falling edge of the initial signal, the adjustment module 171 outputs a second control signal to the output module 172.

[0088] Output module 172 is electrically connected to the frequency control terminal Vc in pixel circuit 15. Output module 172 outputs a first frequency control signal to frequency control terminal Vc according to a first control signal to control pixel circuit 15 to receive data signals, thereby causing the preset area to execute a first display mode. Output module 172 also outputs a second frequency control signal to frequency control terminal Vc according to a second control signal to control pixel circuit 15 to stop receiving data signals, thereby causing the preset area to execute a second display mode. Maintenance module 173 is electrically connected to adjustment module 171 and is used to maintain the stability of the voltage in adjustment module 171 when adjustment module 171 performs voltage adjustment.

[0089] Specifically, the adjustment module 171 includes a third control transistor M3, a fourth control transistor M4, a fourth capacitor C4, and a fifth capacitor C5. The first terminal of the fourth capacitor C4 is electrically connected to the input terminal (input), and the second terminal of the fourth capacitor C4 is electrically connected to the control terminal of the third control transistor M3. The first terminal of the third control transistor M3 is electrically connected to the off voltage terminal VGL, and the second terminal of the third control transistor M3 is electrically connected to the control node Q. The control terminal of the fourth control transistor M4 is electrically connected to the input terminal (input), the first terminal of the fourth control transistor M4 is electrically connected to the on voltage terminal VGH, and the second terminal of the fourth control transistor M4 is electrically connected to the control node Q. The first terminal of the fifth capacitor C5 is electrically connected to the input terminal (input), and the second terminal of the fifth capacitor C5 is electrically connected to the second terminal of the fourth control transistor M4. The third control transistor M3 is turned on when the initial signal is at a rising edge to control the off voltage terminal VGL to output a first-level signal to the control node Q. The fourth control transistor M4 is turned on when the initial signal is at a falling edge to control the on voltage terminal to output a second-level signal to the control node Q.

[0090] Output module 172 includes a fifth control transistor M5 and a sixth control transistor M6. The control terminal of the fifth control transistor M5 is electrically connected to control node Q, its first terminal is electrically connected to the turn-on voltage terminal VGH, and its second terminal is electrically connected to the output terminal. The control terminal of the sixth control transistor M6 is electrically connected to control node Q, its first terminal is electrically connected to the turn-off voltage terminal VGL, and its second terminal is electrically connected to the output terminal. When the display panel 10 executes the first display mode, the fifth control transistor M5 is turned on according to a first level signal, controlling the turn-on voltage terminal VGH to output a second level signal via the output terminal as a first frequency control signal to the frequency control terminal Vc. When the display panel 10 executes the second display mode, the sixth control transistor M6 is turned on according to a second level signal, controlling the turn-off voltage terminal VGL to output a first level signal via the output terminal as a second frequency control signal to the frequency control terminal Vc.

[0091] The sustaining module 173 includes a seventh control transistor M7. The control terminal of the seventh control transistor M7 is electrically connected to the input terminal, the first terminal of the seventh control transistor M7 is electrically connected to the shutdown voltage terminal VGL, and the second terminal of the seventh control transistor M7 is electrically connected to the control terminal of the third control transistor M3. The seventh control transistor M7 is turned on when the initial signal is at a falling edge or when the initial signal is at a first level (low level), so as to control the shutdown voltage terminal VGL to output a first level signal to the control terminal of the third control transistor M3, so as to control the third switch transistor M3 to remain in the off state.

[0092] The conversion circuit 17 outputs a high-level signal (7V) and a low-level signal (-7V) respectively based on the rising and falling edges of the initial signal, which are transmitted to the frequency control terminal Vc of the pixel circuit 15 as the first frequency control signal and the second frequency control signal, so as to control the display panel 10 to execute the first display mode or the second display mode.

[0093] In this embodiment, the third control transistor M3 and the sixth control transistor M6 are N-type transistors, used to conduct under the control of a high-level signal, and the fourth control transistor M4, the fifth control transistor M5, and the seventh control transistor M7 are P-type transistors, used to conduct under the control of a low-level signal. The control terminal of the control transistor can be the gate, the first terminal of the control transistor can be the source, and the second terminal of the control transistor can be the drain. Of course, the third control transistor M3 to the seventh control transistor M7 can be set to other types of transistors as needed, and this application does not limit this.

[0094] Please see Figure 9 , Figure 9 This is a timing diagram of signal output for a pixel unit during the display of multiple consecutive image frames.

[0095] like Figure 9 As shown, when displaying an image on the display panel 10, for example, during the display of three consecutive frames of images, when the first frame of the image is displayed, a first data signal Data1 is written to the preset area to display the image. When the second frame of the image is displayed, no data is written to the preset area to maintain the previous frame of the image. When the third frame of the image is displayed, the preset area is refreshed and written with a second data signal Data2 to display the image. The preset area can be a first display area A or a second display area B.

[0096] When the first frame of the image is displayed, the selection signal terminal K outputs a second-level signal (high level) to control the second control transistor M2 to conduct. The conversion circuit 17 receives the initial signal from the data driving circuit 12 and outputs a first frequency control signal to the frequency control terminal Vc. At this time, the frequency control terminal Vc is at a high level to control the second switching transistor T2. Figure 3 The first data signal Data1 is turned on by the third switch T3, so that the pixel unit P receives the first data signal Data1. In the pixel circuit 15, the first data signal Data1 controls the drive switch DT to turn on, thereby driving the light-emitting element D to emit light to perform the display of the current frame image.

[0097] When the second frame image is displayed, the selection signal terminal K outputs a second level signal (high level) to control the second control transistor M2 to turn on. The conversion circuit 17 receives the initial signal from the data driving circuit and outputs the second frequency control signal to the frequency control terminal Vc. At this time, the frequency control terminal Vc is at a low level to control the second switch transistor T2 and the third switch transistor T3 to turn off. At this time, the pixel unit P does not receive data signals and drives the switch transistor DT to remain on. At this time, the pixel unit P maintains the previous frame image, that is, the image is not refreshed.

[0098] When the third frame image is displayed, the initial signal is output from the selection signal terminal K, and the second level signal (high level) is output from the selection signal terminal K to control the second control transistor M2 to conduct. The conversion circuit 17 receives the initial signal from the data driving circuit 12 and outputs the first frequency control signal to the frequency control terminal Vc. At this time, the frequency control terminal Vc is at a high level to control the second switching transistor T2 ( Figure 3 The second data signal Data2 is turned on by the third switch T3, so that the pixel unit P receives the second data signal Data2. In the pixel circuit 15, the second data signal Data2 controls the drive switch DT to turn on, thereby driving the light-emitting element D to emit light to perform the display of the current frame image.

[0099] The pixel circuit 15 provided in this application embodiment can control whether the pixel units in any column of the display panel receive or not receive data signals, thereby reducing the refresh rate of the preset area and thus reducing power consumption. Furthermore, since the pixel units in the preset area can be directly controlled to receive data signals, the refresh rate of any display area can be controlled to be reduced, thereby further reducing power consumption while ensuring the display effect.

[0100] The above-disclosed embodiments are merely some of the embodiments of this application, and should not be construed as limiting the scope of this application. Those skilled in the art can understand that all or part of the processes for implementing the above embodiments, and equivalent changes made in accordance with the claims of this application, still fall within the scope of this application.

Claims

1. A display panel, comprising a display area and a non-display area, wherein the display area includes multiple data lines, multiple scan lines, and multiple pixel units arranged in an array, the data lines and the scan lines being electrically connected to the pixel units, the pixel units being used to receive data signals from the data lines under the control of scan signals output by the scan lines, and to perform image display according to the data signals, the non-display area including a data driving circuit, a selection circuit, and a conversion circuit, the selection circuit being electrically connected to the data driving circuit; characterized in that The pixel unit includes a driving module, a pre-charge control module, a frequency control module, a storage module, and a light-emitting module. The driving module is electrically connected to the pre-charge control module, the storage module, the frequency control module, and the light-emitting module. During the signal pre-charge phase of a frame image display period, the driving module receives the data signal and transmits it to the storage module for storage through the pre-charge control module. During the image display phase of a frame image display period, the driving module drives the light-emitting module to emit light according to the data signal to perform image display. The frequency control module is electrically connected to the precharge control module and is used to control the precharge control module to receive or stop receiving data signals transmitted to the storage module. When the precharge control module receives the data signal, the pixel unit is used to perform image display at a first refresh rate. When the precharge control module stops receiving the data signal, it is used to perform image display at a second refresh rate. The selection circuit is electrically connected to the data driving circuit, the conversion circuit, and the pixel unit. The conversion circuit is electrically connected to the frequency control module in the pixel unit. The data driving circuit is used to output the data signal and the initial signal to the selection circuit simultaneously. The selection circuit is used to transmit the data signal to the pixel unit and the initial signal to the conversion circuit. The conversion circuit is used to identify the rising edge and falling edge of the initial signal. When the conversion circuit outputs a first frequency control signal to the frequency control module based on the rising edge of the initial signal, the area where the pixel unit is located displays the image at the first refresh rate. When the conversion circuit outputs a second frequency control signal to the frequency control module based on the falling edge of the initial signal, the area where the pixel unit is located displays the image at the second refresh rate.

2. The display panel of claim 1, wherein, The display area includes at least one preset area. When the preset area executes the first refresh rate, the pre-charge control module in the pixel unit receives the data signal during each frame of image display. When the preset area executes the second refresh rate, the pre-charge control module in the pixel unit stops receiving the data signal during the continuous display of multiple frames of images.

3. The display panel of claim 2, wherein, The pixel unit further includes a first reset module, a second reset module, a first light emission control module, and a second light emission control module. The first reset module is electrically connected to the driving module and is used to reset the driving module before the driving module receives the data signal. The second reset module is electrically connected to the light emission module and is used to reset the light emission module before the driving module drives the light emission module. The first light emission control module is electrically connected to the driving module and the power supply voltage terminal. The second light emission control module is electrically connected between the driving module and the light emission module. The first light emission control module and the second light emission control module are used to cooperate with the driving module to drive the light emission module to emit light during the light emission phase.

4. The display panel of claim 3, wherein, The driving module includes a first switching transistor and a driving switching transistor. The control terminal of the first switching transistor is electrically connected to the scan line, the first terminal of the first switching transistor is electrically connected to the data line, the second terminal of the first switching transistor is electrically connected to the first terminal of the driving switching transistor, the control terminal of the driving switching transistor is electrically connected to a first node, and the second terminal of the driving switching transistor is electrically connected to a second node. The first switch is turned on under the control of the scan signal to receive the data signal and transmit it to the driving switch. When the first node receives the first level signal, the driving switch is turned on to transmit the data signal to the second node.

5. The display panel of claim 4, wherein, The pre-charge control module includes a second switch, a third switch, a first capacitor, and a second capacitor. The storage module includes a storage capacitor. The control terminal of the second switch is electrically connected to the frequency control module. The first terminal of the second switch is electrically connected to a reference voltage terminal. The second terminal of the second switch is electrically connected to the first node. The control terminal of the third switch is electrically connected to the frequency control module. The first terminal of the third switch is electrically connected to the second node. The second terminal of the third switch is electrically connected to the first node and then electrically connected to the first terminal of the storage capacitor. The second terminal of the storage capacitor is electrically connected to a power supply voltage terminal. The first terminal of the first capacitor is electrically connected to the control terminal of the second switch. The second terminal of the first capacitor is electrically connected to the power supply voltage terminal. The first terminal of the second capacitor is electrically connected to the control terminal of the third switch. The second terminal of the second capacitor is electrically connected to the power supply voltage terminal. When the area where the pixel unit is located displays an image at the first refresh rate, the frequency control module controls the second switch and the third switch to be turned on. When the second switch is turned on, the reference voltage terminal outputs a first level signal to the first node to control the driving switch to be turned on. The data signal is transmitted to the storage capacitor for storage via the driving switch, the second node, and the third switch. When the area where the pixel unit is located displays an image at the second refresh rate, the frequency control module controls the second switch and the third switch to be turned off to control the storage capacitor to stop receiving the data signal of the current frame image display.

6. The display panel of claim 5, wherein, The frequency control module includes a fourth switch, a fifth switch, and a third capacitor. The control terminal of the fourth switch is electrically connected to the frequency control terminal, the first terminal of the fourth switch is electrically connected to the first signal terminal, the second terminal of the fourth switch is electrically connected to the control terminal of the second switch, the control terminal of the fifth switch is electrically connected to the frequency control terminal, the first terminal of the fifth switch is electrically connected to the second signal terminal, the second terminal of the fifth switch is electrically connected to the control terminal of the third switch, the first terminal of the third capacitor is electrically connected to the frequency control terminal, and the second terminal of the third capacitor is electrically connected to the power supply voltage terminal. When the area where the pixel unit is located displays an image at the first refresh rate, the frequency control terminal controls the fourth and fifth switching transistors to be turned on, so as to control the first and second signal terminals to output a second level signal to the control terminals of the second and third switching transistors, so as to control the second and third switching transistors to be turned on; when the area where the pixel unit is located displays an image at the second refresh rate, the frequency control module controls the fourth and fifth switching transistors to be turned off, so as to control the second and third switching transistors to be turned off.

7. The display panel of claim 6, wherein, The first reset module includes a sixth switch transistor, and the second reset module includes a seventh switch transistor. The control terminal of the sixth switch transistor is electrically connected to a third signal terminal, the first terminal of the sixth switch transistor is electrically connected to a first reset terminal, the second terminal of the sixth switch transistor is electrically connected to a first terminal of the driving switch transistor, the control terminal of the seventh switch transistor is electrically connected to a fourth signal terminal, the first terminal of the seventh switch transistor is electrically connected to a second reset terminal, and the second terminal of the seventh switch transistor is electrically connected to the light-emitting module. The sixth switch is turned on under the control of the third signal terminal to control the first reset terminal to output a reset signal to reset the driving switch. The seventh switch is turned on under the control of the fourth signal terminal to control the second reset terminal to reset the light-emitting module.

8. The display panel of claim 7, wherein, The first light-emitting control module includes an eighth switch, and the second light-emitting control module includes a ninth switch. The control terminal of the eighth switch is electrically connected to the fifth signal terminal, the first terminal of the eighth switch is electrically connected to the first terminal of the driving switch, and the second terminal of the eighth switch is electrically connected to the power supply voltage terminal. The control terminal of the ninth switch is electrically connected to the sixth signal terminal, the first terminal of the ninth switch is electrically connected to the second node, and the second terminal of the ninth switch is electrically connected to the light-emitting module. During the image display stage, the eighth switch is turned on under the control of the fifth signal terminal, the ninth switch is turned on under the control of the sixth signal terminal, the driving switch is turned on under the control of the data signal, and the power supply voltage output from the power supply voltage terminal passes through the eighth switch, the driving switch and the ninth switch to output a power supply voltage to drive the light-emitting module to emit light.

9. The display panel of claim 8, wherein, When the area where the pixel unit is located displays an image at the first refresh rate, the pixel unit performs image display including a continuous first time period, a second time period, a third time period, a fourth time period, a fifth time period, and a sixth time period. During the first time period, the fifth signal terminal outputs a second level signal to control the eighth switch to turn off, thereby controlling the power supply voltage terminal to stop outputting power supply voltage to the driving switch. During the second time period, the frequency control terminal controls the fourth and fifth switching transistors to turn on, the second signal terminal controls the third switching transistor to turn on, and the third signal terminal controls the sixth switching transistor to turn on, so as to control the first reset terminal to reset the driving switching transistor; During the third time period, the first signal terminal controls the second switch to turn on, thereby controlling the reference voltage terminal to output a first level signal to the first node to control the drive switch to turn on; During the fourth time period, the scanning signal controls the first switch to turn on, and the data signal is transmitted to the storage capacitor via the driving switch and the third switch. During the fifth time period, the second signal terminal control point switch is turned off, and the third signal terminal controls the sixth switch to be turned on, so as to control the first reset terminal to reset the drive switch. During the sixth time period, the fifth signal terminal controls the seventh and eighth switching transistors to turn on, the data signal controls the driving switching transistor to turn on, and the power supply voltage terminal outputs power supply voltage to the light-emitting module through the eighth switching transistor, the driving switching transistor, and the ninth switching transistor to control the light-emitting module to emit light. When the area where the pixel unit is located displays an image at the second refresh rate, during the second time period and the third time period, the frequency control terminal outputs a second frequency control signal to control the fourth and fifth switching transistors to turn off, thereby controlling the second and third switching transistors to turn off, and controlling the storage capacitor to stop receiving the data signal.

10. The display panel of any one of claims 1-9, wherein, The selection circuit includes a first control transistor and a second control transistor. The control terminal of the first control transistor is electrically connected to the selection signal terminal. The first terminal of the first control transistor is electrically connected to the data driving circuit. The second terminal of the first control transistor is electrically connected to the pixel unit. The control terminal of the second control transistor is electrically connected to the selection signal terminal. The first terminal of the second control transistor is electrically connected to the data driving circuit. The second terminal of the second control transistor is electrically connected to the conversion circuit. When the selection signal terminal outputs a first level signal, the first control transistor is turned on, and the data driving circuit outputs the data signal to the pixel unit through the first control transistor. When the selection signal terminal outputs a second level signal, the second control transistor is turned on, and the data driving circuit outputs the initial signal to the conversion circuit through the second control transistor.

11. The display panel of claim 10, wherein, The conversion circuit includes an adjustment module, an output module, and a sustaining module. The adjustment module is electrically connected to the data driving circuit and the output module. The adjustment module is used to identify the rising edge and falling edge of the initial signal. When the adjustment module identifies the rising edge of the initial signal, the adjustment module outputs a first control signal to the output module. When the adjustment module identifies the falling edge of the initial signal, the adjustment module outputs a second control signal. The output module outputs a first frequency control signal to the frequency control terminal based on the first control signal. The output module outputs a second frequency control signal to the frequency control terminal based on the second control signal. The sustaining module is electrically connected to the adjustment module and is used to maintain the voltage stability in the adjustment module when the adjustment module performs voltage adjustment.

12. The display panel of claim 11, wherein, The adjustment module includes a third control transistor, a fourth control transistor, a fourth capacitor, and a fifth capacitor. The first terminal of the fourth capacitor is electrically connected to the input terminal, the second terminal of the fourth capacitor is electrically connected to the control terminal of the third control transistor, the first terminal of the third control transistor is electrically connected to the off voltage terminal, the second terminal of the third control transistor is electrically connected to the control node, the control terminal of the fourth control transistor is electrically connected to the input terminal, the first terminal of the fourth control transistor is electrically connected to the on voltage terminal, the second terminal of the fourth control transistor is electrically connected to the control node, and the first terminal of the fifth capacitor is electrically connected to the input terminal, while the second terminal of the fifth capacitor is electrically connected to the second terminal of the fourth control transistor. The third control transistor is turned on according to the rising edge of the initial signal to control the output of a first level signal from the off voltage terminal to the control node, and the fourth control transistor is turned on according to the falling edge of the initial signal to control the output of a second level signal from the on voltage terminal to the control node.

13. The display panel of claim 12, wherein, The output module includes a fifth control transistor and a sixth control transistor, and the sustaining module includes a seventh control transistor. The control terminal of the fifth control transistor is electrically connected to the control node, the first terminal of the fifth control transistor is electrically connected to the turn-on voltage terminal, and the second terminal of the fifth control transistor is electrically connected to the output terminal. The control terminal of the sixth control transistor is electrically connected to the control node, the first terminal of the sixth control transistor is electrically connected to the turn-off voltage terminal, and the second terminal of the sixth control transistor is electrically connected to the output terminal. The control terminal of the seventh control transistor is electrically connected to the input terminal, the first terminal of the seventh control transistor is electrically connected to the turn-off voltage terminal, and the second terminal of the seventh control transistor is electrically connected to the control terminal of the third control transistor. The fifth control transistor is turned on according to the first level signal to control the turn-on voltage terminal to output the first frequency control signal to the frequency control terminal via the output terminal. The sixth control transistor is turned on according to the second level signal to control the turn-off voltage terminal to output the second frequency control signal to the frequency control terminal via the output terminal. The seventh control transistor is turned on when the initial signal is at the first level to control the turn-off voltage terminal to output the first level signal to the control terminal of the third control transistor to control the third control transistor to remain in the off state.

14. A display device comprising: The device includes a power supply module and a display panel as described in any one of claims 1-13, wherein the power supply module is used to provide drive current to the display panel to drive the display panel to perform image display.

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