Semiconductor temperature measuring device and method of manufacturing the same

Abstract

This disclosure provides a semiconductor temperature measuring device and its manufacturing method. The semiconductor temperature measuring device includes: a first wafer and a second wafer stacked along a first direction; a temperature measuring component located between the first wafer and the second wafer; the temperature measuring component includes an interconnect circuit, a temperature measuring device coupled through the interconnect circuit, a power supply, and a main controller; and a shielding structure located between the first wafer and the second wafer and covering the temperature measuring component.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor temperature measuring device and its manufacturing method. Background Technology

[0002] Temperature is a crucial process parameter in integrated circuit manufacturing. Especially as chip dimensions continue to shrink, the temperature uniformity of the wafer surface has an increasingly significant impact on process parameters such as etching rate and thin film deposition quality. Therefore, temperature measurement and control of the wafer surface are extremely important, necessitating real-time measurement of wafer temperature changes during processing using semiconductor temperature sensing devices (e.g., wafer temperature sensing devices). However, traditional wired semiconductor temperature sensing devices require connection to external circuitry, are limited in application range due to wiring length constraints, can introduce contamination, and are difficult to integrate with different process chambers. Wireless temperature sensing technology has emerged to address this issue. However, semiconductor temperature sensing devices used for wireless temperature sensing are subject to interference from complex electromagnetic environments such as high-voltage DC and multi-frequency radio waves within process chambers (e.g., etching process chambers), significantly impacting the accuracy of temperature measurements.

[0003] In view of this, it is urgent to improve semiconductor temperature measurement devices to enhance their anti-interference performance and achieve real-time and accurate monitoring of wafer temperature, thereby optimizing process parameters and improving product yield. Summary of the Invention

[0004] According to some aspects of embodiments of this disclosure, a semiconductor temperature measuring device is provided, comprising:

[0005] A first wafer and a second wafer stacked along a first direction; a temperature sensing component located between the first wafer and the second wafer; the temperature sensing component includes an interconnect circuit, a temperature sensing device coupled through the interconnect circuit, a power supply, and a main controller; a shielding structure located between the first wafer and the second wafer and covering the temperature sensing component.

[0006] In some embodiments, the shielding structure includes:

[0007] A first shielding layer and a second shielding layer connected to the first shielding layer;

[0008] The first and second sub-layers of the first shielding layer respectively cover the first and second surfaces of the temperature measuring component that are opposite to each other along the first direction; the second shielding layer surrounds and covers the outer edge of the temperature measuring component.

[0009] In some embodiments, the semiconductor temperature measuring device further includes:

[0010] Multiple conductive pillars are located between the first wafer and the second wafer, and the multiple conductive pillars are located between the outer edge of the temperature sensing component and the side of the first wafer; each of the conductive pillars penetrates at least the second sublayer of the first shielding layer and is coupled to the first wafer and the second wafer.

[0011] In some embodiments, the plurality of conductive pillars are spaced apart along the circumferential direction of the first wafer.

[0012] In some embodiments, the semiconductor temperature measuring device further includes:

[0013] An adhesive layer comprising a first portion located between the plurality of conductive pillars and the second wafer, and a second portion surrounding and covering the second shielding layer; wherein the second shielding layer has an inner sidewall and an outer sidewall, the second portion surrounding and covering the outer sidewall of the second shielding layer, and the inner sidewall of the second shielding layer covering the outer edge of the temperature sensing component.

[0014] In some embodiments, the semiconductor temperature measuring device further includes:

[0015] A capacitor structure, at least partially located between the first sub-layer and the second sub-layer; the capacitor structure includes a first electrode, a second electrode, and a dielectric layer, the dielectric layer being located between the first electrode and the second electrode;

[0016] The first electrode is coupled to the first sublayer, and the second electrode is coupled to the second sublayer.

[0017] In some embodiments, at least one of the first wafer and the second wafer has a groove for accommodating at least a portion of the temperature sensing component;

[0018] The first sublayer extends into the inner wall of the groove; the capacitor structure is located in the corresponding groove, and the first electrode is coupled to the first sublayer on the inner wall of the groove.

[0019] In some embodiments, the semiconductor temperature measuring device further includes:

[0020] An antenna, which is coupled to the main controller; the antenna is located at the center of the first wafer and the second wafer;

[0021] Multiple temperature measuring devices are arranged in a circumferential direction around the antenna; at least a portion of the interconnect circuitry coupled to the temperature measuring devices is arranged at intervals along the circumferential direction of the antenna.

[0022] According to some aspects of embodiments of this disclosure, a method for manufacturing a semiconductor temperature measuring device is provided, comprising:

[0023] Provide the first wafer;

[0024] A temperature sensing component is formed on a first surface of the first wafer; the temperature sensing component includes an interconnect circuit, a temperature sensing device coupled through the interconnect circuit, a power supply, and a main controller;

[0025] A shielding structure is formed, which covers the temperature measuring component;

[0026] A second wafer is provided and bonded to a first side of the first wafer.

[0027] In some embodiments, forming the shielding structure includes:

[0028] A first shielding layer and a second shielding layer connected to the first shielding layer are formed;

[0029] The first and second sub-layers of the first shielding layer respectively cover the first and second surfaces of the temperature measuring component along the stacking direction parallel to the first and second wafers; the second shielding layer surrounds and covers the outer edge of the temperature measuring component.

[0030] This disclosure provides a semiconductor temperature measuring device that can be used to simulate the temperature distribution of a wafer during a process and measure temperature values. The device comprises a temperature measuring component disposed between a first wafer and a second wafer, and a shielding structure forming between the first and second wafers covering the temperature measuring component. The temperature measuring component includes interconnect circuitry, temperature measuring devices coupled to the interconnect circuitry, a power supply, and a main controller. This provides effective electromagnetic shielding for the temperature measuring component, improving the anti-interference performance and temperature measurement accuracy of the semiconductor temperature measuring device. Furthermore, it prevents mechanical damage and enhances the mechanical protection of the temperature measuring component. Attached Figure Description

[0031] Figure 1 This is one of the top views of a semiconductor temperature measuring device provided in an embodiment of the present disclosure;

[0032] Figure 2 This is one of the cross-sectional schematic diagrams of a semiconductor temperature measuring device provided in an embodiment of the present disclosure;

[0033] Figure 3 This is one of the perspective schematic diagrams of a semiconductor temperature measuring device provided in an embodiment of the present disclosure;

[0034] Figure 4 This is a second perspective view of a semiconductor temperature measuring device provided in an embodiment of the present disclosure;

[0035] Figure 5 This is a second schematic cross-sectional view of a semiconductor temperature measuring device provided in an embodiment of the present disclosure;

[0036] Figure 6 This is one of the structural schematic diagrams of a capacitor structure provided in an embodiment of the present disclosure;

[0037] Figure 7 This is a second schematic diagram of a capacitor structure provided in an embodiment of the present disclosure;

[0038] Figure 8 This is a third schematic cross-sectional view of a semiconductor temperature measuring device provided in an embodiment of the present disclosure;

[0039] Figure 9 This is a second top view schematic diagram of a semiconductor temperature measuring device provided in an embodiment of the present disclosure;

[0040] Figure 10 This is a third top view schematic diagram of a semiconductor temperature measuring device provided in an embodiment of the present disclosure;

[0041] Figure 11 This is a schematic flowchart illustrating a method for manufacturing a semiconductor temperature measuring device according to an embodiment of this disclosure.

[0042] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0043] Exemplary embodiments disclosed herein will now be described in more detail with reference to the accompanying drawings.

[0044] It should be understood that when a component or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers.

[0045] It should be understood that references to "some embodiments" or "an embodiment" throughout the specification mean that a particular feature, structure, or characteristic relating to an embodiment is included in at least one embodiment of this disclosure. Furthermore, these particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0046] In some etching, vapor deposition, or epitaxial wafer systems, wafers are transported into the process cavity and fixed on a wafer carrier tray, which can be held by electrostatic adsorption, vacuum adsorption, or mechanical grippers. Within the process cavity, the wafer undergoes etching, deposition, and other processes. Temperature control components on the wafer carrier tray can heat or cool the wafer to provide and maintain the process temperature, improving process yield. In some embodiments, factors such as defects in the temperature control performance of the wafer carrier tray, deviations in the adjustment or setting of the temperature control components, or misalignment of the wafer on the wafer carrier tray may lead to uneven temperature distribution on the wafer, resulting in reduced process yield. For example, this may cause uneven etching rates or uneven deposition rates in different areas of the wafer. Detecting or measuring the temperature in different areas of the wafer allows for adjustments to the temperature control components or the wafer position to ensure that the temperature in each area of ​​the wafer meets the process control standards.

[0047] In some embodiments, to accurately simulate and measure the temperature distribution in different regions of a wafer, this disclosure provides a semiconductor temperature measuring device, the shape and size of which are the same as the product wafer, or a temperature measuring component including but not limited to temperature measuring devices, set on the wafer. This semiconductor temperature measuring device can also be called a temperature measuring wafer. The semiconductor temperature measuring device or temperature measuring wafer is transferred to a wafer carrier disk in the process cavity and adsorbed, the process is started, and the test signals of the temperature measuring devices distributed in different positions of the semiconductor temperature measuring device are obtained. This can simulate the temperature distribution of the product wafer in the relevant process, thereby realizing in-situ temperature testing of different regions of the product wafer in the process.

[0048] In some embodiments, the test signal for the semiconductor temperature measuring device or the temperature-measuring wafer can be transmitted via wired or wireless transmission. For example, the test signal characterizing the temperature value can be transmitted to an external host or processing unit for data processing via a transmission line; or a wireless transmission module, such as a Bluetooth module or a Wi-Fi module, can transmit the signal through an antenna and have it received by an external host for data processing. In some embodiments, the semiconductor temperature measuring device may be equipped with a memory device, such as a non-volatile memory device including a flash memory card, SSD, or hard disk, to store test data. After the test is completed, the semiconductor temperature measuring device is removed from the process chamber, and the memory device is read to retrieve the test data.

[0049] In some embodiments, taking process equipment with a plasma environment as an example, such as a plasma etching machine or a plasma chemical vapor deposition (PCVD) machine, process gases form plasma within the process chamber to etch or deposit onto the product wafer. These process chambers are equipped with plasma generators or plasma deflectors, and have power supply devices such as high-voltage DC and multi-frequency radio frequency, which can cause significant interference to semiconductor temperature measuring devices. For example, high-voltage DC and multi-frequency radio frequency can cause spike currents in the semiconductor temperature measuring device, or plasma or charges accumulated on the surface of the semiconductor temperature measuring device can generate current, causing electrical interference to the temperature measuring components within the semiconductor temperature measuring device, or even breakdown of some devices, or generating interference noise that reduces signal transmission stability.

[0050] As mentioned above, the uniformity of wafer surface temperature has become a key factor affecting process parameters (e.g., etching accuracy and thin film deposition quality), making real-time temperature measurement increasingly urgent. Although wireless technology overcomes spatial limitations, signal interference in complex electromagnetic environments such as etching chambers leads to a significant increase in temperature measurement errors, becoming a technical bottleneck restricting the accuracy of process control.

[0051] In view of this, the present invention provides a shielding structure covering the temperature measuring component within the semiconductor temperature measuring device to provide effective electromagnetic shielding for the temperature measuring component and reduce interference.

[0052] It should be noted that, here and below, the first direction is parallel to the thickness direction of the wafer, and the second and third directions are both parallel to the plane on which the wafer lies. The second and third directions are both perpendicular to the first direction, and the second and third directions intersect each other. In some specific embodiments, the second direction is perpendicular to the third direction. For example, the first direction may be the extension direction of the Z-axis shown in the figures, the second direction may be the extension direction of the X-axis shown in the figures, and the third direction may be the extension direction of the Y-axis shown in the figures; these will not be elaborated further below.

[0053] In view of this, the present disclosure provides a semiconductor temperature measuring device and a method for manufacturing the same.

[0054] Figure 1 This is a top view schematic diagram of a semiconductor temperature measuring device provided in an embodiment of this disclosure. Figure 2 for Figure 1 The diagram shows a cross-sectional view of the semiconductor temperature sensing device along the tangent direction AA'. (Reference) Figure 1 and Figure 2A semiconductor temperature measuring device 100 includes: a first wafer 102 and a second wafer 104 stacked along a first direction; a temperature measuring component located between the first wafer 102 and the second wafer 104; the temperature measuring component includes an interconnect circuit, a temperature measuring device 114 coupled through the interconnect circuit, a power supply 116, and a main controller 120; and a shielding structure 108 located between the first wafer 102 and the second wafer 104 and covering the temperature measuring component.

[0055] In some implementations, the interconnect circuit can be a strip-shaped first interconnect circuit 1261.

[0056] In some embodiments, such as Figure 1 , Figure 2 and Figure 4 As shown, the shielding structure 108 includes: a first shielding layer and a second shielding layer 1083 connected to the first shielding layer; wherein, the first sub-layer 1081 and the second sub-layer 1082 of the first shielding layer respectively cover the first surface S1 and the second surface S2 of the temperature measuring component opposite to each other along the first direction; the second shielding layer 1083 surrounds and covers the outer edge of the temperature measuring component.

[0057] In some embodiments, the second shielding layer 1083 is the sidewall of the shielding structure 108.

[0058] In some embodiments, the second shielding layer 1083 is annular in the XOY plane.

[0059] In some embodiments, both the first wafer and the second wafer have a first surface and a second surface opposite to each other along a first direction. A first sublayer 1081 of the first shielding layer may extend and lie flat on the first surface of the first wafer, at least covering a portion of the first surface of the first wafer; a second sublayer 1082 of the first shielding layer may extend and lie flat on the second surface of the second wafer, at least covering a portion of the second surface of the second wafer. The materials of the first sublayer 1081 and the second sublayer 1082 of the first shielding layer may be the same or different; the constituent materials of the first sublayer 1081 and the second sublayer 1082 of the first shielding layer may include conductive materials with high magnetic permeability, and may be a single-layer or multi-layer structure, including but not limited to: conductive materials such as silver, copper, aluminum, tungsten, gold, silver, platinum, nickel, titanium, tin, etc., or easily curable materials including the above-mentioned conductive metal materials, such as organosilicon, polymers, etc., which include conductive metal materials. Taking the first sublayer 1081 of the first shielding layer as an example, the first sublayer 1081 of the first shielding layer may be a metal material layer formed by processes such as physical and chemical deposition, sputtering, electroplating, etc.

[0060] In some embodiments, the first sublayer 1081 of the first shielding layer can be formed by curing a conductive paste. The conductive paste may include metal microspheres, metal powder, or other conductive materials with microstructures and an easily curable substrate; it may include, but is not limited to, powders such as gold, silver, copper, and aluminum, and may also include non-metallic microstructure materials such as graphite powder or carbon nanotubes; for example, the conductive paste may be a conductive gold paste, a conductive silver paste, or a conductive copper paste. By selecting the particle size and solid content of the conductive paste, a high-density first sublayer 1081 with good conductivity can be formed.

[0061] In some embodiments, a conductive paste is uniformly coated on the first surface of the first wafer 102. The conductive material (such as metal powder) in the conductive paste has a particle size of less than 0.3 micrometers and a solid content of more than 80%, which can enable the first sublayer 1081 to form a shielding layer that shields against external electromagnetic noise interference with a thickness of micrometers.

[0062] In some embodiments, the second shielding layer 1083 may be a wire mesh structure or a wall structure.

[0063] In some embodiments, the second shielding layer 1083 can be formed by curing a conductive paste, wherein the particle size of the conductive material (such as metal powder) in the conductive paste can be less than 0.3 micrometers and the solid content can be greater than >80%.

[0064] It should be noted that the materials of the first shielding layer and the second shielding layer can be the same or different. When the materials of the first shielding layer and the second shielding layer are the same, there is no clear boundary between the first shielding layer and the second shielding layer in the shielding structure.

[0065] For example, a second O-shaped shielding layer is formed by casting and curing conductive paste to surround and cover the outer edge of the temperature sensing component. The diameter of the O-shaped second shielding layer ranges from 250 to 300 mm. It should be noted that the diameter of the O-shaped second shielding layer is related to the size of the temperature sensing component. In actual use, the diameter of the O-shaped second shielding layer can be reasonably set according to the size of the temperature sensing component.

[0066] In other embodiments, metal wire can be precision wire-cut into a closed-loop structure that matches the contour of the temperature sensing device. Exemplarily, the metal wire is made of copper or silver, and its diameter ranges from 0.5 to 0.8 mm. In one specific embodiment, the metal wire diameter is 0.6 mm, and the diameter of the O-shaped second shielding layer formed by the metal wire is 298.5 mm, 299 mm, 299.5 mm, or 300 mm.

[0067] It should be noted that, in order to illustrate the positional relationships between the first shielding layer, the second shielding layer 1083, and the various structures in the temperature sensing component, Figure 1The top view shown illustrates the shielding structure 108 in perspective and omits structures such as the first wafer 102 and the FPC board 128.

[0068] Here, the outer edge of the temperature sensing component is the device on the XOY plane that is closest to the wafer (e.g., the first wafer or the second wafer). It can be multiple devices, or it can be the edge of the outermost device that is closest to the wafer side.

[0069] In some implementations, such as Figure 2 As shown, the outer edge of the temperature sensing component is the temperature sensing device 114 that is closest to the wafer side on the XOY plane.

[0070] here, Figure 2 To illustrate the positional relationships between the first wafer 102, the second wafer 104, the shielding structure 108, and the main control and power supply components in the temperature sensing assembly, details are omitted. Figure 1 Other structures in the circuit (e.g., the first interconnect circuit 1261).

[0071] In this embodiment, a temperature sensing component is formed between a first wafer and a second wafer of a semiconductor temperature sensing device, and a shielding structure is constructed around the temperature sensing component. Specifically, the shielding structure consists of an interconnected first shielding layer and a second shielding layer, covering the outer edge of the temperature sensing component and its opposing upper and lower surfaces along a first direction, forming a three-dimensional fully enclosed coverage of the temperature sensing component. This architecture, by constructing an equivalent Faraday cage or quasi-Faraday cage structure, can effectively suppress the coupling interference of external electromagnetic fields on the temperature sensing component, thereby significantly improving the accuracy and signal stability of temperature detection.

[0072] In some embodiments, such as Figure 3 As shown, interconnect circuit 126 is located between first wafer 102 and second wafer 104. Interconnect circuit 126 may include single-layer or multi-layer wiring layers, and wiring layers may include multiple interconnects. The interconnects of adjacent wiring layers may extend in the same, intersecting, or perpendicular directions. Interconnect circuit 126 may include strip interconnect circuits (e.g., first interconnect circuit 1261) and ring interconnect circuits 1262. Interconnect circuit 126 may be carried on a printed circuit board (PCB) or a flexible printed circuit (FPC) 128 (see reference). Figure 2 ).

[0073] Reference Figure 3As shown, the semiconductor temperature measuring device may include a first wafer 102, a temperature measuring component 103, and a second wafer 104 sequentially arranged in a first direction (z-direction). The first wafer 102 and the second wafer 104 serve as carriers or cover plates for the temperature measuring component, providing protection for the temperature measuring component 103 and simulating the temperature distribution of the product wafer. The first wafer 102 and the second wafer 104 are aligned or substantially aligned in the first direction. The temperature measuring component 103 is adapted to the shape of the first wafer 102 and the second wafer 104 and is located between them. The temperature measuring component 103 includes multiple temperature measuring devices 114 distributed in different areas of the first wafer 102 and the second wafer 104 to obtain temperature values ​​in different areas. The temperature measuring devices 114 may include various temperature sensors, which collect temperature signals and convert them into electrical signals for output. The first wafer 102 can serve as the bottom wafer of the semiconductor temperature measuring device, and is used to contact wafer fixing devices such as wafer carrier trays. The temperature measuring component is supported on the first wafer 102, and the second wafer 104 serves as a cover layer to protect the temperature measuring component.

[0074] In some embodiments, the positions of the first wafer 102 and the second wafer 104 can be interchanged.

[0075] here, Figure 3 To illustrate the overall positional relationship of the first wafer 102, the second wafer 104, and the temperature sensing component 103, as well as the specific type of interconnection circuit, other structures (such as the main controller and power supply) are omitted.

[0076] Reference Figure 1 The schematic diagram shown illustrates the layout of the temperature sensing assembly on the XOY plane. The temperature sensing assembly may include at least: a temperature sensing device 114, a power supply 116, a main controller 120, and interconnecting circuitry (e.g., a first interconnecting circuit 1261) coupling the various parts. The interconnecting circuitry may be disposed on a circuit board or a flexible circuit board 128 (see reference). Figure 2 Flexible circuit boards facilitate the flexible layout of leads and components, and are adaptable to various installation spaces.

[0077] The main controller 120 may include various computing units, including but not limited to: a microcontroller unit (MCU). The temperature sensing component 103 may also include an ADC acquisition chip coupled to the temperature sensing device 114, which converts the analog signal from the temperature sensing device 114 into a digital signal and transmits it to the main controller 120. Alternatively, the temperature sensing device 114 may be a digital sensor with analog-to-digital conversion capabilities, which can directly convert analog signals into digital signals and transmit them to the main controller 120.

[0078] This disclosure does not limit the number of layers or wiring on the circuit board, but it may include at least a power supply circuit and a data transmission circuit. The temperature sensing component 103 may include multiple strip-shaped or arc-shaped interconnecting circuits 126 to achieve coupling between different devices, power supply in series or parallel, and communication interconnection in serial or parallel modes. Alternatively, the temperature sensing component 103 may be mounted on a circular PCB board and interconnected through the interconnecting circuits 126 on the PCB board.

[0079] The first wafer 102 and the second wafer 104 can be stacked and fixed using bonding adhesive, hot-temperature adhesive, resin, or other adhesive media, or they can be stacked using thermo-press bonding. During testing, the internal temperature of the first wafer 102 and the second wafer 104 is measured by the temperature measuring device 114. The obtained temperature data is uploaded by the main controller to an external host or the cloud, or stored in the memory device in the temperature measuring component. The power supply can be a battery or a wired power supply connected to an external power source, which powers the main controller and the temperature measuring device.

[0080] The main controller of the semiconductor temperature measuring device can be connected to an external host via a data cable for wired transmission, or the semiconductor temperature measuring device has a wireless transmission module 118, which can be coupled to an antenna to transmit wireless signals to send test data to an external host or cloud server. The power source in the semiconductor temperature measuring device using wireless transmission can be an energy storage device such as a battery; there are no restrictions on the battery type, and it can be a rechargeable lithium-ion battery or other batteries. This eliminates some of the pollution associated with wired temperature measurement and avoids the need for through-holes in the processing chamber, reducing manufacturing difficulty and improving temperature measurement performance.

[0081] In some embodiments, the temperature sensing component may be located between the first wafer and the second wafer, or at least one of the first wafer and the second wafer may have a recess, and the components of the temperature sensing component may be disposed in the recess. For example, a recess may be formed in the first wafer, and the temperature sensing device, power supply, and main control unit of the temperature sensing component may be disposed within the recess of the first wafer. The interconnection circuit of the temperature sensing component may be disposed in the recess, or disposed on the surface of the first wafer without being disposed in the recess; the second wafer may not have a recess, and after being thinned, it may be disposed on the temperature sensing component to cover it. In other embodiments, both the first wafer and the second wafer may have recesses, and the recesses of the first wafer and the second wafer may be aligned in a first direction to form a cavity, and the components of the temperature sensing component may be disposed within the cavity, thereby reducing the thickness of the first wafer and the second wafer and improving the temperature testing accuracy.

[0082] In some embodiments, such as Figure 1 and Figure 2As shown, the semiconductor temperature measuring device further includes: a plurality of conductive pillars 122 located between the first wafer 102 and the second wafer 104, the plurality of conductive pillars 122 being located between the outer edge of the temperature measuring component and the side of the first wafer 102; each of the conductive pillars 122 at least penetrates the second sub-layer 1082 of the first shielding layer and is coupled to the first wafer 102 and the second wafer 104.

[0083] In some embodiments, the plurality of conductive pillars 122 are spaced apart along the circumferential direction of the first wafer 102.

[0084] In some embodiments, a plurality of conductive pillars 122 are distributed circumferentially on the inner side of the edges of the first wafer 102 and the second wafer 104, the conductive pillars 122 are located on the outermost outer side of the temperature measuring component, and the plurality of conductive pillars 122 surround the outer edge of the temperature measuring component.

[0085] In some embodiments, the conductive post 122 may be electrically connected to the first wafer 102 and the second wafer 104 through direct contact, or may be electrically connected to a first sublayer on the surface of the first wafer 102 through contact. For example... Figure 2 As shown, the conductive post 122 penetrates the second sublayer 1082 of the first shielding layer and the top of the conductive post 122 is coupled to the second wafer 104, and the bottom of the conductive post 122 is coupled to the first wafer 102 through the flexible circuit board 128 and the first sublayer 1081.

[0086] For example, the conductive pillar 122 can be formed by coating a conductive paste and then curing it. There is no limitation on the shape of the conductive pillar 122; it can be cylindrical or spherical. The cross-sectional shape of the conductive pillar in the XOY plane can be rectangular, circular, or elliptical, or an irregular arc, polygon, or other irregular shape.

[0087] In other embodiments, Figure 1 and Figure 2 The conductive post 122 shown may extend into the first wafer in a first direction or penetrate the first wafer; the conductive post 122 may extend into the second wafer in the first direction or penetrate the second wafer. In some embodiments, the first surface of the first wafer 102 is coupled to the bottom of the conductive post 122, and the second surface of the second wafer 104 is coupled to the top of the conductive post 122; ion implantation may be performed at the landing site of the conductive post 122 on the first surface of the first wafer to form a first doped region coupled to the conductive post 122, thereby reducing the contact resistance between the first wafer 102 and the conductive post 122; ion implantation may be performed at the landing site of the conductive post 122 on the second surface of the second wafer to form a second doped region coupled to the conductive post 122, thereby reducing the contact resistance between the second wafer 104 and the conductive post 122.

[0088] In some embodiments, Figure 1and Figure 2 The conductive pillars are located at or near the edges of the first wafer 102 and the second wafer 104. The conductive pillars can be placed as close as possible to the sides of the first and second wafers, or located on the sides of the first and second wafers, provided the manufacturing process allows. For example... Figure 1 and Figure 2 As exemplified, the temperature sensing component may include multiple devices and interconnecting circuits, such as a main controller, power supply, voltage regulator and multiple temperature sensing components disposed on the first wafer 102. The outer edge of the temperature sensing component is the device of the temperature sensing component closest to the wafer side on the XOY plane, which may be multiple devices or the edge of the outermost device closest to the wafer side.

[0089] In other embodiments, to facilitate temperature measurement of different areas of the wafer, multiple temperature measuring devices are arranged at intervals along the circumferential direction surrounding the center of the first wafer. Multiple rings of temperature measuring devices 114 are arranged sequentially from the inside to the outside of the first wafer in the radial direction. The outermost ring of temperature measuring devices 114 is the outermost edge of the temperature measuring assembly. The conductive post 122 is located outside the outermost ring of temperature measuring devices 114, that is, the conductive post 122 is located outside all the devices in the temperature measuring assembly.

[0090] In other embodiments, other devices may be disposed on the outer edge of the temperature sensing component, such as a main controller or a voltage regulator, and are not limited to temperature sensing devices.

[0091] In this embodiment of the present disclosure, the conductive pillar is located between the outer edge of the temperature measuring component and the side edge of the first wafer. This allows the conductive pillar to be located outside all the components of the temperature measuring component, so that the peak current, accumulated charge, or plasma of the first wafer and the second wafer flows from the outside of the temperature measuring component or from the edge of the wafer without being conducted through the inside of the temperature measuring component, thereby reducing interference and damage to the various components of the temperature measuring component.

[0092] Reference Figure 1 As shown, multiple conductive pillars 122 are distributed at intervals on the inner side of the first wafer and the second wafer, and along the circumferential direction of the side of the first wafer. When the multiple conductive pillars are connected, they can form a circle, an ellipse, or other irregular polygons or arcs. When the multiple conductive pillars are connected, they can surround the outer edge of the temperature measuring component, surround the outermost part of the temperature measuring component, or in other words, when the multiple conductive pillars are connected, they can surround all the components of the temperature measuring component.

[0093] In some embodiments, the semiconductor temperature measuring device further includes a sealing layer 112, wherein the temperature measuring component is wrapped and fixed in a corresponding groove by the sealing layer 112, and the first sub-layer 1081 and the second sub-layer 1082 of the first shielding layer are separated by the intermediate sealing layer 112.

[0094] In some embodiments, the sealing layer 112 has good electrical insulation, temperature resistance, processability, ductility, and curing temperature. Exemplarily, the sealing layer 112 can be an epoxy resin sealant, and the material of the sealing layer 112 includes, but is not limited to, bisphenol-based materials, silicone resins, or polyurethane adhesives.

[0095] In some embodiments, such as Figure 1 and Figure 2 As shown, the semiconductor temperature measuring device further includes an adhesive layer 106, the adhesive layer 106 including a first portion 1061 located between the plurality of conductive pillars 122 and the second wafer and a second portion 1062 surrounding and covering the second shielding layer; wherein, the second shielding layer 1083 has an inner sidewall and an outer sidewall, the second portion 1062 surrounding and covering the outer sidewall of the second shielding layer 1083, and the inner sidewall of the second shielding layer 1083 covering the outer edge of the temperature measuring component.

[0096] In some embodiments, an adhesive layer 106 is located between the first wafer 102 and the second wafer 104 for bonding and fixing the first wafer 102 and the second wafer 104. The adhesive layer 106 may be a bonding adhesive, a heat-sensitive adhesive, a resin, or other adhesive medium. The adhesive layer 106 may include a curable dielectric material, such as resin.

[0097] In some embodiments, along the first direction, the top surface of the adhesive layer 106 is flush with the top surface of the second shielding layer 1083, for example, as shown in... Figure 2 As shown, the top surface of the first portion 1061 of the adhesive layer 106 along the first direction is flush with the top of the second shielding layer 1083. This coplanar design significantly improves the compatibility of subsequent processes: First, during wafer alignment and bonding, the flat interface facilitates achieving micron-level or even submicron-level alignment accuracy; second, during wafer dovetailing, the uniform support surface reduces the risk of mechanical stress concentration, ensuring the structural integrity of the ultrathin wafer; furthermore, this design provides a reference plane for device setup, aiding in precise device positioning.

[0098] It should be noted that the term "flush" in this article should be understood as flush within the allowable range of process error. For example, if the height difference between the top surface of the adhesive layer and the top surface of the second shielding layer is 0 in the first direction, or if there is a deviation within the allowable range of process error in the height difference between the top surface of the adhesive layer and the top surface of the second shielding layer, the top surface of the adhesive layer and the top surface of the second shielding layer are also considered to be flush.

[0099] In some embodiments, such as Figure 5 As shown, the semiconductor temperature measuring device further includes: a capacitor structure 105, at least partially located between the first sub-layer 1081 and the second sub-layer 1082; as Figure 6As shown, the capacitor structure 105 includes a first electrode 1051, a second electrode 1052, and a dielectric layer 1055, wherein the dielectric layer 1055 is located between the first electrode 1051 and the second electrode 1052; the first electrode 1051 is coupled to the first sub-layer 1081, and the second electrode 1052 is coupled to the second sub-layer 1082.

[0100] It should be noted that, Figure 5 To illustrate the position of the capacitor structure in the semiconductor temperature measuring device, only a portion of the structure in the semiconductor temperature measuring device is shown in the diagram.

[0101] In some embodiments, a capacitor structure 105 is provided between the first wafer 102 and the second wafer 104. The capacitor structure 105 may be part of the temperature sensing component or not. The capacitor structure 105 may be provided near electrical appliances such as temperature sensing devices, power supplies, main controllers, voltage regulators, and wireless transmission modules. It may be arranged symmetrically or asymmetrically, or arranged around the circumferential direction of the electrical appliance, such as near the contacts or pins where the electrical appliance is connected to the interconnection circuit 126, in order to reduce the interference of peak current on the electrical appliance.

[0102] In some embodiments, the capacitor structure 105 may include a first electrode 1051, a second electrode 1052, and a dielectric layer 1055 located between the first electrode 1051 and the second electrode 1052. The capacitor structure 105 may include, but is not limited to, a parallel plate capacitor, a columnar capacitor, or other physical structures. Figure 5 In the capacitor structure, the first electrode is coupled to the first surface of the first wafer, or to the first sublayer 1081 on the first surface; the second electrode is coupled to the second surface of the second wafer, or to the second sublayer 1082 on the second surface, with the first and second surfaces facing each other in the first direction. The first electrode 1051 of the capacitor structure 105 is provided with contact points, pins, and other connection structures to be coupled to the first wafer 102, and the second electrode 1052 of the capacitor structure 105 is provided with contact points, pins, and other connection structures to be coupled to the second wafer 104. The coupling can be a direct contact electrical connection or an electrical connection through other conductive structures.

[0103] When using a semiconductor temperature measuring device for temperature testing, if the first wafer 102 or the second wafer 104 experiences a spike current, the spike current of the first wafer 102 or the second wafer 104 charges the capacitor structure 105. The spike current is absorbed by the capacitor structure 105, reducing interference to the temperature measuring components. For example, when the first wafer 102 is in contact with the wafer carrier disk and the second wafer 104 is exposed to the process cavity, a spike current is generated or plasma accumulates on the second wafer 104 during plasma generation. The spike current flows from the second wafer 104 to the first wafer 102 and is absorbed by the capacitor structure 105, reducing the interference and damage of the spike current to the semiconductor temperature measuring device and the wafer carrier disk.

[0104] In some embodiments, the capacitor structure 105 may include a first electrode 1051, a second electrode 1052, and a dielectric layer 1055 that electrically isolates the two electrodes; the capacitor structure 105 may also include a multilayer electrode capacitor, such as a multilayer ceramic capacitor, wherein the dielectric layer 1055 is a ceramic dielectric material; while realizing the miniaturization of the capacitor structure 105, the carrying voltage or carrying current of the capacitor structure 105 may be increased.

[0105] In some embodiments, refer to Figure 6 As shown, the capacitor structure 105 includes a plurality of alternately arranged first electrodes 1051 and second electrodes 1052; a first connection structure 1053 coupled to the plurality of first electrodes 1051; and a second connection structure 1054 coupled to the plurality of second electrodes 1052. The first connection structure 1053 is coupled to a first sublayer 1081, and the second connection structure 1054 is coupled to a second sublayer 1082. The first electrodes 1051 and second electrodes 1052 can be internal electrodes, and the first connection structure 1053 and second connection structure 1054 can serve as external electrodes for connecting to external structures.

[0106] like Figure 6 As illustrated, the first electrode 1051 and the second electrode 1052 can be rectangular, circular, or elliptical, or irregularly polygonal or arc-shaped. The first electrode 1051 and the second electrode 1052 can be, for example... Figure 6 As shown, extending along the XOY plane, the first electrode and the second electrode partially overlap in the Z direction. The first electrode 1051 and the second electrode 1052 are offset from each other in the electrode extension direction, as shown in... Figure 6The first electrode 1051 and the second electrode 1052 are misaligned in the Z direction, with the first side (left side) of the first electrode 1051 in the X direction not aligned with the first side of the second electrode 1052 in the X direction; or, in other words, the dimensions of the first electrode 1051 and the second electrode 1052 are equal or substantially equal in the X direction, with only partial overlap between the first electrode 1051 and the second electrode 1052. The first connecting structure 1053 is located on one side of the electrode extension direction of the first electrode 1051 and is coupled to a plurality of spaced-apart first electrodes 1051. The second connecting structure 1054 is located on one side of the electrode extension direction of the second electrode 1052 and is coupled to a plurality of spaced-apart second electrodes 1052. The first connecting structure 1053 and the second connecting structure 1054 are arranged opposite each other in the extension direction of the first electrode 1051 and are electrically isolated.

[0107] In some embodiments, refer to Figure 6 As shown, the first electrode 1051 has a first end and a second end disposed opposite to each other in the electrode extension direction. The first end of the first electrode 1051 is coupled to the first connecting structure 1053, and the second end is floating or not connected to electricity. The second electrode 1052 also has a first end and a second end disposed opposite to each other in the electrode extension direction. The first end of the first electrode 1051 is coupled to the second connecting structure 1054, and the second end is floating or not connected to electricity. The first end of the first electrode 1051 and the second end of the second electrode 1052 are not aligned in the perpendicular electrode direction (z-direction), and the second end of the second electrode 1052 is away from the first connecting structure 1053. The first end of the second electrode 1052 and the second end of the first electrode 1051 are not aligned in the z-direction, and the second end of the first electrode 1051 is away from the second connecting structure 1054.

[0108] The first connection structure 1053 is coupled to a first sublayer on the first wafer 102, and the second connection structure 1054 is coupled to a second sublayer on the second wafer 104, thereby achieving coupling and conduction between the capacitor structure 105 and the first wafer 102 and the second wafer 104. This disclosure embodiment does not limit the connection method of the first connection structure 1053 and the second connection structure 1054; for example, the first wafer 102 can be... Figure 6 Below the capacitor structure 105, the second wafer 104 can... Figure 6 Above the capacitor structure 105, the bottom of the first connection structure 1053 is in contact with the first sublayer 1081, and the top of the first connection structure 1053 is electrically isolated from the second sublayer 1082 without contact; the top of the second connection structure 1054 is in contact with the second sublayer 1082, and the bottom of the second connection structure 1054 is electrically isolated from the first sublayer 1081 without contact.

[0109] In some embodiments, a first sublayer or a second sublayer may be disposed on either the first wafer 102 or the second wafer 104, or a first sublayer and a second sublayer may be disposed on each of the two wafers respectively. (Refer to...) Figure 7 As shown, it can be Figure 6 The capacitor structure 105 shown is rotated and positioned between the first sub-layer 1081 and the second sub-layer 1082.

[0110] like Figure 8 As exemplified, a first sublayer 1081 is formed on the surface of the first wafer 102, extending to the inner wall of the first recess 1201. A capacitor structure 105 is coupled to the first sublayer 1081 and the second wafer 104. In other examples, referring to the arrangement of the first sublayer 1081 in the first recess 1201, a second sublayer 1082 is formed on the surface of the second wafer 104, extending to the inner wall of the second recess 1202. The capacitor structure 105 is coupled to the second sublayer 1082 and the second wafer 104.

[0111] In some embodiments, it is possible to Figure 8 A second sublayer 1082 is further disposed on the surface of the second wafer 104, and the capacitor structure 105 is coupled to the first sublayer and the second sublayer. The first wafer 102, the first sublayer 1081, the first connection structure 1053, the second connection structure 1054, the second sublayer 1082, and the second wafer 104 are stacked in the Z direction. The first connection structure 1053 is in contact with the first sublayer 1081, and the second connection structure 1054 is in contact with the second sublayer 1082. This reduces the lead distance of the capacitor structure and facilitates the reduction of the thickness of the semiconductor temperature measuring device.

[0112] In some embodiments, at least one of the first wafer 102 and the second wafer 104 has a groove for accommodating at least a portion of the temperature sensing component; the first sublayer extends into the inner wall of the groove; the capacitor structure is located in the corresponding groove, and the first electrode is coupled to the first sublayer on the inner wall of the groove.

[0113] In some embodiments, a groove can be formed in either the first wafer 102 or the second wafer 104, and the depth of the groove can be greater than or equal to the thickness of the corresponding temperature sensing component. The other wafer, after being thinned to serve as a capping layer, may not have a groove formed. Figure 8 As shown, a first groove 1201 is formed in the first wafer 102 to accommodate the temperature measuring component, and the second wafer 104 is thinned to serve as a cover layer to cover the temperature measuring component and the first wafer 102.

[0114] In some embodiments, such as Figure 8As shown, the first wafer 102 has a first groove 1201, and the second wafer 104 has a second groove 1202. The first groove 1201 and the second groove 1202 are aligned to form a cavity, and at least a portion of the temperature measuring component is located in the cavity.

[0115] In some embodiments, refer to Figure 8 As shown, grooves are provided in both the first wafer 102 and the second wafer 104, and the depth of the grooves is less than the device thickness of the temperature sensing component 103. The grooves of the first wafer 102 and the second wafer 104 are aligned. A portion of the temperature sensing component is located in the groove of the first wafer 102, and another portion is located in the groove of the second wafer 104, thereby reducing the thickness of the first wafer 102 and the second wafer 104. For example, taking a temperature sensing device as an example, the bottom of a temperature sensing device is located in the first groove 1201 of the first wafer 102, and the upper part of the temperature sensing device is located in the second groove 1202 of the second wafer 104. The first groove 1201 and the second groove 1202 are aligned in the Z direction. A portion of the interconnect circuit 126 connecting the temperature sensing device is disposed within the first recess 1201, specifically extending along the sidewall and bottom of the first recess 1201. The contacts at the bottom of the temperature sensing device are coupled to the interconnect circuit 126 at the bottom of the first recess 1201. This portion of the interconnect circuit 126 extends from the bottom of the first recess 1201 along the sidewall and is coupled to other devices within the first recess 1201, such as the main controller 120, the power supply 116, or a voltage regulator. The first wafer 102 and the second wafer 104 may have corresponding recesses to accommodate the interconnect circuit 126, or some portions of the interconnect circuit 126 may be disposed on the surface of the first wafer 102, with another portion located within the first recess 1201 of the first wafer 102 to couple to the corresponding devices.

[0116] In some embodiments, Figure 8 The capacitor structure 105 shown can be disposed in the cavity formed by the first groove 1201 and the second groove 1202. The first connection structure 1053 of the capacitor structure 105 can be directly coupled to the first wafer 102, or a contact can be provided on the first connection structure 1053 to be coupled to the first wafer 102. The second connection structure 1054 can be directly coupled to the second wafer 104, or a contact can be provided on the second connection structure 1054 to be coupled to the second wafer 104.

[0117] Taking the first wafer 102 as an example, a first groove 1201 can be formed in the first wafer 102. A first sub-layer 1081 extends on the first surface of the first wafer 102 and extends to the sidewalls and bottom of the first groove 1201 below the first surface. A capacitor structure 105 is disposed in the first groove 1201. A first electrode 1051 or a first connection structure 1053 is coupled to the first sub-layer 1081 at the bottom of the first groove 1201. The second wafer 104 may not have a groove. A second sub-layer 1082 extends on the second surface of the second wafer 104. After the second wafer 104 is thinned, it covers the temperature sensing component. The second sub-layer 1082 is coupled to the second electrode 1052 or the second connection structure 1054.

[0118] In some embodiments, the second wafer 104 may be provided with a second groove 1202, a second sub-layer 1082 extends on a second surface of the second wafer 104 and extends on the sidewall and bottom of the second groove 1202, a capacitor structure 105 is disposed in the cavity formed by aligning the first groove 1201 and the second groove 1202, and a second electrode 1052 or a second connection structure 1054 is coupled to the second sub-layer 1082 at the bottom of the second groove 1202.

[0119] In some embodiments, the first sublayer 1081 extends into the inner wall of the first groove 1201, and the second sublayer 1082 extends into the inner wall of the second groove 1202. The temperature sensing device 114 or main control device 120 of the temperature sensing component may be located within the first groove 1201. The interconnect circuit 126 or a circuit board including the interconnect circuit 126 is located on the first sublayer 1081 within the first groove 1201. The contacts of the temperature sensing device 114 or main control device 120 are coupled to the interconnect circuit 126, and a fixed connection between the contacts or pins and the interconnect circuit 126 can be achieved through soldering. The circuit board carrying the interconnect circuit 126 may be a flexible circuit board with a strip, arc, or other irregular shape adapted to the wafer groove and lead layout; the shape of the circuit board is not limited.

[0120] In some embodiments, such as Figure 1 As shown, the semiconductor temperature measuring device further includes: an antenna 124 coupled to the main controller 120; the antenna 124 is located at the center of the first wafer 102 and the second wafer 104; a plurality of temperature measuring devices 114 are arranged in the circumferential direction around the antenna; and at least a portion of the interconnect circuits 126 coupled to the temperature measuring devices are arranged at intervals along the circumferential direction of the antenna.

[0121] In some implementations, such as Figure 1 , Figure 2 and Figure 9As shown, the temperature measurement component also includes a wireless transmission module 118 coupled to the main controller. The wireless transmission module 118 may include, but is not limited to, a Bluetooth module, a Wi-Fi module, a ZigBee module, etc. The wireless transmission module 118 can be coupled to an antenna to transmit wireless signals. The antenna 124 is a ring coil located at the center of the first wafer 102 and the second wafer 104, and may include multiple nested coils, such as, but not limited to, RF coils. Multiple temperature measurement devices 114 may also be disposed within the internal area of ​​the antenna 124. In other embodiments, the antenna 124 may be located near the center of the first wafer 102 and the second wafer 104, including a horizontally positioned antenna 124.

[0122] In some embodiments, by setting the operating frequency band of the antenna to be different from the main shielding frequency band of the shielding structure, the antenna's operating frequency band is ensured while allowing the antenna's performance in a specific frequency band to remain unaffected.

[0123] In some embodiments, such as Figure 1 , Figure 3 and Figure 9 As shown, the interconnect circuit 126 has multiple components, including a ring-shaped or near-ring-shaped portion and a strip-shaped portion. For example, multiple first interconnect circuits 1261 are spaced apart along the circumferential direction of the outer periphery of the antenna 124. Multiple temperature sensing devices 114 are radially connected to the first interconnect circuits 1261 along the first wafer 102. The temperature sensing devices 114 are arranged along the extension direction of the first interconnect circuits 1261 and coupled to them. The included angle between any two adjacent first interconnect circuits 1261 can be equal, allowing for a more uniform distribution of the temperature sensing devices in different areas within the wafer, enabling temperature detection in different areas of the wafer.

[0124] In some embodiments, multiple temperature measuring devices 114 are arranged in a circular pattern around the antenna 124, which can be multiple rings of temperature measuring devices arranged sequentially from the inside to the outside with the antenna 124 as the center.

[0125] In some embodiments, refer to Figure 9 As shown, the temperature sensing component 103 further includes: a voltage regulator 117 coupled to the interconnection circuit 126; capacitor structures 105 symmetrically distributed outside the electrical components of the temperature sensing component 103; and / or, the capacitor structures 105 are spaced apart around the circumferential direction of the electrical components; wherein, the electrical components of the temperature sensing component 103 include at least one of the following: a temperature sensing device 114, a power supply 116, a main controller 120, and a voltage regulator 117. The input terminal of the voltage regulator 117 is coupled to the power supply 116, and the output terminal of the voltage regulator 117 is coupled to the main controller 120, the temperature sensing device 114, the wireless transmission module, and other electrical components for power supply. Multiple voltage regulators 117 may be included to provide separate power supply for different branches in parallel. The voltage regulator 117 is connected to the power supply 116 and outputs a relatively stable power supply.

[0126] In some embodiments, a voltage regulator 117 supplies power to multiple temperature sensing devices 114, which can constitute a temperature sensing circuit 119 or at least a portion of a temperature sensing circuit 119; the multiple temperature sensing devices 114 can be divided into multiple temperature sensing circuits 119, and each circuit can be powered by a separate voltage regulator 117 to improve power supply stability. For example, the multiple temperature sensing devices 114 can be powered by... Figure 9 The dashed line divides the area into multiple sector-shaped regions, each equipped with a voltage regulator 117 to power multiple temperature measuring devices 114 within the sector-shaped region. Figure 9 The division of the power supply area for the temperature sensing device 114, as well as the setting and number of voltage regulators 117, are merely examples and do not limit other division methods or the number and arrangement of voltage regulators 117. For example, voltage regulators 117a, 117b, 117c, and 117d supply power to the temperature sensing devices 114 in four sector areas, respectively; voltage regulator 117e supplies power to the main controller 120. A voltage regulator, such as voltage regulator 117b, supplying power to multiple temperature sensing devices 114 can constitute a temperature sensing circuit 119 or at least a part of a temperature sensing circuit 119. Multiple temperature sensing devices 114 belonging to a temperature sensing circuit 119 can... Figure 9 The fan-shaped region distribution is shown.

[0127] Reference Figure 9 As shown, the interconnect circuit 126 of the temperature sensing circuit 119 may include a plurality of first interconnect circuits 1261 spaced apart in the circumferential direction along the outer periphery of the antenna 124, the plurality of first interconnect circuits 1261 being radially spaced along the first wafer 102, and including a plurality of branches such as second interconnect circuits 1263 on the first interconnect circuits 1261, the second interconnect circuits 1263 intersecting or perpendicular to the first interconnect circuits 1261; the plurality of second interconnect circuits 1263 located on the same first interconnect circuit 1261 have different lengths, and from the center of the first wafer 102 outwards, the size of the second interconnect circuits 1263 gradually increases to meet the electrical interconnection requirements of the temperature sensing device 114 being uniformly distributed radially. The interconnect circuit 126 may include a power supply circuit and a data transmission circuit.

[0128] It should be noted that, Figure 1 , Figure 3 as well as Figure 9 The document illustrates different structural examples of interconnect circuits. In practical applications, the specific structure of the interconnect circuit can be set according to requirements to achieve coupling between various structures in a semiconductor temperature measuring device.

[0129] The electrical appliance in this embodiment can be any device other than the interconnecting circuit 126. The voltage regulator 117 can include, but is not limited to, a low dropout regulator (LDO). The input terminal of the voltage regulator 117 is coupled to the output terminal of the power supply 116, and the output terminal of the voltage regulator 117 is coupled to electrical appliances such as the main controller 120 and the temperature measuring device 114. The voltage regulator 117 can filter power supply noise, regulate voltage output, and provide a stable power supply voltage.

[0130] The arrangement and quantity of capacitor structure 105 can be set according to the interference tolerance and withstand level of the electrical appliance. Capacitor structure 105 needs to be placed near appliances with high power supply stability. Taking the main controller 120 as an example, the main controller 120 operates by default in a circuit environment with a stable voltage supply. Its input voltage window is narrow. If a surge current occurs, it may cause the entire semiconductor temperature measuring device to shut down, or even cause irreversible damage to the main controller 120. A surge current in the voltage regulator 117 may cause breakdown of the electrical appliance, resulting in irreversible damage. Figure 9 As shown, a capacitor structure 105 can be set near the pins or contacts of electrical appliances such as the main controller 120 and the voltage regulator 117.

[0131] In some embodiments, refer to Figure 10 As shown, capacitor structures 105 can be symmetrically arranged near the pins or contacts of electrical appliances such as the main controller 120 and voltage regulator. There can be two, three, four, or more capacitor structures 105. Multiple capacitor structures 105 can be arranged at intervals around the circumference of the electrical appliance, and can be symmetrically or asymmetrically distributed, such as four capacitor structures 105. The four capacitor structures 105 can form a rectangle or other quadrilateral to enhance the absorption of peak currents and improve the anti-interference performance of the electrical appliance.

[0132] In some embodiments, the first temperature measuring device among the plurality of temperature measuring devices 114 is located at the outer edge of the temperature measuring assembly; the conductive post 122 is located on the side of the first temperature measuring device away from the antenna 124. (Refer to...) Figure 1 As shown, multiple temperature measuring devices 114 are arranged at intervals around the center of the first wafer 102 or around the antenna 124 at the center of the first wafer 102. Multiple layers or multiple rings of temperature measuring devices are provided. The outermost device of the temperature measuring assembly is a ring of temperature measuring devices. For example, multiple first temperature measuring devices are arranged at intervals along the circumferential direction around the antenna. The conductive post 122 is located on the side of the first temperature measuring device away from the antenna 124 in the X or Y direction.

[0133] In some implementations... Figure 10As shown, the conductive post 122 is located outside the outermost first temperature measuring device, and all temperature measuring devices 114 are located between the conductive post 122 and the antenna. Alternatively, multiple conductive posts 122 are arranged around the outermost first temperature measuring device, spaced apart along the circumferential direction outside the outermost first temperature measuring device.

[0134] In some embodiments, the conductive post 122 is located between adjacent first interconnect circuits 1261.

[0135] In some implementations... Figure 10 As shown, the outermost device in the temperature sensing assembly, furthest from the antenna or the first wafer, is the temperature sensing device 114. Conductive pillars 122 surround the outermost temperature sensing device 114, located between the wafer side and the outermost temperature sensing device 114. This allows peak currents, accumulated charges, or plasma from the wafer to flow through the outside of the wafer without being conducted through the inside of the temperature sensing assembly, reducing interference and damage to the various devices within the assembly. Multiple interconnect circuits divide the first wafer into multiple temperature sensing zones. One or more conductive pillars 122 are located between adjacent interconnect circuits (e.g., the first interconnect circuit 1261). All conductive pillars 122 are uniformly distributed along the edge of the first wafer 102, with equal or substantially equal spacing between adjacent conductive pillars 122. Exemplarily, peak currents can be transmitted through the second wafer, the second sublayer, the conductive pillars, the first sublayer, and the first wafer to the ground terminal of the wafer carrier disk, or transmitted to a capacitor structure where they are absorbed.

[0136] This disclosure also provides a method for manufacturing a semiconductor temperature measuring device. Figure 11 This is a schematic flowchart illustrating a method for manufacturing a semiconductor temperature measuring device according to an embodiment of this disclosure. Figure 11 As shown, the manufacturing method of the semiconductor temperature measuring device provided in this embodiment includes the following steps:

[0137] Step S10: Provide the first wafer;

[0138] Step S20: Form a temperature sensing component on the first side of the first wafer; the temperature sensing component includes interconnect circuits, temperature sensing devices coupled through the interconnect circuits, a power supply, and a main controller;

[0139] Step S30: Form a shielding structure that covers the temperature measuring component;

[0140] Step S40: Provide a second wafer and bond the second wafer to the first side of the first wafer.

[0141] In some embodiments, forming the shielding structure includes:

[0142] A first shielding layer and a second shielding layer connected to the first shielding layer are formed;

[0143] The first and second sub-layers of the first shielding layer respectively cover the first and second surfaces of the temperature measuring component along the stacking direction parallel to the first and second wafers; the second shielding layer surrounds and covers the outer edge of the temperature measuring component.

[0144] Combination Figure 1 and Figure 8 The manufacturing process of a semiconductor temperature measuring device is described, and the manufacturing method of the semiconductor temperature measuring device includes:

[0145] A first wafer 102 is provided, and a plurality of first grooves 1201 are formed on a first surface of the first wafer 102;

[0146] A first sublayer 1081 is formed on the first surface of the first wafer 102, and the first sublayer 1081 extends into the sidewall and bottom of the first groove 1201;

[0147] Align the temperature measuring component with the first groove 1201, and place each component of the temperature measuring component in the corresponding first groove 1201;

[0148] A sealing layer 112 is formed on the first surface of the first wafer 102, and the sealing layer 112 can be filled into the first groove 1201;

[0149] A second shielding layer 1083 is formed to surround and cover the outer edge of the temperature measuring component;

[0150] A second wafer 104 is provided, and a plurality of second grooves 1202 are formed on the second surface of the second wafer 104 corresponding to the distribution position of the first grooves 1201 on the first wafer 102.

[0151] A second sublayer 1082 is formed on the second surface of the second wafer 104, and the second sublayer 1082 extends into the sidewall and bottom of the second groove 1202;

[0152] The second wafer 104 is aligned with the first wafer 102, and the second wafer 104 is bonded to the first wafer 102, so that the second groove 1202 is aligned with the first groove 1201. The first sub-layer 1081, the second sub-layer 1082, and the second shielding layer 1083 constitute a shielding structure.

[0153] In some embodiments, the methods for forming the first groove 1201 and the second groove 1202 may include, but are not limited to, dry etching, wet etching, or a combination thereof. Taking the fabrication method of the first sublayer 1081 as an example, a conductive paste is uniformly coated on the surface of the first wafer 102 having the first groove 1201, and the first sublayer 1081 is formed after the conductive paste is cured. Alternatively, the first sublayer 1081 can be formed by physical or chemical deposition, sputtering, or electroplating on the surface of the first wafer 102 having the first groove 1201.

[0154] It should be understood that the phrases "some embodiments," "one embodiment," or "an embodiment" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0155] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0156] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor temperature measuring device, characterized in that, include: A first wafer and a second wafer stacked along a first direction; A temperature sensing component is located between the first wafer and the second wafer; The temperature measuring component includes an interconnecting circuit, a temperature measuring device coupled through the interconnecting circuit, a power supply, and a main controller; A shielding structure, located between the first wafer and the second wafer and covering the temperature sensing component, is used to suppress the coupling interference of external electromagnetic fields to the temperature sensing component. The shielding structure includes a first shielding layer, and a first sublayer and a second sublayer of the first shielding layer respectively cover the first surface and the second surface of the temperature sensing component that are opposite to each other along the first direction. A capacitor structure, at least partially located between the first sub-layer and the second sub-layer; the capacitor structure includes a first electrode, a second electrode, and a dielectric layer, the dielectric layer being located between the first electrode and the second electrode; The first electrode is coupled to the first sublayer, and the second electrode is coupled to the second sublayer; the capacitor structure is used to absorb the peak current borne by the first wafer or the second wafer.

2. The semiconductor temperature measuring device according to claim 1, characterized in that, The shielding structure also includes: A second shielding layer connected to the first shielding layer surrounds and covers the outer edge of the temperature measuring component.

3. The semiconductor temperature measuring device according to claim 2, characterized in that, The semiconductor temperature measuring device also includes: Multiple conductive pillars are located between the first wafer and the second wafer, and the multiple conductive pillars are located between the outer edge of the temperature sensing component and the side of the first wafer; each of the conductive pillars penetrates at least the second sublayer of the first shielding layer and is coupled to the first wafer and the second wafer.

4. The semiconductor temperature measuring device according to claim 3, characterized in that, The plurality of conductive pillars are spaced apart along the circumference of the first wafer.

5. The semiconductor temperature measuring device according to claim 3, characterized in that, The semiconductor temperature measuring device also includes: An adhesive layer comprising a first portion located between the plurality of conductive pillars and the second wafer, and a second portion surrounding and covering the second shielding layer; wherein the second shielding layer has an inner sidewall and an outer sidewall, the second portion surrounding and covering the outer sidewall of the second shielding layer, and the inner sidewall of the second shielding layer covering the outer edge of the temperature sensing component.

6. The semiconductor temperature measuring device according to claim 1, characterized in that, At least one of the first wafer and the second wafer has a groove for accommodating at least a portion of the temperature sensing component; The first sublayer extends into the inner wall of the groove; the capacitor structure is located in the corresponding groove, and the first electrode is coupled to the first sublayer on the inner wall of the groove.

7. The semiconductor temperature measuring device according to claim 1, characterized in that, The semiconductor temperature measuring device also includes: An antenna, which is coupled to the main controller; the antenna is located at the center of the first wafer and the second wafer; Multiple temperature measuring devices are arranged in a circumferential direction around the antenna; at least a portion of the interconnect circuitry coupled to the temperature measuring devices is arranged at intervals along the circumferential direction of the antenna.

8. A method for manufacturing a semiconductor temperature measuring device, used to manufacture the semiconductor temperature measuring device as described in any one of claims 1-7, characterized in that, The manufacturing method includes: Provide the first wafer; A temperature sensing component is formed on a first surface of the first wafer; the temperature sensing component includes an interconnect circuit, a temperature sensing device coupled through the interconnect circuit, a power supply, and a main controller; A shielding structure is formed, which covers the temperature measuring component; A second wafer is provided and bonded to a first side of the first wafer.

9. The manufacturing method according to claim 8, characterized in that, The formation of the shielding structure includes: A first shielding layer and a second shielding layer connected to the first shielding layer are formed; The first and second sub-layers of the first shielding layer respectively cover the first and second surfaces of the temperature measuring component along the stacking direction parallel to the first and second wafers; the second shielding layer surrounds and covers the outer edge of the temperature measuring component.

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