Semiconductor temperature measuring device

Abstract

The embodiment of the present disclosure discloses a semiconductor temperature measuring device, comprising: a first wafer and a second wafer which are stacked; a temperature measuring assembly which is at least partially located between the first wafer and the second wafer; the temperature measuring assembly comprises a power supply, a master control and a plurality of temperature measuring circuits which are coupled through an interconnection circuit; each temperature measuring circuit comprises: a voltage stabilizer; a plurality of temperature measuring devices which are coupled with the voltage stabilizer; the voltage stabilizer of each temperature measuring circuit is coupled with the power supply.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor temperature measuring device. Background Technology

[0002] Some temperature measurement devices are used to record temperature information of wafers during the manufacturing process. This temperature information can be analyzed to adjust equipment parameters and processes. Wired wafer temperature measurement devices embed or attach temperature sensors to the wafer surface and transmit signals via wires. While these devices are simple in structure, they have several drawbacks, such as introducing contamination, disrupting the temperature field on the wafer surface with the wires, and obstructing temperature measurement. Wireless transmission methods are susceptible to various electrical interferences from high-voltage DC and multi-frequency radio waves. Therefore, there is still considerable room for improvement in some wafer inspection devices. Summary of the Invention

[0003] According to some aspects of embodiments of this disclosure, a semiconductor temperature measuring device is provided, comprising: a first wafer and a second wafer stacked together; a temperature measuring component, at least partially located between the first wafer and the second wafer; the temperature measuring component including a power supply, a main control unit, and a plurality of temperature measuring circuits coupled through interconnect circuits; each of the temperature measuring circuits including: a voltage regulator; a plurality of temperature measuring devices coupled to the voltage regulator; and the voltage regulator of each of the temperature measuring circuits coupled to the power supply.

[0004] This disclosure provides a semiconductor temperature measuring device that can be used to simulate the temperature distribution of a wafer during a process and measure temperature values. The semiconductor temperature measuring device includes a first wafer and a second wafer stacked together, and a temperature measuring component located at least partially between the first wafer and the second wafer. The temperature measuring component may include a power supply, a main control unit, and multiple temperature measuring circuits coupled through interconnect circuits. Each temperature measuring circuit includes a voltage regulator and multiple temperature measuring devices coupled to the voltage regulator. The voltage regulators of the multiple temperature measuring circuits are coupled to the power supply. The voltage regulators in each temperature measuring circuit are connected in parallel to the power supply, and the voltage input from the power supply is denoised, modulated, boosted, or bucked to output the operating voltage required by the temperature measuring devices to power the multiple temperature measuring devices belonging to the temperature measuring circuit. This achieves parallel power supply of multiple temperature measuring circuits to improve power supply stability, reduce crosstalk between different power supply parts, and reduce the risk of failure caused by excessive internal peak current. Attached Figure Description

[0005] Figure 1 This is a schematic diagram of a semiconductor temperature measuring device according to an exemplary embodiment;

[0006] Figure 2 and Figure 3 This is a schematic diagram of a semiconductor temperature measuring device according to an embodiment of the present disclosure;

[0007] Figures 4 to 6 This is a schematic diagram of a voltage regulator power supply according to an embodiment of the present disclosure;

[0008] Figure 7 and Figure 8 This is a schematic diagram of interconnect circuit wiring according to an embodiment of the present disclosure;

[0009] Figures 9 to 13 This is a schematic diagram of other semiconductor temperature measuring devices according to embodiments of this disclosure. Detailed Implementation

[0010] Exemplary embodiments disclosed herein will now be described in more detail with reference to the accompanying drawings. It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers.

[0011] It should be understood that references to "some embodiments" or "an embodiment" throughout the specification mean that a particular feature, structure, or characteristic relating to an embodiment is included in at least one embodiment of this disclosure. Furthermore, these particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0012] In some etching, vapor deposition, or epitaxial wafer systems, wafers are transferred into the process chamber and fixed on wafer carriers, which can be held by electrostatic adsorption, vacuum adsorption, or mechanical grippers. Temperature control components on the wafer carriers heat or cool the wafer to provide and maintain the process temperature, improving process yield. Uneven temperature distribution on the wafer causes uneven etching or deposition rates in different areas. Detecting or measuring the temperature in different areas of the wafer allows for adjustment of process parameters to meet process requirements.

[0013] In some embodiments, to accurately simulate and measure the temperature distribution in different regions of a wafer, a semiconductor temperature measuring device is provided. The device has the same shape and size as the product wafer, or is based on the wafer and includes temperature measuring components including, but not limited to, temperature measuring devices. The semiconductor temperature measuring device or the temperature measuring wafer is transferred to the wafer carrier disk in the process cavity for adsorption. After the process is started, the test signals of the temperature measuring devices distributed in different positions of the semiconductor temperature measuring device are obtained, thereby simulating the temperature distribution of the product wafer and performing in-situ testing.

[0014] In some embodiments, the test signal for the semiconductor temperature measuring device or the temperature-measuring wafer can be transmitted via wired or wireless transmission. For example, the test signal characterizing the temperature value is transmitted to the device's main controller, which then transmits it via a transmission line to an external host or processing unit for data processing. Alternatively, the main controller can transmit signals via an antenna through a wireless transmission module, such as a Bluetooth module or a Wi-Fi module, and the signals can be received by the external host for data processing. In some embodiments, the semiconductor temperature measuring device may be equipped with a memory device, such as a non-volatile memory device like a flash memory card, SSD, or hard disk, to store test data. After the test is completed, the semiconductor temperature measuring device is removed from the process chamber, and the memory device is read to retrieve the test data.

[0015] In the power supply network of some semiconductor temperature measuring devices, the power supply, after passing through a voltage regulator, outputs voltage to power electrical appliances. This may include, but is not limited to, powering multiple temperature measuring devices (e.g., 48 / 81 or 99 temperature measuring devices), the main control unit, and wireless transmission modules. The supply voltage is DC 0–5V, for example, 3.2V (DC). Taking some process equipment with plasma environments as an example, such as… Figure 1 The plasma etching machine or plasma-enhanced vapor deposition machine (PCVD machine) shown has a plasma generator or plasma deflector inside the process chamber, and is equipped with high-voltage DC and multi-frequency RF power supplies, which can cause significant interference to semiconductor temperature measuring devices used for temperature testing. In the semiconductor temperature measuring device 10... Figure 1 The wafer carrier disk 200 adsorbs the plasma, and the plasma generator 300 generates plasma for the testing process. The resulting spike current causes electromagnetic interference to the power supply circuit and crosstalk to the communication circuit, leading to problems such as power supply voltage fluctuations, current noise, and even device breakdown, thus reducing the stability of power supply and communication.

[0016] In view of this, embodiments of the present disclosure divide multiple temperature measuring devices into multiple parts and configure a voltage regulator to power each power supply part. For example, all temperature measuring devices are divided into multiple parts, and each part of the temperature measuring devices is coupled to a voltage regulator to form a temperature measuring circuit; in a temperature measuring circuit, the voltage output by the voltage regulator powers the multiple temperature measuring devices belonging to that temperature measuring circuit. The voltage regulators belonging to each temperature measuring circuit are connected in parallel to a power supply (or, the output terminal of the power supply), and the power supply provides independent power to multiple temperature measuring circuits, improving power supply stability and reducing the interference of peak current on the power supply. In other embodiments, a capacitor structure can be provided in the semiconductor temperature measuring device to store charge or absorb peak current, reducing the interference of peak current; or a conductive pillar can be provided in the semiconductor temperature measuring device to transmit the peak current, thereby reducing interference.

[0017] In the accompanying drawings of this disclosure, the first direction can be the thickness direction of the wafer or a vertical direction. The x and y directions can be horizontal directions, intersecting or perpendicular to each other, and the z direction intersects or is perpendicular to the plane formed by the x and y directions, such as the xoy plane; the x and y directions can also be referred to as the second or third direction.

[0018] According to some aspects of embodiments of this disclosure, Figure 2 and Figure 3 A semiconductor temperature measuring device 10 is provided, comprising: Figure 2 As shown, a first wafer 101 and a second wafer 102 are stacked along a first direction (z-direction); a temperature sensing component 110 is at least partially located between the first wafer 101 and the second wafer 102; as shown Figure 3 As shown, the temperature sensing assembly 110 includes a power supply 113, a main controller 114, and multiple temperature sensing circuits 119 coupled via an interconnecting circuit 112. Each temperature sensing circuit 119 includes: a voltage regulator 116; multiple temperature sensing devices 111 coupled to the voltage regulator 116; and the voltage regulator 116 of each temperature sensing circuit 119 is coupled to the power supply 113. This disclosure embodiment... Figure 3 The division and number of temperature sensing circuits 119 are not limited. Each temperature sensing circuit 119 can be configured with a voltage regulator 116 for independent power supply to improve power supply stability. A temperature sensing circuit 119 includes multiple temperature sensing devices 111, and at least one voltage regulator 116 can be configured to power its multiple temperature sensing devices 111 to reduce crosstalk. The multiple voltage regulators 116 included in the multiple temperature sensing circuits 119 are connected in parallel to the power supply 113 for independent power supply.

[0019] In some embodiments, in a temperature sensing circuit 119, multiple temperature sensing devices 111 can be connected in series or in parallel with the output terminal of a voltage regulator 116; the input terminal of the voltage regulator 116 of each temperature sensing circuit 119 can be connected in parallel with the output terminal of a power supply 113. The power supply 113 can be a battery or a wired power supply connected to an external power source, and the power supply 113 supplies power to electrical appliances such as the main controller 114, voltage regulator 116, and temperature sensing devices 111. When the power supply 113 is an energy storage device such as a battery, the voltage regulators 116 of multiple temperature sensing circuits 119 are connected in parallel to the positive terminal of the battery.

[0020] In the temperature sensing component 110, the power supply line or power supply network and communication network are interconnected through the interconnection circuit 112. A part of the interconnection circuit 112 serves as a power supply line to enable the power supply 113 to supply power to various electrical appliances. The power supply connection method includes series or parallel connection and there is no restriction on this. A part of the interconnection circuit 112 serves as a data and control signal transmission path to realize communication interconnection between the main controller 114, the temperature sensing device 111, the wireless transmission module or the digital-to-analog converter (ADC converter).

[0021] In some embodiments, the interconnect circuit 112 may include a single layer or multiple layers of wiring layers, and each wiring layer may include multiple interconnects. The interconnects of adjacent wiring layers may extend in the same direction, intersect, or be perpendicular. The interconnect circuit 112 or the interconnects may include... Figure 2 The diagram shows a strip interconnect circuit 112 (first interconnect circuit 1121) and a ring interconnect circuit 1122; the interconnect circuit 112 can be mounted on a circuit board (PCB) or a flexible circuit board (flexible PCB). Figure 3 In the first interconnect circuit 1121, the first interconnect circuit 1121 extends radially along the first wafer 101. The interconnect circuit 112 may also include multiple branches connected to the first interconnect circuit 1121, such as the second interconnect circuit 1123. The second interconnect circuit 1123 may be a strip circuit, which is distributed radially at intervals on the first interconnect circuit 1121 along the first wafer 101. The second interconnect circuit 1123 intersects or is perpendicular to the first interconnect circuit 1121 to meet the wiring requirements of multiple temperature measuring devices 111 being distributed more evenly in a circular pattern on the first wafer 101.

[0022] In some embodiments, refer to Figure 2 As shown, the semiconductor temperature measuring device 10 may include a first wafer 101, a temperature measuring component 110, and a second wafer 102 arranged sequentially in the z-direction. The first wafer 101 and the second wafer 102 serve as a carrier or cover for the temperature measuring component 110, providing protection for the component and simulating the temperature distribution of the product wafer. The first wafer 101 and the second wafer 102 are aligned or substantially aligned in the z-direction. The temperature measuring component 110 is adapted to the shape of the first wafer 101 and the second wafer 102 and is positioned between them. The temperature measuring component 110 includes multiple temperature measuring devices 111 distributed in different areas of the first wafer 101 and the second wafer 102 to obtain temperature values ​​in different areas. The temperature measuring devices 111 may include various temperature sensors, which collect temperature signals and convert them into electrical signals for output. The first wafer 101 can serve as the bottom wafer of the semiconductor temperature measuring device 10, for contacting wafer fixing devices such as wafer carrier trays. The temperature measuring component 110 is supported on the first wafer 101, and the second wafer 102 serves as a cover layer to protect the temperature measuring component 110. Alternatively, the positions of the first wafer 101 and the second wafer 102 can be interchanged.

[0023] Reference Figure 3The illustrated layout of the temperature sensing component 110 on the xoy plane or relative to the first wafer 101 shows that the temperature sensing component 110 may include at least: a temperature sensing device 111, a power supply 113, a main controller 114, and interconnecting circuits 112 or interconnecting lines coupling the various parts. The interconnecting circuits 112 may be disposed on a circuit board (PCB) or a flexible circuit board (flexible PCB). Flexible circuit boards facilitate flexible layout of leads and devices, adapting to various installation spaces. The main controller 114 may include various computing units or processors, including but not limited to: a microcontroller unit (MCU). The temperature sensing component 110 may also include an ADC acquisition chip or an ADC analog-to-digital converter coupled to the temperature sensing device 111. The ADC acquisition chip converts the analog signal of the temperature sensing device 111 into a digital signal and transmits it to the main controller 114. Alternatively, the temperature sensing device 111 may be a digital sensor with analog-to-digital conversion function, which can directly convert the analog temperature signal into a digital signal and transmit it to the main controller 114.

[0024] This disclosure does not limit the number of layers or wiring on the circuit board, but it may include at least a power supply circuit and a data transmission circuit. The temperature sensing component 110 may include multiple strip-shaped or arc-shaped interconnecting circuits 112 to achieve coupling between different devices, power supply in series or parallel, and communication interconnection in serial or parallel modes. Alternatively, the temperature sensing component 110 may be mounted on a circular PCB board and interconnected through the interconnecting circuits 112 on the PCB board.

[0025] In some embodiments, the first wafer 101 and the second wafer 102 can be stacked and fixed by bonding adhesive, hot-temperature adhesive, resin or other adhesive medium, or the first wafer 101 and the second wafer 102 can be stacked by thermo-press bonding. During testing, the internal temperature of the first wafer 101 and the second wafer 102 is measured by the temperature measuring device 111, and the obtained temperature data is uploaded by the main controller 114 to an external host or cloud, or stored in the memory device in the temperature measuring component 110. The power supply 113 can be a battery or a wired power supply connected to an external power source, and the power supply 113 supplies power to the main controller 114 and the temperature measuring device 111.

[0026] The main controller 114 of the semiconductor temperature measuring device 10 can be connected to an external host via a data cable for wired transmission, or the semiconductor temperature measuring device 10 has a wireless transmission module that sends test data to an external host or cloud server via the antenna 115 of the wireless transmission module. In the semiconductor temperature measuring device 10 using wireless transmission, the power supply 113 can be an energy storage device such as a battery. There are no restrictions on the number, type, or connection method of multiple batteries; they can be rechargeable lithium-ion batteries or other types of batteries. The wireless transmission semiconductor temperature measuring device 10 eliminates some of the contamination associated with wired temperature measurement and avoids the need for through-holes in the processing chamber, reducing manufacturing difficulty and providing good temperature measurement results.

[0027] In some embodiments, the temperature sensing component 110 may be located between the first wafer 101 and the second wafer 102, or at least one of the first wafer 101 and the second wafer 102 may have a groove provided therein, and components of the temperature sensing component 110 may be disposed in the groove, for example, the groove may include Figure 11 The first groove 1081 and / or the second groove 1082 are provided. For example, a groove can be formed in the first wafer 101, and the temperature measuring device 111, power supply 113 and main control 114 of the temperature measuring component 110 are disposed in the groove of the first wafer 101. The interconnect circuit 112 or interconnect line of the temperature measuring component 110 can be disposed in the groove, or disposed on the surface of the first wafer 101 without being disposed in the groove. The second wafer 102 may not have a groove. The second wafer 102 is thinned and disposed on the temperature measuring component 110 to cover the temperature measuring component 110.

[0028] In some embodiments, both the first wafer 101 and the second wafer 102 are provided with grooves. The grooves of the first wafer 101 and the second wafer 102 are aligned in the z-direction to form a cavity. The temperature sensing component 110 is disposed within the cavity, thereby reducing the thickness of the first wafer 101 and the second wafer 102 and improving the temperature measurement accuracy. In this case, part of the temperature sensing component 110 is located within the wafer, and part is located between the two wafers.

[0029] In some embodiments, to improve power supply stability, as follows: Figure 3 The voltage regulator 116 is coupled to the power supply 113. The voltage regulator 116 denoises, modulates, boosts, or bucks the voltage input from the power supply 113 before outputting it to power the main controller 114, temperature sensing device 111, and other electrical appliances. The voltage regulator 116 can be, but is not limited to, a low-dropout linear regulator (LDO). The input terminal of the voltage regulator 116 is coupled to the output terminal of the power supply 113, and the output terminal of the voltage regulator 116 is coupled to the main controller 114, temperature sensing device 111, and other electrical appliances. The voltage regulator 116 can filter noise from the power supply 113, regulate the voltage output, and provide a stable power supply voltage.

[0030] In some embodiments, the semiconductor temperature measuring device 10 can divide the global temperature measuring device 111 into multiple parts, with each temperature measuring device 111 adapted to a separate voltage regulator 116 for independent power supply, and the main control 114 can also be adapted to a separate voltage regulator 116 for independent power supply. (Refer to...) Figure 3 As shown, multiple temperature sensing devices 111 are arranged at intervals along the circumferential direction surrounding the center of the first wafer 101. Multiple rings of temperature sensing devices 111 can be arranged radially from the inside out of the first wafer 101 to simulate and test the temperature of different regions of the wafer. The outermost ring of temperature sensing devices 111 is located at the outer edge of the temperature sensing assembly 110, and the outermost temperature sensing device 111 is the device closest to the wafer side of the temperature sensing assembly 110. The division of the global temperature sensing devices 111 can take various forms. The temperature sensing circuit 119 can be divided according to the diameter of the first wafer 101 into a strip-shaped distribution, or into multiple nested circular distributions, or into a fan-shaped distribution. The interconnect circuit of this embodiment adapts to different arrangements of the temperature sensing circuit 119 and has different wiring paths, and the division of the temperature sensing circuit 119 is not limited.

[0031] In some embodiments, refer to Figure 3 As shown, the semiconductor temperature measuring device 10 includes: an antenna 115 located at the center of the first wafer 101 and the second wafer 102; the antenna 115 is coupled to a main controller 114; the semiconductor temperature measuring device 10 includes a plurality of temperature measuring circuits 119, and the temperature measuring devices 111 included in the plurality of temperature measuring circuits 119 are arranged at intervals in the circumferential direction surrounding the antenna 115; the plurality of temperature measuring devices 111 of the temperature measuring circuits 119 are arranged at intervals in the radial direction of the first wafer 101. In some embodiments, the plurality of temperature measuring devices 111 are circumferentially distributed around the antenna 115, which may be multiple rings of temperature measuring devices 111 arranged sequentially from the inside to the outside with the antenna 115 as the center.

[0032] The temperature sensing component 110 also includes a wireless transmission module coupled to the main controller 114, which may include, but is not limited to, a Bluetooth module, a Wi-Fi module, etc. The wireless transmission module may include an antenna 115 to transmit wireless signals. Figure 3 The antenna 115 is a ring coil located at the center of the first wafer 101 and the second wafer 102, and may include multiple coils, such as, but not limited to, RF coils. In other examples, the antenna 115 may be located near the center of the first wafer 101 and the second wafer 102, including a horizontally positioned antenna 115.

[0033] In some embodiments, the division of the global temperature sensing device 111 can take various forms, such as dividing it into... Figure 3The temperature measuring device 111 is divided into temperature measuring circuits 119 in the radial direction. For example, a temperature measuring circuit 119 may include multiple temperature measuring devices 111 arranged radially and symmetrically (or substantially symmetrically) with respect to the center. That is, a temperature measuring circuit 119 includes multiple temperature measuring devices 111 spaced apart on the diameter of the first wafer 101. These multiple temperature measuring devices 111 have two parts spaced apart with respect to the center (or antenna 115). Figure 3 Eight diameters are shown, which can be divided into eight temperature sensing circuits 119. Multiple temperature sensing devices 111 located near the antenna 115 can be assigned to any one or more radially extending temperature sensing circuits 119. For example, 81 temperature sensing devices 111 can be grouped into eight temperature sensing circuits 119, with eight voltage regulators 116 providing independent power. The number of temperature sensing devices 111 powered by each voltage regulator 116 can be the same or different. Each temperature sensing circuit 119 can be configured with a separate voltage regulator 116 for power supply. The voltage regulator 116 of each temperature sensing circuit 119 is coupled to a power supply 113 and modulates the power supply 113 before outputting it to the corresponding temperature sensing device 111. Multiple voltage regulators 116 coupled to each temperature sensing circuit 119 can be arranged at intervals around the center of the first wafer 101. They can be coupled to and powered by multiple temperature sensing devices 111 on the corresponding temperature sensing circuit 119 through a ring interconnect circuit 1122 and a first interconnect circuit 1121 extending radially along the wafer. Power supply can include series or parallel connections. The first interconnect circuit 1121 can connect multiple temperature sensing devices 111 radially along the first wafer 101. The temperature sensing devices 111 are arranged along the extension direction of the first interconnect circuit 1121 and coupled to it. The included angle between any two adjacent first interconnect circuits 1121 can be equal or substantially equal, allowing for a more uniform distribution of the temperature sensing devices 111 in different areas within the wafer, enabling temperature detection in different areas of the wafer.

[0034] In some embodiments, at least a portion of a temperature sensing circuit 119 may be located in a sector-shaped region of the first wafer 101, such as... Figure 3The first wafer 101 or temperature sensing component 110 is divided into a central region along the extension path of the first interconnect circuit 1121 and the interconnect circuits connecting the first interconnect circuits 1121, and four fan-shaped regions surrounding the central region, such as fan-shaped region LL' and fan-shaped region MM'. An antenna 115 is set at the center (or near the center) of the central region. Other areas of the central region can be equipped with a main controller 114, a voltage regulator 116, a capacitor structure 105, and temperature sensing devices 111. Some of the temperature sensing devices 111 can be located inside the coil of the antenna 115. The central region can also be equipped with an ADC acquisition chip, a wireless transmission module, etc. The fan-shaped regions are divided by the dashed lines in the figure. Taking fan-shaped region LL' as an example, multiple temperature sensing devices 111 located in fan-shaped region LL' are grouped together, and a total of 4 groups of temperature sensing devices 111 are divided. Each group of temperature sensing devices 111 can be powered by a voltage regulator 116.

[0035] In some embodiments, a temperature sensing circuit 119 may include multiple temperature sensing devices 111 in a sector-shaped region LL', a voltage regulator 116, and an interconnection circuit 112 connecting each temperature sensing device 111 and the voltage regulator 116. For example, voltage regulators 116a to 116d supply power to the temperature sensing devices 111 of their respective temperature sensing circuits 119; for instance, voltage regulator 116b supplies power to multiple temperature sensing devices 111 in the sector-shaped region LL'. Multiple temperature sensing devices 111 in the central region may be assigned to any one of voltage regulators 116a to 116d for power supply; for example, voltage regulator 116d supplies power to multiple temperature sensing devices 111 located in the sector-shaped region MM'. Voltage regulator 116e supplies power to the main control unit 114, and other voltage regulators 116 may also be configured to supply power to components such as wireless transmission modules. Voltage regulators 116a to 116e are connected in parallel to the power supply 113. Taking a total of 81 temperature measuring devices 111 globally as an example, 18 temperature measuring devices 111 can be distributed in each sector area; 9 temperature measuring devices 111 can be set in the central area (including multiple temperature measuring devices 111 located in the antenna 115); voltage regulators 116a to 116c supply power to the 18 temperature measuring devices 111 in the corresponding sector area; voltage regulator 116d supplies power to the 18 temperature measuring devices 111 in the corresponding sector area and the 9 temperature measuring devices 111 in the central area.

[0036] Taking the temperature measuring circuit 119 corresponding to the fan-shaped region LL' as an example, the interconnect circuit 112 of the temperature measuring circuit 119 may include a plurality of first interconnect circuits 1121 spaced apart along the circumferential direction of the outer periphery of the antenna 115, the plurality of first interconnect circuits 1121 being radially spaced along the first wafer 101, and including a plurality of branches such as second interconnect circuits 1123 on the first interconnect circuits 1121, the second interconnect circuits 1123 intersecting or perpendicular to the first interconnect circuits 1121, satisfying that the plurality of temperature measuring devices 111 on the fan-shaped region LL' are uniformly distributed in a fan shape, which may include a multi-layer fan-shaped distribution nested sequentially from the inside out.

[0037] In some embodiments, the multiple temperature measuring devices 111 belonging to the temperature measuring circuit 119 are arranged at intervals along the radial direction of the first wafer 101 in the corresponding fan-shaped regions; the multiple second interconnect circuits 1123 located on the same first interconnect circuit 1121 have different lengths, and the size of the second interconnect circuits 1123 gradually increases from the center of the first wafer 101 to the outside to meet the electrical interconnection requirements of the uniform radial distribution of the temperature measuring devices 111.

[0038] In some embodiments, Figure 4 The power supply diagram for the temperature sensing component 110 is shown. (For example...) Figure 4 The four temperature sensing circuits 119 in the example correspond to four voltage regulators 116 connected in parallel to the power supply 113. Each voltage regulator 116 outputs voltage to power multiple temperature sensing devices 111; the power supply method can be parallel or series. The voltage regulators 116 may include corresponding... Figure 3 The voltage regulators 116a, 116b, 116c and 116d of each temperature measuring circuit 119.

[0039] In some embodiments, at least a portion of a temperature sensing circuit 119 may be a circle surrounding the center of a first wafer 101, and multiple temperature sensing circuits 119 may be sequentially nested from the inside to the outside along the radial direction of the first wafer 101; multiple voltage regulators 116 corresponding to each circular temperature sensing circuit 119 may be sequentially arranged along the radial direction of the first wafer 101, located between adjacent circular temperature sensing circuits 119. It is understood that the division and arrangement of the temperature sensing circuits 119 in this embodiment are merely illustrative examples, used only to demonstrate that multiple voltage regulators 116 provide separate power supplies for multiple groups of temperature sensing devices 111; the shape and number of interconnects supplying power to the voltage regulators 116 and their corresponding temperature sensing devices 111 are not limited.

[0040] In some embodiments, Figure 3 A multiplexer is also installed in the central area where the antenna 115 is located. By switching the multiplexer, multiple temperature measuring devices 111 on the corresponding temperature measuring circuit 119 can be selected to read temperature data, reducing the occupation of the communication channel.

[0041] In some embodiments, refer to Figure 5 As shown, the temperature sensing circuit 119 also includes a filter circuit 117 coupled to the power supply 113, which may include, but is not limited to, a passive filter (LC filter); the filter circuit 117 may be composed of, but is not limited to, a combination of inductors, capacitors, and resistors, used to reduce or eliminate noise and interference from the power supply 113 and provide a stable power supply output. In some specific embodiments, the filter circuit 117 may include, but is not limited to, an inductor and resistor connected in series between the power supply 113 and the voltage regulator 116; the filter circuit 117 may include, but is not limited to, a capacitor connected in parallel with the voltage regulator 116 and connected to the power supply 113. Figure 5 A separate voltage regulator 116 is set up to supply power to the main control 114, and a filter circuit 117 coupled to the power supply 113 is set up to eliminate noise and interference from the power supply 113.

[0042] In some embodiments, Figure 6 The example illustrates the power supply circuit diagram for the two temperature sensing devices 111 and the voltage regulator 116 in any temperature sensing circuit 119; refer to Figure 6 As shown, the voltage regulator 116 includes a first ground terminal GND, an output terminal OUT, and a first input terminal IN; the temperature sensing device 111 includes a first terminal (terminal 1) and a second terminal (terminal 2); wherein, the first terminal of the temperature sensing device 111 is coupled to the output terminal OUT of the voltage regulator 116, and the second terminal of the temperature sensing device 111 is coupled to the first ground terminal GND of the voltage regulator 116; the first input terminal IN of the voltage regulator 116 is coupled to the power supply 113.

[0043] The power supply interface of the temperature sensing device 111 may include two terminals, such as the first terminal for connecting to the power supply voltage (positive potential) and the second terminal for grounding or the negative terminal of the battery. The temperature sensing device 111 also includes a communication interface for transmitting control commands from the main controller 114 or for transmitting collected temperature data. Figure 6 Only the power supply terminals of the temperature measuring device 111 are shown; the terminals used for communication are not shown.

[0044] The voltage regulator 116 may include at least a first input terminal IN for coupling to the output terminal of the power supply 113 or the positive terminal of the battery, for receiving the power supply voltage, and a load such as a resistor or transistor may also be coupled between the first input terminal IN and the output terminal of the power supply 113; a ground terminal GND for providing grounding; and an output terminal OUT for outputting the modulated operating voltage. The first terminals of multiple temperature sensing devices 111 are connected in parallel to the output terminal OUT of the voltage regulator 116, and the second terminals of the temperature sensing devices 111 are all coupled to the ground terminal GND of the voltage regulator 116.

[0045] In some embodiments, the voltage regulator 116 can be controlled by a switching circuit to control its voltage input or output, thereby controlling whether the voltage regulator 116 operates, and thus controlling whether the temperature sensing device 111 (or temperature sensing circuit 119) operates. The switching circuit can be selected by the main controller 114 and controlled to turn on or off; the switching circuit may include, but is not limited to, transistors or signal selectors. Alternatively, the voltage regulator 116 may integrate an enable circuit. When the enable terminal of the enable circuit is input with a high level, or a voltage within a preset voltage range, the voltage regulator 116 is connected and operates, outputting a modulated operating voltage; when the enable terminal of the enable circuit is input with a low level, or a voltage outside the preset voltage range, the voltage regulator 116 is disconnected and does not operate. At this time, the output terminal OUT of the voltage regulator 116 is floating or outputs 0V.

[0046] In some embodiments, refer to Figure 6 As shown, the voltage regulator 116 further includes: a second input terminal EN (enable terminal), coupled to the power supply 113; the voltage regulator 116 is configured such that: in response to the second input terminal EN of the voltage regulator 116 being applied a high level, and the first input terminal IN of the voltage regulator 116 being connected to the output voltage of the power supply 113; the output terminal OUT of the voltage regulator 116 outputs the operating voltage of the temperature measuring device 111.

[0047] The second input terminal EN is connected in parallel with the first input terminal IN to the output terminal of power supply 113. A resistor can be connected in series with the second input terminal EN to divide the voltage, preventing voltage surges and adjusting the enable voltage of the input enable terminal within a preset voltage range. When the second input terminal EN is applied high, and the first input terminal IN of voltage regulator 116 is connected to the output voltage of power supply 113, the output terminal OUT of voltage regulator 116 outputs a modulated voltage to power temperature sensing device 111. This output voltage can be recorded as the operating voltage of temperature sensing device 111. When the second input terminal EN is applied low or no voltage is applied, the output terminal OUT of voltage regulator 116 outputs 0V or floats. This enables automatic power-on activation of voltage regulator 116, reducing energy consumption. Voltage regulator 116 may also include a second ground terminal EP. The second ground terminal EP can be grounded for heat dissipation, or connected to a metal shielding layer to reduce interference, or the second ground terminal EP can be used to enhance the physical connection strength between voltage regulator 116 and the PCB board.

[0048] In some embodiments, refer to Figure 6As shown, the temperature measuring circuit 119 further includes a filter circuit 117. The first terminal of the filter circuit 117 is coupled to the power supply 113, and the second terminal of the filter circuit 117 is grounded. The filter circuit 117 includes a first capacitor 1171. The first terminal of the first capacitor 1171 is coupled to the power supply 113, and the second terminal of the first capacitor 1171 is grounded. The first terminal of the filter circuit 117 can be an input terminal, and the second terminal can be an output terminal. The first terminal is used to couple to the output terminal of the power supply 113, and the second terminal is used to ground to reduce noise in the power supply 113 and improve power supply stability. The filter circuit 117 can be connected in parallel with the voltage regulator 116 to the output terminal of the power supply 113, and is connected in parallel with both the first input terminal IN and the second input terminal EN of the voltage regulator 116. The filter circuit 117 may include... Figure 6 The example first capacitor 1171, its first terminal, the first input terminal IN of the voltage regulator 116, and the second input terminal EN are connected in parallel to the output terminal of the power supply 113, and the second terminal of the first capacitor 1171 is grounded. The filter circuit 117 may also include an inductor coupled to the output terminal of the power supply 113. The power supply voltage passes through the inductor and is then connected to the first input terminal IN and the second input terminal EN of the voltage regulator 116 to reduce the noise of the power supply 113.

[0049] In some embodiments, the interconnect circuit 112 for connecting the power supply and communication between the various devices of the temperature sensing assembly 110 may be carried on a circuit board and may include multiple interconnect lines; Figure 7 Part a illustrates the layout of multiple interconnect lines on a portion of a circuit board. Figure 7 Section b shows a schematic cross-section of multiple interconnects along the z-direction at AA'. (Refer to...) Figure 7 As shown, interconnect circuit 112 includes interconnects 1124a, 1124b, 1124c, 1124d, and 1124e. Interconnects 1124a and 1124c are configured to transmit power supply voltage. For example, interconnect 1124a can be used to couple the first terminal of temperature sensing device 111 to the output terminal OUT of voltage regulator 116, and interconnect 1124c can be used to couple the output terminal of power supply 113 to the first input terminal IN of voltage regulator 116. Interconnects 1124b and 1124c can be used to ground or connect to the negative terminal of a battery. For example, interconnect 1124b is coupled to the second terminal of temperature sensing device 111 to the first ground terminal GND of voltage regulator 116; interconnect 1124c is configured as the common ground wire of temperature sensing assembly 110. Figure 7 This is just an example; interconnects may have many more branch lines, and there is no limitation on this. Figure 7 In the process, the interconnect circuit 112 also includes interconnect lines (not shown) for transmitting control signals and temperature data signals. Figure 7 Only the interconnects of the power supply network section are shown.

[0050] Because the interconnect circuit 112 is only arranged on a single wiring layer, when the line width and spacing of each interconnect meet the design requirements, the width dimension D1 of the interconnect circuit 112 is relatively large, resulting in a large closed loop area and a large induced electromotive force in an alternating magnetic field environment. This disclosure provides an interconnect circuit 112 design scheme that uses multiple wiring layers to reduce the width dimension of the interconnect circuit 112, decrease the circuit loop area, reduce the RF induced electromotive force, and mitigate RF interference problems.

[0051] In some embodiments, refer to Figure 8 As shown, the first wafer 101 and the second wafer 102 are stacked along a first direction (z direction); the interconnect circuit 112 includes at least: a first wiring layer 1001 and a second wiring layer 1002 stacked along the z direction; at least a portion of the interconnects of the first wiring layer 1001 are coupled to the power supply 113, and at least a portion of the interconnects of the second wiring layer 1002 are grounded.

[0052] The interconnect circuit 112 may include multiple stacked wiring layers, with no restrictions on the wiring shape, line width, number, or branches of each wiring layer. For example, a first wiring layer 1001 and a second wiring layer 1002 may be stacked in the z-direction. The first wiring layer 1001 includes multiple interconnects for transmitting power supply voltage. These interconnects may be disposed on the wiring layer or at least partially embedded within it. The interconnects of the first wiring layer 1001 may be used, but are not limited to, to couple to the output terminal of the power supply 113, the first terminal of the temperature sensing device 111, the first input terminal IN of the voltage regulator 116, etc., to provide power supply voltage. The second wiring layer 1002 includes multiple interconnects for grounding, such as coupling to the second terminal of the temperature sensing device 111, the first ground terminal GND of the voltage regulator 116, the second ground terminal EP, and the negative terminal of the battery, etc.

[0053] In some embodiments, Figure 8 Part b shows Figure 8 The diagram illustrates the cross-section of multiple interconnects at BB' along the z-direction in part a. The first wiring layer 1001 is illustrated with first interconnect 1125a and second interconnect 1125b. The first wiring layer 1001 also has more interconnects, not shown. The second wiring layer 1002 is exemplified by third interconnect 1126a and fourth interconnect 1126b. While meeting the design requirements for interconnect line width and spacing, the width dimension D2 of the interconnect circuit 112 can be reduced. For example, D2 can intersect at D1, reducing it by 33.3%, which can reduce the RF induced electromotive force by more than 20%, thus reducing interference problems in the RF environment. In some embodiments, Figure 7 The interconnect 1124e, which serves as the common ground wire, can be set in Figure 8The second wiring layer 1002. The interconnect circuit 112 also includes interconnects (not shown) for transmitting control signals and temperature data signals. Figure 8 Only the interconnects of the power supply network section are shown.

[0054] In other examples, more routing layers can be set, such as Figure 8 The first wiring layer 1001 serves as a power layer, the second wiring layer 1002 serves as a ground layer, a third wiring layer serves as a control signal transmission layer, and a fourth wiring layer serves as a data transmission layer for transmitting acquired temperature data. The wiring layers are isolated by insulating layers and electrically interconnected through metal vias or conductive channels penetrating the interconnect layers. For example, the top and bottom layers of the interconnect circuit 112 are the third and fourth wiring layers, respectively, with the first wiring layer 1001 and the second wiring layer 1002 located in the middle layer to reduce power supply and communication interference. Alternatively, the interconnect lines transmitting control signals and data may be located on the same wiring layer. The multiple wiring layers of the interconnect circuit 112 may have other stacking arrangements and are not limited to the stacking example exemplified in this disclosure.

[0055] In some embodiments, unlike Figure 8 The interconnects of adjacent routing layers shown are arranged in parallel, and they intersect or are perpendicular to each other to reduce parasitic capacitance and inductance. Different interconnects or interconnects in different regions on a routing layer extend in different directions. Intersect or are perpendicular to each other in the z-direction of corresponding regions of adjacent routing layers to reduce interference.

[0056] In some embodiments, refer to Figure 3 As exemplified, the temperature sensing circuit 119 includes at least: a first interconnect circuit 1121 coupled to a plurality of temperature sensing devices 111, the first interconnect circuit 1121 extending radially along the first wafer 101; as Figure 8 As exemplified, the first interconnect circuit 1121 includes at least: a first interconnect 1125a and a second interconnect 1125b located on the first wiring layer 1001; and a third interconnect 1126a located on the second wiring layer 1002, the third interconnect 1126a being grounded; wherein, the first terminal of the temperature sensing device 111 is coupled to the output terminal OUT of the voltage regulator 116 at least through the first interconnect 1125a; the first input terminal IN of the voltage regulator 116 is coupled to the power supply 113 at least through the second interconnect 1125b; and the second terminal of the temperature sensing device 111 is coupled to the first ground terminal GND of the voltage regulator 116 at least through the third interconnect 1126a. Alternatively, for example, the fourth interconnect 1126b of the second wiring layer 1002 may be coupled to the second ground terminal EP of the voltage regulator 116.

[0057] In some embodiments, refer to Figure 9As shown, the semiconductor temperature measuring device 10 further includes: a first conductive layer 103 located on a first surface of a first wafer 101; a second conductive layer 104 located on a second surface of a second wafer 102; and a capacitor structure 105, at least partially located between the first wafer 101 and the second wafer 102; the capacitor structure 105 may include... Figure 10 The device comprises a first electrode 1051, a second electrode 1052, and a dielectric layer 1055, with the dielectric layer 1055 located between the first electrode 1051 and the second electrode 1052. The first electrode 1051 is coupled to a first conductive layer 103, and the second electrode 1052 is coupled to a second conductive layer 104. Multiple conductive pillars are located between the first conductive layer 103 and the second conductive layer 104. These pillars are situated between the outer edge of the temperature sensing component 110 and the side edge of the first wafer 101. Each conductive pillar is coupled to both the first conductive layer 103 and the second conductive layer 104. A first surface is the surface of the first wafer 101 in the positive z-direction, and a second surface is the surface of the second wafer 102 in the negative z-direction. The first and second surfaces are arranged face-to-face in the z-direction, and neither the first nor the second surface is limited to the front or back side of the wafer.

[0058] The first conductive layer 103 may extend and lie flat on the first surface of the first wafer 101, at least covering a portion of the first surface of the first wafer 101; the second conductive layer 104 may extend and lie flat on the second surface of the second wafer 102, at least covering a portion of the second surface of the second wafer 102. The materials of the first conductive layer 103 and the second conductive layer 104 may be the same or different; the constituent materials of the first conductive layer 103 and the second conductive layer 104 may include conductive materials with high magnetic permeability, and may be a single-layer structure or a multi-layer structure, including but not limited to: conductive materials such as silver, copper, aluminum, tungsten, gold, silver, platinum, nickel, titanium, tin, etc., or easily curable materials including the above-mentioned conductive metal materials, such as organosilicon, polymers, etc., which include conductive metal materials.

[0059] In some embodiments, the first conductive layer 103 can be formed by curing a conductive paste. The conductive paste may include metal microspheres, metal powder, or other conductive materials with microstructures and easily curable substrates; it may include, but is not limited to, powders such as gold, silver, copper, and aluminum, and may also include non-metallic microstructure materials such as graphite powder or carbon nanotubes; for example, the conductive paste may be conductive gold paste, conductive silver paste, or conductive copper paste. By selecting the particle size and solid content of the conductive silver paste, a high-density first conductive layer 103 can be formed, which has good conductivity. In some embodiments, a conductive paste is uniformly coated on the first surface of the first wafer 101. The particle size of the conductive material (such as metal powder) in the conductive paste may be less than 0.3 micrometers, and the solid content may be greater than >80%, which allows the first conductive layer 103 to form a complete shielding layer with a thickness of micrometers. While shielding some external electromagnetic noise interference, it can also form a good conductive circuit with the capacitor structure 105, absorb peak current, and reduce the interference and damage of peak current.

[0060] In some embodiments, taking the first conductive layer 103 as an example, the first conductive layer 103 is a metal material layer formed by processes such as physical and chemical deposition, sputtering, and electroplating.

[0061] The capacitor structure 105 is located between the first conductive layer 103 and the second conductive layer 104. The capacitor structure 105 may include a first electrode 1051, a second electrode 1052, and a dielectric layer 1055 electrically isolating the two electrodes. The capacitor structure 105 may also include a multilayer capacitor, such as a multilayer ceramic capacitor, where the dielectric layer 1055 is a ceramic dielectric material. This miniaturization of the capacitor structure 105 increases its voltage or current carrying capacity. The first electrode 1051 and the second electrode 1052 of the capacitor structure 105 may be provided with contact points, pins, or other connection structures to couple with the conductive layer. This coupling can be a contact connection or an electrical connection through other conductive structures. When the first wafer 101 or the second wafer 102 experiences a peak current, the peak current charges the capacitor. The peak current is absorbed by the capacitor to reduce interference with the temperature sensing component 110 and to reduce interference and damage to the wafer carrier disk.

[0062] In some embodiments, refer to Figure 10As shown, the capacitor structure 105 includes a plurality of alternately arranged first electrodes 1051 and second electrodes 1052; a first connection structure 1053 coupled to the plurality of first electrodes 1051; and a second connection structure 1054 coupled to the plurality of second electrodes 1052. The first connection structure 1053 is coupled to a first conductive layer 103, and the second connection structure 1054 is coupled to a second conductive layer 104. The first electrodes 1051 and second electrodes 1052 can be internal electrodes, and the first connection structure 1053 and second connection structure 1054 can serve as external electrodes for connecting to external structures.

[0063] like Figure 10 As illustrated, the first electrode 1051 and the second electrode 1052 can be rectangular, circular, or elliptical, or irregularly polygonal or arc-shaped. The first electrode 1051 and the second electrode 1052 can be, for example... Figure 10 As shown, extending along the xoy plane, the first electrode 1051 and the second electrode 1052 partially overlap in the z-direction. The first electrode 1051 and the second electrode 1052 are offset from each other in the electrode extension direction, as shown in... Figure 10 The first electrode 1051 is offset in the x-direction, and the first side (left side) of the second electrode 1052 in the x-direction is not aligned with the first side of the second electrode 1052 in the z-direction; or, in other words, the dimensions of the first electrode 1051 and the second electrode 1052 in the x-direction are equal or substantially equal, and the first electrode 1051 and the second electrode 1052 only partially overlap. The first connecting structure 1053 is located on one side of the electrode extension direction of the first electrode 1051, and the first connecting structure 1053 is coupled to a plurality of spaced-apart first electrodes 1051; the second connecting structure 1054 is located on one side of the electrode extension direction of the second electrode 1052, and the second connecting structure 1054 is coupled to a plurality of spaced-apart second electrodes 1052. The first connecting structure 1053 and the second connecting structure 1054 are arranged opposite each other in the extension direction of the first electrode 1051, and the first connecting structure 1053 and the second connecting structure 1054 are electrically isolated.

[0064] In some embodiments, refer to Figure 10As shown, the first electrode 1051 has a first end and a second end disposed opposite to each other in the electrode extension direction. The first end of the first electrode 1051 is coupled to the first connecting structure 1053, and the second end is floating or not connected to electricity. The second electrode 1052 also has a first end and a second end disposed opposite to each other in the electrode extension direction. The first end of the first electrode 1051 is coupled to the second connecting structure 1054, and the second end is floating or not connected to electricity. The first end of the first electrode 1051 and the second end of the second electrode 1052 are not aligned in the perpendicular electrode direction (z-direction), and the second end of the second electrode 1052 is away from the first connecting structure 1053. The first end of the second electrode 1052 and the second end of the first electrode 1051 are not aligned in the z-direction, and the second end of the first electrode 1051 is away from the second connecting structure 1054.

[0065] The first connection structure 1053 is coupled to the first semiconductor layer on the first wafer 101, and the second connection structure 1054 is coupled to the second semiconductor layer on the second wafer 102, thereby realizing the coupling and conduction of the capacitor structure 105 with the first wafer 101 and the second wafer 102. This embodiment does not limit the connection method of the first connection structure 1053 and the second connection structure 1054; for example, the first wafer 101 can be... Figure 10 Below the capacitor structure 105, the second wafer 102 can... Figure 10 Above the capacitor structure 105, the bottom of the first connection structure 1053 is in contact with the first conductive layer 103, and the top of the first connection structure 1053 is electrically isolated from the second conductive layer 104 without contact; the top of the second connection structure 1054 is in contact with the second conductive layer 104, and the bottom of the second connection structure 1054 is electrically isolated from the first conductive layer 103 without contact.

[0066] In some embodiments, a conductive layer may be provided on either the first wafer 101 or the second wafer 102, or a conductive layer may be provided on both wafers. Figure 10 The capacitor structure 105 is rotated and then positioned between the first conductive layer 103 and the second conductive layer 104.

[0067] like Figure 11 As exemplified, a first conductive layer 103 is disposed on the surface of the first wafer 101, extending to the inner wall of the first groove 1081, and a capacitor structure 105 is coupled to the first conductive layer 103 and the second wafer 102. In other examples, referring to the arrangement of the first conductive layer 103 in the first groove 1081, a second conductive layer 104 is disposed on the surface of the second wafer 102, extending to the inner wall of the second groove 1082, and a capacitor structure 105 is coupled to the second conductive layer 104 and the first wafer 101.

[0068] In some embodiments, it is possible to Figure 11 A second conductive layer 104 is further disposed on the surface of the second wafer 102, and the capacitor structure 105 is coupled to the two conductive layers. The first conductive layer 103, the first connection structure 1053, the second connection structure 1054, the second conductive layer 104, and the second wafer 102 are stacked sequentially in the z-direction, which reduces the lead distance of the capacitor structure 105 and facilitates the reduction of the thickness of the semiconductor temperature measuring device 10.

[0069] In some embodiments, refer to Figure 12 As shown, multiple conductive pillars 106 are distributed circumferentially on the inner edges of the first wafer 101 and the second wafer 102. The conductive pillars 106 are located on the outermost part of the temperature sensing component 110, surrounding the outer edge of the temperature sensing component 110. The conductive pillars 106 can be electrically connected to the first wafer 101 and the second wafer 102, or to the first conductive layer 103 on the surface of the first wafer 101, and to the second conductive layer 104 on the second wafer 102. The conductive pillars 106 can be formed by coating a conductive paste and then curing it. There are no restrictions on the shape of the conductive pillars 106; they can be cylindrical or spherical. The cross-sectional shape of the conductive pillar 106 in the xoy plane can be rectangular, circular, or elliptical, or an irregular arc, polygon, or other irregular shape.

[0070] In some embodiments, Figure 9 The conductive post 106 can extend into or penetrate the first wafer 101 in the z-direction; the conductive post 106 can also extend into or penetrate the second wafer 102 in the z-direction. In some embodiments, the first surface of the first wafer 101 is coupled to the bottom of the conductive post 106, and the second surface of the second wafer 102 is coupled to the top of the conductive post 106; ion implantation can be performed at the landing site of the conductive post 106 on the first surface of the first wafer 101 to form a first doped region coupled to the conductive post 106, thereby reducing the contact resistance between the first wafer 101 and the conductive post 106; ion implantation can be performed at the landing site of the conductive post 106 on the second surface of the second wafer 102 to form a second doped region coupled to the conductive post 106, thereby reducing the contact resistance between the second wafer 102 and the conductive post 106.

[0071] In some embodiments, the outermost ring and outermost edge of the temperature sensing component can be temperature sensing devices, such as... Figure 13 The temperature measuring device 111a shown may be a main controller 114 or a voltage regulator 116, etc., and is not limited to the temperature measuring device 111.

[0072] In some embodiments, Figure 13As shown, multiple first interconnect circuits 1121 divide the first wafer 101 into multiple temperature sensing zones. One or more conductive pillars 106 are located between adjacent first interconnect circuits 1121. All conductive pillars 106 are uniformly distributed along the edge of the first wafer 101, and the spacing between adjacent conductive pillars 106 is equal or substantially equal. The conductive pillars 106 are located outside the outermost temperature sensing device 111a. For example, Figure 1 The peak current in the wafer can be transmitted to the ground terminal of the wafer carrier disk through the second wafer 102, the second conductive layer 104, the conductive pillar 106, the first conductive layer 103, and the first wafer 101, or it can be transmitted to the capacitor structure 105 and absorbed.

[0073] In some embodiments, the conductive post 106 is located near the sides of the first wafer and the second wafer, at the outermost edge of the temperature sensing component, and can be positioned as follows: Figure 13 As shown, they are located between adjacent first interconnect circuits 1121; or as Figure 12 As shown, the temperature sensing component is located between the extensions of adjacent first interconnect circuits 1121, and its maximum size in the xoy plane is smaller than that of the first wafer.

[0074] In some embodiments, the semiconductor temperature sensing device further includes: a conductive ring located between the first wafer 101 and the second wafer 102, the conductive ring surrounding the outer edge of the temperature sensing component 110, the conductive ring being located at the edge of the first wafer 101 and the second wafer 102, and the conductive ring being coupled to the first conductive layer 103 and the second conductive layer 104. The position of the conductive ring may be relative to... Figure 12 or Figure 13 The position of the intermediate conductive pillar 106 is the same, and it is about to be Figure 12 or Figure 13 The conductive post 106 in the diagram can be replaced with a conductive ring, which can be a wire mesh structure or a wall structure. Alternatively, in... Figure 12 or Figure 13 A conductive ring is provided around the conductive post 106. The conductive ring is connected to the first conductive layer 103 and the second conductive layer 104 to form a shielding structure, such as a Faraday cage or a Faraday cage-like structure, to reduce electromagnetic interference.

[0075] In some embodiments, at least one of the first wafer and the second wafer has a groove for accommodating at least a portion of the temperature sensing component; a first conductive layer extends into the inner wall of the groove; a capacitor structure is located in the corresponding groove, and a first electrode is coupled to the first conductive layer on the inner wall of the groove.

[0076] A groove can be formed in either the first wafer 101 or the second wafer 102. The depth of the groove can be greater than or equal to the thickness of the corresponding temperature sensing component 110. The other wafer can be thinned to serve as a cover layer and does not need to have a groove. For example, a first groove 1081 can be formed in the first wafer 101 to accommodate the temperature sensing component 110, and the second wafer 102 can be thinned to serve as a cover layer to cover the temperature sensing component 110 and the first wafer 101.

[0077] In some embodiments, refer to Figure 11 As shown, the first wafer 101 has a first groove 1081, and the second wafer 102 has a second groove 1082. The first groove 1081 and the second groove 1082 are aligned to form a cavity, and at least a portion of the temperature measuring component 110 is located in the cavity.

[0078] Figure 11 For example, taking temperature sensing device 111 as an example, the bottom of temperature sensing device 111 is located in the first groove 1081 of the first wafer 101, and the upper part of temperature sensing device 111 is located in the second groove 1082 of the second wafer 102. The first groove 1081 and the second groove 1082 are aligned in the z-direction. A portion of the interconnect circuit 112 connecting temperature sensing device 111 is disposed in the first groove 1081, specifically extending to the sidewall and bottom of the first groove 1081. The contacts at the bottom of temperature sensing device 111 are coupled to the interconnect circuit 112 at the bottom of the first groove 1081. This portion of interconnect circuit 112 extends out of the first groove 1081 from the bottom along the sidewall and is coupled to other devices in the first groove 1081, such as the main controller 114, the power supply 113, or the voltage regulator 116. The first wafer 101 and the second wafer 102 may be provided with corresponding grooves to accommodate the interconnect circuit 112, or some parts of the interconnect circuit 112 may be provided on the surface of the first wafer 101, and another part may be located in the first groove 1081 of the first wafer 101 to couple the corresponding device.

[0079] In some embodiments, Figure 10 The capacitor structure 105 shown can be disposed in the cavity formed by the first groove 1081 and the second groove 1082. The connection junction of the capacitor structure 105 can be directly coupled to the conductive layer, or a contact point can be provided on the connection structure to be coupled to the conductive layer.

[0080] A first groove 1081 may be formed in the first wafer 101. A first conductive layer 103 extends on the first surface of the first wafer 101 and extends to the sidewalls and bottom of the first groove 1081 below the first surface. A capacitor structure 105 is disposed in the first groove 1081. A first electrode 1051 or a first connection structure 1053 is coupled to the first conductive layer 103 at the bottom of the first groove 1081. The second wafer 102 may not have a groove. A second conductive layer 104 extends on the second surface of the second wafer 102. After the second wafer 102 is thinned, it covers the temperature sensing component 110. The second conductive layer 104 is coupled to the second electrode 1052 or the second connection structure 1054.

[0081] The second wafer 102 may be provided with a second groove 1082, the second conductive layer 104 extends on the second surface of the second wafer 102 and extends on the sidewall and bottom of the second groove 1082, the capacitor structure 105 is disposed in the cavity formed by aligning the first groove 1081 and the second groove 1082, and the second electrode 1052 or the second connection structure 1054 is coupled to the second conductive layer 104 at the bottom of the second groove 1082.

[0082] In some embodiments, the first conductive layer 103 extends into the inner wall of the first groove 1081, and the second conductive layer 104 extends into the inner wall of the second groove 1082. The temperature sensing device 111 or main control device 114 of the temperature sensing assembly 110 may be located within the first groove 1081. The interconnect circuit 112 or a circuit board including the interconnect circuit 112 is located on the first conductive layer 103 within the first groove 1081. The contacts of the temperature sensing device 111 or main control device 114 are coupled to the interconnect circuit 112, and a fixed connection between the contacts or pins and the interconnect circuit 112 can be achieved by soldering. The circuit board carrying the interconnect circuit 112 may be a flexible circuit board with a strip, arc, or other irregular shape adapted to the wafer groove and lead layout; the shape of the circuit board is not limited. An insulating material may be provided between the interconnect circuit 112 and the first conductive layer 103 for isolation.

[0083] In some embodiments, refer to Figure 9 and Figure 11 As shown, the semiconductor temperature measuring device also includes an adhesive layer 107 located between the first wafer 101 and the second wafer 102 for bonding and fixing the first wafer 101 and the second wafer 102. The adhesive layer 107 can be a bonding adhesive, a hot-dip mordant, resin, or other adhesive medium. The adhesive layer 107 may include a curable dielectric material, such as resin. The adhesive layer 107 can fill the first groove 1081 of the first wafer 101 and the second groove 1082 of the second wafer 102. After the two wafers are aligned and contacted, they are cured. The temperature measuring component 110 is wrapped and fixed in the corresponding groove by the adhesive layer 107 or adhesive material. The first conductive layer 103 and the second conductive layer 104 are separated by the intermediate adhesive layer 107.

[0084] In some embodiments, the arrangement and number of capacitor structures 105 can be set according to the interference resistance and interference tolerance of the electrical appliance. Capacitor structures 105 need to be set near electrical appliances with high power supply stability. In some embodiments, the capacitor structures are symmetrically distributed on the outside of the electrical appliance of the temperature measuring component; and / or, the capacitor structures are arranged at intervals around the circumferential direction of the electrical appliance; wherein, the electrical appliance of the temperature measuring component includes at least one of a temperature measuring device, a power supply, a main controller, and a voltage regulator.

[0085] like Figure 12 As shown, a capacitor structure 105 can be placed near the pins or contacts of electrical appliances such as the main controller 114 and the voltage regulator 116. (Refer to...) Figure 13 As shown, capacitor structures 105 can be symmetrically arranged near the pins or contacts of electrical appliances such as the main controller 114 and voltage regulator 116. There can be two, three, four, or more capacitor structures 105. Multiple capacitor structures 105 can be arranged at intervals around the circumference of the electrical appliance, and can be symmetrically or asymmetrically distributed, such as four capacitor structures 105. The four capacitor structures 105 form a rectangle or other quadrilateral to enhance the absorption of peak currents and improve the anti-interference performance of the electrical appliance.

[0086] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor temperature measuring device, characterized by comprising: include: The first and second wafers are stacked together; The temperature sensing component is at least partially located between the first wafer and the second wafer; The temperature measuring component includes a power supply, a main controller, and multiple temperature measuring circuits coupled together via interconnecting circuits. Each of the aforementioned temperature measuring circuits includes: Voltage regulator; Multiple temperature sensing devices are coupled to the voltage regulator; The voltage regulators of each of the temperature measuring circuits are coupled to the power supply; A first conductive layer is located on the first surface of the first wafer; The second conductive layer is located on the second surface of the second wafer, with the first surface and the second surface facing each other. A capacitor structure is located between the first conductive layer and the second conductive layer; The capacitor structure includes a first electrode, a second electrode, and a dielectric layer, wherein the dielectric layer is located between the first electrode and the second electrode. The first electrode is coupled to the first conductive layer, and the second electrode is coupled to the second conductive layer; The interconnect circuit is electrically isolated from both the first conductive layer and the second conductive layer, and the capacitor structure is used to absorb plasma and peak currents accumulated on the first wafer or the second wafer.

2. The semiconductor temperature measuring device according to claim 1, characterized in that, The voltage regulator includes: a first ground terminal, an output terminal, and a first input terminal; The temperature measuring device includes: a first end and a second end; The first end of the temperature measuring device is coupled to the output end of the voltage regulator, and the second end of the temperature measuring device is coupled to the first ground end of the voltage regulator; the first input end of the voltage regulator is coupled to the power supply.

3. The semiconductor temperature measuring device according to claim 2, wherein The voltage regulator also includes: The second input terminal is coupled to the power supply; the voltage regulator is configured as follows: In response to a high level being applied to the second input terminal of the voltage regulator and the first input terminal of the voltage regulator being connected to the output voltage of the power supply, the output terminal of the voltage regulator outputs the operating voltage of the temperature measuring device.

4. The semiconductor temperature measuring device according to claim 3, characterized in that, The temperature measuring circuit also includes: A filter circuit, wherein the first terminal of the filter circuit is coupled to the power supply, and the second terminal of the filter circuit is grounded.

5. The semiconductor temperature measuring device according to claim 2, characterized in that, The first wafer and the second wafer are stacked along a first direction; the interconnect circuit includes at least: A first wiring layer and a second wiring layer are stacked along the first direction; at least a portion of the interconnects of the first wiring layer are coupled to the power supply, and at least a portion of the interconnects of the second wiring layer are grounded.

6. The semiconductor temperature measuring device according to claim 5, characterized in that, The temperature measuring circuit includes at least: a first interconnecting circuit coupled to the plurality of temperature measuring devices; The first interconnect circuit includes at least: A first interconnect and a second interconnect located in the first wiring layer; and a third interconnect located in the second wiring layer, wherein the third interconnect is grounded; Wherein, the first end of the temperature measuring device is coupled to the output end of the voltage regulator at least through the first interconnect line; The first input terminal of the voltage regulator is coupled to the power supply at least through the second interconnect line; The second end of the temperature measuring device is coupled to the first ground terminal of the voltage regulator at least through the third interconnect line.

7. The semiconductor temperature measuring device according to claim 1, characterized in that, The semiconductor temperature measuring device includes: An antenna is located at the center of the first wafer and the second wafer; the antenna is coupled to the main controller; The semiconductor temperature measuring device includes a plurality of temperature measuring circuits, and the temperature measuring devices included in the plurality of temperature measuring circuits are arranged at intervals in the circumferential direction surrounding the antenna. The multiple temperature measuring devices of the temperature measuring circuit are arranged at intervals along the radial direction of the first wafer.

8. The semiconductor temperature measuring device according to claim 1, characterized in that, The semiconductor temperature measuring device also includes: Multiple conductive pillars are located between the first conductive layer and the second conductive layer; the multiple conductive pillars are located between the outer edge of the temperature sensing component and the side edge of the first wafer; each of the conductive pillars is coupled to the first conductive layer and the second conductive layer.

9. The semiconductor temperature measuring device according to claim 8, characterized in that, At least one of the first wafer and the second wafer has a groove for accommodating at least a portion of the temperature sensing component; The first conductive layer extends into the inner wall of the groove; the capacitor structure is located in the corresponding groove, and the first electrode is coupled to the first conductive layer on the inner wall of the groove.

10. The semiconductor temperature measuring device according to claim 8, characterized in that, The capacitor structure is symmetrically distributed on the outside of the electrical appliance of the temperature sensing component; and / or, The capacitor structure is arranged at intervals around the circumferential direction of the electrical appliance; wherein, the electrical appliance of the temperature measuring component includes at least one of the temperature measuring device, the power supply, the main controller, and the voltage regulator.

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