A method for fabricating a semiconductor structure and the semiconductor structure.

Abstract

This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself. The method includes providing a substrate comprising multiple fin structures and an isolation structure. The fin structures in the region to be processed include predetermined sub-parts protruding from the isolation structure. A first dielectric layer is formed, and a sacrificial merging structure is formed. A sacrificial epitaxial layer covers the top of the first dielectric layer and the predetermined sub-parts, and covers the upper sidewalls of the predetermined sub-parts. The sacrificial epitaxial layers located on adjacent predetermined sub-parts are merged and connected in the region between adjacent regions to be processed. A second dielectric layer is formed, covering the surface and peripheral region of the sacrificial merging structure. A groove structure is formed, and the sacrificial merging structure, a portion of the first dielectric layer, and a portion of the second dielectric layer are removed. The remaining first dielectric layer is located at least around the groove structure, and the second dielectric layer is located in the peripheral region of the orthographic projection of the sacrificial merging structure onto the substrate. The tops of the first and second dielectric layers are higher than the upper surface of the groove structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and in particular to a method for preparing a semiconductor structure and the semiconductor structure thereof. Background Technology

[0002] With the development and advancement of technology, semiconductor devices are constantly evolving towards miniaturization and high integration, resulting in increasingly smaller device sizes. In some semiconductor devices with shorter channel lengths, the gate's control over the channel weakens. To improve this control, researchers have developed 3D transistors and multi-channel transistor structures to enhance gate control over the channel.

[0003] However, there are still many problems in the fabrication process of semiconductor devices that need to be improved. Summary of the Invention

[0004] This disclosure provides a method for fabricating a semiconductor structure. The method includes providing a substrate, forming a first dielectric layer at least on the lower sidewall of a predetermined sub-part, forming a sacrificial merging structure, forming a second dielectric layer covering the surface and peripheral area of ​​the sacrificial merging structure, removing at least a portion of the predetermined sub-part to form a groove structure, and removing the sacrificial merging structure, a portion of the first dielectric layer, and a portion of the second dielectric layer.

[0005] The substrate includes a plurality of fin-like structures extending along a first direction and isolation structures located between the fin-like structures. Each fin-like structure includes a processing region for forming source / drain regions. The fin-like structures in the processing regions include predetermined sub-portions protruding from the isolation structures. The first direction is parallel to the plane of the substrate.

[0006] The sacrificial merging structure includes a sacrificial epitaxial layer. The sacrificial epitaxial layer covers the top of the first dielectric layer and the preset sub-part, as well as the upper sidewall of the preset sub-part, and the sacrificial epitaxial layers located on adjacent preset sub-parts are merged and connected in the region between adjacent areas to be processed.

[0007] The remaining first dielectric layer is located at least around the groove structure. The second dielectric layer is located in the peripheral region of the orthogonal projection of the sacrificial merging structure onto the substrate. The tops of the first and second dielectric layers are higher than the upper surface of the groove structure.

[0008] In some embodiments, the second direction is parallel to the plane of the substrate and intersects the first direction. The portion of the first dielectric layer between adjacent areas to be processed along the second direction is defined as a predetermined segment. A second dielectric layer is formed covering the surface and peripheral region of the sacrificial merging structure, specifically including a second dielectric layer forming sidewalls covering the predetermined segment of the first dielectric layer, the surface of the sacrificial merging structure, and the isolation structure.

[0009] In some embodiments, at least a portion of the preset sub-parts is removed to form a groove structure, and a sacrificial merging structure is removed. The portion of the first dielectric layer and the portion of the second dielectric layer further include performing an etching process and removing the sacrificial merging structure, a portion of the height of the first dielectric layer, a portion of the height of the second dielectric layer, and removing the second dielectric layer located on the surface of the isolation structure.

[0010] During the etching process, at least a portion of the predetermined sub-section of the fin structure is removed to form a groove structure. The retained first dielectric layer is located at least around the groove structure, and the retained second dielectric layer is located on the sidewall of the predetermined section.

[0011] In some embodiments, a substrate is provided, the substrate including a plurality of fin structures extending along a first direction and an isolation structure located between the fin structures, further including providing a substrate, performing an etching process on the substrate and filling an isolation material to form an isolation structure between the fin structures.

[0012] During the etching process on the substrate, a portion of the substrate is removed to form fin-like structures on the substrate. The fin-like structures protrude from the surface of the isolation structure.

[0013] In some embodiments, after providing a substrate and before forming a first dielectric layer, the method further includes forming a gate material layer, forming a mask layer, and etching the gate material layer using the mask layer as a mask to form a gate structure.

[0014] The gate material layer covers the surfaces of the fin structure and the isolation structure.

[0015] The mask layer includes a first mask layer and a second mask layer from bottom to top.

[0016] The gate structure spans the fin structure, and the regions on both sides of the gate structure constitute the processing area.

[0017] In some embodiments, prior to forming the gate structure, the method further includes forming an oxide material layer that covers the surfaces of the fin structure and the isolation structure.

[0018] In the same process of etching the gate material layer using the mask layer as a mask to form the gate structure, the method also includes etching the oxide material layer to remove part of the oxide material layer to form the gate oxide layer. The gate oxide layer is located between the gate structure and the fin structure, and the surfaces of the gate oxide layer and the gate structure on the same side of the area to be processed are flush with each other.

[0019] In some embodiments, forming a first dielectric layer on the lower sidewall of a preset sub-part further includes: forming a first dielectric material layer and performing an etching process.

[0020] The first dielectric material layer covers the surfaces of the gate structure and the isolation structure, and also covers the surfaces of the fin structure that are not covered by the gate structure and the isolation structure.

[0021] In the etching process, the portion of the first dielectric material layer located at the top and part of the sidewalls of the mask layer is removed, and the portion of the first dielectric material layer located at the top and part of the sidewalls of the preset sub-part is also removed, and the remaining first dielectric material layer constitutes the first dielectric layer; wherein, the top of the first dielectric layer is not lower than the upper surface of the first mask layer.

[0022] In some embodiments, after removing the preset sub-parts of the fin structure, the sacrificial merging structure, a portion of the first dielectric layer and a portion of the second dielectric layer, the method further includes forming an epitaxial layer that fills the groove structure and merges adjacent regions to be processed to form a merged structure, the merged structure being used as a source / drain region.

[0023] In some embodiments, the first dielectric layer comprises at least a material composed of silicon, carbon, and nitrogen, and the second dielectric layer comprises a nitride material.

[0024] This disclosure also provides a semiconductor structure, which includes a substrate, a first dielectric layer, and a second dielectric layer.

[0025] The substrate includes a plurality of fin-like structures extending along a first direction and an isolation structure located between the fin-like structures, wherein conductive structures are disposed on the fin-like structures; wherein the first direction is parallel to the plane of the substrate.

[0026] The first dielectric layer is located at least around the conductive structure; the portion of the first dielectric layer excluding the portion located between adjacent conductive structures in the second direction is defined as a predetermined segment. The second direction, a plane parallel to the substrate, intersects the first direction.

[0027] The second dielectric layer is located on the sidewall of a predetermined section of the first dielectric layer.

[0028] In some embodiments, adjacent conductive structures are interconnected along the second direction to form a merged structure, which is used as a source / drain region.

[0029] The semiconductor structure fabrication method and semiconductor structure provided in this disclosure include: providing a substrate; forming a first dielectric layer at least on the lower sidewall of a predetermined sub-section; forming a sacrificial merging structure; forming a second dielectric layer covering the surface and peripheral region of the sacrificial merging structure; removing at least a portion of the predetermined sub-section to form a groove structure; and removing the sacrificial merging structure, a portion of the first dielectric layer, and a portion of the second dielectric layer. The substrate includes a plurality of fin-like structures extending along a first direction and an isolation structure located between the fin-like structures. Each fin-like structure includes a region to be processed for forming source / drain regions. Each fin-like structure in the region to be processed includes a predetermined sub-section protruding from the isolation structure. The first direction is parallel to the plane of the substrate. The sacrificial merging structure includes a sacrificial epitaxial layer. The sacrificial epitaxial layer covers the top of the first dielectric layer and the predetermined sub-section, and covers the upper sidewall of the predetermined sub-section. Sacrificial epitaxial layers on adjacent predetermined sub-sections are merged and connected in the region between adjacent regions to be processed. The remaining first dielectric layer is located at least around the groove structure. The second dielectric layer is located in the peripheral region of the orthographic projection of the sacrificial merging structure onto the substrate. The tops of the first and second dielectric layers are higher than the upper surface of the groove structure.

[0030] As can be seen, in this embodiment of the present disclosure, after the formation of the first dielectric layer and before the formation of the second dielectric layer, a sacrificial merging structure is first formed. The sacrificial epitaxial layer includes a sacrificial epitaxial layer covering the top of the first dielectric layer, the top of the preset sub-part, and the upper sidewall of the preset sub-part. The sacrificial epitaxial layer on the preset sub-part merges and connects between adjacent areas to be processed. In this way, the area in the first direction and located between adjacent areas to be processed can be covered before the formation of the second dielectric layer. This makes it difficult for the second dielectric layer to grow in this area when it is formed later. As a result, after the steps of removing part of the preset sub-part to form a groove structure and removing the sacrificial merging structure, part of the first dielectric layer, and part of the second dielectric layer are completed, the material layer remaining in the area in the first direction and located between adjacent areas to be processed, i.e., between two adjacent fin structures, can have an ideal height. This avoids the situation in the traditional process where the second dielectric layer remaining in this area still has a large height, which can easily prevent the normal merging of the epitaxial structures subsequently grown on the adjacent areas to be processed. This allows the epitaxial structures subsequently grown on adjacent regions to be processed to achieve a good merging effect in the preparation method provided in this embodiment, thereby improving the performance of the final semiconductor structure.

[0031] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0034] Figure 2 and Figure 3 A process flow diagram of the method for preparing the fin-like structure provided in the embodiments of this disclosure;

[0035] Figures 4a to 10c A process flow diagram of a method for fabricating a semiconductor structure provided in this disclosure embodiment, wherein, Figure 4a , Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a and Figure 10a A top view schematic diagram of the semiconductor structure during the fabrication process provided in the embodiments of this disclosure; Figure 4b , Figure 5b , Figure 6b , Figure 7b , Figure 8b , Figure 9b and Figure 10b The semiconductor structure provided in the embodiments of this disclosure is fabricated along the following paths during the fabrication process: Figure 4a , Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a and Figure 10a A detailed sectional view taken along the A1-A2 direction; Figure 4c , Figure 5c , Figure 6c , Figure 7c , Figure 8c , Figure 9c and Figure 10c The semiconductor structure provided in the embodiments of this disclosure is fabricated along the following paths during the fabrication process: Figure 4a , Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a and Figure 10a Detailed sectional view taken along the B1-B2 direction. Detailed Implementation

[0036] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0037] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0038] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0039] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0040] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0042] In semiconductor structures, to improve device performance, epitaxial materials grown on two or more adjacent fin structures are often merged together. This merging requires the epitaxial materials to be grown as close as possible to the two or more fin structures. However, in conventional fabrication processes, the small distance between two or more fin structures makes it difficult to effectively remove the material layer in the region between adjacent fin structures. These residual material layers hinder the merging of epitaxial materials on adjacent fin structures.

[0043] Based on this, the technical solution of the present disclosure embodiment is proposed as follows:

[0044] This disclosure provides a method for fabricating a semiconductor structure, such as... Figure 1 The preparation method includes the following steps:

[0045] Step S101: Provide a substrate, the substrate including a plurality of fin structures extending along a first direction and an isolation structure located between the fin structures, the fin structures including a region to be processed for forming a source / drain region, the fin structure in the region to be processed including a preset sub-part protruding from the isolation structure; wherein, the first direction is parallel to the plane of the substrate;

[0046] Step S102: Form a first dielectric layer at least on the lower sidewall of the preset sub-part;

[0047] Step S103: Form a sacrificial merging structure, which includes a sacrificial epitaxial layer. The sacrificial epitaxial layer covers the top of the first dielectric layer and the preset sub-part and the upper sidewall of the preset sub-part. The sacrificial epitaxial layers located on adjacent preset sub-parts are merged and connected in the region between adjacent areas to be processed.

[0048] Step S104: Form a second dielectric layer covering the surface and peripheral area of ​​the sacrificial merging structure;

[0049] Step S105: Remove at least a portion of the preset sub-parts to form a groove structure, and remove the sacrificial merging structure, a portion of the first dielectric layer and a portion of the second dielectric layer. The remaining first dielectric layer is located at least around the groove structure, and the second dielectric layer is located in the outer region of the orthogonal projection of the sacrificial merging structure on the substrate. The tops of the first dielectric layer and the second dielectric layer are higher than the upper surface of the groove structure.

[0050] As can be seen, in this embodiment of the present disclosure, after the formation of the first dielectric layer and before the formation of the second dielectric layer, a sacrificial merging structure is first formed. The sacrificial epitaxial layer includes a sacrificial epitaxial layer covering the top of the first dielectric layer, the top of the preset sub-part, and the upper sidewall of the preset sub-part. The sacrificial epitaxial layer on the preset sub-part merges and connects between adjacent areas to be processed. In this way, before the formation of the second dielectric layer, the area between adjacent areas to be processed in the direction intersecting the first direction is covered, making it difficult for the second dielectric layer to grow in this area when it is formed later. Thus, after the steps of removing part of the preset sub-part to form the groove structure and removing the sacrificial merging structure, part of the first dielectric layer, and part of the second dielectric layer are completed, the material layer retained in the area between adjacent areas to be processed, i.e., between two adjacent fin structures, in the direction intersecting the first direction can have an ideal height. This avoids the situation in the traditional process where the second dielectric layer retained in this area still has a large height, which can easily prevent the normal merging of the epitaxial structures subsequently grown on the adjacent areas to be processed. This allows the epitaxial structures subsequently grown on adjacent regions to be processed to achieve a good merging effect in the preparation method provided in this embodiment, thereby improving the performance of the final semiconductor structure.

[0051] It should be understood that, although Figure 1 The steps are shown sequentially as indicated by the arrows, but they are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are performed; they can be executed in other orders. Figure 1At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0052] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0053] Figure 2 and Figure 3 A process flow diagram of the method for preparing the fin-like structure provided in the embodiments of this disclosure; Figures 4a to 10c A process flow diagram of a method for fabricating a semiconductor structure provided in this disclosure embodiment, wherein, Figure 4a , Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a and Figure 10a A top view schematic diagram of the semiconductor structure during the fabrication process provided in the embodiments of this disclosure; Figure 4b , Figure 5b , Figure 6b , Figure 7b , Figure 8b , Figure 9b and Figure 10b The semiconductor structure provided in the embodiments of this disclosure is fabricated along the following paths during the fabrication process: Figure 4a , Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a and Figure 10a A detailed sectional view taken along the A1-A2 direction; Figure 4c , Figure 5c , Figure 6c , Figure 7c , Figure 8c , Figure 9c and Figure 10c The semiconductor structure provided in the embodiments of this disclosure is fabricated along the following paths during the fabrication process: Figure 4a , Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a and Figure 10a Detailed sectional view taken along the B1-B2 direction.

[0054] It should be noted that, in order to clearly illustrate the interaction between the gate structure 16 located below the mask layer 17 and the other material layers formed, in Figure 4a , Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a and Figure 10a The mask layer 17 is omitted in both cases.

[0055] The preparation method provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings.

[0056] First, execute step S101, as follows: Figure 2 and Figure 3 As shown, where, Figure 3 Figure (a) is a schematic diagram of the structure of the fin-like structure 11 formed on the substrate 101 and the isolation structure 12 located between the fin-like structures 11 provided in the embodiment of this disclosure. Figure 3 Figure (b) is a top view of a fin structure 11 formed on a substrate 101 and an isolation structure 12 located between the fin structures 11, according to an embodiment of the present disclosure. A substrate 10 is provided, which includes a plurality of fin structures 11 extending along a first direction and an isolation structure 12 located between the fin structures 11. Each fin structure 11 includes a processing region A for forming a source / drain region. The fin structure 11 in the processing region A includes a predetermined sub-part P protruding from the isolation structure 12. The first direction is parallel to the plane of the substrate 10.

[0057] In some embodiments, a substrate 10 is provided, the substrate 10 including a plurality of fin structures 11 extending along a first direction and an isolation structure 12 located between the fin structures 11, specifically including the following steps.

[0058] A substrate 101 is provided, and an etching process is performed on the substrate 101 to remove a portion of the substrate 101 to form fin-like structures 11 on the substrate 101. An isolation material is then filled to form an isolation structure 12 between the fin-like structures 11. The fin-like structures 11 protrude from the surface of the isolation structure 12.

[0059] Here, substrate 101 can be a semiconductor substrate. The materials of the semiconductor substrate specifically include elemental semiconductor materials (e.g., silicon (Si) substrate, germanium (Ge) substrate, etc.), or III-V compound semiconductor materials (e.g., gallium nitride (GaN) substrate, gallium arsenide (GaAs) substrate, indium phosphide (InP) substrate, etc.), or II-VI compound semiconductor materials, or organic semiconductor materials, or other semiconductor materials known in the art. In a specific embodiment, substrate 101 is a silicon substrate.

[0060] In addition to the methods described above, in other embodiments, the fin structure 11 and the isolation structure 12 can also be obtained by forming a material layer on the substrate 101. Specifically, the choice can be made flexibly according to the actual situation, and no specific limitation is made here.

[0061] In actual operation, the materials involved in forming the fin structure 11 and the isolation structure 12 can be grown using one or more thin film deposition processes. Specifically, the thin film deposition processes include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or combinations thereof.

[0062] Next, proceed to step S102, as follows: Figures 5a to 6c As shown, a first dielectric layer 13 is formed at least on the lower sidewall of the preset sub-part P.

[0063] In some embodiments, such as Figures 4a to 4c As shown, after providing the substrate 10 and before forming the first dielectric layer 13, the fabrication method further includes:

[0064] A gate material layer (not shown) is formed, which covers the surfaces of the fin structure 11 and the isolation structure 12.

[0065] A mask layer 17 is formed, which includes a first mask layer 171 and a second mask layer 172 from bottom to top;

[0066] The gate material layer (not shown) is etched using the mask layer 17 as a mask to form the gate structure 16. The gate structure 16 spans the fin structure 11, and the regions on both sides of the gate structure 16 constitute the processing area A.

[0067] In some embodiments, the material of the gate structure 16 may include, but is not limited to, at least one or a combination of polysilicon, a barrier material, and a conductive metal. The barrier material may include, but is not limited to, titanium nitride, and the conductive metal may include, but is not limited to, tungsten.

[0068] In this embodiment of the disclosure, the gate structure 16 covers the top and two sidewalls of the fin structure 11, that is, it surrounds it on three sides. This helps to enhance the gate structure 16's control over the channel region in the final semiconductor structure, prevent the occurrence of short-channel effects, and help to improve the performance of the final semiconductor structure.

[0069] In some embodiments, the material of the first mask layer 171 includes, but is not limited to, silicon nitride, and the material of the second mask layer 172 includes, but is not limited to, silicon oxide.

[0070] Continue to refer to Figures 4a to 4c In some embodiments, the fabrication method further includes, prior to forming the gate structure 16:

[0071] An oxide material layer (not shown) is formed, which covers the surfaces of the fin structure 11 and the isolation structure 12.

[0072] In the same process of etching the gate material layer (not shown) using mask layer 17 as a mask to form the gate structure 16, the fabrication method also includes:

[0073] The oxide material layer (not shown) is etched to remove part of the oxide material layer (not shown) to form the gate oxide layer 15. The gate oxide layer 15 is located between the gate structure 16 and the fin structure 11, and the surfaces of the gate oxide layer 15 and the gate structure 16 on the same side of the area to be processed A are flush with each other.

[0074] In some embodiments, the material of the gate oxide layer 15 may include, but is not limited to, at least one or a combination of low dielectric constant materials or high dielectric constant materials.

[0075] In practice, the material of the gate oxide layer 15 may include, but is not limited to, oxides. However, it is not limited to this. In some embodiments, the material of the gate oxide layer 15 may also include high-K dielectric materials, which may include, but are not limited to, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO2), hafnium silicon oxide (HfSixOy), hafnium silicon nitride oxide (HfSiON), hafnium zirconate (HfZrO4), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy), and / or praseodymium oxide (Pr2O3), etc.

[0076] Continue to refer to Figures 5a to 6c In some embodiments, a first dielectric layer 13 is formed on the lower sidewall of the preset sub-part P, comprising:

[0077] A first dielectric material layer 13a is formed, which covers the surfaces of the gate structure 16 and the isolation structure 12, and also covers the surface of the fin structure 11 that is not covered by the gate structure 16 and the isolation structure 12.

[0078] An etching process is performed to remove the portion of the first dielectric material layer 13a located at the top and part of the sidewalls of the mask layer 17, and to remove the portion of the first dielectric material layer 13a located at the top and part of the sidewalls of the preset sub-part P. The remaining first dielectric material layer 13a constitutes the first dielectric layer 13. The top of the first dielectric layer 13 is not lower than the upper surface of the first mask layer 171.

[0079] In some embodiments, such as Figure 6b As shown, during the removal of the first dielectric layer 13a located on top of the preset sub-part P, a portion of the material in the top region of the preset sub-part P can also be removed. This facilitates the complete removal of the first dielectric material layer 13a located on top of the preset sub-part P, and also helps the sacrificial epitaxial layer E formed in the subsequent step S103 to be smoothly merged and connected in the region between adjacent areas to be processed A.

[0080] In some embodiments, the first dielectric layer 13 comprises at least a material composed of silicon, carbon, and nitrogen.

[0081] However, this is not the only one. In some embodiments, the first dielectric layer 13 may also contain oxygen. In this case, the material used for the first dielectric layer 13 may include a material composed of silicon, oxygen, carbon and nitrogen.

[0082] In some embodiments, the first dielectric layer 13 may consist of only a single material layer.

[0083] However, it is not limited to this and may also consist of multiple material layers. For example, in some specific embodiments, the first dielectric layer may include a silicon carbide (SiCN) layer adjacent to the gate structure 16 and a silicon carbon oxide (SiOCN) layer away from the gate structure 16.

[0084] Understandably, the formation of the first dielectric layer 13 can create good electrical isolation between adjacent gate structures 16 and between the gate structure 16 and the source / drain regions ultimately formed on the region to be processed A.

[0085] Understandably, the first dielectric layer 13 can provide electrical isolation at multiple locations, enabling the final semiconductor structure to have good electrical performance.

[0086] In some embodiments, the portion of the first dielectric layer 13 excluding the area between adjacent regions A to be processed in the second direction is defined as a preset segment C; wherein, the second direction is parallel to the plane of the substrate 10 and intersects the first direction.

[0087] In this embodiment of the disclosure, the defined preset segment C may include: all remaining portions of the first dielectric layer 13 except for the portion located between adjacent regions A to be processed in the second direction. In subsequent process steps, the portion located between adjacent regions A to be processed will be protected to a certain extent, which can suppress the formation of the second dielectric layer 14 at that location to a large extent. In this way, it will help the epitaxial layers finally formed on the adjacent regions A to be processed to be successfully merged, so as to obtain a semiconductor structure with good electrical performance.

[0088] In addition, in this embodiment of the present disclosure, the arrangement that the top of the first dielectric layer 13 is not lower than the upper surface of the first mask layer 171 can help protect the surface of the gate structure 16 located below the first mask layer 171 from the influence of the etching solution during subsequent etching operations, thereby helping the final gate structure 16 to have good integrity to achieve good electrical performance.

[0089] Next, proceed to step S103, as follows: Figure 7a , Figure 7b and Figure 7c As shown, a sacrificial merging structure La is formed. The sacrificial merging structure La includes a sacrificial epitaxial layer E. The sacrificial epitaxial layer E covers the top of the first dielectric layer 13 and the upper sidewall of the preset sub-part P. The sacrificial epitaxial layers E located on adjacent preset sub-parts P are merged and connected in the region between adjacent areas to be processed A.

[0090] In some embodiments, the process for forming the sacrificial epitaxial layer E can be a selective epitaxial growth process.

[0091] Understandably, due to the selectivity of epitaxial growth, a physical isolation material layer needs to be formed on the sidewalls of the gate structure before the epitaxial process, and an electrical isolation layer needs to be formed between the gate structure and other conductive structures. Therefore, during the fabrication of the semiconductor structure, it is necessary to perform the operations of forming a first dielectric layer and a second dielectric layer on the sidewalls of the gate structure. Simultaneously, due to the small distance between adjacent fin structures and the existence of many situations that prevent the epitaxial material on adjacent fin structures from merging together, the material of the second dielectric layer deposited after the formation of the first dielectric layer will merge between adjacent fin structures (equivalent to the processing area in this embodiment). This makes it extremely difficult for the plasma etching process to remove the second dielectric layer (such as silicon nitride) between adjacent fin structures, resulting in a larger second dielectric layer height compared to other locations after etching. This prevents the subsequent merging of the epitaxial silicon that is actually needed, affecting device performance.

[0092] In this embodiment, since a first dielectric layer 13 is formed on the lower sidewall of the preset sub-part P and the sidewall of the gate structure 16, and a mask layer 17 is provided on the top of the gate structure 16, the sacrificial epitaxial layer E is selectively epitaxially grown only on the sidewall and top of the preset sub-part P in the processing area A. When the sacrificial epitaxial layers E on adjacent processing areas A grow to a certain extent, they will merge. In this way, the desired sacrificial merged structure La can be obtained, which may include the portion covering the first dielectric layer 13 and the top and upper sidewall of the preset sub-part P, as well as the portion located between adjacent processing areas A.

[0093] Furthermore, as mentioned earlier, in conventional processes, without forming a sacrificial epitaxial layer, the formation of a second dielectric layer is performed immediately after the formation of the first dielectric layer. This results in a situation where, after the formation of the groove structure and the removal of part of the first and second dielectric layers are completed, a second dielectric layer with a relatively large height remains in the area between adjacent areas to be processed. This is because, during the formation of the second dielectric layer, due to its large thickness, the second dielectric layer located on the sidewalls of the two first dielectric layers in this area (the area between adjacent areas to be processed) is prone to merging. As a result of merging, the size of the second dielectric layer in this area will be significantly larger than that in other areas, making it difficult to remove the second dielectric layer in this area to the same height as in other areas under the same etching conditions.

[0094] In this embodiment of the disclosure, because the sacrificial merging structure La pre-masks the portion located between adjacent areas to be processed A in this step, the subsequent formation of the second dielectric layer 14 (attached) is performed more efficiently. Figure 8b During step S104), the second dielectric layer 14 may be difficult to form in the area between adjacent areas to be processed A, thus preventing the subsequent formation of the groove structure T (see Appendix for details). Figure 9b After step S105 and the step of removing part of the first dielectric layer 13 and the second dielectric layer 14, there is a situation where a relatively large height of the second dielectric layer 14 remains in the region located between adjacent areas to be processed A. Conversely, in this embodiment of the present disclosure, after the step of etching the first dielectric layer 13 and the second dielectric layer 14, the material layer remaining between adjacent areas to be processed A can have an ideal height dimension, which paves the way for the subsequent formation of a true source / drain merging structure L (see appendix for details). Figure 10cThis provides favorable conditions for the smooth merging of epitaxial materials on adjacent regions A to be processed. Simultaneously, the second dielectric layer 14, retained in the peripheral region of the sacrificial epitaxial layer La, can also have a suitable height, effectively performing its electrical isolation function and improving the performance of the final semiconductor structure.

[0095] In some embodiments, the number of regions A to be processed where the epitaxial material used to form the merged structure L is located can be multiple, such as 2, 3, 4 or even more. Specifically, the selection can be made flexibly according to the actual situation, and no specific limitation is made here.

[0096] In some specific embodiments, the number of regions A to be processed, where the epitaxial material used to form the merged structure L is located, can be two.

[0097] Understandably, the merged structure L (which can be used as a source / drain region), the single fin structure 11, and the portion of the gate structure located on the fin structure 11 can together constitute a transistor structure. Forming the merged structure L by forming epitaxial material is commonly used to merge a single fin structure 11 belonging to a single transistor, providing sufficient epitaxial material in the source and drain, and relaxing requirements on the contact setup process.

[0098] Then, proceed to step S104, as follows: Figures 8a to 8c As shown, a second dielectric layer 14 is formed covering the surface and peripheral region of the sacrificial merging structure La.

[0099] In some embodiments, a second dielectric layer 14 is formed covering the surface and peripheral region of the sacrificial merging structure La, including:

[0100] A second dielectric layer 14 is formed, covering the sidewalls of the predetermined section C of the first dielectric layer 13, the surface of the sacrificial merging structure La, and the isolation structure 12.

[0101] In some embodiments, the second dielectric layer 14 includes a nitride material, such as silicon nitride or other nitride materials.

[0102] In some embodiments, the thickness of the second dielectric layer 14 may be greater than the thickness of the first dielectric layer 13. The first dielectric layer 13 and the thicker second dielectric layer 14 can provide good electrical isolation for the semiconductor structure, including but not limited to providing good electrical isolation at locations such as, for example, between adjacent gate structures 16, and between the gate structure 16 and the source / drain regions ultimately formed on the region to be processed A.

[0103] Finally, proceed with step S105, as follows: Figures 9a to 9cAs shown, at least a portion of the preset sub-part P is removed to form the groove structure T, and the sacrificial merging structure La, a portion of the first dielectric layer 13 and a portion of the second dielectric layer 14 are removed. The remaining first dielectric layer 13 is located at least around the groove structure T, and the second dielectric layer 14 is located in the outer region of the orthographic projection of the sacrificial merging structure La onto the substrate 10. The tops of the first dielectric layer 13 and the second dielectric layer 14 are higher than the upper surface of the groove structure T.

[0104] In some embodiments, the removal of the preset sub-part P when forming the groove structure T can include various cases. For example, the entire preset sub-part P can be removed to form the groove structure T, or a portion of the preset sub-part P can be removed to form the groove structure T. Specifically, the choice can be made flexibly according to the actual situation, and no specific limitation is made here.

[0105] In any of the above embodiments, at least a portion of the preset sub-part P is removed to form the groove structure T, and the sacrificial merging structure La, a portion of the first dielectric layer 13, and a portion of the second dielectric layer 14 are removed, including:

[0106] An etching process is performed to remove at least a portion of the preset sub-part P of the fin structure 11 to form a groove structure T; the sacrificial merging structure La, a portion of the height of the first dielectric layer 13, a portion of the height of the second dielectric layer 14, and the second dielectric layer 14 located on the surface of the isolation structure 12 are removed. The remaining first dielectric layer 13 is located around the groove structure T, and the remaining second dielectric layer 14 is located on the sidewall of the preset section C.

[0107] Understandably, in this embodiment, because the pre-formed sacrificial merging structure La covers the area between adjacent processing areas A in step S103, the probability of forming the second dielectric layer 14 in the area between adjacent processing areas A is greatly reduced in step S104. Therefore, after performing the formation of the groove structure T and the removal of part of the first dielectric layer 13 and part of the second dielectric layer 14, the material layer in this area can be etched to a lower height, providing good growth space for the subsequently formed epitaxial material. This process technology can effectively improve the problem of epitaxial material layers not merging and improve device performance.

[0108] In other words, in this embodiment of the present disclosure, after step S105, the dielectric layer in the region between adjacent regions A to be processed can have a lower height dimension, thereby providing a good precondition for the merging of epitaxial materials located on adjacent regions A to be processed in the subsequent epitaxial growth process to obtain source / drain regions, which is beneficial to improving the performance of the final semiconductor structure.

[0109] In some embodiments, such as Figures 10a to 10c As shown, after removing the pre-defined sub-part P, the sacrificial merging structure La, a portion of the first dielectric layer 13, and a portion of the second dielectric layer 14 from the fin structure 11, the fabrication method further includes:

[0110] An epitaxial layer is formed, and the epitaxial layer fills the groove structure T to form a conductive structure 18. During the process, the conductive structures 18 will be merged and connected between adjacent areas to be processed A, that is, the conductive structures 18 at this location will be interconnected to form a merged structure L, which is used as a source / drain region.

[0111] In some embodiments, the materials of the merging structure L and the sacrificial merging structure La may be the same or different. In some specific embodiments, the merging structure L may comprise at least one of epitaxially stressed silicon material, germanium material, or silicon-germanium material.

[0112] Because the fabrication method provided in this disclosure can achieve a good merging effect on the source / drain regions on adjacent regions to be processed A, and the method of forming a merged structure L by forming epitaxial material is typically used to merge a single fin structure 11 belonging to a single transistor, sufficient epitaxial material can be provided in the source and drain, allowing for a wide range of selectable settings for various process parameters in the process steps of forming the contact structure, which helps to obtain a contact structure with good performance. In addition, the source / drain regions with good merging effect and the contact structure with good performance also help to improve the performance of the final semiconductor structure.

[0113] Furthermore, it should be noted that, in this embodiment of the disclosure, in order to clearly illustrate the relationship between the gate structure 16 located below the mask layer 17 and the other material layers formed, Figure 4a , Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a and Figure 10a The middle mask layer 17 is not shown.

[0114] This disclosure also provides a semiconductor structure, such as... Figure 9c and Figure 10c As shown, the semiconductor structure includes:

[0115] The substrate 10 includes a plurality of fin structures 11 extending along a first direction and an isolation structure 12 located between the fin structures 11. A conductive structure 18 is disposed on the fin structure 11.

[0116] A first dielectric layer 13 is located at least around the conductive structure 18; the portion of the first dielectric layer 13 excluding the portion between adjacent conductive structures 18 in the second direction is defined as a predetermined segment C; wherein the plane of the second direction parallel to the substrate 10 intersects the first direction;

[0117] The second dielectric layer 14 is located on the sidewall of the preset section C of the first dielectric layer 13.

[0118] In some embodiments, the second direction may be perpendicular to the extension direction of the fin structure 11, but is not limited thereto. Other appropriate angles may also be present between them. In particular, they may be flexibly selected according to the actual situation, and no specific limitation is made here.

[0119] As can be seen in this embodiment, the region where the conductive structure 18 is located on the fin structure 11 is regarded as the region to be processed, because a sacrificial merging structure La is pre-formed on the region originally intended to form the merging structure L before the merging structure L and the second dielectric layer 14 are formed (see appendix for details). Figure 7b and attached Figure 7c Because of this, the probability of the second dielectric layer 14 being formed subsequently growing between adjacent regions A is greatly reduced. This allows the material layer remaining between adjacent regions A to have an ideal height dimension after the etching steps to form the first dielectric layer 13 and the second dielectric layer 14 are completed. This provides a good prerequisite for the subsequent formation of a true merged structure L for the source / drain region, allowing the epitaxial material to grow normally in this region. When the epitaxial material grown on the region A reaches an extremely close degree, a merged structure with a merging effect can be obtained.

[0120] Continue to refer to Figure 10c In some embodiments, adjacent conductive structures 18 are interconnected along the second direction to form a merged structure L, which is used as a source / drain region.

[0121] Forming a merged structure L by forming epitaxial material is typically used to merge individual fin structures 11 belonging to a single transistor. Sufficient epitaxial material can be provided in the source and drain, allowing for a wider range of choices in the process parameters during the contact structure formation step, thus contributing to obtaining a high-performance contact structure. Furthermore, a well-merged source / drain region and a high-performance contact structure also contribute to improving the performance of the final semiconductor structure.

[0122] It should be noted that the semiconductor structure and its fabrication method provided in this disclosure can be applied to any semiconductor device including this structure, and no further limitations are imposed here. The embodiments of the semiconductor device fabrication method provided in this disclosure and the embodiments of the semiconductor device belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.

[0123] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The preparation method includes: A substrate is provided, the substrate including a plurality of fin-like structures extending along a first direction and an isolation structure located between the fin-like structures, the fin-like structures including a region to be processed for forming a source / drain region, the fin-like structure in the region to be processed including a predetermined sub-portion protruding from the isolation structure; wherein, the first direction is parallel to the plane of the substrate; A first dielectric layer is formed, at least on the lower sidewall of the preset sub-part; A sacrificial merging structure is formed, the sacrificial merging structure including a sacrificial epitaxial layer, the sacrificial epitaxial layer covering the top of the first dielectric layer and the preset sub-part and covering the upper sidewall of the preset sub-part, and the sacrificial epitaxial layers located on adjacent preset sub-parts are merged and connected in the region between adjacent regions to be processed; A second dielectric layer is formed covering the surface and peripheral area of ​​the sacrificial merging structure; At least a portion of the preset sub-parts is removed to form a groove structure, and the sacrificial merging structure, a portion of the first dielectric layer, and a portion of the second dielectric layer are removed. The remaining first dielectric layer is located at least around the groove structure, and the second dielectric layer is located in the peripheral region of the orthographic projection of the sacrificial merging structure onto the substrate. The tops of the first dielectric layer and the second dielectric layer are higher than the upper surface of the groove structure.

2. The preparation method according to claim 1, characterized in that, The second direction is parallel to the plane of the substrate and intersects the first direction. The portion of the first dielectric layer excluding the area between adjacent areas to be processed in the second direction is defined as a preset segment. Forming a second dielectric layer covering the surface and peripheral region of the sacrificial merging structure, comprising: A second dielectric layer is formed to cover the sidewalls of the predetermined section of the first dielectric layer, the surface of the sacrificial merging structure, and the isolation structure.

3. The preparation method according to claim 2, characterized in that, At least a portion of the preset sub-parts is removed to form a groove structure, and the sacrificial merging structure, a portion of the first dielectric layer, and a portion of the second dielectric layer are removed, including: An etching process is performed to remove at least a portion of the predetermined sub-parts of the fin structure to form a groove structure; the sacrificial merging structure, a portion of the first dielectric layer, a portion of the second dielectric layer, and the second dielectric layer located on the surface of the isolation structure are removed, with the remaining first dielectric layer located at least around the groove structure and the remaining second dielectric layer located on the sidewall of the predetermined section.

4. The preparation method according to claim 1, characterized in that, The substrate is provided, the substrate including a plurality of said fin structures extending along a first direction and said isolation structures located between said fin structures, including: Provide a base; An etching process is performed on the substrate to remove a portion of the substrate in order to form the fin structure on the substrate; An insulating material is filled to form an insulating structure between the fin-like structures, the fin-like structures protruding from the surface of the insulating structure.

5. The preparation method according to claim 1, characterized in that, After providing the substrate and before forming the first dielectric layer, the fabrication method further includes: A gate material layer is formed, which covers the surfaces of the fin structure and the isolation structure; A mask layer is formed, the mask layer comprising a first mask layer and a second mask layer from bottom to top; The gate material layer is etched using the mask layer as a mask to form a gate structure, the gate structure spanning the fin structure, and the regions located on both sides of the gate structure constitute the processing area.

6. The preparation method according to claim 5, characterized in that, Prior to forming the gate structure, the fabrication method further includes: An oxide material layer is formed, which covers the surfaces of the fin structure and the isolation structure; In the same process of etching the gate material layer using the mask layer as a mask to form the gate structure, the fabrication method further includes: The oxide material layer is etched to remove a portion of the oxide material layer to form a gate oxide layer. The gate oxide layer is located between the gate structure and the fin structure, and the surfaces of the gate oxide layer and the gate structure on the same side of the area to be processed are flush with each other.

7. The preparation method according to claim 5, characterized in that, The formation of the first dielectric layer on the lower sidewall of the preset sub-part includes: A first dielectric material layer is formed, which covers the surfaces of the gate structure and the isolation structure, and also covers the surfaces of the fin structure that are not covered by the gate structure and the isolation structure. An etching process is performed to remove the portion of the first dielectric material layer located at the top and part of the sidewalls of the mask layer, and to remove the portion of the first dielectric material layer located at the top and part of the sidewalls of the preset sub-part, leaving the remaining first dielectric material layer as the first dielectric layer; wherein the top of the first dielectric layer is not lower than the upper surface of the first mask layer.

8. The preparation method according to claim 1, characterized in that, After removing the predetermined sub-part of the fin structure, the sacrificial merging structure, a portion of the first dielectric layer, and a portion of the second dielectric layer, the fabrication method further includes: An epitaxial layer is formed, which fills the groove structure and merges adjacent regions to be processed to form a merged structure, which is used as the source / drain region.

9. The preparation method according to claim 1, characterized in that, The first dielectric layer comprises at least a material composed of silicon, carbon, and nitrogen, and the second dielectric layer comprises a nitride material.

10. A semiconductor structure, characterized in that, The semiconductor structure includes: The substrate includes a plurality of fin-like structures extending along a first direction and an isolation structure located between the fin-like structures, wherein conductive structures are disposed on the fin-like structures; wherein, the first direction is parallel to the plane of the substrate, and along a second direction, adjacent conductive structures are interconnected to form a merged structure, the merged structure being used as a source / drain region; A first dielectric layer is located at least around the conductive structure; the portion of the first dielectric layer excluding the portion between adjacent conductive structures in a second direction is defined as a predetermined segment; wherein the second direction is a plane parallel to the substrate that intersects the first direction; The second dielectric layer is located on the sidewall of the preset section of the first dielectric layer, and along the second direction, the second dielectric layer is not disposed between adjacent conductive structures in each of the conductive structures included in the merged structure.

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