Semiconductor structure and method of fabricating the same

Abstract

Embodiments of the present disclosure disclose a semiconductor structure and a manufacturing method thereof. The manufacturing method comprises: providing a substrate, the substrate comprising a semiconductor body; forming a sacrificial structure covering a partial region of the semiconductor body; the semiconductor body extending along a first direction and penetrating the sacrificial structure, the sacrificial structure extending along a second direction; the second direction intersecting the first direction; forming a first mask layer and a second mask layer covering at least a sidewall of the sacrificial structure, the sidewall extending along a third direction; the first mask layer being located between the sacrificial structure and the second mask layer; a plane formed by the first direction and the second direction intersecting the third direction; performing etching on the semiconductor body between at least partially adjacent sacrificial structures in the first direction to form a first recess; removing the second mask layer on the sidewall of the sacrificial structure to expose the first mask layer; and forming an active region in the first recess.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure and its fabrication method. Background Technology

[0002] In the fabrication processes of some semiconductor structures, particularly for 3D transistors and multi-channel field-effect transistors, the corresponding channel structure is formed first. The source and drain electrodes are then formed at the corresponding source and drain locations within the channel structure. However, this process can cause over-etching damage to other film layers, increasing the risk of leakage current and reducing fabrication yield. Therefore, there is still room for improvement in the fabrication processes of some semiconductor structures. Summary of the Invention

[0003] According to some aspects of embodiments of this disclosure, a method for fabricating a semiconductor structure is provided, comprising: providing a substrate, the substrate including a semiconductor body; forming a sacrificial structure covering a portion of the semiconductor body; the semiconductor body extending along a first direction and penetrating the sacrificial structure, the sacrificial structure extending along a second direction; the second direction intersecting the first direction; forming a first mask layer and a second mask layer at least covering sidewalls of the sacrificial structure, the sidewalls extending along a third direction; the first mask layer being located between the sacrificial structure and the second mask layer; a plane formed by the first direction and the second direction intersecting the third direction; performing etching on at least a portion of the semiconductor body adjacent to the sacrificial structure in the first direction to form a first groove; removing the second mask layer on the sidewall of the sacrificial structure to expose the first mask layer; and forming an active region in the first groove.

[0004] In some embodiments, the semiconductor body extends into the sacrificial structure at one end in the third direction, and a portion of the semiconductor body is located between two adjacent sacrificial structures; the fabrication method further includes: forming a first dielectric layer between the semiconductor body and the sacrificial structure, the first dielectric layer covering the semiconductor body; at least a portion of the first dielectric layer is covered by the sacrificial structure; the fabrication method further includes: penetrating the first dielectric layer between two adjacent sacrificial structures in the third direction; the penetrating first dielectric layer is located at the opening end of the first groove, and the penetrating first dielectric layer protrudes from the sidewall of the opening end of the first groove in the first direction.

[0005] In some embodiments, the first mask layer and the second mask layer are stacked in the third direction; the first mask layer covers the first dielectric layer between two adjacent sacrificial structures; the first mask layer is located between the first dielectric layer and the second mask layer in the third direction; the fabrication method further includes: penetrating the second mask layer and the first mask layer between two adjacent sacrificial structures in the first direction to expose the first dielectric layer.

[0006] In some embodiments, the first mask layer and the second mask layer cover the end of the sacrificial structure away from the semiconductor body; the fabrication method further includes: when the second mask layer penetrates between two adjacent sacrificial structures in the first direction, removing the second mask layer covering the end of the sacrificial structure away from the semiconductor body; when the first mask layer penetrates between two adjacent sacrificial structures in the first direction, removing the first mask layer covering the end of the sacrificial structure away from the semiconductor body.

[0007] In some embodiments, after the first mask layer extends through the first direction between two adjacent sacrificial structures, the remaining first mask layer forms a protrusion at one end near the first groove; the protrusion extends away from the sacrificial structure along the first direction.

[0008] In some embodiments, the method of forming the sacrificial structure includes: forming a sacrificial gate covering a portion of the semiconductor body; forming a first isolation structure at one end of the sacrificial gate away from the semiconductor body; and forming a second isolation structure covering a sidewall of the sacrificial gate extending in a third direction, the second isolation structure covering a sidewall of the first isolation structure extending in the third direction.

[0009] In some embodiments, the fabrication method further includes: removing the first isolation structure and the sacrificial gate to form a first trench, and forming a gate structure in the first trench.

[0010] In some embodiments, the manufacturing method further includes cleaning the sidewalls of the first groove during the removal of the second mask layer.

[0011] According to some aspects of embodiments of this disclosure, a semiconductor structure is provided, comprising: a semiconductor body extending along a first direction; a gate structure extending along a second direction intersecting the first direction, wherein the gate structure covers a portion of the semiconductor body; the semiconductor body extending through the gate structure along the first direction; a portion of the semiconductor body being located between two adjacent gate structures; a first dielectric layer being located between the semiconductor body and the gate structure, wherein at least a portion of the first dielectric layer is covered by the gate structure; and an active region being at least partially embedded in the semiconductor body; wherein the active region is located between two adjacent gate structures and exposed between two adjacent gate structures.

[0012] In some embodiments, the semiconductor structure further includes: at least a portion of the first dielectric layer covering a sidewall of the semiconductor body extending along the first direction; at least a portion of the first dielectric layer covering a portion of the active region in a third direction; and a plane formed by the first direction and the second direction intersecting the third direction.

[0013] This disclosure provides a method for fabricating a semiconductor structure, comprising forming a sacrificial structure covering a portion of a semiconductor body; the semiconductor body extending along a first direction and penetrating the sacrificial structure extending along a second direction, forming a first mask layer and a second mask layer that at least cover the sidewalls of the sacrificial structure extending along a third direction; the first mask layer being located between the sidewalls of the sacrificial structure and the second mask layer; etching is performed on the semiconductor body between two adjacent sacrificial structures in the first direction to form a first groove, removing the second mask layer on the sidewalls of the sacrificial structure to expose the first mask layer; an active region is formed in the first groove; the second mask layer and the first mask layer improve the blocking performance of the sacrificial structure during etching, reducing over-etching damage to the sacrificial structure; the second mask layer can reduce the etching damage of the first mask layer during etching, which is beneficial for maintaining the morphology and stability of the sacrificial structure and improving the fabrication yield. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment;

[0015] Figures 2 to 6 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment;

[0016] Figure 7 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0017] Figures 8 to 19 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0018] Figure 20 This is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0019] Figures 21 to 24 This is a schematic diagram illustrating another method for fabricating a semiconductor structure according to an embodiment of the present disclosure. Detailed Implementation

[0020] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0021] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. Spatial relation terms such as "below," "under," "below," "below," "above," "over," etc., are used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "below" or "under" or "below" other elements or features would be oriented "on" other elements or features. Therefore, the exemplary terms "below" and "under" can include both upper and lower orientations. The device may be oriented in other ways (rotated 90 degrees or other orientations) and the spatial description used herein shall be interpreted accordingly.

[0022] It should be understood that the phrases "some embodiments" or "an embodiment" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "some embodiments" or "an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0023] In some semiconductor structure fabrication processes that include transistors, the semiconductor body of the transistor can be formed first. The semiconductor body can be doped to define the source, drain, and channel regions of the transistor. The doping process can include, but is not limited to, diffusion, ion implantation, etc. A conductive layer is formed as the gate of the transistor. Depending on the connection and layout of the transistor, the continuous conductive layer can be cut to meet the needs of integrated circuit design.

[0024] In some embodiments, a sacrificial structure or sacrificial gate may be formed first, and then a conductive material may be used to replace the sacrificial structure to form the gate. In some embodiments, a conductive material may be deposited at the location where the gate is to be formed to form the gate.

[0025] In some embodiments, ion implantation can be performed on different regions of the semiconductor body to define source, drain, and channel regions. In other embodiments, a patterned mask layer is used as an etching mask to etch a portion of the semiconductor body, removing some semiconductor material to form a trench, in which source and drain electrodes are epitaxially grown. During the epitaxial process in the trench, a dopant gas, such as B2H6 or PH3, can be added to the process gas for epitaxial deposition to dope the semiconductor material during epitaxial growth, improving the doping uniformity of the source and drain electrodes; the source and drain electrodes may also be referred to as active regions, such as a first active region and a second active region. After forming the active regions in the trench, ion implantation can be performed on the active regions to further dope them to increase the doping concentration, or the active regions can be thermally treated to activate the doped elements and improve the diffusion uniformity of the doped elements; or the active regions can be plasma-treated to activate the doped elements and improve the diffusion uniformity of the doped elements. This disclosure provides a method for fabricating a semiconductor structure. The first direction mentioned below can be the x-direction illustrated in the figures, the second direction can be the y-direction, and the third direction can be the z-direction. The z-direction is the thickness direction or vertical direction of the device. The x-direction and the y-direction can intersect or be perpendicular to each other, and the xoy plane intersects or is perpendicular to the z-direction.

[0026] According to some aspects of embodiments of the present disclosure, a method for fabricating a semiconductor structure is provided, the method including: referring to... Figure 1As shown, a semiconductor body 110 extending along the x-direction is provided. The semiconductor body 110 may be a strip, ridge, fin, or protrusion structure protruding from a substrate, a semiconductor layer, or other material layer. The cross-sectional shape of the semiconductor body 110 in the yoz plane may include, but is not limited to: rectangle, triangle, or other regular or irregular polygons; and including circles, ellipses, or other regular or irregular arcs. Different regions of the semiconductor body 110 may be doped to form the source, drain, and channel of a transistor. The transistor may include, but is not limited to, a three-dimensional transistor, a multi-channel field-effect transistor, a vertical transistor, a planar transistor, or other types of transistors. This disclosure does not limit the type of transistor. Figure 1 Only one sacrificial structure 120 is shown as an example, but multiple sacrificial structures 120 arranged along the x-direction may also be included.

[0027] Reference Figure 1 As shown, a sacrificial structure 120 is formed to cover a portion of the semiconductor body 110. The sacrificial structure 120 extends along the y-direction and covers the protruding and exposed top surface and sidewalls of the semiconductor body 110. The semiconductor body 110 penetrates the bottom portion of the sacrificial structure 120 along the x-direction. A portion of the semiconductor body 110 is exposed relative to the sacrificial structure 120 between adjacent sacrificial structures 120. The semiconductor body 110 and the sacrificial structure 120 can be isolated by a first dielectric layer 101. The first dielectric layer 101 may exist only at the location where the semiconductor body 110 is covered by the sacrificial structure 120. The first dielectric layer 101 is covered by the semiconductor body 110 and... Figure 1 Not shown in the image.

[0028] Or, such as Figure 2 The first dielectric layer 101, as exemplified, may cover the protruding top surface and sidewalls of the semiconductor body 110, with a portion of the first dielectric layer 101 covered by the semiconductor body 110. Exemplarily, the cross-sectional shape of the semiconductor body 110 in the yoz plane may include, but is not limited to, a rectangle or approximately a rectangle. The top surface of the semiconductor body 110 and its two sidewalls in the y direction are covered by the first dielectric layer 101, which is covered by the sacrificial structure 120. The bottom surface of the semiconductor body 110 is not exposed and does not contact the sacrificial structure 120.

[0029] In some other embodiments, the semiconductor body 110 may be surrounded by a sacrificial structure 120 in a direction perpendicular to the x-direction. The sacrificial structure 120 surrounds the top and bottom surfaces of the semiconductor body 110 that are disposed opposite to each other in the z-direction, and surrounds the two sidewalls that are disposed opposite to each other in the y-direction. In this case, the first dielectric layer 101 located between the semiconductor body 110 and the sacrificial structure 120 surrounds the semiconductor body 110 in a direction perpendicular to the x-direction.

[0030] In some embodiments, at least a portion of the sacrificial structure 120 may be replaced with a conductive gate structure, the first dielectric layer 101 may serve as the gate dielectric layer of the transistor, and the gate structure may serve as the control gate of the transistor; the portion of the semiconductor body 110 covered by the sacrificial structure 120 may serve as the channel region of the transistor, and the portion of the semiconductor body 110 exposed after penetrating the sacrificial structure 120 along the x-direction, or located between two adjacent sacrificial structures 120 in the x-direction, may serve as the source and drain of the transistor, and the positions of the source and drain may be interchanged; the source and drain may be doped, and the channel region may be inverted by source doping.

[0031] In some other embodiments, the semiconductor body 110 portion between two adjacent sacrificial structures 120 can be etched to form a groove, and an active region can be epitaxially formed in the groove using the semiconductor body 110 as a seed layer, serving as the source and drain of the transistor; during epitaxial growth, a doping gas can be introduced to dope the active region, thereby increasing the diffusion uniformity of the doped elements in the active region.

[0032] In some embodiments, refer to Figure 2 As shown, it can be based on Figure 1 The semiconductor structure shown is deposited to form a first mask layer 102, which can cover... Figure 1 The exposed surfaces of the semiconductor structure shown, such as the first mask layer 102, can cover the top of the sacrificial structure 120 and the sidewalls extending along the z direction. The first mask layer 102 can also cover the top surface of the exposed semiconductor body 110 region between two adjacent sacrificial structures 120 and the sidewalls extending along the z direction. Figure 2 The example structure corresponds to Figure 1 A schematic diagram of the cross-sectional structure along the xoz plane at position AA' after covering the first mask layer 102. Figure 2 The example semiconductor body 110 may correspond to Figure 1 Semiconductor body 110, Figure 2 The example sacrifice structure 120 is Figure 1 The partial sacrificial structure 120 covers the top surface of the semiconductor body 110. Figure 2 A portion of the first dielectric layer 101 covering the top surface of the semiconductor body 110 is also shown. The portion of the first dielectric layer 101 covering the sidewalls of the semiconductor body 110 extending in the z-direction is not shown due to the cross-sectional direction.

[0033] For example, the constituent materials of the semiconductor body 110 may include, but are not limited to: elemental semiconductor materials (e.g., silicon, germanium), III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. For example, silicon, germanium, or silicon carbide. The constituent materials of the sacrificial structure 120 may include, but are not limited to, silicon, and the crystal form of silicon is not limited, such as polycrystalline silicon. The sacrificial structure 120 may include multi-layer materials. The constituent materials of the first dielectric layer 101 may include, but are not limited to: insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. The constituent materials of the first mask layer 102 may include, but are not limited to: silicon nitride, silicon oxide, silicon oxynitride, amorphous carbon, etc. For example, the mask layer material can be selected according to the different selectivity of different materials for etchants. For example, if the semiconductor body 110 is silicon and the first dielectric layer 101 is silicon oxide, the first mask layer 102 may include silicon nitride to increase the etch-blocking performance of the mask layer on the sacrificial structure 120 and reduce over-etching damage to the sacrificial structure 120.

[0034] Reference Figure 3 As shown, the first mask layer 102 portion between two adjacent sacrificial structures 120 in the x-direction is etched, and the first mask layer 102 portion between two adjacent sacrificial structures 120 is etched in the z-direction to expose the first dielectric layer 101. When etching through the first mask layer 102, the first mask layer 102 covering the top of the sacrificial structure 120 may be removed or not removed, as shown. Figure 4 The first mask layer 102 on top of the sacrificial structure 120 shown can be etched away. The etching process may include, but is not limited to, dry etching, wet etching, or a combination thereof.

[0035] Reference Figure 4 As shown, using the first mask layer 102 as an etching mask, the first dielectric layer 101 between two adjacent sacrificial structures 120 is etched, and the semiconductor body 110 below the first dielectric layer 101 is etched to form a groove 12. Before epitaxially growing the active region 131 in the groove 12, the groove 12 is cleaned to remove residual debris from the dry etching process, remove the oxide layer on the inner wall of the groove 12, provide a smoother and cleaner landing surface for epitaxial growth, improve the contact performance between the active region 131 and the semiconductor body 110, and reduce void defects and tip discharge. The cleaning process may include, but is not limited to, wet etching cleaning, dry plasma etching cleaning, or a combination thereof; the groove 12 may be cleaned multiple times to improve the cleaning yield. For example, the plasma concentration and bias bombardment power used in the dry plasma cleaning process of the groove 12 may be less than the corresponding parameters in the etching process of the groove 12.

[0036] Reference Figure 5As shown, an active region 131 is formed by epitaxy or deposition in the groove 12. The active region 131 can be doped during the epitaxy process or by ion implantation doping after the epitaxy is completed.

[0037] In some specific embodiments, in the case of Figure 4 When the groove 12 shown is cleaned, some etchants used to etch silicon oxide will etch the first dielectric layer 101 exposed in the groove 12, reducing the size of the first dielectric layer 101 in the x direction. This results in the gate structure formed by the subsequent replacement of the sacrificial structure 120 not having a large-sized first dielectric layer 101 to isolate it from the active region 131, causing leakage between the gate structure 141 and the active region 131. Alternatively, after the first dielectric layer 101 is over-etched, a gap appears between the gate structure 141 and the active region 131, causing leakage between the gate structure and the active region 131 or even direct contact between the gate structure and the active region 131, resulting in a shift in the transistor threshold voltage or even failure.

[0038] In some specific embodiments, such as Figure 6 It shows Figure 5 A schematic diagram of the cross-section at BB' on the xoy plane. Figure 6 In a partially enlarged schematic diagram of the first dielectric layer 101, the over-etched first dielectric layer 101 is insufficient to shield the end of the sacrificial structure 120 in the x-direction. That is, a portion of the end of the sacrificial structure 120 is not isolated from the active region 131 by the first dielectric layer 101. Subsequently, after replacing the sacrificial structure 120 with conductive material to form the gate structure, there is a risk of leakage between the gate structure and the active region 131. Furthermore, a gap 11 may exist between the first dielectric layer 101 and the active region 131. This gap 11 may be filled by conductive material during the formation of the gate structure 141, causing direct contact between the gate structure and the active region 131, leading to transistor failure and reduced device fabrication yield. In other specific embodiments, the first mask layer 102 may be damaged by over-etching, resulting in damage and instability to the sacrificial structure 120, causing uneven morphology and dimensions of the subsequent gate structure. In view of this, the present disclosure provides a method for fabricating a semiconductor structure, which reduces over-etching of the first dielectric layer 101, reduces leakage current between the gate structure and the active region 131, improves device fabrication yield, and maintains good stability. Figure 6 The semiconductor body 110 shown can serve as a channel region between the active regions 131.

[0039] According to some aspects of embodiments of this disclosure, Figure 7A method for fabricating a semiconductor structure is provided, the method comprising: providing a substrate including a semiconductor body; forming a sacrificial structure covering a portion of the semiconductor body; the semiconductor body extending along a first direction and penetrating the sacrificial structure, the sacrificial structure extending along a second direction; the second direction intersecting the first direction; forming a first mask layer and a second mask layer at least covering the sidewalls of the sacrificial structure, the sidewalls extending along a third direction; the first mask layer being located between the sacrificial structure and the second mask layer; a plane formed by the first direction and the second direction intersecting the third direction; performing etching on at least a portion of the semiconductor body adjacent to the sacrificial structure in the first direction to form a first groove; removing the second mask layer on the sidewall of the sacrificial structure to expose the first mask layer; and forming an active region in the first groove.

[0040] Specifically, refer to Figure 1 As shown, a semiconductor body 110 is formed on a substrate, which may be thinned or removed; a sacrificial structure 120 is formed covering a portion of the semiconductor body 110. The semiconductor body 110 extends along the x-direction and penetrates the sacrificial structure 120, while the sacrificial structure 120 extends along the y-direction. The y-direction may intersect or be perpendicular to the x-direction. Figure 8 The example structure can be corresponding to Figure 1 A schematic diagram showing the first mask layer 102 and the second mask layer 103 covering the area along position AA'. Figure 8 A portion of the first dielectric layer 101 covering the top surface of the semiconductor body 110 is also shown. The portion of the first dielectric layer 101 covering the sidewalls of the semiconductor body 110 extending in the z-direction is not shown due to the orientation of the cross-sectional view.

[0041] Reference Figure 8 As shown, a first mask layer 102 and a second mask layer 103 are formed to at least cover the sidewalls of the sacrificial structure 120 extending in the z-direction. The first mask layer 102 and the second mask layer 103 may be formed by selective deposition on the sacrificial structure 120. Alternatively, the first mask layer 102 may be formed as follows: Figure 2 The sidewalls of the sacrificial structure 120 and the first dielectric layer 101 covering the space between adjacent sacrificial structures 120 are shown, as... Figure 3 The diagram shows the removal of the first mask layer 102 between two adjacent sacrificial structures 120. A second mask layer 103 formed on the first mask layer 102 can cover the first dielectric layer 101 between the two adjacent sacrificial structures 120. Then, the second mask layer 103 between the two adjacent sacrificial structures 120 is removed to form... Figure 8 The second mask layer 103 is shown.

[0042] Reference Figure 9As shown, the first dielectric layer 101 between two adjacent sacrificial structures 120 is etched to penetrate the first dielectric layer 101; the semiconductor body 110 below the first dielectric layer 101 is etched to form a first groove 13, which may not completely penetrate the semiconductor body 110 in the z direction.

[0043] Reference Figure 10 As shown, a cleaning process is performed on the first groove 13, and the second mask layer 103 is removed; after the second mask layer 103 is removed, it can be epitaxially or deposited in the first groove 13 to form Figure 11 The removal of the second mask layer 103 in the active region 131 shown can increase the gas channel for epitaxial process gases to enter the first groove 13, which is beneficial to expanding the epitaxial process window. Figure 11 The shape of the active region 131 shown is merely an example. The upper surface of the active region 131 may protrude from, be flush with, or be lower than the first dielectric layer 101. The cross-sectional shape of the active region 131 in the xoz plane may include, but is not limited to, a circle, an ellipse, an arc, or other irregular shapes, or a shape composed of straight lines and arcs. The shape of the active region 131 is not limited in this embodiment. The first mask layer 102 may be removed or retained. The first mask layer 102 may serve as a mask layer for subsequent etching of the active region 131 to adjust the height of the active region 131.

[0044] Reference Figure 12 As shown, a gate structure 141 is formed by replacing the sacrificial structure 120 with a conductive material. The first dielectric layer 101 overlaps with the active region 131 in the z-direction. The projection of the first dielectric layer 101 in the z-direction overlaps with the projection of the active region 131 in the z-direction, which can increase the isolation of the first dielectric layer 101 from the gate structure 141 and the active region 131, and reduce the leakage current between the gate structure 141 and the active region 131.

[0045] In this embodiment, the second mask layer 103 protects the first mask layer 102 from over-etching during the formation of the first groove 13, which is beneficial for improving the morphology and stability of the first mask layer 102. A more intact first mask layer 102 helps maintain the stability of the sacrificial structure 120, improves the morphology and dimensional uniformity of the subsequently formed gate structure 141, increases the manufacturing yield, and provides better etching resistance for subsequent processes. The introduction of the second mask layer 103 can increase the overall size of the mask layer and the sacrificial structure 120 in the x-direction, while reducing the size of the mask layer. Figure 8 The opening size of the etched semiconductor body 110 makes... Figure 9 The size of the first groove 13 formed in the x direction is beneficial to increasing the channel size between the two active regions 131 and reducing transistor leakage, while keeping the device integration level unchanged.

[0046] In some embodiments, the fabrication method further includes cleaning (or etching) the sidewalls of the first groove 13 during the removal of the second mask layer 103.

[0047] The cleaning process of the first groove 13 and the removal process of the second mask layer 103 can be integrated into the same process step to reduce manufacturing costs. For example, the second mask layer 103 can be removed during the cleaning process. The oxide layer in the first groove 13 can be a thin layer of oxide in contact with air. The debris residue in the first groove 13 is minimal or non-existent due to plasma bombardment. The etching amount for removing the oxide layer and debris residue in the first groove 13 is less or equal to the etching amount for removing the second mask layer 103. The first groove 13 also meets the cleaning process requirements after the second mask layer 103 is removed. The removal or disappearance of the second mask layer 103 can be used as the end point of the cleaning process to reduce over-etching of the first dielectric layer 101 and enlargement of the size of the first groove 13 caused by over-cleaning, which is beneficial for process integration and online process monitoring. For example, the second mask layer 103 may include silicon oxide, and the first mask layer 102 may include silicon nitride.

[0048] In some embodiments, the semiconductor body 110 extends into the sacrificial structure 120 at one end in the z-direction, and a portion of the semiconductor body 110 is located between two adjacent sacrificial structures 120; the fabrication method further includes: forming a first dielectric layer 101 between the semiconductor body 110 and the sacrificial structure 120, the first dielectric layer 101 covering the semiconductor body 110; at least a portion of the first dielectric layer 101 is covered by the sacrificial structure 120; the fabrication method further includes: penetrating the first dielectric layer 101 between two adjacent sacrificial structures 120 in the x-direction along the z-direction; the penetrating first dielectric layer 101 is located at the opening end of the first groove 13, and the penetrating first dielectric layer 101 protrudes from the sidewall of the opening end of the first groove 13 in the x-direction.

[0049] like Figure 8 The sacrificial structure 120 shown is Figure 1 The portion of the sacrificial structure 120 covering the top surface of the semiconductor body 110 is not shown; see reference to... Figure 1 The example of a sacrificial structure 120 extending along the y-direction has a semiconductor body 110 extending into the sacrificial structure 120 at its top in the positive z-direction. The portion of the semiconductor body 110 not covered by the sacrificial structure 120 is exposed relative to the sacrificial structure 120, or exposed between two adjacent sacrificial structures 120 in the x-direction. The first dielectric layer 101 may cover the top surface and sidewalls of the semiconductor body 110, and the sacrificial structure 120 covers a portion of the first dielectric layer 101. Figures 8 to 10 The first dielectric layer 101 shown is a partial film layer covering the top surface of the semiconductor body 110.

[0050] Reference Figure 10 As shown, the introduction of the second mask layer 103 increases the total mask layer thickness compared to the single first mask layer 102, allowing more of the first dielectric layer 101 to be covered by the mask layer, thus reducing over-etching of the first dielectric layer 101 during the cleaning process. Figure 10 As shown, after the second mask layer 103 is removed in the cleaning process, a portion of the first dielectric layer 101 protrudes from the second mask layer 103 along the x-direction, and the sidewalls of the first groove 13 are provided by a semiconductor material; the first dielectric layer 101 may protrude from the sidewall of the opening end of the first groove 13 along the x-direction, or the first dielectric layer 101 may cover a portion of the active region 131 in the z-direction, or the projection of the first dielectric layer 101 in the z-direction may overlap with the projection of the active region 131 in the z-direction. Figure 11 As shown, the active region 131 and the sacrificial structure 120 can be well isolated by the first dielectric layer 101, which is conducive to the subsequent formation of... Figure 20 After the gate structure 141 shown, the first dielectric layer 101 protrudes from the end of the gate structure 141 in the x direction and isolates the gate structure 141 and the active region 131 in the y direction, thereby reducing leakage current in the active region 131 and avoiding the risk of direct contact, reducing the parasitic capacitance between the gate structure 141 and the active region 131, and improving the manufacturing yield and device stability.

[0051] In some embodiments, refer to Figure 13 As shown, the first mask layer 102 and the second mask layer 103 are stacked in the z-direction; the first mask layer 102 covers the first dielectric layer 101 between two adjacent sacrificial structures 120; the first mask layer 102 is located between the first dielectric layer 101 and the second mask layer 103 in the z-direction; the fabrication method further includes: referring to Figure 14 As shown, a second mask layer 103 and a first mask layer 102 are inserted between two adjacent sacrificial structures 120 in the x-direction to expose the first dielectric layer 101.

[0052] Reference Figure 13 As shown, a first mask layer 102 and a second mask layer 103 are deposited on the exposed surface and sidewalls of the sacrificial structure 120, the first dielectric layer 101, and the deposition process may include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). (Refer to...) Figure 14As shown, the region between two adjacent sacrificial structures 120 in the x-direction is etched, and the first dielectric layer 101 is exposed by penetrating the second mask layer 103 and the first mask layer 102 in the z-direction. The etching of the second mask layer 103 and the etching of the first mask layer 102 can be performed simultaneously or in steps.

[0053] In some embodiments, the first mask layer 102 and the second mask layer 103 cover the end of the sacrificial structure 120 away from the semiconductor body 110; see reference Figure 14 As shown, the fabrication method further includes: when penetrating the second mask layer 103 between two adjacent sacrificial structures 120 in the x-direction, removing the second mask layer 103 covering the end of the sacrificial structure 120 away from the semiconductor body 110; when penetrating the first mask layer 102 between two adjacent sacrificial structures 120 in the x-direction, removing the first mask layer 102 covering the end of the sacrificial structure 120 away from the semiconductor body 110. After penetrating the second mask layer 103 and the first mask layer 102 between two adjacent sacrificial structures 120, the top of the sacrificial structure 120 may be exposed or not exposed; exposing the top of the sacrificial structure 120 facilitates subsequent etching to remove the sacrificial structure 120 or remove at least a portion of the sacrificial structure 120 to form a trench, in which a gate structure 141 is formed.

[0054] In some embodiments, refer to Figure 15 As shown, after penetrating the first mask layer 102 between two adjacent sacrificial structures 120 in the x-direction, the remaining first mask layer 102 forms a protrusion 1021 at one end near the first groove 13; the protrusion 1021 extends away from the sacrificial structure 120 in the x-direction. (Refer to...) Figure 15 As shown, the first dielectric layer 101 and the semiconductor body 110 are etched using the second mask layer 103 and the first mask layer 102 as etching masks to form... Figure 15 The first groove 13 shown is subjected to a cleaning process, during which the second mask layer 103 is removed. The portion of the first mask layer 102 covered by the second mask layer 103 in the z-direction is not etched, forming a protrusion 1021. The protrusion 1021 covers the first dielectric layer 101, reducing over-etching damage to the first dielectric layer 101 during the cleaning process and reducing damage to the first dielectric layer 101 in subsequent steps such as fabricating the gate structure 141.

[0055] In some embodiments, refer to Figure 16 As shown, an active region 131 is formed in the first groove 13. For example, Figure 15The example active region 131 has a cross-sectional shape in the xoz plane that is a pattern composed of straight lines and arcs, with the bottom of the active region 131 being arc-shaped. In some other embodiments, when forming the first groove 13 by etching the semiconductor body 110, the semiconductor body 110 can be etched laterally along the x or y direction, such that the first dielectric layer 101 protrudes from the sidewall of the opening end of the first groove 13 along the x direction, and the first dielectric layer 101 covers a portion of the active region 131 in the z direction.

[0056] In some embodiments, refer to Figure 17 As shown, the sacrificial structure 120 may include multiple film structures. For example, the method of forming the sacrificial structure 120 includes: forming a sacrificial gate 121 covering a portion of the semiconductor body 110; forming a first isolation structure 122 at the end of the sacrificial gate 121 away from the semiconductor body 110; forming a second isolation structure 123, the second isolation structure 123 covering the sidewall of the sacrificial gate 121 extending in the z-direction, and the second isolation structure 123 covering the sidewall of the first isolation structure 122 extending in the z-direction.

[0057] The top of the first isolation structure 122 may be covered by a first mask layer 102 and a second mask layer 103; the second mask layer 103 is removed after the first groove 13 is formed; the first isolation structure 122 may be a barrier layer to reduce the oxidation of the sacrificial gate 121 and to reduce over-etch damage to the sacrificial gate 121 when the first mask layer 102 and the second mask layer 103 on top of the sacrificial gate 121 are removed. The first isolation structure 122 may include multiple barrier layers, such as a first barrier layer 1221 and a second barrier layer 1222 stacked sequentially on the sacrificial gate 121. For example, the first barrier layer 1221 may include, but is not limited to, silicon nitride, the second barrier layer 1222 may include, but is not limited to, silicon oxide, and the sacrificial gate 121 may include, but is not limited to, silicon.

[0058] The second isolation structure 123 can be a sidewall structure, covering the sidewall of the sacrificial gate 121 that is not penetrated by the semiconductor body 110. The second isolation structure 123 can be used to define the position of the gate structure 141, and can also be used to support and electrically isolate the gate structure 141, thereby improving device stability. The second isolation structure 123 may include, but is not limited to, insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. The second isolation structure 123 may include a single-layer film structure or a multilayer film structure.

[0059] In some embodiments, the manufacturing method further includes: referring to Figure 18 As shown, the first isolation structure 122 and the sacrificial gate 121 are removed to form the first trench 14, see reference. Figure 19As shown, a gate structure 141 is formed in the first trench 14. The sidewalls of the first trench 14 may be provided by a second isolation structure 123. The gate structure 141 may include, but is not limited to, conductive materials such as tungsten, copper, aluminum, cobalt, ruthenium, nickel, titanium, gold, silver, or platinum. During the etching process to remove the first isolation structure 122 and the sacrificial gate 121, the first mask layer 102 acts as an etching mask to reduce etching damage to the first dielectric layer 101.

[0060] In some embodiments, dielectric material may be used for filling. Figure 17 After the structure shown, the first isolation structure 122 is chemically mechanically polished to reduce the film height of the sacrificial structure 120 to expose the sacrificial gate 121. The sacrificial gate 121 is then replaced to form the gate structure 141, thereby adjusting the height of the gate structure 141 and improving the manufacturing process window.

[0061] According to some aspects of embodiments of this disclosure, Figure 20 Provide a semiconductor structure, Figure 20 for Figure 19 A schematic diagram of the cross-sectional structure of the semiconductor structure at CC' in the xoy plane, refer to... Figure 20 and Figure 19 As shown, the semiconductor structure includes: a semiconductor body 110 extending along a first direction (x-direction); a gate structure 141 extending along a second direction (y-direction) intersecting the x-direction, and the gate structure 141 covering a portion of the semiconductor body 110; the semiconductor body 110 penetrating the gate structure 141 along the x-direction; a portion of the semiconductor body 110 located between two adjacent gate structures 141; a first dielectric layer 101 located between the semiconductor body 110 and the gate structure 141, at least a portion of the first dielectric layer 101 being covered by the gate structure 141; and an active region 131, at least partially embedded in the semiconductor body 110; the active region 131 located between two adjacent gate structures 141 and exposed between them. The active region 131 does not completely penetrate the semiconductor body 110; the active region 131 is exposed on the surface of the semiconductor body 110 near the gate structure 141 and can be coupled to a connection structure to obtain power.

[0062] exist Figure 20 In the first dielectric layer 101, the first dielectric layer 101 protrudes from the end of the gate structure 141 in the x direction. The size of the first dielectric layer 101 in the x direction between two adjacent active regions 131 is larger than the size of the gate structure in the x direction. The first dielectric layer 101 isolates the gate structure 141 and the active region 131 in the y direction, reducing leakage current of the active region 131 and avoiding direct contact, reducing parasitic capacitance between the gate structure 141 and the active region 131, and improving manufacturing yield and device stability. Figure 20 The semiconductor body 110 shown can serve as a channel region between the active regions 131.

[0063] In some embodiments, the gate structure 141 may include a single-layer conductive structure or a multi-layer structure. Exemplarily, the gate structure 141 may include a core and a connecting layer surrounding the sidewalls and bottom of the core; the core may include tungsten, and the connecting layer may include titanium nitride and / or an aluminum-titanium alloy.

[0064] In some embodiments, refer to Figure 19 As shown, the semiconductor structure further includes: a second isolation structure 123 extending along the y-direction; the second isolation structure 123 covers the sidewalls of the gate structure 141 extending along the z-direction. The cross-sectional shape of the second isolation structure 123 in the yoz plane may be the same as the cross-sectional shape of the sidewalls of the gate structure 141 in the yoz plane; the second isolation structure 123 is used to define or limit the position of the gate structure 141, and the second isolation structure 123 serves as a barrier layer in the fabrication process of the gate structure 141, reducing damage to the dielectric material. The second isolation structure 123 provides electrical isolation for the gate structure 141 and also reduces the diffusion of material components in the gate structure 141 to the surrounding area, reducing leakage current. The second isolation structure 123 may include a single-layer film structure or a multi-layer film structure.

[0065] In some embodiments, refer to Figure 12 As shown, the semiconductor structure further includes: at least a portion of the first dielectric layer 101 covering the sidewalls of the semiconductor body 110 extending along the x-direction; at least a portion of the first dielectric layer 101 covering a portion of the active region 131 in the third direction (z-direction); and a plane formed by the x-direction and the y-direction intersecting the z-direction.

[0066] The first dielectric layer 101 may cover the protruding top surface and sidewalls of the semiconductor body 110. A portion of the first dielectric layer 101 is covered by the semiconductor body 110. The first dielectric layer 101 is penetrated to form an opening exposing the active region 131. The top of the active region 131 may be flush with the first dielectric layer 101, or may protrude from the first dielectric layer 101, or may be below the first dielectric layer 101. The first dielectric layer 101 may cover a portion of the active region 131 in the z-direction, and the projection of the first dielectric layer 101 in the z-direction overlaps with the projection of the active region 131 in the z-direction.

[0067] According to some aspects of embodiments of this disclosure, referring to Figure 21As shown, the semiconductor body is formed on the substrate 200, or other parts of the semiconductor body may be located in the substrate 200; the semiconductor structure may include a first region 201 and a second region 202; the first region 201 may be a core region, and the second region 202 may be an input / output region (IO region), which is used to connect with external integrated circuits for electrical signal interconnection. The transistors in the core region and the IO region are formed simultaneously. When forming the source and drain of the transistors, the distance between the source / drain recesses of the transistors in the core region and the IO region and the sacrificial structure 120 is equal or close. Subsequently, the gate structure 141 is formed by replacing the sacrificial structure 120 with conductive material, so that the distance between the source / drain of the transistors in the core region and the gate structure in the IO region is equal or close. However, the devices in the core region and the devices in the IO region have different functions. The core region requires a lower operating voltage, while the IO region requires a higher operating voltage. Therefore, the distance between the source / drain of the transistor and the gate structure is difficult to meet the higher operating voltage of the IO region when meeting the operating voltage of the core region, resulting in a decrease in the reliability of the IO region devices and affecting the overall performance of the semiconductor structure. In some embodiments, a first mask layer 102 may be formed on the sidewalls of the sacrificial structures in the first region 201 and the second region 202, and a second mask layer 103 covering the first mask layer 102 may be formed on the sidewalls of the sacrificial structure 120 in a certain region (e.g., the second region 202) to adjust the shape or lateral width of the first groove 13 in different regions.

[0068] Reference Figure 21 As shown, a mask pattern 150 is formed covering the second region 202, exposing the first region 201. The mask pattern 150 may include, but is not limited to, photoresist or other dielectric layers. (Refer to...) Figure 22 As shown, the second mask layer 103 on the first region 201 is etched using mask pattern 150 as an etching mask to expose the first mask layer 102. (Refer to...) Figure 23 As shown, the mask pattern 150 on the second region 202 is removed to expose the second mask layer 103 of the second region 202. At this time, the mask layers on the second region 202 are the first mask layer 102 and the second mask layer 103, and the mask layer on the first region 201 is the first mask layer 102, such that the mask thickness on the sidewall of the sacrificial structure 120 in the second region 202 is greater than the mask thickness on the sidewall of the sacrificial structure 120 in the first region 201. (Refer to...) Figure 24As shown, etching is performed on the region between adjacent sacrificial structures 120 to form a first groove 13, including etching a first mask layer 102 and / or a second mask layer 103, a first dielectric layer 101, and a semiconductor body 110 of a certain thickness between the sacrificial structures 120. A first distance w1 exists between the sacrificial structure 120 located in the first region 201 and the sidewall of the first groove 13 on one side therein, and a second distance w2 exists between the sacrificial structure 120 located in the second region 202 and the sidewall of the first groove 13 on one side therein; the second region 202 has a thicker mask thickness, which allows the second distance w2 to be greater than the first distance w1; this increases the distance between the source / drain of the transistor in the second region 202 (IO region) and the subsequent gate structure 141 to meet higher operating voltages and reduce gate-induced drain leakage current.

[0069] In some embodiments, for Figure 24 The first groove 13 in the first groove is cleaned and the second mask layer 103 is removed. After the second mask layer 103 is removed, it can be epitaxially or deposited in the first groove 13 to form an active region 131. The conductive material replaces the sacrificial structure 120 to form a gate structure 141.

[0070] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a semiconductor body; A first dielectric layer is formed to cover the semiconductor body, and a sacrificial structure is formed to cover a portion of the first dielectric layer and a portion of the semiconductor body; the semiconductor body extends into the sacrificial structure at one end in a third direction, and a portion of the semiconductor body is located between two adjacent sacrificial structures; The semiconductor body extends along a first direction and penetrates the sacrificial structure, while the sacrificial structure extends along a second direction; The second direction intersects with the first direction; A first mask layer and a second mask layer are formed to at least cover the sidewalls of the sacrificial structure, the sidewalls extending along a third direction; the first mask layer is located between the sacrificial structure and the second mask layer; the plane formed by the first direction and the second direction intersects the third direction; The first dielectric layer extends along the third direction through the space between two adjacent sacrificial structures in the first direction; Etching is performed on at least a portion of the semiconductor body between the adjacent sacrificial structures in the first direction to form a first groove; the first dielectric layer through which the groove is formed is located at the opening end of the first groove, and the first dielectric layer through which the groove is formed protrudes from the sidewall of the opening end of the first groove along the first direction. Remove the second mask layer on the sidewall of the sacrificial structure to expose the first mask layer; An active region is formed in the first groove.

2. The manufacturing method according to claim 1, characterized in that, The first mask layer and the second mask layer are stacked upwards on the third side; The first mask layer covers the first dielectric layer between two adjacent sacrificial structures; The first mask layer is located between the first dielectric layer and the second mask layer in the third direction; the fabrication method further includes: The second mask layer extends through the first mask layer between two adjacent sacrificial structures in the first direction, as well as the first mask layer, to expose the first dielectric layer.

3. The manufacturing method according to claim 2, characterized in that, The first mask layer and the second mask layer cover the end of the sacrificial structure away from the semiconductor body; the fabrication method further includes: When penetrating the second mask layer between two adjacent sacrificial structures in the first direction, the second mask layer covering the end of the sacrificial structure away from the semiconductor body is removed; When passing through the first mask layer between two adjacent sacrificial structures in the first direction, the first mask layer covering the end of the sacrificial structure away from the semiconductor body is removed.

4. The manufacturing method according to claim 2, characterized in that, After passing through the first mask layer between two adjacent sacrificial structures in the first direction, the remaining first mask layer forms a protrusion at one end near the first groove; the protrusion extends away from the sacrificial structure along the first direction.

5. The manufacturing method according to claim 1, characterized in that, The method of forming the sacrificial structure includes: A sacrificial gate is formed that covers a portion of the semiconductor body; A first isolation structure is formed at the end of the sacrificial gate away from the semiconductor body; A second isolation structure is formed, which covers the sidewall of the sacrificial gate extending along the third direction, and the second isolation structure covers the sidewall of the first isolation structure extending along the third direction.

6. The manufacturing method according to claim 5, characterized in that, The manufacturing method further includes: The first isolation structure and the sacrificial gate are removed to form a first trench, and a gate structure is formed in the first trench.

7. The manufacturing method according to claim 1, characterized in that, The manufacturing method further includes: During the removal of the second mask layer, the sidewalls of the first groove are cleaned.

8. A semiconductor structure, characterized in that, include: The semiconductor body extends along a first direction; A gate structure extends along a second direction intersecting the first direction, and the gate structure covers a portion of the semiconductor body; The semiconductor body extends through the gate structure along the first direction; a portion of the semiconductor body is located between two adjacent gate structures. A first dielectric layer covering the semiconductor body is located between the semiconductor body and the gate structure, and at least a portion of the first dielectric layer is covered by the gate structure. The active region is at least partially embedded in the semiconductor body; The active region is located between two adjacent gate structures and is exposed between two adjacent gate structures; A portion of the first dielectric layer covers a portion of the active region in a third direction; the plane formed by the first direction and the second direction intersects with the third direction.

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