半导体结构及其制造方法
By introducing interconnects and isolation regions into the fin structure of the 3D transistor, the problems of insufficient current supply and redundant structure are solved, achieving more efficient current merging and simplified process.
CN121099646BActive Publication Date: 2026-07-17SHENZHEN PENGXIN MICRO INTEGRATED CIRCUIT MFG CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN PENGXIN MICRO INTEGRATED CIRCUIT MFG CO LTD
- Filing Date
- 2024-11-20
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
During the miniaturization of 3D transistors, limited current supply and incomplete etching of the dummy gate material lead to redundant structures, affecting performance.
Method used
The design employs a fin structure, including connection areas and isolation regions between fins. By forming electrode regions on the connection areas, incomplete etching of epitaxial connections and dummy gate materials is avoided, thus reducing process complexity.
Benefits of technology
This improves the current supply capability of 3D transistors, reduces the formation of redundant structures, and enhances performance and process reliability.
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Smart Images
Figure CN121099646B_ABST
Abstract
本公开涉及半导体技术领域，尤其涉及一种半导体结构及其制造方法。半导体结构包括：衬底；位于衬底上的鳍片结构，所述鳍片结构包括：在第一方向上延伸且在不同于所述第一方向的第二方向上间隔开的两根鳍片，以及位于所述两根鳍片之间且与所述两根鳍片连接的第一连接部；位于每根鳍片的两侧的隔离区；横跨所述鳍片结构且位于所述隔离区上的栅极结构，所述栅极结构包括栅极，所述栅极横跨所述第一连接部在所述第一方向上的第一边缘部分和所述两根鳍片；第一电极区，位于所述栅极结构的一侧，且位于所述两根鳍片和所述第一连接部上；以及第二电极区，位于所述栅极结构的另一侧，且位于所述两根鳍片上。
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