Improved low-power current-limiting circuit with adjustable current limitation

Abstract

The application relates to an improved low-power current-limiting circuit with adjustable current limitation, and belongs to the electronic technical field.The improved low-power current-limiting circuit with adjustable current limitation comprises a current comparator circuit and a variable current extraction circuit, a reference current is introduced, different extraction current values can be obtained according to different current-limiting resistors through I-V-I conversion, branches passing through adjustable resistors and branches passing through current-limiting resistors are respectively connected to input ends of the current comparator circuit, and the output signal controls the gate voltage of a power tube; thereby, the low-power current-limiting circuit with adjustable current limitation is realized.The improved low-power current-limiting circuit with adjustable current limitation has the advantages of simple structure, low cost and wide application in various devices requiring current limitation.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and particularly to the field of integrated circuit technology, specifically to an improved low-power current limiting circuit with adjustable current limiting. Background Technology

[0002] With the development of semiconductor technology, various traditional instruments and meters are rapidly being updated and iterated. In certain scenarios, we need to limit the load current, which inevitably requires the introduction of current-limiting circuits into the circuit. Traditional current-limiting circuits in instruments and meters mostly use fuses for protection, but inevitably, once the current is too large, traditional fuses will burn out and need to be replaced. Therefore, electronic fuses, i.e., electronic current-limiting circuits, have seen rapid development.

[0003] Traditional current limiting circuits, such as Figure 1 and 2 As shown, it is common practice to use a current-sensing resistor or a sampling transistor to mirror the power transistor current to obtain the sampled current. The detected current signal is converted into a voltage signal, compared with a preset voltage by an operational amplifier, and the output control the gate of the power transistor, thereby achieving current limiting. From the diagram, it can be seen that traditional current-limiting circuit structures, whether using a current-sensing resistor or a current mirror to mirror the power transistor, require circuits such as operational amplifier 1, operational amplifier 2, and a reference voltage. Therefore, the circuit structure is complex, and the self-power consumption of the current-limiting circuit is relatively large, making it difficult to achieve extremely low-power current-limiting circuits. Furthermore, the current-limiting circuit that mirrors the power transistor current using a sampling transistor suffers from the problem that when the input voltage is very low, the VDS of the sampling transistor can affect the accuracy of the sampled current.

[0004] Therefore, it is necessary to study an improved low-power current limiting circuit that uses a current sensing resistor. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide an improved low-power current limiting circuit with adjustable current limiting using a current sensing resistor.

[0006] To achieve the above objectives, the improved low-power current limiting circuit with adjustable current limiting of the present invention has the following configuration:

[0007] This improved low-power current limiting circuit with adjustable current limiting includes: a variable current extraction circuit and a current comparator circuit.

[0008] The variable current extraction circuit extracts different current values ​​based on different current-limiting resistors R2, thereby obtaining different current-limiting values; the variable current extraction circuit obtains the reference current Iin through IVI conversion.

[0009] The input voltage VIN is connected to the input terminals of the variable current extraction circuit and the current comparator circuit via an adjustable resistor R1; the input voltage VIN is also connected to the input terminal of the current comparator circuit via a current sensing resistor r.

[0010] The output of the current comparator circuit is connected to the gate of the power transistor N0. The drain of the power transistor N0 is connected to the input voltage VIN via the current sensing resistor r. The source of the power transistor N0 is the output voltage VOUT of the current-limiting adjustable improved low-power current limiting circuit.

[0011] In this improved low-power current limiting circuit with adjustable current limiting, the reference current Iin flows through the upper end of the current limiting resistor R2 and the negative input terminal of comparator M1 in the variable current extraction circuit; the lower end of the current limiting resistor R2 is connected to GND; the output terminal of comparator M1 is connected to the gate of NMOS transistor N1, the positive input terminal of comparator M1 is connected to the source of NMOS transistor N1 and the upper end of resistor R3, and the lower end of resistor R3 is connected to GND; the drain of NMOS transistor N1 is connected to the drain of PMOS transistor P3; the drain and gate of PMOS transistor P3 are connected together with the gate of PMOS transistor P4. P3 and P4 form a current mirror, with a width-to-length ratio of 1:1. The source of P3 is connected to power supply VDD. The source of P4 is connected to power supply VDD, and the drain of P4 is connected to the drain of N2. The drain and gate of N2 and the gate of N3 are connected together, forming a current mirror with N2 and N3, with a width-to-length ratio of 1:K. The source of N2 is connected to GND. The source of N3 is connected to GND, and the input voltage VIN is connected to the drain of N3 via an adjustable resistor R1.

[0012] In this improved low-power current limiting circuit with adjustable current limiting, the reference current Iin flows into the drain of NMOS transistor N4 in the current comparator circuit; the drain and gate of NMOS transistor N4 are connected to the gates of NMOS transistors N5, NMOS transistor N6, and NMOS transistor N7; NMOS transistors N4, N5, N6, and N7 form a current mirror with a width-to-length ratio of 1:1:1:1; the sources of NMOS transistors N4, N5, N6, and N7 are connected to GND; the drain of NMOS transistor N5 is connected to the control terminal of switch S1 and the drain of PMOS transistor P1; the drain and gate of PMOS transistor P1 are connected to the gate of PMOS transistor P2. The PMOS transistors P1 and P2 are connected to form a current mirror; the width-to-length ratio of PMOS transistors P1 and P2 is 1:1; the source of PMOS transistor P1 is connected to the lower end of the adjustable resistor R1 and the drain of NMOS transistor N3 in the variable current extraction circuit; the drain of PMOS transistor P2 is connected to the drain of NMOS transistor N6; the source of PMOS transistor P2 is connected to the lower end of the current sensing resistor R and the drain of power transistor N0; the upper end of switch S1 is connected to power supply VDD; the lower end of switch S1 is connected to the drain of NMOS transistor N7 and the control terminal of switch S2; the upper end of switch S2 is connected to the gate of power transistor N0; the lower end of switch S2 is connected to GND.

[0013] In this improved low-power current limiting circuit with adjustable current limiting, the switching transistor S1 is an NMOS transistor N8, and the switching transistor S2 is an NMOS transistor N9.

[0014] In this improved low-power current limiting circuit with adjustable current limiting, the gate of the power transistor N0 is connected to a charge pump.

[0015] The improved low-power current-limiting circuit with adjustable current limiting according to this invention includes a current comparator circuit and a variable current extraction circuit. A reference current is introduced, and through IVI conversion, different extraction current values ​​can be obtained based on different current-limiting resistors R2. The branch passing through the adjustable resistor R1 and the branch passing through the current-sensing resistor r are respectively connected to the input terminal of the current comparator circuit, and the output signal controls the gate voltage of the power transistor; thus realizing a low-power current-limiting circuit with adjustable current limiting. Furthermore, the improved low-power current-limiting circuit with adjustable current limiting of this invention has a simple structure, low cost, and can be widely used in various devices requiring current limiting applications. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a current-limiting circuit with a current-sensing resistor in the prior art.

[0017] Figure 2 This is a schematic diagram of a current-limiting circuit for a sampling tube mirror circuit in the prior art;

[0018] Figure 3This is a schematic block diagram of the improved low-power current limiting circuit with adjustable current limiting according to the present invention.

[0019] Figure 4 This is a schematic diagram of an improved low-power current limiting circuit with adjustable current limiting according to the present invention.

[0020] Figure 5 This is a detailed circuit diagram of an embodiment of an improved low-power current limiting circuit with adjustable current limiting according to the present invention;

[0021] Figure 6 This is a simulation diagram of the current limiting operation of the present invention when an overcurrent occurs in the circuit. Detailed Implementation

[0022] To better understand the technical content of this invention, the following embodiments are provided for detailed explanation.

[0023] Please see Figure 3 The diagram shown is a structural schematic of the improved low-power current limiting circuit with adjustable current limiting according to the present invention.

[0024] In one embodiment, the improved low-power current limiting circuit with adjustable current limiting of the present invention includes: a variable current extraction circuit and a current comparator circuit.

[0025] The variable current extraction circuit extracts different current values ​​based on different current-limiting resistors R2, thereby obtaining different current-limiting values; the variable current extraction circuit obtains the reference current Iin through IVI conversion.

[0026] The input voltage VIN is connected to the input terminals of the variable current extraction circuit and the current comparator circuit via an adjustable resistor R1; the input voltage VIN is also connected to the input terminal of the current comparator circuit via a current sensing resistor r.

[0027] The output of the current comparator circuit is connected to the gate of the power transistor N0. The drain of the power transistor N0 is connected to the input voltage VIN via the current sensing resistor r. The source of the power transistor N0 is the output voltage VOUT of the current-limiting adjustable improved low-power current limiting circuit.

[0028] In a preferred embodiment, in the variable current extraction circuit, the reference current Iin flows through the upper end of the current-limiting resistor R2 and the negative input terminal of comparator M1; the lower end of the current-limiting resistor R2 is connected to GND; the output terminal of comparator M1 is connected to the gate of NMOS transistor N1, the positive input terminal of comparator M1 is connected to the source of NMOS transistor N1 and the upper end of resistor R3, and the lower end of resistor R3 is connected to GND; the drain of NMOS transistor N1 is connected to the drain of PMOS transistor P3; the drain and gate of PMOS transistor P3 are connected together with the gate of PMOS transistor P4, and PMOS transistors P3 and P4... A current mirror is formed by PMOS transistors P3 and P4, with a width-to-length ratio of 1:1. The source of PMOS transistor P3 is connected to the power supply VDD. The source of PMOS transistor P4 is also connected to the power supply VDD, and the drain of PMOS transistor P4 is connected to the drain of NMOS transistor N2. The drain and gate of NMOS transistor N2 and the gate of NMOS transistor N3 are connected together, forming a current mirror with NMOS transistors N2 and N3, with a width-to-length ratio of 1:K. The source of NMOS transistor N2 is connected to GND. The source of NMOS transistor N3 is also connected to GND. The input voltage VIN is connected to the drain of NMOS transistor N3 via an adjustable resistor R1.

[0029] In another preferred embodiment, in the current comparator circuit, the reference current Iin flows into the drain of NMOS transistor N4; the drain and gate of NMOS transistor N4 are connected to the gates of NMOS transistors N5, NMOS transistor N6, and NMOS transistor N7; NMOS transistors N4, N5, N6, and N7 form a current mirror with a width-to-length ratio of 1:1:1:1; the sources of NMOS transistors N4, N5, N6, and N7 are connected to GND; the drain of NMOS transistor N5 is connected to the control terminal of switch S1 and the drain of PMOS transistor P1; the drain and gate of PMOS transistor P1 are connected to the gate of PMOS transistor P2. A current mirror is formed; the width-to-length ratio of PMOS transistors P1 and P2 is 1:1; the source of PMOS transistor P1 is connected to the lower end of the adjustable resistor R1 and the drain of NMOS transistor N3 in the variable current extraction circuit; the drain of PMOS transistor P2 is connected to the drain of NMOS transistor N6; the source of PMOS transistor P2 is connected to the lower end of the current sensing resistor R and the drain of power transistor N0; the upper end of switch S1 is connected to power supply VDD; the lower end of switch S1 is connected to the drain of NMOS transistor N7 and the control terminal of switch S2; the upper end of switch S2 is connected to the gate of power transistor N0; the lower end of switch S2 is connected to GND.

[0030] In a further preferred embodiment, the switching transistor S1 can be selected as NMOS transistor N8, and the switching transistor S2 can be selected as NMOS transistor N9.

[0031] In a more preferred embodiment, the gate of the power transistor N0 is connected to a charge pump.

[0032] In the application of this invention, the improved low-power current-limiting circuit with adjustable current limiting can be used as follows: Figure 5 The specific circuit implementation is shown.

[0033] In this circuit, the current sensing resistor is r, R1 is an adjustable resistor, and R2 is a current-limiting resistor. The variable current extraction circuit obtains the current from the reference current Iin through IVI conversion, i.e., I3 = Iin * R2 / R3. P3 and P4 form a current mirror, where P3:P4 = 1:1, so the current flowing through P3 and P4 is in a 1:1 ratio. NMOS transistors N2 and N3 form a current mirror, where N2:N3 = 1:K, i.e., I3:I4:I0 = 1:1:K in the diagram, i.e., I0 = K * Iin * R2 / R3. According to Kirchhoff's current law, the sum of the currents flowing into the same node is equal to the sum of the currents flowing out, so I5 = I0 + I1 in the circuit. NMOS transistors N4, N5, N6, and N7 form a current mirror, where N4:N5:N6:N7 = 1:1:1:1, i.e., Iin:I1:I2 = 1:1:1 in the diagram. Since I1 = I2, P1 and P2 form a 1:1 current mirror, therefore V1 = V2. That is, VIN - VR1 = VIN - Vr, where the current flowing through the current sensing resistor r is I6 = I. Then:

[0034] VIN-I5*R1=VIN-I*r

[0035] VIN-(I0+I1)*R1=VIN-I*r

[0036] I = Iin*(K*R2 / R3+1)*R1 / r

[0037] To reduce circuit power consumption, a reference current Iin can be set to 1uA, then the current limit value I = (K*R2 / R3+1)*R1 / r*10 -6

[0038] Typically, the current-sensing resistor *r* is the parasitic resistance at the input terminal of the power transistor N0. Its resistance is very small and highly sensitive to changes. The adjustable resistor *R1* can vary according to the current-sensing resistor *r*, thus ensuring stable current limiting. Once R1 is adjusted to stabilize the current limiting, it can be considered a fixed value. Since resistor *R3* is a fixed internal resistor and *K* is a fixed proportional value, a current-limiting formula that only depends on the current-limiting resistor *R2* can be obtained, namely:

[0039] I = (K*R2 / R3+1)*R1 / r*10 -6

[0040] Therefore, an improved circuit of the present invention, by introducing a reference current and reducing one operational amplifier, can obtain a low-power current-limiting circuit with a fixed current-limiting formula. Furthermore, Figure 4 In the figure, the switching transistors S1 and S2 can be, but are not limited to, devices such as MOSFETs and BJTs that function as switches; the current mirror in the figure can be a MOSFET, a BJT transistor, etc., and the current ratio can be, but is not limited to, 1:1; the module that supplies power to the gate voltage GATE in the figure can be, but is not limited to, a charge pump or a pull-up resistor.

[0041] The simulation diagram of the improved low-power current limiting circuit with adjustable current limiting of the present invention during overcurrent operation is shown below. Figure 6 As shown.

[0042] The improved low-power current-limiting circuit with adjustable current limiting according to this invention includes a current comparator circuit and a variable current extraction circuit. A reference current is introduced, and through IVI conversion, different extraction current values ​​can be obtained based on different current-limiting resistors R2. The branch passing through the adjustable resistor R1 and the branch passing through the current-sensing resistor r are respectively connected to the input terminal of the current comparator circuit, and the output signal controls the gate voltage of the power transistor; thus realizing a low-power current-limiting circuit with adjustable current limiting. Furthermore, the improved low-power current-limiting circuit with adjustable current limiting of this invention has a simple structure, low cost, and can be widely used in various devices requiring current limiting applications.

[0043] In this specification, the invention has been described with reference to specific embodiments thereof. However, it will be apparent that various modifications and variations can be made without departing from the spirit and scope of the invention. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

Claims

1. An improved low-power current limiting circuit with adjustable current limiting, characterized in that, include: Variable current extraction circuit and current comparator circuit; The variable current extraction circuit extracts different current values ​​based on different current-limiting resistors R2, thereby obtaining different current-limiting values; the variable current extraction circuit obtains the reference current Iin through IVI conversion. The input voltage VIN is connected to the input terminals of the variable current extraction circuit and the current comparator circuit via an adjustable resistor R1; the input voltage VIN is also connected to the input terminal of the current comparator circuit via a current sensing resistor r. The output of the current comparator circuit is connected to the gate of the power transistor N0. The drain of the power transistor N0 is connected to the input voltage VIN via the current sensing resistor r. The source of the power transistor N0 is the output voltage VOUT of the current-limiting adjustable improved low-power current-limiting circuit. In the variable current extraction circuit, the reference current Iin flows through the upper end of the current-limiting resistor R2 and the negative input terminal of comparator M1; the lower end of the current-limiting resistor R2 is connected to GND; the output terminal of comparator M1 is connected to the gate of NMOS transistor N1, and the positive input terminal of comparator M1 is connected to the source of NMOS transistor N1 and the upper end of resistor R3, the lower end of resistor R3 is connected to GND; the drain of NMOS transistor N1 is connected to the drain of PMOS transistor P3; the drain and gate of PMOS transistor P3 are connected together with the gate of PMOS transistor P4, and PMOS transistors P3 and P4 form a current mirror. The width-to-length ratio of PMOS transistors P3 and P4 is 1:1; the source of PMOS transistor P3 is connected to power supply VDD; the source of PMOS transistor P4 is connected to power supply VDD, and the drain of PMOS transistor P4 is connected to the drain of NMOS transistor N2; the drain and gate of NMOS transistor N2 and the gate of NMOS transistor N3 are connected together, and NMOS transistors N2 and N3 form a current mirror, with a width-to-length ratio of 1:K; the source of NMOS transistor N2 is connected to GND; the source of NMOS transistor N3 is connected to GND, and the input voltage VIN is connected to the drain of NMOS transistor N3 via an adjustable resistor R1.

2. The improved low-power current limiting circuit with adjustable current limiting according to claim 1, characterized in that, In the current comparator circuit, the reference current Iin flows into the drain of NMOS transistor N4; the drain and gate of NMOS transistor N4 are connected to the gates of NMOS transistors N5, NMOS transistor N6, and NMOS transistor N7, forming a current mirror with a width-to-length ratio of 1:1:1:1; the sources of NMOS transistors N4, N5, N6, and N7 are connected to GND; the drain of NMOS transistor N5 is connected to the control terminal of switch S1 and the drain of PMOS transistor P1; the drain and gate of PMOS transistor P1 are connected to the gate of PMOS transistor P2, forming a current mirror; the width-to-length ratio of PMOS transistors P1 and P2 is 1:1; the source of PMOS transistor P1... The lower end of the adjustable resistor R1 is connected to the drain of the NMOS transistor N3 in the variable current extraction circuit; the drain of the PMOS transistor P2 is connected to the drain of the NMOS transistor N6; the source of the PMOS transistor P2 is connected to the lower end of the current sensing resistor r and the drain of the power transistor N0; the upper end of the switch S1 is connected to the power supply VDD; the lower end of the switch S1 is connected to the drain of the NMOS transistor N7 and the control terminal of the switch S2; the upper end of the switch S2 is connected to the gate of the power transistor N0; and the lower end of the switch S2 is connected to GND.

3. The improved low-power current limiting circuit with adjustable current limiting according to claim 2, characterized in that, The switching transistor S1 is an NMOS transistor N8, and the switching transistor S2 is an NMOS transistor N9.

4. The improved low-power current limiting circuit with adjustable current limiting according to claim 2, characterized in that, The gate of the power transistor N0 is connected to a charge pump.

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