A dynamic power management circuit based on input voltage or current and method thereof

Abstract

The application discloses a kind of dynamic power management circuit based on input voltage or current and method thereof, including power tube M2, resistance R3, resistance R4, operational amplifier A3, gate drive circuit, SCP short-circuit protection circuit, current detection module, resistance R1, resistance R2 and operational amplifier A1, when system current ISYS is less than input current limit IIN_LIM, LDO loop normally works, provides stable voltage for system, ensure normal operation of system;If system current ISYS exceeds IIN_LIM, the current provided from VIN end will be limited to IIN_LIM;If short circuit occurs to ground at SYS end, or instantaneous current demand reaches 10xK times of reference short-circuit current IREF_SCP, short-circuit protection mechanism will be triggered, and power tube is closed.

Description

Technical Field

[0001] This invention relates to a power management circuit and method, particularly a dynamic power management circuit and method based on input voltage or current, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] With the rapid expansion of the emerging portable device market (such as TWS Bluetooth earphones, VR glasses, and smartwatches), improving the performance of power supply systems faces numerous challenges. Battery management systems need to possess efficient and rapid current handling capabilities, and their charging process typically includes four stages: trickle charging, constant current charging, constant voltage charging, and cutoff. As system functions and complexity continue to increase, the risk of system failure due to transient overvoltage and overcurrent phenomena increases significantly.

[0003] All power supplies limit their output current or power. For example, a USB 2.0 port's maximum output current is limited to 0.5A, while a high-speed USB 3.0 port is limited to 0.9A. If the system requires more current than the power supply can provide, the power supply will fail; similarly, if the supply voltage is lower than the minimum voltage required for the system to operate normally, the system will malfunction. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a dynamic power management circuit and method based on input voltage or current to realize LDO current and voltage limiting and short-circuit protection.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A dynamic power management circuit based on input voltage or current includes a power transistor M2, resistors R3 and R4, an operational amplifier A3, a gate drive circuit, an SCP short-circuit protection circuit, a current sensing module, resistors R1 and R2, and operational amplifier A1. The source of power transistor M2 is connected to one end of resistor R3 and the load SYS. The other end of resistor R3 is connected to one end of resistor R4 and the non-inverting input of operational amplifier A3 to generate the signal SYS_FB. The inverting input of operational amplifier A3 is connected to a reference voltage VREF3. The output of operational amplifier A3 is connected to the first input of the gate drive circuit to generate the signal OUT2. The input of the current sensing module is connected to the drain of power transistor M2 to sample the current of power transistor M2 and convert it into a sampling voltage. The output of the current sensing module outputs the sampling voltage IIN_FB. One end of resistor R1 is connected to the input voltage VIN. The other end of resistor R1, along with one end of resistor R2, is connected to the first inverting input of operational amplifier A1 to generate the signal VIN_FB. The first non-inverting input of operational amplifier A1 is connected to the reference voltage VREF2. The second inverting input of operational amplifier A1 is connected to the reference voltage VREF1. The second non-inverting input of operational amplifier A1 is connected to the sampling voltage IIN_FB. The output of operational amplifier A1 is connected to the second input of the gate drive circuit to generate the signal OUT2. The first input of the SCP short-circuit protection circuit is connected to the drain of power transistor M2. The second input of the SCP short-circuit protection circuit is connected to the load SYS. The output of the SCP short-circuit protection circuit is connected to the third input of the gate drive circuit to generate the signal SD. The output of the gate drive circuit is connected to the gate of power transistor M2.

[0006] Furthermore, the current detection module includes PMOS transistor M1 and PMOS transistor M... S The system consists of operational amplifier A2, PMOS transistor M0, and sampling resistor R_ISET. The drain of PMOS transistor M1 is connected to the drain of power transistor M2 and the non-inverting input of operational amplifier A2, generating a signal V. X The gate of PMOS transistor M1 and PMOS transistor M S The gate is connected to the bias voltage VBIAS, the source of PMOS transistor M1 and PMOS transistor M S The source of the PMOS transistor is connected to the input voltage VIN. S The drain of the transistor is connected to the inverting input of operational amplifier A2 and the source of PMOS transistor M0. The output of operational amplifier A2 is connected to the gate of PMOS transistor M0. The drain of PMOS transistor M0 is connected to one end of sampling resistor R_ISET and generates sampling voltage IIN_FB. The other end of sampling resistor R_ISET is grounded.

[0007] Furthermore, the PMOS transistor M1 and PMOS transistor M S To form a PMOS current mirror, and PMOS transistors M1 and M... S The current ratio is 1:K.

[0008] Furthermore, the gate drive circuit includes a current source I0 and an NMOS transistor M. 8c PMOS transistor M 8b and PMOS transistor M 8a One end of the current source I0 is connected to the input voltage VIN, and the other end of the current source I0 is connected to the NMOS transistor M. 8c The drain of the PMOS transistor M 8b The source and PMOS transistor M 8a The source of the NMOS transistor is connected to the gate of the power transistor M2, and the output of the gate drive circuit is connected to the gate of the power transistor M2. 8c The gate of the PMOS transistor is connected to the signal SD as the third input terminal of the gate drive circuit. 8b The gate of the PMOS transistor is connected to signal OUT1 as the second input terminal of the gate drive circuit. 8a The gate of the NMOS transistor is connected to the first input terminal of the gate drive circuit, which is connected to the signal OUT2. 8c The source of the PMOS transistor M 8b The drain and PMOS transistor M 8a The drain electrode is grounded.

[0009] Furthermore, the SCP short-circuit protection circuit includes an NMOS transistor M. P Comparator CMP1, comparator CMP2, and OR gate, NMOS transistor M P The drain of the transistor is connected to the drain of power transistor M2 as the input terminal of the SCP short-circuit protection circuit. NMOS transistor M... P The gate of the NMOS transistor is connected to the gate of the power transistor M2. P The source of the circuit is connected to the first input terminal of comparator CMP1 and generates current ISCP. The second input terminal of comparator CMP1 is connected to the reference current IEF_SCP. The first input terminal of comparator CMP2 is connected to the load SYS and generates voltage VSYS. The second input terminal of comparator CMP2 is connected to the reference voltage VREF_SCP. The output terminal of comparator CMP1 is connected to the first input terminal of OR gate. The output terminal of comparator CMP2 is connected to the second input terminal of OR gate. The output terminal of OR gate serves as the output terminal of the SCP short-circuit protection circuit and generates signal SD.

[0010] Furthermore, the NMOS transistor M P Together with power transistor M2, they form an NMOS current mirror, and NMOS transistor M... PThe current ratio of the power transistor M2 is 1:10K.

[0011] Furthermore, the operational amplifier A1 includes current source I1, current source I2, switch S1, switch S2, and PMOS transistor M. 3a PMOS transistor M 3b PMOS transistor M 4a PMOS transistor M 4b PMOS transistor M 7a PMOS transistor M 7b PMOS transistor M 6a PMOS transistor M 6b NMOS transistor M 5a and NMOS transistor M 5b One end of current source I1, one end of current source I2, and PMOS transistor M 7a The source and PMOS transistor M 7b The source of the current source I1 is connected to the input voltage VIN, and the other end of the current source I1 is connected to one end of the switch S1. The other end of the switch S1 is connected to the PMOS transistor M. 3a The source and PMOS transistor M 3b The source connection of the PMOS transistor M 3a The gate of the PMOS transistor is connected to the signal VIN_FB as the first inverting input of operational amplifier A1. 3b The gate of the amplifier is connected to the reference voltage VREF2 as the first non-inverting input terminal of the operational amplifier A1. The other end of the current source I2 is connected to one end of the switch S2, and the other end of the switch S2 is connected to the PMOS transistor M. 4a The source and PMOS transistor M 4b The source connection of the PMOS transistor M 4a The gate of the PMOS transistor is connected to the reference voltage VREF1 as the second inverting input of operational amplifier A1. 4b The gate of the PMOS transistor is connected to the sampling voltage IIN_FB as the second non-inverting input of operational amplifier A1. 3a The drain of the PMOS transistor M 4a The drain of the NMOS transistor M 5a The drain of the PMOS transistor M 6a The drain of the PMOS transistor M 7a The gate and PMOS transistor M 7b The gate connection of the PMOS transistor M 3b The drain of the PMOS transistor M 4b The drain of the NMOS transistor M 5b The drain and PMOS transistor M 6b The drain of the PMOS transistor is connected and used as the output of operational amplifier A1 to generate signal OUT1. 6a The gate of the PMOS transistor M6b The gate connection of the PMOS transistor M 6a The source and PMOS transistor M 7a The drain connection of the PMOS transistor M 6b The source and PMOS transistor M 7b The drain connection of the NMOS transistor M 5a The gate of the NMOS transistor M 5b Gate connection of NMOS transistor M 5a The source and NMOS transistor M 5b The source is grounded. Switch S1 is controlled by control signal ctl1, and switch S2 is controlled by control signal ctl2. Control signal ctl1 and control signal ctl2 are a pair of inverted signals.

[0012] Furthermore, the control signals ctl1 and ctl2 are provided by a control signal generation circuit, which includes a comparator CMP3, an inverter INV1, and an inverter INV2. The first input terminal of the comparator CMP3 is connected to the signal VIN_FB, the second input terminal of the comparator CMP3 is connected to the reference voltage VREF2, the output terminal of the comparator CMP3 is connected to the input terminal of the inverter INV1, the output terminal of the inverter INV1 is connected to the input terminal of the inverter INV2 and generates the control signal ctl1, and the output terminal of the inverter INV2 generates the control signal ctl2.

[0013] A management method for a dynamic power management circuit based on input voltage or current includes the following steps: When the voltage VSYS of the load SYS is greater than or equal to the preset value SYSM, the voltage divider signal SYS_FB obtained by voltage division through resistors R3 and R4 is greater than or equal to the reference voltage VREF3. At this time, the signal OUT3 is low, and the PMOS transistor M... 8a When the gate is turned on, the gate drive circuit drives the PMOS transistor M. 8a The power transistor M2 is driven to operate, and the LDO control loop responds, controlling the output load voltage VSYS at a preset value through the power transistor M2. ; When the voltage VSYS of the load SYS is less than the preset value SYSM, the voltage divider signal SYS_FB is less than the reference voltage VREF3. At this time, the signal OUT3 is high, and the PMOS transistor M... 8a Shut down; the system is now in DPM mode. DPM mode: PMOS transistor M 3a PMOS transistor M 3b Forming the first differential input pair, PMOS transistor M 4a PMOS transistor M 4bThis forms the second differential input pair. The first and second differential input pairs are controlled to operate at different times by a pair of inverting signals. When the input voltage VIN is sufficiently high, i.e., the signal VIN_FB after voltage division by resistors R1 and R2 is greater than or equal to the reference voltage VREF2, the first differential input pair does not operate, and the second differential input pair operates, clamping the sampling voltage IIN_FB to the reference voltage VREF1. At this time, the current flowing through the power transistor M2 is... This limits the maximum current of the load SYS. When the signal VIN_FB is less than the reference voltage VREF2, the first differential input pair operates, while the second differential input pair does not, clamping the signal VIN_FB to the reference voltage VREF2. At this time, the input voltage... This limits the minimum voltage of the input voltage VIN; When DPM mode is triggered, signal OUT1 is low, and the gate drive circuit activates through PMOS transistor M. 8b Drive power transistor M2 to work; When the current ISCP is greater than the reference current IEF_SCP or the voltage VSYS is greater than the reference voltage VREF_SCP, the signal SD is high, and the NMOS transistor M... 8c When the transistor is turned on, the gate charge of the power transistor M2 is quickly released, and when the power transistor M2 is turned off, the load SYS is protected.

[0014] Compared with existing technologies, this invention has the following advantages and effects: This invention provides a dynamic power management circuit and method based on input voltage or current. When the system current ISYS is less than the input current limit IIN_LIM, the LDO loop operates normally, providing a stable voltage to the system and ensuring normal system operation. If the system current ISYS exceeds IIN_LIM, the current supplied from the VIN terminal will be limited to IIN_LIM. If a short circuit occurs to ground at the SYS terminal, or the instantaneous current demand reaches 10×K times the reference short-circuit current IREF_SCP, a short-circuit protection mechanism will be triggered, and the power transistor will be turned off. Furthermore, if the voltage at the VIN terminal is lower than the set limit VIN_LIM, this voltage will be limited to VIN_LIM by the control loop. At this time, the maximum supply current at the SYS terminal will be lower than the preset value of IIN_LIM. If the current demand at the SYS terminal continues to exceed this preset value, the voltage at the SYS terminal will drop rapidly. Once it falls below the reference short-circuit protection voltage VREF_SCP, the short-circuit protection circuit will be triggered, and the power transistor will be turned off. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a dynamic power management circuit based on input voltage or current according to the present invention.

[0016] Figure 2 This is a circuit diagram of the current detection module of the present invention.

[0017] Figure 3 This is a circuit diagram of the gate driving circuit of the present invention.

[0018] Figure 4 This is a circuit diagram of the operational amplifier A1 of the present invention. Detailed Implementation

[0019] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0020] like Figure 1 As shown, this invention discloses a dynamic power management circuit based on input voltage or current, comprising a power transistor M2, resistors R3 and R4, an operational amplifier A3, a gate drive circuit, an SCP short-circuit protection circuit, a current detection module, resistors R1 and R2, and operational amplifier A1. The source of power transistor M2 is connected to one end of resistor R3 and the load SYS. The other end of resistor R3 is connected to one end of resistor R4 and the non-inverting input of operational amplifier A3 to generate the signal SYS_FB. The inverting input of operational amplifier A3 is connected to a reference voltage VREF3. The output of operational amplifier A3 is connected to the first input of the gate drive circuit to generate the signal OUT2. The input of the current detection module is connected to the drain of power transistor M2 to sample the current of power transistor M2 and convert it into a sampling voltage. The output of the current detection module outputs the sampling voltage IIN_FB. One end of resistor R1 is connected to the input voltage VIN. The other end of resistor R1, along with one end of resistor R2, is connected to the first inverting input of operational amplifier A1 to generate the signal VIN_FB. The first non-inverting input of operational amplifier A1 is connected to the reference voltage VREF2. The second inverting input of operational amplifier A1 is connected to the reference voltage VREF1. The second non-inverting input of operational amplifier A1 is connected to the sampling voltage IIN_FB. The output of operational amplifier A1 is connected to the second input of the gate drive circuit to generate the signal OUT2. The first input of the SCP short-circuit protection circuit is connected to the drain of power transistor M2. The second input of the SCP short-circuit protection circuit is connected to the load SYS. The output of the SCP short-circuit protection circuit is connected to the third input of the gate drive circuit to generate the signal SD. The output of the gate drive circuit is connected to the gate of power transistor M2.

[0021] likeFigure 2 As shown, the current detection module includes PMOS transistor M1 and PMOS transistor M2. S The system consists of operational amplifier A2, PMOS transistor M0, and sampling resistor R_ISET. The drain of PMOS transistor M1 is connected to the drain of power transistor M2 and the non-inverting input of operational amplifier A2, generating a signal V. X The gate of PMOS transistor M1 and PMOS transistor M S The gate is connected to the bias voltage VBIAS, the source of PMOS transistor M1 and PMOS transistor M S The source of the PMOS transistor is connected to the input voltage VIN. S The drain of the transistor is connected to the inverting input of operational amplifier A2 and the source of PMOS transistor M0. The output of operational amplifier A2 is connected to the gate of PMOS transistor M0. The drain of PMOS transistor M0 is connected to one end of sampling resistor R_ISET and generates sampling voltage IIN_FB. The other end of sampling resistor R_ISET is grounded.

[0022] PMOS transistor M1 and PMOS transistor M S To form a PMOS current mirror, and PMOS transistors M1 and M... S The current ratio is 1:K.

[0023] like Figure 3 As shown, the gate drive circuit includes a current source I0 and an NMOS transistor M. 8c PMOS transistor M 8b and PMOS transistor M 8a One end of the current source I0 is connected to the input voltage VIN, and the other end of the current source I0 is connected to the NMOS transistor M. 8c The drain of the PMOS transistor M 8b The source and PMOS transistor M 8a The source of the NMOS transistor is connected to the gate of the power transistor M2, and the output of the gate drive circuit is connected to the gate of the power transistor M2. 8c The gate of the PMOS transistor is connected to the signal SD as the third input terminal of the gate drive circuit. 8b The gate of the PMOS transistor is connected to signal OUT1 as the second input terminal of the gate drive circuit. 8a The gate of the NMOS transistor is connected to the first input terminal of the gate drive circuit, which is connected to the signal OUT2. 8c The source of the PMOS transistor M 8b The drain and PMOS transistor M 8a The drain electrode is grounded.

[0024] like Figure 1 As shown, the SCP short-circuit protection circuit includes an NMOS transistor M. PComparator CMP1, comparator CMP2, and OR gate, NMOS transistor M P The drain of the transistor is connected to the drain of power transistor M2 as the input terminal of the SCP short-circuit protection circuit. NMOS transistor M... P The gate of the NMOS transistor is connected to the gate of the power transistor M2. P The source of the circuit is connected to the first input terminal of comparator CMP1 and generates current ISCP. The second input terminal of comparator CMP1 is connected to the reference current IEF_SCP. The first input terminal of comparator CMP2 is connected to the load SYS and generates voltage VSYS. The second input terminal of comparator CMP2 is connected to the reference voltage VREF_SCP. The output terminal of comparator CMP1 is connected to the first input terminal of OR gate. The output terminal of comparator CMP2 is connected to the second input terminal of OR gate. The output terminal of OR gate serves as the output terminal of the SCP short-circuit protection circuit and generates signal SD.

[0025] NMOS transistor M P Together with power transistor M2, they form an NMOS current mirror, and NMOS transistor M... P The current ratio of the power transistor M2 is 1:10K.

[0026] like Figure 4 As shown, operational amplifier A1 includes current source I1, current source I2, switch S1, switch S2, and PMOS transistor M. 3a PMOS transistor M 3b PMOS transistor M 4a PMOS transistor M 4b PMOS transistor M 7a PMOS transistor M 7b PMOS transistor M 6a PMOS transistor M 6b NMOS transistor M 5a and NMOS transistor M 5b One end of current source I1, one end of current source I2, and PMOS transistor M 7a The source and PMOS transistor M 7b The source of the current source I1 is connected to the input voltage VIN, and the other end of the current source I1 is connected to one end of the switch S1. The other end of the switch S1 is connected to the PMOS transistor M. 3a The source and PMOS transistor M 3b The source connection of the PMOS transistor M 3a The gate of the PMOS transistor is connected to the signal VIN_FB as the first inverting input of operational amplifier A1. 3b The gate of the amplifier is connected to the reference voltage VREF2 as the first non-inverting input terminal of the operational amplifier A1. The other end of the current source I2 is connected to one end of the switch S2, and the other end of the switch S2 is connected to the PMOS transistor M. 4aThe source and PMOS transistor M 4b The source connection of the PMOS transistor M 4a The gate of the PMOS transistor is connected to the reference voltage VREF1 as the second inverting input of operational amplifier A1. 4b The gate of the PMOS transistor is connected to the sampling voltage IIN_FB as the second non-inverting input of operational amplifier A1. 3a The drain of the PMOS transistor M 4a The drain of the NMOS transistor M 5a The drain of the PMOS transistor M 6a The drain of the PMOS transistor M 7a The gate and PMOS transistor M 7b The gate connection of the PMOS transistor M 3b The drain of the PMOS transistor M 4b The drain of the NMOS transistor M 5b The drain and PMOS transistor M 6b The drain of the PMOS transistor is connected and used as the output of operational amplifier A1 to generate signal OUT1. 6a The gate of the PMOS transistor M 6b The gate connection of the PMOS transistor M 6a The source and PMOS transistor M 7a The drain connection of the PMOS transistor M 6b The source and PMOS transistor M 7b The drain connection of the NMOS transistor M 5a The gate of the NMOS transistor M 5b Gate connection of NMOS transistor M 5a The source and NMOS transistor M 5b The source is grounded. Switch S1 is controlled by control signal ctl1, and switch S2 is controlled by control signal ctl2. Control signal ctl1 and control signal ctl2 are a pair of inverted signals.

[0027] Control signals ctl1 and ctl2 are provided by a control signal generation circuit, which includes a comparator CMP3, an inverter INV1, and an inverter INV2. The first input of comparator CMP3 is connected to the signal VIN_FB, and the second input of comparator CMP3 is connected to the reference voltage VREF2. The output of comparator CMP3 is connected to the input of inverter INV1, and the output of inverter INV1 is connected to the input of inverter INV2 to generate control signal ctl1. The output of inverter INV2 generates control signal ctl2.

[0028] A management method for a dynamic power management circuit based on input voltage or current includes the following steps: When the voltage VSYS of the load SYS is greater than or equal to the preset value SYSM, the voltage divider signal SYS_FB obtained by voltage division through resistors R3 and R4 is greater than or equal to the reference voltage VREF3. At this time, the signal OUT3 is low, and the PMOS transistor M... 8a When the gate is turned on, the gate drive circuit drives the PMOS transistor M. 8a The power transistor M2 is driven to operate, and the LDO control loop responds, controlling the output load voltage VSYS at a preset value through the power transistor M2. .

[0029] When the voltage VSYS of the load SYS is less than the preset value SYSM, the voltage divider signal SYS_FB is less than the reference voltage VREF3. At this time, the signal OUT3 is high, and the PMOS transistor M... 8a Shut down; the system is now in DPM mode.

[0030] DPM mode: PMOS transistor M 3a PMOS transistor M 3b Forming the first differential input pair, PMOS transistor M 4a PMOS transistor M 4b This forms the second differential input pair. The first and second differential input pairs are controlled to operate at different times by a pair of inverting signals. When the input voltage VIN is sufficiently high, i.e., the signal VIN_FB after voltage division by resistors R1 and R2 is greater than or equal to the reference voltage VREF2, the first differential input pair does not operate, and the second differential input pair operates, clamping the sampling voltage IIN_FB to the reference voltage VREF1. At this time, the current flowing through the power transistor M2 is... This limits the maximum current of the load SYS to IIN_LIM=I2. .

[0031] When the signal VIN_FB is less than the reference voltage VREF2, the first differential input pair operates, while the second differential input pair does not, clamping the signal VIN_FB to the reference voltage VREF2. At this time, the input voltage... This limits the minimum input voltage VIN to VIN_LIM = .

[0032] When DPM mode is triggered, signal OUT1 is low, and the gate drive circuit activates through PMOS transistor M. 8b The power transistor M2 is driven to work.

[0033] When the current ISCP is greater than the reference current IEF_SCP or the voltage VSYS is greater than the reference voltage VREF_SCP, the signal SD is high, and the NMOS transistor M... 8c When the transistor is turned on, the gate charge of the power transistor M2 is quickly released, and when the power transistor M2 is turned off, the load SYS is protected.

[0034] This invention provides a dynamic power management circuit and method based on input voltage or current. When the system current ISYS is less than the input current limit IIN_LIM, the LDO loop operates normally, providing a stable voltage to the system and ensuring normal system operation. If the system current ISYS exceeds IIN_LIM, the current supplied from the VIN terminal will be limited to IIN_LIM. If a short circuit occurs to ground at the SYS terminal, or the instantaneous current demand reaches 10×K times the reference short-circuit current IREF_SCP, a short-circuit protection mechanism will be triggered, and the power transistor will be turned off. Furthermore, if the voltage at the VIN terminal is lower than the set limit VIN_LIM, this voltage will be limited to VIN_LIM by the control loop. At this time, the maximum supply current at the SYS terminal will be lower than the preset value of IIN_LIM. If the current demand at the SYS terminal continues to exceed this preset value, the voltage at the SYS terminal will drop rapidly. Once it falls below the reference short-circuit protection voltage VREF_SCP, the short-circuit protection circuit will be triggered, turning off the power transistor.

[0035] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A dynamic power management circuit based on input voltage or current, characterized in that: This circuit includes a power transistor M2, resistors R3 and R4, operational amplifier A3, a gate drive circuit, an SCP short-circuit protection circuit, a current sensing module, resistors R1 and R2, and operational amplifier A1. The source of power transistor M2 is connected to one end of resistor R3 and the load SYS. The other end of resistor R3 is connected to one end of resistor R4 and the inverting input of operational amplifier A3, generating the signal SYS_FB. The non-inverting input of operational amplifier A3 is connected to the reference voltage VREF3. The output of operational amplifier A3 is connected to the first input of the gate drive circuit, generating the signal OUT2. The input of the current sensing module is connected to the drain of power transistor M2 to sample the current of power transistor M2 and convert it into a sampling voltage. The output of the current sensing module outputs the sampling voltage IIN_FB. One end of resistor R1 is connected to the input voltage. VIN, the other end of resistor R1 and one end of resistor R2 are connected to the first inverting input of operational amplifier A1 to generate signal VIN_FB, the first non-inverting input of operational amplifier A1 is connected to reference voltage VREF2, the second inverting input of operational amplifier A1 is connected to reference voltage VREF1, the second non-inverting input of operational amplifier A1 is connected to sampling voltage IIN_FB, the output of operational amplifier A1 is connected to the second input of gate drive circuit to generate signal OUT1, the first input of SCP short circuit protection circuit is connected to drain of power transistor M2, the second input of SCP short circuit protection circuit is connected to load SYS, the output of SCP short circuit protection circuit is connected to the third input of gate drive circuit to generate signal SD, and the output of gate drive circuit is connected to gate of power transistor M2; The operational amplifier A1 includes current source I1, current source I2, switch S1, switch S2, and PMOS transistor M. 3a PMOS transistor M 3b PMOS transistor M 4a PMOS transistor M 4b PMOS transistor M 7a PMOS transistor M 7b PMOS transistor M 6a PMOS transistor M 6b NMOS transistor M 5a and NMOS transistor M 5b One end of current source I1, one end of current source I2, and PMOS transistor M 7a The source and PMOS transistor M 7b The source of the current source I1 is connected to the input voltage VIN, and the other end of the current source I1 is connected to one end of the switch S1. The other end of the switch S1 is connected to the PMOS transistor M. 3a The source and PMOS transistor M 3b The source connection of the PMOS transistor M 3a The gate of the PMOS transistor is connected to the signal VIN_FB as the first inverting input of operational amplifier A1. 3b The gate of the amplifier is connected to the reference voltage VREF2 as the first non-inverting input terminal of the operational amplifier A1. The other end of the current source I2 is connected to one end of the switch S2, and the other end of the switch S2 is connected to the PMOS transistor M. 4a The source and PMOS transistor M 4b The source connection of the PMOS transistor M 4a The gate of the PMOS transistor is connected to the reference voltage VREF1 as the second inverting input of operational amplifier A1. 4b The gate of the PMOS transistor is connected to the sampling voltage IIN_FB as the second non-inverting input of operational amplifier A1. 3a The drain of the PMOS transistor M 4a drain of NMOS transistor M 5a The drain of the PMOS transistor M 6a The drain of the PMOS transistor M 7a The gate and PMOS transistor M 7b The gate connection of the PMOS transistor M 3b The drain of the PMOS transistor M 4b drain of NMOS transistor M 5b The drain and PMOS transistor M 6b The drain of the PMOS transistor is connected and used as the output of operational amplifier A1 to generate signal OUT1. 6a The gate of the PMOS transistor M 6b The gate connection of the PMOS transistor M 6a The source and PMOS transistor M 7a The drain connection of the PMOS transistor M 6b The source and PMOS transistor M 7b The drain connection of the NMOS transistor M 5a The gate of the NMOS transistor M 5b Gate connection of NMOS transistor M 5a The source and NMOS transistor M 5b The source is grounded. Switch S1 is controlled by control signal ctl1, and switch S2 is controlled by control signal ctl2. Control signal ctl1 and control signal ctl2 are a pair of inverted signals. The control signals ctl1 and ctl2 are provided by a control signal generation circuit, which includes a comparator CMP3, an inverter INV1, and an inverter INV2. The first input terminal of the comparator CMP3 is connected to the signal VIN_FB, the second input terminal of the comparator CMP3 is connected to the reference voltage VREF2, the output terminal of the comparator CMP3 is connected to the input terminal of the inverter INV1, the output terminal of the inverter INV1 is connected to the input terminal of the inverter INV2 and generates the control signal ctl1, and the output terminal of the inverter INV2 generates the control signal ctl2.

2. The dynamic power management circuit based on input voltage or current according to claim 1, characterized in that: The current detection module includes PMOS transistor M1 and PMOS transistor M. S The system consists of operational amplifier A2, PMOS transistor M0, and sampling resistor R_ISET. The drain of PMOS transistor M1 is connected to the drain of power transistor M2 and the non-inverting input of operational amplifier A2, generating a signal V. X The gate of PMOS transistor M1 and PMOS transistor M S The gate is connected to the bias voltage VBIAS, the source of PMOS transistor M1 and PMOS transistor M S The source of the PMOS transistor is connected to the input voltage VIN. S The drain of the transistor is connected to the inverting input of operational amplifier A2 and the source of PMOS transistor M0. The output of operational amplifier A2 is connected to the gate of PMOS transistor M0. The drain of PMOS transistor M0 is connected to one end of sampling resistor R_ISET and generates sampling voltage IIN_FB. The other end of sampling resistor R_ISET is grounded.

3. A dynamic power management circuit based on input voltage or current according to claim 2, characterized in that: The PMOS transistor M1 and PMOS transistor M S To form a PMOS current mirror, and PMOS transistors M1 and M... S The current ratio is 1:K.

4. The dynamic power management circuit based on input voltage or current according to claim 1, characterized in that: The gate drive circuit includes a current source I0 and an NMOS transistor M. 8c PMOS transistor M 8b and PMOS transistor M 8a One end of the current source I0 is connected to the input voltage VIN, and the other end of the current source I0 is connected to the NMOS transistor M. 8c The drain of the PMOS transistor M 8b The source and PMOS transistor M 8a The source of the NMOS transistor is connected to the gate of the power transistor M2, and the output of the gate drive circuit is connected to the gate of the power transistor M2. 8c The gate of the PMOS transistor is connected to the signal SD as the third input terminal of the gate drive circuit. 8b The gate of the PMOS transistor is connected to signal OUT1 as the second input terminal of the gate drive circuit. 8a The gate of the NMOS transistor is connected to the first input terminal of the gate drive circuit, which is connected to the signal OUT2. 8c The source of the PMOS transistor M 8b The drain and PMOS transistor M 8a The drain electrode is grounded.

5. A dynamic power management circuit based on input voltage or current according to claim 1, characterized in that: The SCP short-circuit protection circuit includes an NMOS transistor M. P Comparator CMP1, comparator CMP2, and OR gate, NMOS transistor M P The drain of the transistor is connected to the drain of power transistor M2 as the input terminal of the SCP short-circuit protection circuit. NMOS transistor M... P The gate of the NMOS transistor is connected to the gate of the power transistor M2. P The source of the circuit is connected to the first input terminal of comparator CMP1 and generates current ISCP. The second input terminal of comparator CMP1 is connected to the reference current IEF_SCP. The first input terminal of comparator CMP2 is connected to the load SYS and generates voltage VSYS. The second input terminal of comparator CMP2 is connected to the reference voltage VREF_SCP. The output terminal of comparator CMP1 is connected to the first input terminal of OR gate. The output terminal of comparator CMP2 is connected to the second input terminal of OR gate. The output terminal of OR gate serves as the output terminal of the SCP short-circuit protection circuit and generates signal SD.

6. A dynamic power management circuit based on input voltage or current according to claim 5, characterized in that: The NMOS transistor M P Together with power transistor M2, they form an NMOS current mirror, and NMOS transistor M... P The current ratio of the power transistor M2 is 1:10K.

7. A management method for a dynamic power management circuit based on input voltage or current as described in any one of claims 1-6, characterized in that... Includes the following steps: When the voltage VSYS of the load SYS is greater than or equal to the preset value SYSM, the voltage divider signal SYS_FB obtained by voltage division through resistors R3 and R4 is greater than or equal to the reference voltage VREF3. At this time, the signal OUT3 is low, and the PMOS transistor M... 8a When the PMOS transistor is turned on, the gate drive circuit drives the PMOS transistor M. 8a The power transistor M2 is driven to operate, and the LDO control loop responds, controlling the output load voltage VSYS at a preset value through the power transistor M2. ; When the voltage VSYS of the load SYS is less than the preset value SYSM, the voltage divider signal SYS_FB is less than the reference voltage VREF3. At this time, the signal OUT3 is high, and the PMOS transistor M... 8a Shut down; the system is now in DPM mode. DPM mode: PMOS transistor M 3a PMOS transistor M 3b Forming the first differential input pair, PMOS transistor M 4a PMOS transistor M 4b This forms the second differential input pair. The first and second differential input pairs are controlled to operate at different times by a pair of inverting signals. When the input voltage VIN is sufficiently high, i.e., the signal VIN_FB after voltage division by resistors R1 and R2 is greater than or equal to the reference voltage VREF2, the first differential input pair does not operate, and the second differential input pair operates, clamping the sampling voltage IIN_FB to the reference voltage VREF1. At this time, the current flowing through the power transistor M2 is... This limits the maximum current of the load SYS. When the signal VIN_FB is less than the reference voltage VREF2, the first differential input pair operates, while the second differential input pair does not, clamping the signal VIN_FB to the reference voltage VREF2. At this time, the input voltage... This limits the minimum voltage of the input voltage VIN; When DPM mode is triggered, signal OUT1 is low, and the gate drive circuit activates through PMOS transistor M. 8b Drive power transistor M2 to work; When the current ISCP is greater than the reference current IEF_SCP or the voltage VSYS is greater than the reference voltage VREF_SCP, the signal SD is high, and the NMOS transistor M... 8c When the transistor is turned on, the gate charge of the power transistor M2 is quickly released, and when the power transistor M2 is turned off, the load SYS is protected.

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