A low voltage power supply with simultaneous output zero temperature reference circuit

Abstract

The application provides a zero-temperature reference circuit with low-voltage power supply and simultaneous output, belongs to the technical field of semiconductor low-voltage power supply, and provides a PATA current by adopting a self-biasing mode. Since the self-biasing does not need to use an operational amplifier, a CTAT current is generated on the basis of the PTAT current, a zero-temperature current reference can be obtained by superimposing the PTAT current and the CTAT current, a PTAT voltage is obtained by applying the PTAT current to a resistor, and a zero-temperature voltage reference can be obtained by superimposing two negative-temperature-coefficient transistor emitter junction voltages on the PTAT voltage, which can be directly applied to occasions requiring low-voltage power supply and simultaneously requiring zero-temperature current reference and zero-temperature voltage reference. The problems that the conventional operational amplifier feedback structure reference circuit cannot provide low-voltage power supply and simultaneously provide zero-temperature voltage reference and zero-temperature current reference are overcome.

Description

Technical Field

[0001] This application belongs to the field of semiconductor low-voltage power supply technology, and specifically relates to a zero-temperature reference circuit that simultaneously outputs low-voltage power supply. Background Technology

[0002] As a core module of analog chips, the bandgap reference circuit generates a reference output independent of temperature, power supply voltage, and process variations by integrating the physical quantities of positive temperature coefficient (PTAT) and negative temperature coefficient (CTAT). Its core value lies in providing a high-precision reference voltage and a stable reference current. The reference voltage provides the foundation for ADC / DAC quantization, power supply monitoring, and sensor calibration, while the reference current provides long-tailed bias current for internal modules such as comparators, operational amplifiers, and current mirrors within the analog chip.

[0003] In existing technologies, most traditional reference circuits obtain a voltage reference through feedback from operational amplifiers. Due to the input-output swing limitation of operational amplifiers, there are certain requirements for the operating voltage of the reference circuit, which cannot meet the needs of low-voltage operation scenarios. The offset of operational amplifiers will also affect the output accuracy of the reference. The closed-loop design of operational amplifiers is also easily affected by multi-stage feedback, which can cause oscillation of the reference output. Moreover, in most cases, only a zero-temperature voltage reference can be provided, while a zero-temperature current reference requires an additional circuit structure. Summary of the Invention

[0004] In view of the above problems, this invention proposes a zero-temperature reference circuit that provides both low-voltage power supply and simultaneous zero-temperature current and zero-temperature voltage references. It can be directly applied to applications requiring low-voltage power supply and simultaneous provision of zero-temperature voltage and zero-temperature current references. This overcomes the problem that traditional operational amplifier feedback structure reference circuits cannot provide both low-voltage power supply and simultaneous provision of zero-temperature voltage and zero-temperature current references.

[0005] This application provides an embodiment of a zero-temperature reference circuit that simultaneously supplies low-voltage power and outputs power, comprising:

[0006] Start-up circuit, positive temperature coefficient PTAT current generation circuit, negative temperature coefficient CTAT current generation circuit, zero-temperature current reference generation circuit and zero-temperature voltage reference generation circuit;

[0007] The positive temperature coefficient current generation circuit is used to generate a positive temperature coefficient current. The first and fourth signal lines in the positive temperature coefficient current are respectively applied to the four common source cascode current mirror structures: the startup circuit, the negative temperature coefficient CTAT current generation circuit, the zero temperature current reference generation circuit, and the zero temperature voltage reference generation circuit. The third signal line is applied to the negative temperature coefficient current generation circuit.

[0008] The startup circuit is connected to the positive temperature coefficient current generation circuit through the first signal line and the fourth signal line, which is used to prevent the positive temperature coefficient current generation circuit from working at the parallel point when the chip is powered on, and to start the positive temperature coefficient current generation circuit.

[0009] The negative temperature coefficient current generating circuit is connected to the positive temperature coefficient current generating circuit through the first signal line, the fourth signal line and the third signal line, and is used to generate negative temperature coefficient current.

[0010] The zero-temperature current reference generation circuit is connected to the positive temperature coefficient circuit through the first signal line and the fourth signal line, and to the negative temperature coefficient circuit through the fifth signal line, in order to generate a zero-temperature current reference.

[0011] The zero-temperature voltage reference generation circuit is connected to the positive temperature coefficient circuit through the first signal line and the fourth signal line, and to the negative temperature coefficient circuit through the fifth signal line, in order to generate a zero-temperature voltage reference.

[0012] Preferably, the positive temperature coefficient PTAT current generating circuit includes:

[0013] First P-tube PM1, second P-tube PM2, third P-tube PM3, fourth P-tube PM4, fifth P-tube PM5, sixth P-tube PM6, seventh P-tube PM7, eighth P-tube PM8 and ninth P-tube PM9.

[0014] The third N-tube NM3, the fourth N-tube NM4, the fifth N-tube NM5, the sixth N-tube NM6, the seventh N-tube NM7, the eighth N-tube NM8, and the ninth N-tube NM9;

[0015] The first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4;

[0016] The source of the first P-type transistor PM1 is connected to the power supply, and the drain is shorted to the gate and connected to the first signal line. The drain of the first P-type transistor PM1 is connected to the drain of the fourth N-type transistor NM4.

[0017] The source of the fourth N-transistor NM4 is connected to the drain of the third N-transistor NM3, and the gate of the fourth N-transistor NM4 is connected to the second signal line.

[0018] The source of the third N-transistor NM3 is connected to the emitter of the first transistor Q1, and the gate of the third N-transistor NM3 is connected to the third signal line; the collector and base of the first transistor Q1 are shorted and then connected to the ground terminal.

[0019] Preferably, the positive temperature coefficient PTAT current generating circuit further includes:

[0020] The source of the fourth P-tube PM4 is connected to the power supply, and its drain is connected to the source of the second P-tube PM2. The gate of the fourth P-tube PM4 is shorted to the drain of the second P-tube PM2 and connected to the fourth signal line. The gate of the fourth P-tube PM4 is shorted to the drain of the second P-tube PM2 and then connected to the gate of the fifth P-tube PM5.

[0021] The drain of the second P-type transistor PM2 is connected to the drain of the seventh N-type transistor NM7; the gate of the second P-type transistor PM2 is connected to the gate of the third P-type transistor PM3.

[0022] The source of the seventh N-transistor NM7 is connected to the drain of the fifth N-transistor NM5, and the gate of the seventh N-transistor NM7 is connected to the gate of the eighth N-transistor NM8. After the gates of the seventh N-transistor NM7 and the eighth N-transistor NM8 are connected, a terminal is led out and connected to the second signal line.

[0023] The source of the fifth N-transistor NM5 is connected to the first terminal of the zero resistance R0. The gate of the fifth N-transistor NM5 is connected to the gate of the sixth N-transistor NM6 and a terminal is led out to connect to the third signal line. A terminal is led out between the gate of the fifth N-transistor NM5 and the gate of the sixth N-transistor NM6 and connected to the drain of the eighth N-transistor NM8.

[0024] The second end of the zero resistor R0 is connected to the emitter of the second transistor Q2, and the collector and base of the second transistor Q2 are shorted and then connected to the ground terminal.

[0025] Preferably, the positive temperature coefficient PTAT current generating circuit further includes:

[0026] The source of the fifth P transistor PM5 is connected to the power supply, and the drain of the fifth P transistor PM5 is connected to the source of the third P transistor PM3. The gate of the fifth P transistor PM5 is shorted to the drain of the second P transistor PM2 and connected to the fourth signal line. The gate of the fifth P transistor PM5 is shorted to the drain of the second P transistor PM2 and then connected to the gate of the fourth P transistor PM4.

[0027] The drain of the third P transistor PM3 is connected to the drain of the eighth N transistor NM8. The terminal led out between the drain of the third P transistor PM3 and the drain of the eighth N transistor NM8 is connected to the common gate terminal between the fifth N transistor NM5 and the sixth N transistor NM6 and connected to the third signal line.

[0028] The source of the eighth N-transistor NM8 is connected to the drain of the sixth N-transistor NM6, and the source of the sixth N-transistor NM6 is connected to the emitter of the third transistor Q3.

[0029] A terminal is led out between the source of the sixth N-transistor NM6 and the emitter of the third transistor Q3 and connected to the drain of the sixth P-transistor PM6; the collector and base of the third transistor Q3 are shorted and then connected to the ground terminal.

[0030] The source of the seventh P transistor PM7 is connected to the power supply, the drain of the seventh P transistor PM7 is connected to the source of the sixth P transistor PM6, and the gate of the seventh P transistor PM7 is connected to the fourth signal line.

[0031] The drain of the sixth P-type transistor PM6 is connected to the emitter of the third transistor, and the gate of the sixth P-type transistor PM6 is connected to the first signal line.

[0032] Preferably, the positive temperature coefficient PTAT current generating circuit further includes:

[0033] The source of the ninth P-type transistor PM9 is connected to the power supply, the drain of the ninth P-type transistor PM9 is connected to the source of the eighth P-type transistor PM8, and the gate of the ninth P-type transistor PM9 is connected to the fourth signal line.

[0034] The drain of the eighth P transistor PM8 is connected to the drain of the ninth N transistor NM9, and a terminal is led out between the drain of the eighth P transistor PM8 and the drain of the ninth N transistor NM9 and connected to the second signal line; the gate of the eighth P transistor PM8 is connected to the first signal line.

[0035] The gate and drain of the ninth N-transistor NM9 are shorted together; the source of the ninth N-transistor NM9 is connected to the emitter of the fourth transistor Q4.

[0036] The collector and base of the fourth transistor Q4 are shorted and then connected to the ground terminal.

[0037] Preferably, the startup circuit includes:

[0038] Zero P-tube PM0;

[0039] Zero N tube NM0, first N tube NM1, and second N tube NM2;

[0040] Transistor Q0 (zeroth transistor);

[0041] The source of the zero-P transistor PM0 is connected to the power supply, the gate of the zero-P transistor PM0 is grounded, and the drain of the zero-P transistor PM0 is connected to the drain of the zero-N transistor NM0. After the drain of the zero-P transistor PM0 is connected to the drain of the zero-N transistor NM0, the sixth signal line is connected.

[0042] The zeroth N-transistor NM0, the first N-transistor NM1, and the second N-transistor NM2 are connected to the common source, and the terminal after the common source connection is connected to the emitter of the zeroth transistor Q0; the gate of the zeroth N-transistor NM0 is connected to the third signal line; the drain of the first N-transistor NM1 is connected to the first signal line; the drain of the second N-transistor NM2 is connected to the fourth signal line; the gates of the first N-transistor NM1 and the second N-transistor NM2 are connected to the sixth signal line.

[0043] The collector and base of the zeroth transistor Q0 are shorted and then connected to the ground terminal.

[0044] Preferably, the negative temperature coefficient CTAT current generating circuit includes:

[0045] The tenth P-tube PM10, the eleventh P-tube PM11, the twelfth P-tube PM12, and the thirteenth P-tube PM13;

[0046] The tenth N-tube, NM10;

[0047] First resistor R1 and zeroth capacitor C0;

[0048] The source of the eleventh P-type transistor PM11 is connected to the power supply; the drain of the eleventh P-type transistor PM11 is connected to the source of the tenth P-type transistor PM10; the gate of the eleventh P-type transistor PM11 is connected to the fourth signal line, and the gate of the tenth P-type transistor PM10 is connected to the first signal line; the drain of the tenth P-type transistor PM10 is connected to the drain of the tenth N-type transistor NM10, and a terminal is led out between the drain of the tenth P-type transistor PM10 and the drain of the tenth N-type transistor NM10 to connect to the fifth signal line; the terminal is also led out between the drain of the tenth P-type transistor PM10 and the drain of the tenth N-type transistor NM10 to connect to the gate of the thirteenth P-type transistor PM13 and the first end of the zero capacitor C0.

[0049] The source of the tenth N transistor NM10 is connected to the first terminal of the first resistor R1, and the lead-out terminal between the source of the tenth N transistor NM10 and the first terminal of the first resistor R1 is connected to the second terminal of the zero capacitor C0. The lead-out terminal between the source of the tenth N transistor NM10 and the first terminal of the first resistor R1 is also connected to the drain of the twelfth P transistor PM12; the second terminal of the first resistor R1 is grounded.

[0050] The source of the thirteenth P-type transistor PM13 is connected to the power supply, and the drain of the thirteenth P-type transistor PM13 is connected to the source of the twelfth P-type transistor PM12; the gate of the twelfth P-type transistor PM12 is connected to the first signal line.

[0051] Preferably, the zero-temperature current reference generation circuit includes:

[0052] Pipe 14 PM14, pipe 15 PM15, and pipe 16 PM16;

[0053] Eleventh N-tube NM11;

[0054] The fifteenth P-type transistor PM15 and the sixteenth P-type transistor PM16 are connected with common source and common drain, and the common source terminal is connected to the power supply, and the common drain terminal is connected to the source of the fourteenth P-type transistor PM14; the gate of the fifteenth P-type transistor PM15 is connected to the fifth signal line, and the gate of the sixteenth P-type transistor PM16 is connected to the fourth signal line.

[0055] The drain of the fourteenth P-type transistor PM14 is connected to the drain of the eleventh N-type transistor NM11, and the gate of the fourteenth P-type transistor PM14 is connected to the first signal line; a reference current source IREF is led out between the drain of the fourteenth P-type transistor PM14 and the drain of the eleventh N-type transistor NM11.

[0056] The drain of the eleventh N transistor NM11 is connected to the gate, and the source of the eleventh N transistor NM11 is grounded.

[0057] Preferably, the zero-temperature voltage reference generation circuit includes:

[0058] Pipe 17 PM17, Pipe 18 PM18, Pipe 19 PM19, Pipe 20 PM20, Pipe 21 PM21, and Pipe 22 PM22.

[0059] Transistor Q5 (fifth) and transistor Q6 (sixth);

[0060] Second resistor R2;

[0061] The drain of the eighteenth P-tube PM18 is connected to the source of the seventeenth P-tube PM17, the drain of the twentieth P-tube PM20 is connected to the source of the nineteenth P-tube PM19, and the drain of the twenty-second P-tube PM22 is connected to the source of the twenty-first P-tube PM21.

[0062] The eighteenth P-tube PM18, the twentieth P-tube PM20, and the twenty-second P-tube PM22 are connected to the common source, and the common source terminal is connected to the power supply.

[0063] The drain of the seventeenth P-type transistor PM17 is connected to the first terminal of the second resistor R2, and the drain of the seventeenth P-type transistor PM17 and the first terminal of the second resistor R2 are connected to the gate of the fifth transistor Q5. The gate of the seventeenth P-type transistor PM17 is connected to the first signal line, and the second terminal of the second resistor R2 is grounded.

[0064] Preferably, the zero-temperature voltage reference generation circuit further includes:

[0065] First capacitor C1;

[0066] The drain of the nineteenth P-type transistor PM9 is connected to the emitter of the fifth transistor Q5. A terminal is led out between the drain of the nineteenth P-type transistor PM19 and the emitter of the fifth transistor Q5 and connected to the gate of the sixth transistor Q6. The collector of the fifth transistor Q5 is grounded.

[0067] The drain of the 21st P-type transistor PM21 is connected to the emitter of the 6th transistor Q6. A terminal is led out between the drain of the 21st P-type transistor PM21 and the emitter of the 6th transistor Q6 and connected to the first terminal of the first capacitor C1. The collector of the 6th transistor Q6 is connected to the second terminal of the first capacitor C1 and grounded. A reference voltage source VREF is led out between the drain of the 21st P-type transistor PM21 and the emitter of the 6th transistor Q6.

[0068] The beneficial effects of this invention are:

[0069] This application provides a PATA current using a self-biasing method. Since self-biasing eliminates the need for an operational amplifier, it has very low operating voltage requirements and also eliminates the impact of operational amplifier offset on reference accuracy. Furthermore, a CTAT current is generated based on the PTAT current. By superimposing the PTAT and CTAT currents, a zero-temperature current reference is obtained. A PTAT voltage is obtained by applying the PTAT current to a resistor. Superimposing two negative temperature coefficient transistor emitter-junction voltages on this PTAT voltage yields a zero-temperature voltage reference. This can be directly applied to applications requiring low-voltage supply and simultaneous zero-temperature current and zero-temperature voltage references. It overcomes the problem that traditional operational amplifier feedback reference circuits cannot provide low-voltage supply and simultaneously provide zero-temperature voltage and zero-temperature current references.

[0070] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures pointed out in the description and the drawings. Attached Figure Description

[0071] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0072] Figure 1 A schematic diagram of a zero-temperature reference circuit structure that provides low-voltage power supply and output is shown.

[0073] Figure 2 The topology of the positive temperature coefficient PTAT current generation circuit in the embodiment is shown.

[0074] Figure 3 The topology diagram of the startup circuit in the embodiment is shown;

[0075] Figure 4The topology of the negative temperature coefficient CTAT current generation circuit in the embodiment is shown;

[0076] Figure 5 The topology of the zero-temperature current reference generation circuit in the embodiment is shown;

[0077] Figure 6 The topology of the zero-temperature voltage reference generation circuit in the embodiment is shown;

[0078] Figure 7 The diagram shows the topology of a zero-temperature reference circuit that simultaneously outputs low-voltage power in the embodiment. Detailed Implementation

[0079] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0080] It should be noted that the terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," "longitudinal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings.

[0081] This addresses the problem that traditional operational amplifier feedback structure reference circuits cannot provide low-voltage power supply and simultaneously provide zero-temperature voltage and zero-temperature current references.

[0082] This application provides an embodiment of a zero-temperature reference circuit that simultaneously supplies low-voltage power and outputs it; see [link to relevant documentation]. Figure 1 ,include:

[0083] The circuit consists of: a starting circuit XI2, a positive temperature coefficient PTAT current generation circuit XI1, a negative temperature coefficient CTAT current generation circuit XI3, a zero-temperature current reference generation circuit XI4, and a zero-temperature voltage reference generation circuit XI5.

[0084] The positive temperature coefficient current generation circuit XI1 is used to generate a positive temperature coefficient current. The first signal line net1 and the fourth signal line net4 in the positive temperature coefficient current are respectively applied to the four common source cascode current mirror structures: the startup circuit XI2, the negative temperature coefficient CTAT current generation circuit XI3, the zero temperature current reference generation circuit XI4, and the zero temperature voltage reference generation circuit XI5. The third signal line net3 is applied to the negative temperature coefficient current generation circuit XI3.

[0085] Specifically, see Figure 1 The positive temperature coefficient (PTAT) current generation circuit XI1 is used to generate PTAT positive temperature coefficient current. The two signal lines net1 and net4 generated by XI1 provide voltage bias for the common source and common gate current mirror structure of the four modules: startup circuit XI2, CTAT current generation circuit XI3, zero-temperature current reference generation circuit XI4, and zero-temperature voltage reference generation circuit XI5. The net3 signal line generated by XI1 provides voltage bias for the CTAT current generation circuit XI3 module.

[0086] The startup circuit is connected to the positive temperature coefficient current generation circuit through the first signal line net1 and the fourth signal line net4. It is used to prevent the positive temperature coefficient current generation circuit from working at the parallel point when the chip is powered on, and to start the positive temperature coefficient current generation circuit.

[0087] Specifically, see Figure 1 The startup circuit XI2 is used to prevent the PTAT current generation circuit XI1 from operating at the parallel point when the chip is powered on. It can quickly start the PTAT current generation circuit XI1. XI2 is connected to the two signal lines net1 and net4 provided by the PTAT current generation circuit XI1.

[0088] The negative temperature coefficient current generating circuit is connected to the positive temperature coefficient current generating circuit through the first signal line net1, the fourth signal line net4 and the third signal line net3, and is used to generate negative temperature coefficient current.

[0089] Specifically, see Figure 1 The negative temperature coefficient CTAT current generation circuit XI3 is used to generate CTAT (negative temperature coefficient) current. XI3 is connected to the three signal lines net1, net4 and net3 provided by the PTAT current generation circuit XI1. At the same time, it generates the net5 signal and connects it to the zero temperature current reference generation circuit XI4.

[0090] The zero-temperature current reference generation circuit is connected to the positive temperature coefficient circuit through the first signal line net1 and the fourth signal line net1, and to the negative temperature coefficient circuit through the fifth signal line net5, in order to generate a zero-temperature current reference.

[0091] Specifically, see Figure 1 The zero-temperature current reference generation circuit XI4 is used to generate a zero-temperature current reference. XI4 is connected to the two signal lines net1 and net4 provided by the PTAT current generation circuit XI1, and is also connected to the net5 signal generated by the CTAT current generation circuit XI3. Finally, it generates the IREF zero-temperature reference current bias signal.

[0092] The zero-temperature voltage reference generation circuit is connected to the positive temperature coefficient circuit through the first signal line net1 and the fourth signal line net4, and to the negative temperature coefficient circuit through the fifth signal line net5, in order to generate a zero-temperature voltage reference.

[0093] Specifically, see Figure 1 The zero-temperature voltage reference generation circuit XI5 is used to generate a zero-temperature voltage reference. XI5 is connected to the two signal lines net1 and net4 provided by the PTAT current generation circuit XI1, and finally generates the zero-temperature reference voltage bias signal VREF.

[0094] It should be noted that the names of the components in this application are represented by commonly used abbreviations in the art, and are not custom markings defined by the applicant. For example, R0 represents the zeroth resistor, PM13 represents the thirteenth P-type MOSFET, and C0 represents the zeroth capacitor. Therefore, the abbreviations used for components in this application are understandable to those skilled in the art.

[0095] The following is a detailed description of the zero-temperature reference circuit structure and circuit topology of this application.

[0096] In some specific implementation methods, see Figure 2 and Figure 5 The positive temperature coefficient PTAT current generating circuit includes:

[0097] First P-tube PM1, second P-tube PM2, third P-tube PM3, fourth P-tube PM4, fifth P-tube PM5, sixth P-tube PM6, seventh P-tube PM7, eighth P-tube PM8 and ninth P-tube PM9.

[0098] The third N-tube NM3, the fourth N-tube NM4, the fifth N-tube NM5, the sixth N-tube NM6, the seventh N-tube NM7, the eighth N-tube NM8, and the ninth N-tube NM9;

[0099] The first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4;

[0100] The source of the first P-type transistor PM1 is connected to the power supply, and the drain is shorted to the gate and connected to the first signal line. The drain of the first P-type transistor PM1 is connected to the drain of the fourth N-type transistor NM4.

[0101] The source of the fourth N-transistor NM4 is connected to the drain of the third N-transistor NM3, and the gate of the fourth N-transistor NM4 is connected to the second signal line.

[0102] The source of the third N-transistor NM3 is connected to the emitter of the first transistor Q1, and the gate of the third N-transistor NM3 is connected to the third signal line; the collector and base of the first transistor Q1 are shorted and then connected to the ground terminal.

[0103] The positive temperature coefficient PTAT current generation circuit further includes:

[0104] The source of the fourth P-tube PM4 is connected to the power supply, and its drain is connected to the source of the second P-tube PM2. The gate of the fourth P-tube PM4 is shorted to the drain of the second P-tube PM2 and connected to the fourth signal line. The gate of the fourth P-tube PM4 is shorted to the drain of the second P-tube PM2 and then connected to the gate of the fifth P-tube PM5.

[0105] The drain of the second P-type transistor PM2 is connected to the drain of the seventh N-type transistor NM7; the gate of the second P-type transistor PM2 is connected to the gate of the third P-type transistor PM3.

[0106] The source of the seventh N-transistor NM7 is connected to the drain of the fifth N-transistor NM5, and the gate of the seventh N-transistor NM7 is connected to the gate of the eighth N-transistor NM8. After the gates of the seventh N-transistor NM7 and the eighth N-transistor NM8 are connected, a terminal is led out and connected to the second signal line.

[0107] The source of the fifth N-transistor NM5 is connected to the first terminal of the zero resistance R0. The gate of the fifth N-transistor NM5 is connected to the gate of the sixth N-transistor NM6 and a terminal is led out to connect to the third signal line. A terminal is led out between the gate of the fifth N-transistor NM5 and the gate of the sixth N-transistor NM6 and connected to the drain of the eighth N-transistor NM8.

[0108] The second end of the zero resistor R0 is connected to the emitter of the second transistor Q2, and the collector and base of the second transistor Q2 are shorted and then connected to the ground terminal.

[0109] The positive temperature coefficient PTAT current generation circuit further includes:

[0110] The source of the fifth P transistor PM5 is connected to the power supply, and the drain of the fifth P transistor PM5 is connected to the source of the third P transistor PM3. The gate of the fifth P transistor PM5 is shorted to the drain of the second P transistor PM2 and connected to the fourth signal line. The gate of the fifth P transistor PM5 is shorted to the drain of the second P transistor PM2 and then connected to the gate of the fourth P transistor PM4.

[0111] The drain of the third P transistor PM3 is connected to the drain of the eighth N transistor NM8. The terminal led out between the drain of the third P transistor PM3 and the drain of the eighth N transistor NM8 is connected to the common gate terminal between the fifth N transistor NM5 and the sixth N transistor NM6 and connected to the third signal line.

[0112] The source of the eighth N-transistor NM8 is connected to the drain of the sixth N-transistor NM6, and the source of the sixth N-transistor NM6 is connected to the emitter of the third transistor Q3.

[0113] A terminal is led out between the source of the sixth N-transistor NM6 and the emitter of the third transistor Q3 and connected to the drain of the sixth P-transistor PM6; the collector and base of the third transistor Q3 are shorted and then connected to the ground terminal.

[0114] The source of the seventh P transistor PM7 is connected to the power supply, the drain of the seventh P transistor PM7 is connected to the source of the sixth P transistor PM6, and the gate of the seventh P transistor PM7 is connected to the fourth signal line.

[0115] The drain of the sixth P-type transistor PM6 is connected to the emitter of the third transistor, and the gate of the sixth P-type transistor PM6 is connected to the first signal line.

[0116] The source of the ninth P-type transistor PM9 is connected to the power supply, the drain of the ninth P-type transistor PM9 is connected to the source of the eighth P-type transistor PM8, and the gate of the ninth P-type transistor PM9 is connected to the fourth signal line.

[0117] The drain of the eighth P transistor PM8 is connected to the drain of the ninth N transistor NM9, and a terminal is led out between the drain of the eighth P transistor PM8 and the drain of the ninth N transistor NM9 and connected to the second signal line; the gate of the eighth P transistor PM8 is connected to the first signal line.

[0118] The gate and drain of the ninth N-transistor NM9 are shorted together; the source of the ninth N-transistor NM9 is connected to the emitter of the fourth transistor Q4.

[0119] The collector and base of the fourth transistor Q4 are shorted and then connected to the ground terminal.

[0120] Specifically, see Figure 2 and Figure 7The PTAT current generation circuit XI1 consists of PMOS transistors PM1, PM2, PM3, PM4, PM5, PM6, PM7, PM8, PM9, NMOS transistors NM3, NM4, NM5, NM6, NM7, NM8, NM9, and PNP transistors Q1, Q2, Q3, Q4. The circuit composed of PM2, PM3, PM4, PM5 and NM5, NM6, NM7, NM8 is a typical self-biased structure. The branch composed of PM1, NM4, NM3, and Q1 provides the bias voltage signal net1 for this self-biased structure, and the branch composed of PM9, PM8, NM9, and Q4 provides the bias voltage signal net2 for this self-biased structure. The common-source cascode current mirror composed of PM7 and PM6 provides current to transistor Q3.

[0121] When the PTAT current generation circuit XI1 is working, since the width-to-length ratios of transistors PM4, PM2, PM5, and PM3 are equal, the potentials at points A and B are forced to be equal under the action of the common-source cascode current mirror. The gate voltage of transistor NM5 is equal to the gate voltage of transistor NM6, and the voltage flowing through them is equal. Therefore, the overdrive voltages of transistors NM5 and NM6 are equal, i.e., VA = VB. Since the width-to-length ratio of transistors PM7 and PM8 is M times that of transistors PM5 and PM3, the current flowing through transistors PM7, PM8, and Q3 is also M times that of transistors PM5 and PM3. The number of parallel Q2 transistors is N times that of Q3 transistors, so the current flowing through Q4 should be N*M+1 times the single-transistor current of Q2. Therefore, the current I flowing through resistor R0 is... R0 for:

[0122]

[0123] Among them, V EBQ2 and V EBQ3 The emitter-junction voltages of transistors Q2 and Q3 are V, respectively. T Let I be the thermal voltage, k be Boltzmann's constant, T be the thermodynamic temperature, q be the electron charge, and R0 be the resistance of the zeroth resistance R0. From the above formula, we can see that I R0 It is directly proportional to the thermodynamic temperature T, and has a positive temperature coefficient. Because the current flowing through the PM4 and PM2 tubes is related to I... R0 Since the width-to-length ratios of PM4, PM2, PM5, and PM3 tubes are equal, the current in PM4 and PM5 tubes is also equal to I. R0 I R0 The current is biased by the voltages of net1 and net2 and copied to other circuits in multiples by the current mirror structure for current biasing.

[0124] This module adopts a self-biased structure without op-amps, which has low power supply voltage requirements. It only requires two overdrive voltages of NM6 and PM5 and the diode turn-on voltage of Q2 or Q3 to work normally, making it very suitable for low power supply voltage operating conditions.

[0125] In some specific implementation methods, see Figure 3 The startup circuit includes:

[0126] Zero P tube PM0;

[0127] Zero N tube NM0, first N tube NM1, and second N tube NM2;

[0128] Transistor Q0 (zeroth transistor);

[0129] The source of the zero-P transistor PM0 is connected to the power supply, the gate of the zero-P transistor PM0 is grounded, and the drain of the zero-P transistor PM0 is connected to the drain of the zero-N transistor NM0. After the drain of the zero-P transistor PM0 is connected to the drain of the zero-N transistor NM0, the sixth signal line is connected.

[0130] The zeroth N-transistor NM0, the first N-transistor NM1, and the second N-transistor NM2 are connected to the common source, and the terminal after the common source connection is connected to the emitter of the zeroth transistor Q0; the gate of the zeroth N-transistor NM0 is connected to the third signal line; the drain of the first N-transistor NM1 is connected to the first signal line; the drain of the second N-transistor NM2 is connected to the fourth signal line; the gates of the first N-transistor NM1 and the second N-transistor NM2 are connected to the sixth signal line.

[0131] The collector and base of the zeroth transistor Q0 are shorted and then connected to the ground terminal.

[0132] Specifically, see Figure 3 and Figure 7 XI2 consists of PMOS transistor PM0, NMOS transistors NM0, NM1, NM2, and PNP transistor Q0. PM0 uses an inverting transistor to limit the current flowing through PNP transistor Q0. When the PTAT current generation circuit XI1 is operating at its parallel point, the current of NM6 is zero, so net3 is low, NM0 is off, net6 is high, NM1 and NM2 conduct, pulling net1 and net4 low, and the power supply VDD begins to inject current into transistors PM4 and PM5. Current begins to flow into NM6, and the PTAT current generation circuit XI1 starts to operate. At the same time, the potential of net3 begins to rise, NM0 conducts, pulling net6 low, and NM1 and NM2 are off. After this startup is completed, the startup circuit no longer has any effect on the PTAT current generation circuit.

[0133] In some specific implementation methods, see Figure 4The negative temperature coefficient CTAT current generation circuit includes:

[0134] The tenth P-tube PM10, the eleventh P-tube PM11, the twelfth P-tube PM12, and the thirteenth P-tube PM13;

[0135] The tenth N-tube, NM10;

[0136] First resistor R1 and zeroth capacitor C0;

[0137] The source of the eleventh P-type transistor PM11 is connected to the power supply; the drain of the eleventh P-type transistor PM11 is connected to the source of the tenth P-type transistor PM10; the gate of the eleventh P-type transistor PM11 is connected to the fourth signal line, and the gate of the tenth P-type transistor PM10 is connected to the first signal line; the drain of the tenth P-type transistor PM10 is connected to the drain of the tenth N-type transistor NM10, and a terminal is led out between the drain of the tenth P-type transistor PM10 and the drain of the tenth N-type transistor NM10 to connect to the fifth signal line; the terminal is also led out between the drain of the tenth P-type transistor PM10 and the drain of the tenth N-type transistor NM10 to connect to the gate of the thirteenth P-type transistor PM13 and the first end of the zero capacitor C0.

[0138] The source of the tenth N transistor NM10 is connected to the first terminal of the first resistor R1, and the lead-out terminal between the source of the tenth N transistor NM10 and the first terminal of the first resistor R1 is connected to the second terminal of the zero capacitor C0. The lead-out terminal between the source of the tenth N transistor NM10 and the first terminal of the first resistor R1 is also connected to the drain of the twelfth P transistor PM12; the second terminal of the first resistor R1 is grounded.

[0139] The source of the thirteenth P-type transistor PM13 is connected to the power supply, and the drain of the thirteenth P-type transistor PM13 is connected to the source of the twelfth P-type transistor PM12; the gate of the twelfth P-type transistor PM12 is connected to the first signal line.

[0140] Specifically, see Figure 4 and Figure 7 The CTAT current generation circuit XI3 consists of PMOS transistors PM10, PM11, PM12, PM13, NMOS transistor NM10, capacitor C0, and resistor R1. The function of capacitor C0 is to stabilize the voltage output on the net5 signal. PM10 and PM11 form a common source cascode current mirror to provide bias current for NM10.

[0141] Net4 and Net1 are voltage biases drawn from the PTAT current generation circuit XI1, which provide current to the NM10 transistor through a common-source cascode current mirror. Since the width-to-length ratio of PM11 and PM10 is equal to that of PM5 and PM3, the current flowing through the NM10 transistor should be equal to the current flowing through the NM6 transistor. Therefore, the overdrive voltage of the NM10 transistor should be equal to the overdrive voltage of the NM6 transistor. In other words, the voltage at point C should be equal to the voltages at points A and B, i.e., V... A=V B =V C The voltage at point B comes from the emitter voltage V of Q3. EBQ3 V EBQ3 Under constant current bias and a negative temperature coefficient voltage, the current I flowing through resistor R1 is... R1 for:

[0142]

[0143] I R1 For a current with a negative temperature coefficient, then:

[0144] I R1 =I NM10 +I PM13

[0145] but:

[0146] I PM13 =I R1 -I NM10 =I R1 -I R0

[0147] I R1 For a negative temperature coefficient current, I R0 For a current with a positive temperature coefficient, adding a negative sign results in a current with a negative temperature coefficient. Therefore, I... PM13 This is a negative temperature coefficient current, which generates a CTAT (negative temperature coefficient) current.

[0148] In some specific implementation methods, see Figure 5 The zero-temperature current reference generation circuit XI4 includes:

[0149] Pipe 14 PM14, pipe 15 PM15, and pipe 16 PM16;

[0150] Eleventh N-tube NM11;

[0151] The fifteenth P-type transistor PM15 and the sixteenth P-type transistor PM16 are connected with common source and common drain, and the common source terminal is connected to the power supply, and the common drain terminal is connected to the source of the fourteenth P-type transistor PM14; the gate of the fifteenth P-type transistor PM15 is connected to the fifth signal line, and the gate of the sixteenth P-type transistor PM16 is connected to the fourth signal line.

[0152] The drain of the fourteenth P-type transistor PM14 is connected to the drain of the eleventh N-type transistor NM11, and the gate of the fourteenth P-type transistor PM14 is connected to the first signal line; a reference current source IREF is led out between the drain of the fourteenth P-type transistor PM14 and the drain of the eleventh N-type transistor NM11.

[0153] The drain of the eleventh N transistor NM11 is connected to the gate, and the source of the eleventh N transistor NM11 is grounded.

[0154] Specifically, see Figure 5 and Figure 7 The zero-temperature current reference generation circuit XI4 consists of PMOS transistors PM14, PM15, PM16, and NMOS transistor NM11. The zero-temperature reference current flowing through the source of transistor PM16 is obtained by linearly superimposing the PTAT current flowing through the source of transistor PM15. Finally, the zero-temperature reference current flowing through transistor NM11 is provided to other modules for biasing via the IREF signal in the form of a current mirror.

[0155] Specifically, assuming the aspect ratio of PM15 tube is T times that of PM13 tube, and the aspect ratio of PM16 tube is K times that of PM4 tube, then the current flowing through NM11 tube is:

[0156] I NM11 =I PM15 +I PM16 =T*I R0 +K*I PM13

[0157] Differentiating both sides with respect to thermodynamic temperature T, we have:

[0158]

[0159] When I NM11 When the current is zero temperature, we have:

[0160]

[0161] in The term is a positive number. If the term is negative, then adjusting the coefficients of T and K will necessarily make... This establishes a zero-temperature current reference.

[0162] In some specific implementation methods, see Figure 6 Zero-temperature voltage reference generation circuit, including:

[0163] Pipe 17 PM17, Pipe 18 PM18, Pipe 19 PM19, Pipe 20 PM20, Pipe 21 PM21, Pipe 22 PM22;

[0164] Transistor Q5 (fifth) and transistor Q6 (sixth);

[0165] The second resistor and the first capacitor;

[0166] The drain of the eighteenth P-tube PM18 is connected to the source of the seventeenth P-tube PM17, the drain of the twentieth P-tube PM20 is connected to the source of the nineteenth P-tube PM19, and the drain of the twenty-second P-tube PM22 is connected to the source of the twenty-first P-tube PM21.

[0167] The eighteenth P-tube PM18, the twentieth P-tube PM20, and the twenty-second P-tube PM22 are connected to the common source, and the common source terminal is connected to the power supply.

[0168] The drain of the seventeenth P-type transistor PM17 is connected to the first terminal of the second resistor, and the drain of the seventeenth P-type transistor PM17 and the first terminal of the second resistor are connected to the gate of the fifth transistor Q5. The gate of the seventeenth P-type transistor PM17 is connected to the first signal line, and the second terminal of the second resistor is grounded.

[0169] The drain of the nineteenth P-type transistor PM9 is connected to the emitter of the fifth transistor Q5. A terminal is led out between the drain of the nineteenth P-type transistor PM19 and the emitter of the fifth transistor Q5 and connected to the gate of the sixth transistor Q6. The collector of the fifth transistor Q5 is grounded.

[0170] The drain of the 21st P-type transistor PM21 is connected to the emitter of the 6th transistor Q6. A terminal is led out between the drain of the 21st P-type transistor PM21 and the emitter of the 6th transistor Q6 and connected to the first terminal of the first capacitor. The collector of the 6th transistor Q6 is connected to the second terminal of the first capacitor and grounded. A reference voltage source VREF is led out between the drain of the 21st P-type transistor PM21 and the emitter of the 6th transistor Q6.

[0171] Specifically, see Figure 6 and Figure 7 The zero-temperature voltage reference generation circuit XI5 consists of PMOS transistors PM17, PM18, PM19, PM20, PM21, and PM22, capacitor C1, resistor R2, and PNP transistors Q5 and Q6. The PTAT current flowing through PM18 acts on resistor R2 to generate the PTAT voltage, which is then superimposed with the negative temperature coefficient emitter voltages of the two PNP transistors Q5 and Q6 to obtain the zero-temperature coefficient voltage reference VREF.

[0172] The aspect ratio of the PM20 transistor is the same as that of the PM22 transistor. Ignoring the base current, the emitter currents flowing through transistors Q5 and Q6 are equal, therefore the emitter voltages of transistors Q5 and Q6 are also equal.

[0173] V EB(Q5) =V EB(Q6)

[0174] Assuming the aspect ratio of the PM18 tube is L times that of the PM4 tube, then the voltage across resistor R2 is:

[0175] V R2 =IPM18 *R2=L*I R0 *R2

[0176] The voltage of VREF is then:

[0177] VREF = V R2 +V EB(Q5) +V EB(Q6) =V R2 +2*V EB(Q5)

[0178] =L*I R0 *R² + 2*V EB(Q5)

[0179] Differentiating both sides with respect to thermodynamic temperature T, we have:

[0180]

[0181] When VREF is the zero-temperature voltage, we have:

[0182]

[0183] in The term is a positive number. If the term is negative, then adjusting the value of L or R2 will necessarily make This establishes a zero-temperature voltage reference.

[0184] This application is applied to low power supply voltage operating conditions and can provide a zero-temperature reference current and a zero-temperature reference voltage simultaneously with fewer components and a simple circuit structure, which can meet the reference requirements of most analog chips.

[0185] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A zero-temperature reference circuit that simultaneously supplies low-voltage power and outputs a voltage reference, characterized in that, include: Start-up circuit, positive temperature coefficient PTAT current generation circuit, negative temperature coefficient CTAT current generation circuit, zero-temperature current reference generation circuit and zero-temperature voltage reference generation circuit; The positive temperature coefficient PTAT current generation circuit is used to generate a positive temperature coefficient current. The first and fourth signal lines in the positive temperature coefficient current are respectively applied to the four common source cascode current mirror structures: the startup circuit, the negative temperature coefficient CTAT current generation circuit, the zero temperature current reference generation circuit, and the zero temperature voltage reference generation circuit. The third signal line is applied to the negative temperature coefficient current generation circuit. The positive temperature coefficient PTAT current generation circuit includes: First P-tube PM1, second P-tube PM2, third P-tube PM3, fourth P-tube PM4, fifth P-tube PM5, sixth P-tube PM6, seventh P-tube PM7, eighth P-tube PM8 and ninth P-tube PM9. The third N-tube NM3, the fourth N-tube NM4, the fifth N-tube NM5, the sixth N-tube NM6, the seventh N-tube NM7, the eighth N-tube NM8, and the ninth N-tube NM9; The first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4; The source of the first P-type transistor PM1 is connected to the power supply, and the drain is shorted to the gate and connected to the first signal line. The drain of the first P-type transistor PM1 is connected to the drain of the fourth N-type transistor NM4. The source of the fourth N-transistor NM4 is connected to the drain of the third N-transistor NM3, and the gate of the fourth N-transistor NM4 is connected to the second signal line. The source of the third N-transistor NM3 is connected to the emitter of the first transistor Q1, and the gate of the third N-transistor NM3 is connected to the third signal line; the collector and base of the first transistor Q1 are shorted and then connected to the ground terminal. The positive temperature coefficient PTAT current generation circuit further includes: The source of the fourth P-tube PM4 is connected to the power supply, and its drain is connected to the source of the second P-tube PM2. The gate of the fourth P-tube PM4 is shorted to the drain of the second P-tube PM2 and connected to the fourth signal line. The gate of the fourth P-tube PM4 is shorted to the drain of the second P-tube PM2 and then connected to the gate of the fifth P-tube PM5. The drain of the second P-type transistor PM2 is connected to the drain of the seventh N-type transistor NM7; the gate of the second P-type transistor PM2 is connected to the gate of the third P-type transistor PM3. The source of the seventh N-transistor NM7 is connected to the drain of the fifth N-transistor NM5, and the gate of the seventh N-transistor NM7 is connected to the gate of the eighth N-transistor NM8. After the gates of the seventh N-transistor NM7 and the eighth N-transistor NM8 are connected, a terminal is led out and connected to the second signal line. The source of the fifth N-transistor NM5 is connected to the first terminal of the zero resistance R0. The gate of the fifth N-transistor NM5 is connected to the gate of the sixth N-transistor NM6 and a terminal is led out to connect to the third signal line. A terminal is led out between the gate of the fifth N-transistor NM5 and the gate of the sixth N-transistor NM6 and connected to the drain of the eighth N-transistor NM8. The second end of the zero resistor R0 is connected to the emitter of the second transistor Q2, and the collector and base of the second transistor Q2 are shorted and then connected to the ground terminal. The positive temperature coefficient PTAT current generation circuit further includes: The source of the fifth P transistor PM5 is connected to the power supply, and the drain of the fifth P transistor PM5 is connected to the source of the third P transistor PM3. The gate of the fifth P transistor PM5 is shorted to the drain of the second P transistor PM2 and connected to the fourth signal line. The gate of the fifth P transistor PM5 is shorted to the drain of the second P transistor PM2 and then connected to the gate of the fourth P transistor PM4. The drain of the third P transistor PM3 is connected to the drain of the eighth N transistor NM8. The terminal led out between the drain of the third P transistor PM3 and the drain of the eighth N transistor NM8 is connected to the common gate terminal between the fifth N transistor NM5 and the sixth N transistor NM6 and connected to the third signal line. The source of the eighth N-transistor NM8 is connected to the drain of the sixth N-transistor NM6, and the source of the sixth N-transistor NM6 is connected to the emitter of the third transistor Q3. A terminal is led out between the source of the sixth N-transistor NM6 and the emitter of the third transistor Q3 and connected to the drain of the sixth P-transistor PM6; the collector and base of the third transistor Q3 are shorted and then connected to the ground terminal. The source of the seventh P transistor PM7 is connected to the power supply, the drain of the seventh P transistor PM7 is connected to the source of the sixth P transistor PM6, and the gate of the seventh P transistor PM7 is connected to the fourth signal line. The drain of the sixth P-type transistor PM6 is connected to the emitter of the third transistor, and the gate of the sixth P-type transistor PM6 is connected to the first signal line. The positive temperature coefficient PTAT current generation circuit further includes: The source of the ninth P-type transistor PM9 is connected to the power supply, the drain of the ninth P-type transistor PM9 is connected to the source of the eighth P-type transistor PM8, and the gate of the ninth P-type transistor PM9 is connected to the fourth signal line. The drain of the eighth P transistor PM8 is connected to the drain of the ninth N transistor NM9, and a terminal is led out between the drain of the eighth P transistor PM8 and the drain of the ninth N transistor NM9 and connected to the second signal line; the gate of the eighth P transistor PM8 is connected to the first signal line. The gate and drain of the ninth N-transistor NM9 are shorted together; the source of the ninth N-transistor NM9 is connected to the emitter of the fourth transistor Q4. The collector and base of the fourth transistor Q4 are shorted and then connected to the ground terminal; The startup circuit is connected to the positive temperature coefficient current generation circuit through the first signal line and the fourth signal line, which is used to prevent the positive temperature coefficient current generation circuit from working at the parallel point when the chip is powered on, and to start the positive temperature coefficient current generation circuit. The negative temperature coefficient current generating circuit is connected to the positive temperature coefficient current generating circuit through the first signal line, the fourth signal line and the third signal line, and is used to generate negative temperature coefficient current. The negative temperature coefficient CTAT current generation circuit includes: The tenth P-tube PM10, the eleventh P-tube PM11, the twelfth P-tube PM12, and the thirteenth P-tube PM13; The tenth N-tube, NM10; First resistor R1 and zeroth capacitor C0; The source of the eleventh P-type transistor PM11 is connected to the power supply; the drain of the eleventh P-type transistor PM11 is connected to the source of the tenth P-type transistor PM10; the gate of the eleventh P-type transistor PM11 is connected to the fourth signal line, and the gate of the tenth P-type transistor PM10 is connected to the first signal line; the drain of the tenth P-type transistor PM10 is connected to the drain of the tenth N-type transistor NM10, and a terminal is led out between the drain of the tenth P-type transistor PM10 and the drain of the tenth N-type transistor NM10 to connect to the fifth signal line; the terminal is also led out between the drain of the tenth P-type transistor PM10 and the drain of the tenth N-type transistor NM10 to connect to the gate of the thirteenth P-type transistor PM13 and the first end of the zero capacitor C0. The source of the tenth N transistor NM10 is connected to the first terminal of the first resistor R1, and the lead-out terminal between the source of the tenth N transistor NM10 and the first terminal of the first resistor R1 is connected to the second terminal of the zero capacitor C0. The lead-out terminal between the source of the tenth N transistor NM10 and the first terminal of the first resistor R1 is also connected to the drain of the twelfth P transistor PM12; the second terminal of the first resistor R1 is grounded. The source of the thirteenth P-type transistor PM13 is connected to the power supply, and the drain of the thirteenth P-type transistor PM13 is connected to the source of the twelfth P-type transistor PM12; the gate of the twelfth P-type transistor PM12 is connected to the first signal line. The zero-temperature current reference generation circuit is connected to the positive temperature coefficient circuit through the first signal line and the fourth signal line, and to the negative temperature coefficient circuit through the fifth signal line, in order to generate a zero-temperature current reference. The zero-temperature voltage reference generation circuit is connected to the positive temperature coefficient circuit through the first signal line and the fourth signal line, and to the negative temperature coefficient circuit through the fifth signal line, in order to generate a zero-temperature voltage reference.

2. The zero-temperature reference circuit according to claim 1, characterized in that, The startup circuit includes: Zero P-tube PM0; Zero N tube NM0, first N tube NM1, and second N tube NM2; Transistor Q0 (zeroth transistor); The source of the zero-P transistor PM0 is connected to the power supply, the gate of the zero-P transistor PM0 is grounded, and the drain of the zero-P transistor PM0 is connected to the drain of the zero-N transistor NM0. After the drain of the zero-P transistor PM0 is connected to the drain of the zero-N transistor NM0, the sixth signal line is connected. The zeroth N-transistor NM0, the first N-transistor NM1, and the second N-transistor NM2 are connected to the common source, and the terminal after the common source connection is connected to the emitter of the zeroth transistor Q0; the gate of the zeroth N-transistor NM0 is connected to the third signal line; the drain of the first N-transistor NM1 is connected to the first signal line; the drain of the second N-transistor NM2 is connected to the fourth signal line; the gates of the first N-transistor NM1 and the second N-transistor NM2 are connected to the sixth signal line. The collector and base of the zeroth transistor Q0 are shorted and then connected to the ground terminal.

3. The zero-temperature reference circuit according to claim 1, characterized in that, The zero-temperature current reference generation circuit includes: Pipe 14 PM14, pipe 15 PM15, and pipe 16 PM16; Eleventh N-tube NM11; The fifteenth P-type transistor PM15 and the sixteenth P-type transistor PM16 are connected with common source and common drain, and the common source terminal is connected to the power supply, and the common drain terminal is connected to the source of the fourteenth P-type transistor PM14; the gate of the fifteenth P-type transistor PM15 is connected to the fifth signal line, and the gate of the sixteenth P-type transistor PM16 is connected to the fourth signal line. The drain of the fourteenth P-type transistor PM14 is connected to the drain of the eleventh N-type transistor NM11, and the gate of the fourteenth P-type transistor PM14 is connected to the first signal line; a reference current source IREF is led out between the drain of the fourteenth P-type transistor PM14 and the drain of the eleventh N-type transistor NM11. The drain of the eleventh N transistor NM11 is connected to the gate, and the source of the eleventh N transistor NM11 is grounded.

4. The zero-temperature reference circuit according to claim 1, characterized in that, Zero-temperature voltage reference generation circuit, including: Pipe 17 PM17, Pipe 18 PM18, Pipe 19 PM19, Pipe 20 PM20, Pipe 21 PM21, and Pipe 22 PM22. Transistor Q5 (fifth) and transistor Q6 (sixth); Second resistor R2; The drain of the eighteenth P-tube PM18 is connected to the source of the seventeenth P-tube PM17, the drain of the twentieth P-tube PM20 is connected to the source of the nineteenth P-tube PM19, and the drain of the twenty-second P-tube PM22 is connected to the source of the twenty-first P-tube PM21. The eighteenth P-tube PM18, the twentieth P-tube PM20, and the twenty-second P-tube PM22 are connected to the common source, and the common source terminal is connected to the power supply. The drain of the seventeenth P-type transistor PM17 is connected to the first terminal of the second resistor R2, and the drain of the seventeenth P-type transistor PM17 and the first terminal of the second resistor R2 are connected to the gate of the fifth transistor Q5. The gate of the seventeenth P-type transistor PM17 is connected to the first signal line, and the second terminal of the second resistor R2 is grounded.

5. The zero-temperature reference circuit according to claim 4, characterized in that, The zero-temperature voltage reference generation circuit also includes: First capacitor C1; The drain of the nineteenth P-type transistor PM9 is connected to the emitter of the fifth transistor Q5. A terminal is led out between the drain of the nineteenth P-type transistor PM19 and the emitter of the fifth transistor Q5 and connected to the gate of the sixth transistor Q6. The collector of the fifth transistor Q5 is grounded. The drain of the 21st P-type transistor PM21 is connected to the emitter of the 6th transistor Q6. A terminal is led out between the drain of the 21st P-type transistor PM21 and the emitter of the 6th transistor Q6 and connected to the first terminal of the first capacitor C1. The collector of the 6th transistor Q6 is connected to the second terminal of the first capacitor C1 and grounded. A reference voltage source VREF is led out between the drain of the 21st P-type transistor PM21 and the emitter of the 6th transistor Q6.

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