FPGA-based RS485 bus non-blocking access communication method and system
By implementing non-blocking RS485 bus access communication through FPGA, the system latency and data conflict problems caused by half-duplex communication of RS485 bus are solved, realizing efficient and flexible bus communication, which is suitable for internal communication of high-orbit satellites.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIAN MICROELECTRONICS TECH INST
- Filing Date
- 2025-08-27
- Publication Date
- 2026-07-31
AI Technical Summary
Traditional 485 buses are limited by half-duplex communication, requiring the master node to query each slave node one by one, which increases system latency and easily leads to bus contention and data conflicts.
The non-blocking access communication method of RS485 bus based on FPGA is adopted. When the master node detects that the bus is idle, it sends read and write commands. The slave nodes detect and execute the commands in real time. The communication between master and slave is realized through FPGA, and the bus idle threshold is set for priority sorting.
It enables non-blocking access of the master node to each child node, improves bus efficiency, reduces system latency, avoids data conflicts, and has high concurrency and flexibility, making it suitable for internal communication of high-orbit satellites.
Smart Images
Figure CN121116873B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of communication technology and relates to an FPGA-based RS485 bus non-blocking access communication method and system. Background Technology
[0002] Traditional satellite backups typically employ cold or hot backups for full system backup. Compared to systems without backups, both cold and hot backups can improve system reliability by approximately 20% under the same application environment. However, full system backups concentrate the failure risk, only tolerating system-wide failures. For high-orbit satellites with high orbital requirements and long lifespans, a single board failure necessitates the termination of the entire system, reducing the satellite's lifespan. In contrast, fine-grained board-level cross-backup can improve system reliability by approximately 30%, and board-level redundancy allows for partial fault switching without affecting the overall system. It can tolerate multiple board failures, thus extending the overall satellite lifespan.
[0003] Traditional satellite communication within a single unit uses the EMIF bus. However, the EMIF bus has many data and address lines, making it difficult to implement backend routing during single-board cross-backup. Therefore, other buses are needed for internal communication and cross-backup within the unit. The commonly used CAN bus lacks high-level chips and is unsuitable for high-orbit applications, while the 1553 bus control chip is expensive and complex to control. Therefore, the RS-485 bus is used as the physical and data link layers for communication, and FPGA is used to implement communication between one master and multiple slave nodes on the RS-485 bus. However, the traditional RS-485 bus is limited by half-duplex communication, requiring the master node to query each slave node individually, increasing system latency and easily leading to bus contention and data conflicts. Summary of the Invention
[0004] The purpose of this invention is to solve the problems in the existing technology where the traditional RS485 bus is limited by half-duplex communication, requiring the master node to query each slave node one by one, which increases system latency and easily leads to bus contention and data conflicts. The invention provides an FPGA-based RS485 bus non-blocking access communication method and system to avoid system latency and improve bus efficiency.
[0005] To achieve the above objectives, the present invention employs the following technical solution:
[0006] An FPGA-based non-blocking RS485 bus communication method includes an RS485 bus, with one master node and multiple child nodes on the RS485 bus. The RS485 bus communication method includes the following steps:
[0007] The master node obtains read and write commands. When it detects that the RS485 bus is idle, the master node sends the read and write commands to the RS485 bus.
[0008] Each child node monitors read and write commands on the RS485 bus in real time. When it detects that the read and write command on the bus is consistent with its own read and write command, the child node executes the write command and generates feedback data based on the read command. When it detects that the bus is idle, it sends feedback data to the RS485 bus.
[0009] The master node verifies the read data returned by the child node, and stores the read data after the verification is successful.
[0010] A further improvement of the present invention is that:
[0011] During detection, the bus idle thresholds of the master node and the child node are set, and the bus idle thresholds of the master node and the child node are prioritized.
[0012] The bus idle threshold interval between different child nodes is 2 bytes of data transmission time.
[0013] When prioritizing the bus idle thresholds of the master node and the child node, the bus idle threshold of the child node with the highest priority is 2 bytes of data transmission time.
[0014] When prioritizing the bus idle thresholds of the master node and the child nodes, the bus idle threshold of the master node is greater than the bus idle threshold of any child node.
[0015] The master node acquires read / write commands. When it detects that the bus is idle, the master node sends read / write commands to the RS485 bus, including:
[0016] The processor frames data according to the application layer protocol and writes read and write instructions to the RS485 transmit buffer of the master node FPGA.
[0017] The master node parses the validity of the read and write commands to obtain the parsed read and write commands. When it receives a complete frame of data and detects that the bus is idle, the master node sends the read and write commands to the RS485 bus.
[0018] Each sub-node monitors read and write commands on the RS485 bus in real time, including:
[0019] Each child node monitors the data on the RS485 bus in real time. When it detects an instruction whose child node address code matches its own child node address code in the data on the bus, it checks the instruction. If the instruction is correct, it executes the instruction.
[0020] An FPGA-based RS485 bus non-blocking access communication system includes an RS485 bus, on which there is one master node and multiple child nodes. The RS485 bus communication method includes:
[0021] The master node processing module 1 is used for the master node to obtain read and write instructions. When the RS485 bus is detected to be idle, the master node sends the read and write instructions to the RS485 bus.
[0022] The sub-node processing module is used for each sub-node to detect read and write commands on the RS485 bus in real time. When the read and write command on the bus is detected to be consistent with its own read and write command, the sub-node executes the write command and generates feedback data according to the read command. When the bus is detected to be idle, the sub-node sends feedback data to the RS485 bus. The master node verifies the read data fed back by the sub-node. If the verification is correct, the read data is stored.
[0023] It also includes a priority sorting module, which is used to set the bus idle threshold of the master node and the bus idle threshold of the child node during detection, and to sort the bus idle thresholds of the master node and the child node by priority.
[0024] The bus idle threshold interval between different child nodes is 2 bytes of data transmission time.
[0025] Compared with the prior art, the present invention has the following beneficial effects:
[0026] This invention discloses a non-blocking access communication method for RS485 bus based on FPGA. The RS485 bus has one master node and multiple slave nodes. The master node can access each slave node non-blockingly through the RS485 bus. Each slave node detects read and write commands on the RS485 bus in real time and executes the corresponding operation. Communication between one master and multiple slave nodes on the RS485 bus is realized through FPGA. The communication system has high concurrency capability and strong flexibility. The master node can initiate communication at any time, and the master node's access operation is non-blocking. It can continue to execute other tasks or initiate the next access without waiting for the slave nodes' reply. The master node does not need to query each slave node one by one, avoiding system delay and improving bus efficiency.
[0027] Furthermore, in this invention, a bus idle threshold is set for the master node and a bus idle threshold for the slave nodes. The bus idle thresholds of the master node and the slave nodes are prioritized. The master node and each slave node perform bus idle detection and priority evaluation in a distributed manner to ensure that high-priority data is transmitted first. Attached Figure Description
[0028] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0029] Figure 1 This is a schematic diagram of the communication principle of the present invention. Detailed Implementation
[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0031] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.
[0032] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0033] In the description of the embodiments of the present invention, it should be noted that if terms such as "upper," "lower," "horizontal," or "inner" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, terms such as "first" and "second" are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0034] Furthermore, the use of the term "horizontal" does not imply that the component must be absolutely horizontal, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.
[0035] In the description of the embodiments of the present invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific circumstances.
[0036] The present invention will now be described in further detail with reference to the accompanying drawings:
[0037] See Figure 1 This invention discloses a non-blocking access communication method for RS485 bus based on FPGA, comprising the following steps:
[0038] Step 1: The master node obtains read / write commands. When the bus is detected to be idle, the master node sends read / write commands to the RS485 bus.
[0039] Specifically: When the processor accesses each child node through the master node, it frames the data according to the application layer protocol, writes the read and write instructions into the 485 transmit buffer of the master node FPGA, parses the validity of the data, and sends the data to the 485 bus when it receives a complete frame of data and detects that the bus is idle.
[0040] Step 2: Each child node detects the consistency between the read / write commands on the RS485 bus and its own read / write commands in real time. When the consistency between the read / write commands on the bus and its own read / write commands is detected, the child node starts to execute the write command and feeds back the read data to the bus according to the read command.
[0041] Specifically: Each child node monitors the data on the 485 bus in real time. When it detects an instruction whose address code matches its own, it checks the instruction. If the instruction is correct, write instructions are executed directly, and read instructions are sent out when the bus is detected to be idle.
[0042] Step 3: The master node verifies the read data returned by the child node, and stores the data after the verification is successful;
[0043] Specifically: The master node FPGA verifies the read data returned on the bus, and if the verification is correct, it buffers the data in the 485 receive buffer.
[0044] Furthermore, in this invention, the processor can send instructions randomly, and only needs to periodically read the master node data to complete the access to each child node.
[0045] Furthermore, in this invention, during detection, a bus idle threshold for the master node and a bus idle threshold for the child node are set, and the bus idle thresholds for the master node and the child node are prioritized, specifically including:
[0046] When the 485 bus is held high, it is in an idle state. To enable the master node and each child node to perform bus idle detection in a distributed manner, evaluate priorities, and execute instructions in order according to their priorities to send data, different bus idle thresholds are set for the master node and child nodes in the FPGA design. The bus idle threshold for the highest priority child node is set to 2 bytes of data transmission time, and the bus idle threshold interval between different child nodes is 2 bytes of data transmission time. Since the master node is the data initiator, its bus idle threshold is set to the longest to prevent data conflicts between the master node and child nodes.
[0047] Furthermore, in this invention, the 485 bus access is converted into EMIF bus access for each individual board through a bus protocol. The bus application layer protocol is shown in Table 1:
[0048] Table 1 Bus Application Layer Protocol
[0049]
[0050] (1) Frame header: 0xEB90, used to determine the start of a frame of data;
[0051] (2) Operation type code: 0xAA, the master node performs a write operation on one or more registers of a child node; 0x55, the master node performs a read operation on one or more registers of a child node;
[0052] (3) Child node address code: Each child node is assigned a fixed child node address code, and a maximum of 16 child nodes can be connected. If there are more than 16 child nodes, the length of this item can be increased.
[0053] (4) Operation control code: 0011, the master node performs continuous read / write operations on the offset address of a certain child node, and the number of consecutive writes is the frame length; 1100, the master node performs read / write operations on a certain child node starting from the offset address and incrementing by 1, and the increment is the frame length.
[0054] (5) Offset address code: 0x0000-0xFFFF, the register address of each functional module inside the child node;
[0055] (6) Frame length: used to identify the number of bytes in the data field;
[0056] (7) Data Field: When the master node performs a write operation on a child node's register, this field stores the data to be written, with a maximum length of 1024 bytes. When the master node performs a read operation on a child node's register, this field is always empty in the read command frame. In the data frame returned by the child node to the master node, this field contains the data returned by the child node, with a maximum length of 1024 bytes. When the data in the data field consists of data from multiple addresses, the data at the lower address comes first, followed by the data at the higher address.
[0057] (8) Checksum: The sum of the frame data (from the operation type code to the last byte of the data field).
[0058] This invention enables the processor to access different child nodes in a non-blocking manner through the design of the application layer protocol, and achieves ordered data transmission between the master node and each child node through idle detection and priority autonomous judgment of each node.
[0059] Furthermore, in application, the method of this invention successfully solved the design requirement of cross-backup for a certain type of high-orbit satellite mission computer. In this computer, each board adopts cross-backup, RS485 is used as the internal bus for communication, and the processor on the master node achieves non-blocking access to the sub-nodes of each board through an FPGA. The master node FPGA implements caching and judgment of processor access data, caching and judgment of data of each sub-node, and autonomous arbitration of bus idle time and bus priority. The sub-node FPGA completes data parsing and autonomous arbitration of bus idle time and bus priority.
[0060] This invention also discloses an FPGA-based RS485 bus non-blocking access communication system, including an RS485 bus, a master node and multiple child nodes on the RS485 bus, and an RS485 bus communication method including:
[0061] The master node processing module 1 is used for the master node to obtain read and write instructions. When the bus is detected to be idle, the master node sends the read and write instructions to the RS485 bus.
[0062] The sub-node processing module is used for each sub-node to detect the consistency between the read and write commands on the RS485 bus and its own read and write commands in real time. When the consistency between the read and write commands on the bus and its own read and write commands is detected, the sub-node starts to execute the write command and feeds back the read data to the bus according to the read command.
[0063] The second master node processing module is used by the master node to verify the read data fed back by the child nodes, and to store the data after the verification is correct.
[0064] This invention proposes an FPGA-based RS485 bus non-blocking access communication system and method, suitable for internal communication within a single high-orbit satellite. The system uses an FPGA to implement communication between one master and multiple slave nodes via an RS485 bus. The master node can access each slave node non-blockingly via the RS485 bus. Slave nodes confirm instruction ownership by comparing the target ID in the data packet header with their own node ID, and confirm the instruction attribute and execute the corresponding operation based on the instruction code and address code in the data packet header. The master node and each slave node perform distributed bus idle detection and priority evaluation to ensure that high-priority data is transmitted first. Compared to traditional communication systems, this system has higher concurrency capabilities and greater flexibility. The master node can initiate communication at any time, and its access operation is non-blocking, allowing it to continue executing other tasks or initiate the next access without waiting for a response from a slave node. The system uses an RS485 bus for communication, offering low cost and interference resistance, meeting the spacecraft's requirements for reliability, radiation resistance, and low power consumption.
[0065] The above are merely preferred embodiments of the present invention and are not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A non-blocking access communication method for RS485 bus based on FPGA, characterized in that, The RS485 bus includes one master node and multiple slave nodes. The RS485 bus communication method includes the following steps: The master node obtains read and write commands. When it detects that the RS485 bus is idle, the master node sends the read and write commands to the RS485 bus. Each child node monitors read and write commands on the RS485 bus in real time. When it detects that the read and write command on the bus is consistent with its own read and write command, the child node executes the write command and generates feedback data based on the read command. When it detects that the bus is idle, it sends feedback data to the RS485 bus. The master node verifies the read data returned by the child node, and stores the read data after the verification is correct. During detection, the bus idle thresholds for the master node and the child node are set, and the bus idle thresholds for the master node and the child node are prioritized. The bus idle threshold interval between different child nodes is 2 bytes of data transmission time. When prioritizing the bus idle thresholds of the master node and the child node, the bus idle threshold of the child node with the highest priority is 2 bytes of data transmission time. When prioritizing the bus idle threshold of the master node and the bus idle threshold of the child nodes, the bus idle threshold of the master node is greater than the bus idle threshold of any child node. The master node acquires read / write commands. When it detects that the bus is idle, the master node sends read / write commands to the RS485 bus, including: The processor frames data according to the application layer protocol and writes read and write instructions to the RS485 transmit buffer of the master node FPGA. The master node parses the validity of the read and write commands to obtain the parsed read and write commands. When it receives a complete frame of data and detects that the bus is idle, the master node sends the read and write commands to the RS485 bus. The master node can initiate communication at any time, and the master node's access operation is non-blocking. It can continue to execute other tasks or initiate the next access without waiting for the child nodes' response. The master node does not need to query each child node one by one.
2. The FPGA-based RS485 bus non-blocking access communication method according to claim 1, characterized in that, Each sub-node monitors read and write commands on the RS485 bus in real time, including: Each child node monitors the data on the RS485 bus in real time. When it detects an instruction whose child node address code matches its own child node address code in the data on the bus, it checks the instruction. If the instruction is correct, it executes the instruction.
3. An FPGA-based RS485 bus non-blocking access communication system for implementing the method of claim 1, characterized in that, This includes an RS485 bus, which has one master node and multiple slave nodes. RS485 bus communication methods include: The master node processing module 1 is used for the master node to obtain read and write instructions. When the RS485 bus is detected to be idle, the master node sends the read and write instructions to the RS485 bus. The sub-node processing module is used for each sub-node to detect read and write commands on the RS485 bus in real time. When the read and write command on the bus is detected to be consistent with its own read and write command, the sub-node executes the write command and generates feedback data according to the read command. When the bus is detected to be idle, the sub-node sends feedback data to the RS485 bus. The master node verifies the read data fed back by the sub-node. After the verification is correct, the read data is stored. It also includes a priority sorting module, which is used to set the bus idle threshold of the master node and the bus idle threshold of the child node during detection, and to sort the bus idle threshold of the master node and the bus idle threshold of the child node by priority. The bus idle threshold interval between different child nodes is 2 bytes of data transmission time.