A method for generating and verifying a standard analog circuit cell library

Abstract

This invention discloses a method for generating and verifying a standard cell library for analog circuits, relating to the field of analog circuit design technology. The method includes: acquiring various types of standard cell requirements needed in circuit design; drawing initial layout data for at least one type based on the standard cell requirements; generating other types of standard cell layout data using automated tools; integrating the initial layout data and other types of standard cell layout data into a unified standard cell library; and using verification tools to perform consistency verification on each standard cell in the standard cell library. This invention draws and generates standard cell layouts for multiple process types and automatically integrates circuit symbols and layouts into a unified standard cell library using scripting tools; it employs a batch verification mode to perform layout and circuit consistency verification and design rule checks to ensure that the layout conforms to process specifications. This effectively improves the design efficiency and quality of the standard cell library, providing a reliable foundation for analog circuit design.

Description

Technical Field

[0001] This invention belongs to the field of analog circuit design technology, and in particular relates to a method for generating and verifying a standard cell library for analog circuits. Background Technology

[0002] The development of high-speed, high-performance standard cell libraries in analog circuit design faces complex technical challenges. Traditional standard cell libraries often fail to meet the specific high-speed and high-performance requirements of analog circuits, leading to low design efficiency and limited performance. Currently, in high-speed, high-performance chip design, designers typically choose to customize a layout of high-speed, high-performance standard cells (std cells) suitable for analog circuits, rather than directly using standard digital standard cells provided by the foundry. This leads to the following drawbacks: 1. The R&D cycle has increased significantly, and project costs have risen. 2. As the complexity and performance requirements of chips increase, the number and types of std cells will also increase. Manual operation and verification of each one is tedious and prone to omissions.

[0003] Therefore, constructing a high-speed, high-performance standard cell library suitable for analog circuits has become a critical issue that urgently needs to be addressed. This involves several technical challenges: First, how to determine a list of high-speed, high-performance standard cells suitable for analog circuits to cover the specific needs of analog design. Second, how to efficiently draw and generate standard cell layouts for different process technologies to adapt to various process conditions. Third, how to achieve automatic integration of circuit symbols and layouts to improve the consistency and usability of the cell library. Furthermore, layout and circuit consistency verification and design rule checks are also key aspects of ensuring the quality of the cell library; how to efficiently complete these verification tasks in batch verification mode. For cells that do not meet the requirements, how to optimize them through parameter adjustment and repeated verification to improve the overall quality of the cell library. Finally, how to generate a standard cell library containing layouts and symbols for multiple process technologies, enabling it to directly support the high-speed, high-performance design flow of analog circuits, thereby significantly improving the efficiency and quality of analog circuit design. Summary of the Invention

[0004] The purpose of this invention is to provide a method for generating and verifying a standard analog circuit cell library, which can be achieved through the following technical solutions: This application provides a method for generating and verifying a standard cell library for analog circuits, comprising the following steps: Obtain the various types of standard cell requirements needed in circuit design; Based on the standard unit requirements, draw initial layout data for at least one type; Generate other types of standard cell layout data using automated tools; The initial layout data and the other types of standard cell layout data are integrated into a unified standard cell library; The consistency of each standard unit in the standard unit library is verified using a verification tool, and the verification results are obtained.

[0005] Preferably, the step of drawing initial layout data for at least one type according to the standard unit requirements includes: Determine the circuit structure of the target standard unit based on circuit design requirements; For the target standard unit, draw layout data corresponding to the first type; Perform post-simulation verification on the layout data of the first type and obtain simulation results; Adjust the layout data of the first type based on the simulation results until the design specifications are met; The adjusted layout data of the first type is used as the initial layout data, which serves as the basis for generating other types of standard unit layout data in the future.

[0006] Preferably, the generation of other types of standard cell layout data using automated tools includes: The initial layout data is used as the base template; Using a preset script tool, process parameters are adjusted for the basic template to generate standard cell layout data corresponding to the second type; Using the script tool, process parameters are adjusted for the basic template to generate standard cell layout data corresponding to the third type. A preliminary check is performed on the standard unit layout data of the second type and the third type to confirm their structural consistency with the initial layout data; The standard unit layout data of the second type and the third type are stored as data to be integrated.

[0007] Preferably, the step of integrating the initial layout data and the other types of standard cell layout data into a unified standard cell library includes: The symbol data of the initial layout data and other types of standard unit layout data are obtained through automated scripts; The symbol data is loaded one by one into a preset unit library framework; The automated script concatenates the symbol data to generate a unified symbol view. Acquire the layout data of the initial layout data and other types of standard unit layout data; The layout data is imported one by one into the unit library framework, and the layout is stitched together by the automated script to generate a unified layout view; The unified symbol view and the unified layout view are integrated into a unified standard cell library.

[0008] Preferably, the step of using a verification tool to perform consistency verification on each standard unit in the standard unit library to obtain the verification result includes: A list of names of all standard units in the standard unit library is obtained by using a preset script; For each standard unit in the name list, extract its symbol data and layout data; Through layout and principles Figure 1 The consistency verification tool compares the symbol data and the layout data to determine whether there are any inconsistencies. If there are inconsistencies, it records the corresponding standard unit name and inconsistency details. The layout data is validated using a rule checking tool to obtain the rule validation results. Based on the verification results of the rules and the details of the inconsistency, the final verification result is generated.

[0009] Preferably, the acquisition of the various types of standard cell requirements needed in the circuit design includes: Based on the circuit design objectives, determine the required standard unit function categories in the analog circuit; For the aforementioned standard unit functional categories, the impact of different process types on the performance of the standard unit is analyzed; Based on the degree of influence, various process types suitable for the circuit design objectives are determined; For each of the aforementioned process types, a corresponding list of standard unit requirements is generated; The standard unit requirement list is used to categorize and organize the types and quantities of standard units required for each process type. The standard unit requirement list will be used as the basis for subsequent drawing and generation of layout data.

[0010] Preferably, the step of integrating the initial layout data and the other types of standard cell layout data into a unified standard cell library further includes: The file structure of the initial layout data and other types of standard unit layout data is read using a preset integration tool; Based on the file structure, determine whether the data format of each standard unit is consistent. If they are inconsistent, then use the integration tool to standardize the data format. The standardized initial layout data and other types of standard unit layout data are stored in a preset database; The integration tool is used to classify and manage the data in the database, generating a unified standard unit library. The unified standard unit library is backed up and stored.

[0011] The beneficial effects of this invention are as follows: This invention discloses a design method for a high-speed, high-performance analog circuit standard cell library. By obtaining a list of high-speed, high-performance standard cells suitable for analog circuits, standard cell layouts are drawn and generated for various process types. A scripting tool is used to automatically integrate circuit symbols and layouts into a unified standard cell library. A batch verification mode is employed to verify the layout and circuit consistency of the standard cells and to check design rules, ensuring that the layout conforms to process specifications. For cells that do not meet the requirements, optimization is achieved through parameter adjustment and repeated verification. The final generated standard cell library contains layouts and symbols for multiple process types, which can be directly used to support the high-speed, high-performance design flow of analog circuits, effectively improving the design efficiency and quality of the standard cell library and providing a reliable foundation for analog circuit design. Attached Figure Description

[0012] To better understand and implement this application, the technical solution is described in detail below with reference to the accompanying drawings.

[0013] Figure 1 A flowchart illustrating the steps of a method for generating and verifying a standard analog circuit cell library, as provided in an embodiment of this application. Detailed Implementation

[0014] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, exemplary embodiments will be described in detail below, examples of which are illustrated in the accompanying drawings. In the following description relating to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of methods and systems consistent with some aspects of this application as detailed in the appended claims.

[0015] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to any and all possible combinations comprising one or more of the associated listed items.

[0016] The following detailed description of the specific implementation methods, features, and effects of the present invention, in conjunction with the accompanying drawings and preferred embodiments, is provided in detail.

[0017] Please see Figure 1 This application provides a method for generating and verifying a standard analog circuit cell library, comprising the following steps: S1, obtain the various types of standard cell requirements needed in circuit design; S2, Based on the standard unit requirements, draw initial layout data for at least one type; S3 generates other types of standard cell layout data through automated tools; S4, integrate the initial layout data and the other types of standard cell layout data into a unified standard cell library; S5. Use a verification tool to perform consistency verification on each standard unit in the standard unit library and obtain the verification results.

[0018] Step S1, which involves obtaining the various types of standard cell requirements needed for the circuit design, includes: Based on the circuit design objectives, determine the required standard unit function categories in the analog circuit; For the aforementioned standard unit functional categories, the impact of different process types on the performance of the standard unit is analyzed; Based on the degree of influence, various process types suitable for the circuit design objectives are determined; For each of the aforementioned process types, a corresponding list of standard unit requirements is generated; The standard unit requirement list is used to categorize and organize the types and quantities of standard units required for each process type. The standard unit requirement list will be used as the basis for subsequent drawing and generation of layout data.

[0019] Step S2, which involves drawing initial layout data for at least one type based on the standard unit requirements, includes: Determine the circuit structure of the target standard unit based on circuit design requirements; For the target standard unit, draw layout data corresponding to the first type; Perform post-simulation verification on the layout data of the first type and obtain simulation results; Adjust the layout data of the first type based on the simulation results until the design specifications are met; The adjusted layout data of the first type is used as the initial layout data, which serves as the basis for generating other types of standard unit layout data in the future.

[0020] Step S3, which involves generating other types of standard cell layout data using automated tools, includes: The initial layout data is used as the base template; Using a preset script tool, process parameters are adjusted for the basic template to generate standard cell layout data corresponding to the second type; Using the script tool, process parameters are adjusted for the basic template to generate standard cell layout data corresponding to the third type. A preliminary check is performed on the standard unit layout data of the second type and the third type to confirm their structural consistency with the initial layout data; The standard unit layout data of the second type and the third type are stored as data to be integrated.

[0021] Step S4, which involves integrating the initial layout data and the other types of standard cell layout data into a unified standard cell library, includes: The symbol data of the initial layout data and other types of standard unit layout data are obtained through automated scripts; The symbol data is loaded one by one into a preset unit library framework; The automated script concatenates the symbol data to generate a unified symbol view. Acquire the layout data of the initial layout data and other types of standard unit layout data; The layout data is imported one by one into the unit library framework, and the layout is stitched together by the automated script to generate a unified layout view; The unified symbol view and the unified layout view are integrated into a unified standard cell library.

[0022] Step S5, which involves using a verification tool to perform consistency verification on each standard unit in the standard unit library and obtaining the verification result, includes: A list of names of all standard units in the standard unit library is obtained by using a preset script; For each standard unit in the name list, extract its symbol data and layout data; Through layout and principles Figure 1 The consistency verification tool compares the symbol data and the layout data to determine whether there are any inconsistencies. If there are inconsistencies, it records the corresponding standard unit name and inconsistency details. The layout data is validated using a rule checking tool to obtain the rule validation results. Based on the verification results of the rules and the details of the inconsistency, the final verification result is generated.

[0023] Step S4 further includes: The file structure of the initial layout data and other types of standard unit layout data is read using a preset integration tool; Based on the file structure, determine whether the data format of each standard unit is consistent. If they are inconsistent, then use the integration tool to standardize the data format. The standardized initial layout data and other types of standard unit layout data are stored in a preset database; The integration tool is used to classify and manage the data in the database, generating a unified standard unit library. The unified standard unit library is backed up and stored.

[0024] Specifically, this application will provide a more detailed analysis and explanation of the above steps: a method for generating and verifying a standard analog circuit cell library, comprising: Obtain a list of standard cell circuits required for circuit design, including circuit design information for high-speed, high-performance standard cells suitable for analog circuits, and make an initial selection for at least one process type.

[0025] The process begins by obtaining circuit design requirements documents and extracting information including analog circuit functional descriptions and performance parameters. Based on these descriptions, a standard cell database is queried to filter for high-speed, high-performance standard cell circuit designs suitable for analog circuits. If the filtering results include multiple process types, at least one process type, such as LVT, is initially selected by comparing process type parameters to obtain an initial standard cell list. Using the selected process type, preliminary layout design data for the corresponding standard cells is generated, including symmetry requirements and dummy addition rules. Preliminary post-simulation analysis is performed using the layout design data to obtain analog performance parameters for phase angle, amplitude, and frequency. If the post-simulation analysis results fail to meet preset performance thresholds, the layout design parameters are adjusted, and the layout design data is regenerated. Based on the adjusted layout design data, EMIR analysis is performed to determine if parasitic parameters meet the analog circuit performance requirements. Layout design data that passes EMIR analysis is obtained, and scripts are used to generate standard cell layout data for other process types, such as SLVT and RVT. By integrating layout data from all process types, a final standard cell circuit list containing circuit design information and layout parameters is generated.

[0026] It should be noted that LVT, SLVT, and RVT mentioned above are technology nodes for different types of transistors (especially MOSFETs), and their differences mainly lie in the threshold voltage (Vth) of the transistor. Specifically, LVT (Low Voltage Threshold) indicates a low threshold voltage, used to provide higher performance, but with larger leakage current and higher power consumption; SLVT (Super Low Voltage Threshold) indicates an ultra-low threshold voltage, used to provide extremely high performance and faster switching speeds, but with even larger leakage current and more difficult power management; RVT (Regular Voltage Threshold) indicates a regular threshold voltage, used for designs that balance performance and power consumption requirements, with lower leakage current.

[0027] Furthermore, a dummy (virtual / redundant structure) is a non-functional but physically functional auxiliary structure whose core function is to reduce the impact of manufacturing process variations on circuit performance by balancing the physical environment of the layout. EMIR (Electromigration and IR Drop) is a core component of physical verification for integrated circuits (especially advanced process chips), used to evaluate the reliability and stability of the chip's power network. Its core objective is to ensure that the power / ground network does not fail due to electromigration under high current density, while keeping the voltage drop (IR Drop) of critical circuit nodes within acceptable limits to avoid functional abnormalities.

[0028] Based on the initially selected process type, a standard cell layout of the corresponding type is drawn. After the standard cell layout is drawn, post-simulation and electromagnetic interference analysis are performed to ensure that the layout meets the design requirements.

[0029] Based on the standard cell circuit list provided by the circuit engineer, obtain the initially selected process type, such as LVT, and determine the corresponding layout design rules and parameters. Using layout design tools and the obtained design rules and parameters, draw the LVT type standard cell layout to obtain preliminary layout data. If the preliminary layout data is complete, use post-simulation tools to verify the timing and functionality of the layout to determine if it meets the circuit design specifications. Based on the post-simulation results, if timing or functionality is found to be non-compliant, adjust the layout parameters and redraw to obtain updated layout data. Use electromagnetic interference analysis tools to perform EMIR analysis on the updated layout data to determine if there are any areas exceeding the EMI limit. If the EMI analysis results show that the limits are exceeded, optimize the layout routing and symmetry, and add dummy structures to obtain optimized layout data. Based on the optimized layout data, use scripting tools to generate SLVT and RVT type standard cell layouts to obtain layout data for extended process types. The scripting tool imports all standard cell circuit symbols (graphical abstract representations of standard cells) and layout data of extended process types into a unified cell one by one, and automatically splices them to obtain integrated layout and symbol data. A verification tool then checks the consistency of the integrated layout and symbol data to determine if it meets the overall design requirements, resulting in the final verified layout data.

[0030] Using a pre-defined script tool, standard cell layouts for other process types are generated from the drawn process type layout. The generation process includes automatic adjustment of layout parameters to adapt to different process characteristics.

[0031] Specifically, the process involves acquiring standard cell circuit design data provided by circuit engineers, extracting circuit parameters and topology of LVT-type standard cells to obtain the basic data for initial layout drawing. Based on the extracted LVT-type standard cell circuit parameters, layout data for LVT-type standard cells is automatically generated using layout drawing tools, resulting in the initial layout of the LVT layout. The generated LVT layout is then functionally verified and its parameters checked using post-simulation tools, and layout parameters are adjusted to obtain LVT layout data that meets post-simulation requirements. Electromigration and voltage drop analysis are performed on the LVT layout using EMIR analysis tools to optimize layout routing and power networks, resulting in LVT layout data that passes EMIR verification. A preset script tool is then acquired, loading the LVT layout data and process parameter configuration files for SLVT and RVT types to determine the basic data for generating layouts of other process types. The script tool is used to map process parameters to the LVT layout data, automatically adjusting layout dimensions, interlayer spacing, and device parameters to obtain preliminary data for SLVT and RVT type layouts. If the generated SLVT and RVT layout data do not meet the process rules, a script tool is used to call the design rule check function to correct the parameters that violate the rules, thus obtaining layout data that conforms to the process rules. Based on the SLVT and RVT layout data, a script tool automatically stitches all standard cells into a unified cell, adjusting the layout coordinates and connections to obtain integrated layout data. A layout verification tool is then used to perform functional and consistency checks on the integrated SLVT and RVT layout data, optimizing the stitching boundaries to obtain the final SLVT and RVT standard cell layout data.

[0032] The script tool integrates the circuit symbols of all standard cells into a unified cell library. The integration process simultaneously completes the automatic stitching of the layout, reducing manual adjustment steps.

[0033] The process begins by acquiring LVT-type standard cell circuit design data provided by circuit engineers. A script is used to parse the circuit topology and parameters, resulting in standardized circuit symbol descriptions. Based on these descriptions, a layout generation script is used to draw the initial layout of the LVT-type standard cells, yielding preliminary layout data. This preliminary layout data is then validated using post-simulation tools to determine if it meets post-simulation and EMIR requirements, resulting in a set of validated LVT layouts. Next, the validated LVT layout set is used, and a script is employed to extract the geometric features and layout rules, obtaining template parameters for the LVT layout. Based on these template parameters, a script is used to generate layout data for SLVT and RVT-type standard cells, resulting in an extended type layout set. A layout stitching algorithm is then used to integrate the LVT, SLVT, and RVT-type layout data into a unified cell library, resulting in a preliminary integrated cell library. Finally, a parasitic parameter extraction tool is used to analyze the preliminary integrated cell library data, identifying any instances of excessive parasitic parameters and providing optimization requirements. Based on the optimization requirements data, an automatic adjustment script is used to perform symmetry optimization and dummy addition on the layout of the cell library, resulting in the final integrated cell library. A layout verification tool is then used to comprehensively check the final integrated cell library to determine if it meets the phase, amplitude, and frequency requirements of analog circuits, yielding verified standard cell library data.

[0034] Extract a list of names of all standard cells from a unified standard cell library. This list is used for batch processing in subsequent verification steps to ensure coverage of all cells.

[0035] The script scans the directory structure of the unified cell library to obtain the symbol file paths of all standard cells. Based on these paths, it parses the file content one by one to extract the name field for each standard cell. The extracted name fields are stored using a data structure to generate an initial list of standard cell names. The script then scans the layout directory of the unified cell library to obtain the layout file paths of all standard cells. Based on these paths, it parses the layout file metadata to extract the corresponding standard cell names. If a name extracted from the layout file matches a name in the initial name list, the name's validity is confirmed, and the name list is updated. By comparing the names extracted from the symbol and layout files, it determines if there are any missing or redundant names and generates a complete name list. A batch processing script formats the complete name list into the input file required for the verification step. The verification script loads the formatted input file to obtain the standard cell name list for subsequent verification.

[0036] The layout and circuit consistency of each standard cell in the standard cell library are verified using a preset verification tool. The consistency verification adopts a batch mode to process the correspondence of all cells.

[0037] The script extracts circuit symbol data and layout data for all standard cells from the standard cell library, resulting in a unified formatted circuit and layout dataset. Based on the extracted circuit symbol data, a circuit netlist is generated for each standard cell, defining the description file for the circuit logic relationships. Based on the extracted layout data, a layout netlist is generated for each standard cell, defining the description file for the layout geometry. A pre-set verification tool performs an initial format check on the circuit and layout netlists of each standard cell, resulting in consistent netlist pairs. In batch processing mode, all standard cell netlist pairs are input to the layout and circuit consistency verification module to obtain preliminary consistency verification results. If the preliminary results show inconsistencies, an automated netlist comparison algorithm is executed on the inconsistent standard cells to determine the specific differences. Based on the difference data, a pre-set correction script is invoked to batch adjust the layout or circuit netlists, resulting in corrected netlist pairs. The verification tool re-executes consistency verification on the corrected netlist pairs to obtain the final verification pass status. Based on the final verification pass status, a verification report is generated for each standard cell, determining the overall consistency result of the standard cell library.

[0038] For the layouts in the standard cell library, a unified design rule verification is performed using a design rule checking tool. The verification results are used to confirm whether the layouts conform to the process specifications.

[0039] The process involves: acquiring all LVT type layout data from the standard cell library and extracting layout geometry and parameters; using the extracted geometry, calling the design rule check tool to perform preliminary design rule verification and obtaining a preliminary verification report; if errors violating process specifications are found in the preliminary verification report, automatically adjusting the layout parameters using a layout editing algorithm to generate corrected layout data; using the corrected layout data, re-calling the design rule check tool for secondary verification and obtaining a secondary verification report; and based on the secondary verification report, determining whether all LVT type layouts fully comply with process specifications and generating LVT type layouts. The process involves: verifying the LVT type layout data; obtaining the verified LVT type layout data; generating standard cell layout data of SLVT and RVT types using a script; using the generated SLVT and RVT type layout data, calling the design rule checking tool to perform design rule verification, and obtaining verification reports for SLVT and RVT type layouts; based on the SLVT and RVT type verification reports, determining whether there are layouts that violate process specifications, and generating a list of non-compliant layouts; and automatically adjusting the non-compliant SLVT and RVT type layouts using a layout optimization algorithm to obtain the final layout data that conforms to the process specifications.

[0040] The final standard cell library is generated based on the results of conformance verification and design rule verification. The final standard cell library contains standard cell layouts and symbols for all process types for subsequent circuit design.

[0041] Specifically, based on the standard cell circuit list provided by the circuit engineer, all LVT-type standard cell circuit design data are automatically extracted to generate the corresponding initial layout template. Using a layout generation tool, the LVT-type standard cell layout is automatically drawn based on the initial template to obtain preliminary layout data. Post-simulation tools are used to verify the preliminary layout data, and combined with EMIR analysis, it is determined whether the layout meets performance requirements. If the layout meets performance requirements, a script is used to convert the LVT-type layout data into SLVT and RVT-type layout data to obtain a multi-process type layout dataset. An automated splicing script is then used to connect all LVT and SLVT-type standard cell circuits. The standard cell layouts of LVT and RVT types are imported one by one into a unified layout cell to generate a spliced ​​layout library. A corresponding symbol library is automatically generated based on the standard cell circuit design data, and all symbols are imported into a unified symbol cell to obtain a preliminary symbol library. A consistency verification tool is used to match and verify the spliced ​​layout library with the preliminary symbol library to determine if they are completely consistent. A design rule checking tool is used to verify the process rules of the spliced ​​layout library to determine if the layout meets manufacturing requirements. Based on the results of the consistency verification and design rule verification, the layout library and symbol library are integrated to generate a final standard cell library containing standard cells of all process types.

[0042] If any standard units in the verification results do not meet the requirements, the parameters of the standard units are adjusted using a script tool, and the verification steps are repeated until the design requirements are met.

[0043] Layout and schematic analysis were performed on each standard cell using the calibre lvs tool in hcell mode. Figure 1Consistency verification is performed to obtain a list of non-compliant standard cells. Based on the verification results, the non-compliant standard cells are analyzed, and their layout and schematic parameter deviation data are extracted. A script tool is used to analyze the deviation data to determine the parameter types and adjustment ranges that need adjustment. The script tool automatically modifies the layout parameters of the standard cells according to the determined parameter types and adjustment ranges. The modified standard cell layout is then re-imported into the target cell using the script tool, and a splicing operation is performed. The calibre lvs tool is used to re-perform hcell mode verification on the modified standard cells to obtain new verification results. If the new verification results still contain non-compliant standard cells, the process returns to the previous steps to extract new deviation data. The calibre drc tool is used to perform a Design Rule Check (DRC) on the standard cells verified by LVS to obtain DRC verification results. If the DRC verification results contain cells that violate the rules, the process returns to the previous steps to determine new parameter adjustment ranges.

[0044] It should be noted that the Calibre LVS tool mentioned above is a physical verification tool used to ensure the electrical connection consistency between the integrated circuit layout and the schematic, preventing chip malfunction due to physical implementation errors; while the hcell (Hierarchical Cell) mode is a hierarchical verification strategy in Calibre LVS, which extracts and verifies the consistency between the layout and schematic for standard cells or modules that are reused in the design, avoiding redundant calculations and significantly improving verification efficiency.

[0045] After the final standard cell library is generated, it is output to the design environment to support the high-speed, high-performance design flow of analog circuits.

[0046] This process involves obtaining high-speed, high-performance requirements for analog circuits in chip design, extracting key analog signal indicators such as phase angle, amplitude, and frequency, and determining customized design constraints for the standard cell library. Based on these constraints, an automated script tool scans existing standard cell libraries to select an initial set of cells suitable for analog circuits, resulting in a preliminary candidate list. Parasitic parameter analysis is performed on the cells in the candidate list to calculate the phase and amplitude frequency characteristics of each cell in high-speed signal transmission, identifying cell sets that conform to the small-signal model of analog signals. If a cell set meets the design constraints, a layout splicing script imports the selected cell symbols and layouts one by one into a unified cell library, resulting in an integrated standard cell library prototype. Based on this prototype, a symmetry optimization algorithm is executed to automatically add virtual cells to reduce the impact of parasitic parameters, determining the optimized layout structure. A layout verification tool checks the optimized layout structure for design rules and performs electrical characteristic simulations to obtain verified standard cell library data. Finally, a data conversion script formats the verified standard cell library data into a design environment-compatible library file, resulting in an output standard cell library. The formatted standard cell library file is transferred to the chip design platform via the design environment interface protocol to determine its usability within the design environment. Based on the design environment feedback, a functional verification script for the library file is executed to simulate a high-speed, high-performance design flow, resulting in a target standard cell library that supports analog circuit design.

[0047] Therefore, this application automatically generates all other types of standard cells through scripts; it also automatically loads all circuits into one cell through scripts, and automatically loads all layouts into the same cell and splices them together through scripts; it can also automatically obtain a list of all custom standard cells and output them in the format required by the hcell mode of the calibre lvs tool.

[0048] In summary, this invention discloses a design method for a high-speed, high-performance analog circuit standard cell library. It obtains a list of high-speed, high-performance standard cells suitable for analog circuits, draws and generates standard cell layouts for various process types, and automatically integrates circuit symbols and layouts into a unified standard cell library using scripting tools. A batch verification mode is employed to verify the layout and circuit consistency of the standard cells and check design rules, ensuring that the layout conforms to process specifications. For cells that do not meet the requirements, optimization is achieved through parameter adjustment and repeated verification. The final generated standard cell library contains layouts and symbols for multiple process types, which can be directly used to support the high-speed, high-performance design flow of analog circuits, effectively improving the design efficiency and quality of the standard cell library and providing a reliable foundation for analog circuit design.

[0049] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0050] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A method for generating and verifying a standard analog circuit cell library, characterized in that: Includes the following steps: Obtain the various types of standard cell requirements needed in circuit design; Based on the standard unit requirements, draw initial layout data for at least one type; Generate other types of standard cell layout data using automated tools; The initial layout data and the other types of standard cell layout data are integrated into a unified standard cell library; Each standard unit in the standard unit library was subjected to consistency verification using a verification tool, and the verification results were obtained. The step of drawing initial layout data for at least one type according to the standard unit requirements includes: Determine the circuit structure of the target standard unit based on circuit design requirements; For the target standard unit, draw layout data corresponding to the first type; Perform post-simulation verification on the layout data of the first type and obtain simulation results; Adjust the layout data of the first type based on the simulation results until the design specifications are met; The adjusted layout data of the first type is used as the initial layout data, which serves as the basis for generating other types of standard unit layout data in the future. The generation of other types of standard cell layout data through automated tools includes: The initial layout data is used as the base template; Using a preset script tool, process parameters are adjusted for the basic template to generate standard cell layout data corresponding to the second type; Using the script tool, process parameters are adjusted for the basic template to generate standard cell layout data corresponding to the third type. A preliminary check is performed on the standard unit layout data of the second type and the third type to confirm their structural consistency with the initial layout data; The standard unit layout data of the second type and the third type are stored as data to be integrated.

2. The method for generating and verifying a standard analog circuit cell library according to claim 1, characterized in that: The process of integrating the initial layout data and other types of standard cell layout data into a unified standard cell library includes: The symbol data of the initial layout data and other types of standard unit layout data are obtained through automated scripts; The symbol data is loaded one by one into a preset unit library framework; The automated script concatenates the symbol data to generate a unified symbol view. Acquire the layout data of the initial layout data and other types of standard unit layout data; The layout data is imported one by one into the unit library framework, and the layout is stitched together by the automated script to generate a unified layout view; The unified symbol view and the unified layout view are integrated into a unified standard cell library.

3. The method for generating and verifying a standard analog circuit cell library according to claim 1, characterized in that: The process of using a verification tool to perform consistency verification on each standard unit in the standard unit library, and obtaining the verification results, includes: A list of names of all standard units in the standard unit library is obtained by using a preset script; For each standard unit in the name list, extract its symbol data and layout data; The symbol data and the layout data are compared using a layout and schematic consistency verification tool to determine if there are any inconsistencies. If there are inconsistencies, the corresponding standard cell name and inconsistency details are recorded. The layout data is validated using a rule checking tool to obtain the rule validation results. Based on the verification results of the rules and the details of the inconsistency, the final verification result is generated.

4. The method for generating and verifying a standard analog circuit cell library according to claim 1, characterized in that: The requirements for various types of standard cells needed in the acquisition circuit design include: Based on the circuit design objectives, determine the required standard unit function categories in the analog circuit; For the aforementioned standard unit functional categories, the impact of different process types on the performance of the standard unit is analyzed; Based on the degree of influence, various process types suitable for the circuit design objectives are determined; For each of the aforementioned process types, a corresponding list of standard unit requirements is generated; The standard unit requirement list is used to categorize and organize the types and quantities of standard units required for each process type. The standard unit requirement list will be used as the basis for subsequent drawing and generation of layout data.

5. The method for generating and verifying a standard analog circuit cell library according to claim 1, characterized in that: The process of integrating the initial layout data and the other types of standard cell layout data into a unified standard cell library also includes: The file structure of the initial layout data and other types of standard unit layout data is read using a preset integration tool; Based on the file structure, determine whether the data format of each standard unit is consistent. If they are inconsistent, then use the integration tool to standardize the data format. The standardized initial layout data and other types of standard unit layout data are stored in a preset database; The integration tool is used to classify and manage the data in the database, generating a unified standard unit library. The unified standard unit library is backed up and stored.

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