Display panel, driving method thereof and display device

Abstract

Embodiments of the present application provide a display panel, a driving method thereof and a display device. The display panel comprises a plurality of sub-pixels, each of which comprises a pixel circuit and a light emitting device electrically connected. The i-th row of sub-pixels comprises a plurality of sub-pixels arranged along a first direction, and a plurality of rows of sub-pixels are arranged along a second direction intersecting the first direction, where i is any positive integer. One working cycle of the pixel circuit comprises a reset stage, a data writing stage and a light emitting stage. In the reset stage and / or the data writing stage of the (i+1)-th row of sub-pixels, the i-th row of sub-pixels is in the light emitting stage, and the (i+2)-th row of sub-pixels is in the light emitting stage. The present application can make the multiple rows of sub-pixels in the same area not dark at the same time, which is conducive to reducing the dark state obviousness of the dark state sub-pixel row, thereby weakening the bright-dark difference recognized by the human eye, and realizing the eye protection function of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and its driving method, and a display device. Background Technology

[0002] With the development of display technology, consumers have increasingly higher requirements for the performance of display panels, especially for eye protection. However, in current technologies, the brightness fluctuations within frames of a display are quite noticeable, which is detrimental to eye protection. Therefore, a solution is urgently needed. Summary of the Invention

[0003] In view of this, embodiments of this application provide a display panel and its driving method, as well as a display device, to solve the above-mentioned problems.

[0004] In a first aspect, embodiments of this application provide a display panel including a plurality of sub-pixels. Each sub-pixel includes a pixel circuit and a light-emitting device electrically connected together. The i-th row of sub-pixels includes a plurality of sub-pixels arranged along a first direction. The multiple rows of sub-pixels are arranged along a second direction, which intersects with the first direction. Here, i is any positive integer. One working cycle of the pixel circuit includes a reset phase, a data writing phase, and a light emission phase. During the reset phase and / or data writing phase of the (i+1)th row sub-pixel, the (i)th row sub-pixel is in the light emission phase, and the (i+2)th row sub-pixel is in the light emission phase.

[0005] Secondly, based on the same inventive concept, embodiments of this application provide a driving method for a display panel. The display panel includes multiple sub-pixels, the i-th row of sub-pixels includes multiple sub-pixels arranged along a first direction, and the multiple rows of sub-pixels are arranged along a second direction, which intersects with the first direction, where i is any positive integer; the method includes: In a frame of the display panel, during the period when the (i+1)th row of sub-pixels is not emitting light, the (i)th row of sub-pixels is driven to emit light, and the (i+2)th row of sub-pixels is also driven to emit light.

[0006] Thirdly, based on the same inventive concept, embodiments of this application provide a display device, including the display panel as provided in the first aspect.

[0007] In this embodiment, during the reset phase and / or data writing phase of the (i+1)th row of sub-pixels, the (i+2)th row of sub-pixels is set to be in the light-emitting phase t3, and the (i+2)th row of sub-pixels is also in the light-emitting phase t3. Then, during at least a portion of the time when the (i+1)th row of sub-pixels is in the dark state, the two rows of sub-pixels adjacent to it and located on opposite sides of it can be in the light-emitting state. This helps to prevent multiple rows of sub-pixels in the same area from darkening simultaneously, reducing the visibility of the dark state of the (i+1)th row of sub-pixels, weakening the difference between light and dark perceived by the human eye, thereby reducing the harm of the screen to the human eye and realizing the eye protection function of the display panel. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 A schematic diagram of a display panel provided in an embodiment of this application; Figure 2 for Figure 1 A schematic diagram of a mid-pixel circuit; Figure 3 for Figure 2 The image shows a timing diagram of a pixel circuit. Figure 4 A driving timing diagram for a display panel provided in an embodiment of this application; Figure 5 A timing diagram for driving a display panel, provided for related technologies; Figure 6 This is a schematic diagram illustrating the brightness and darkness of a display screen in related technologies; Figure 7 This application provides a schematic diagram of the brightness and darkness of a display screen according to an embodiment of the present application. Figure 8 A driving timing diagram for yet another display panel provided in an embodiment of this application; Figure 9 A schematic diagram of the driving sequence of a display panel provided in an embodiment of this application; Figure 10 A schematic diagram illustrating the driving sequence of another display panel provided in an embodiment of this application; Figure 11 for Figure 10 A timing diagram of the middle driver group; Figure 12 A driving timing diagram for yet another display panel provided in an embodiment of this application; Figure 13A schematic diagram of yet another display panel provided in an embodiment of this application; Figure 14 for Figure 13 A cascaded sequence diagram of intermediate shift register units; Figure 15 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0010] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0011] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0012] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0013] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, the character " / " in this article generally indicates that the related objects before and after it have an "or" relationship.

[0014] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0015] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of this application. Figure 2 for Figure 1 A schematic diagram of a mid-pixel circuit. Figure 3 for Figure 2 The image shows a timing diagram of a pixel circuit.

[0016] This application embodiment provides a display panel 01, such as Figure 1As shown, the display panel 01 includes multiple sub-pixels 10. Each sub-pixel 10 includes a pixel circuit 11 and a light-emitting device 12 electrically connected to each other. The pixel circuit 11 is used to drive the light-emitting device 12 to emit light. The light-emitting device 12 can be an organic light-emitting diode (OLED), a sub-millimeter light-emitting diode (Mini-LED), or a micro light-emitting diode (Micro-LED; this application does not specifically limit this).

[0017] The i-th row of sub-pixels 10_i includes multiple sub-pixels 10 arranged along the first direction X, and multiple rows of sub-pixels 10 are arranged along the second direction Y, which intersects with the first direction X, where i is any positive integer.

[0018] In other words, multiple sub-pixels 10 arranged along the first direction X can form a row of sub-pixels, which can also be called a sub-pixel row. Multiple sub-pixel rows are arranged along the second direction Y.

[0019] For example, the first direction X is the row direction of the display panel 01, and the second direction Y is the column direction of the display panel 01.

[0020] Combination Figure 2 and Figure 3 As shown, one operating cycle T of the pixel circuit 11 includes a reset phase t1, a data writing phase t2, and a light-emitting phase t3. The data writing phase t2 occurs after the reset phase t1, and the light-emitting phase t3 occurs after the data writing phase t2. During the reset phase t1 and the data writing phase t2, the light-emitting device 12 does not emit light, that is, the sub-pixel 10 does not emit light. During the light-emitting phase t3, the light-emitting device 12 emits light, that is, the sub-pixel 10 emits light.

[0021] Within the same row of sub-pixels 10, the operating states of each pixel circuit 11 can be the same. That is, the pixel circuits 11 in a row of sub-pixels 10 can all be in the reset phase t1, or all in the data writing phase t2, or all in the light emission phase t3.

[0022] Among them, combined Figure 3 and Figure 4 As shown, Figure 4 The timing diagram of a display panel provided in this application embodiment shows that during the reset phase t1 and / or data writing phase t2 of the (i+1)th row sub-pixel 10_i+1, the (i)th row sub-pixel 10_i is in the light-emitting phase t3, and the (i+2)th row sub-pixel 10_i+2 is in the light-emitting phase t3.

[0023] In other words, in a frame of the display panel 01, during the period when at least part of the sub-pixel 10_i+1 in the (i+1)th row is not emitting light, both the sub-pixel 10_i in the (i+1)th row (the sub-pixel in the row above the sub-pixel 10_i+1) and the sub-pixel 10_i+2 in the (i+2)th row (the sub-pixel in the row below the sub-pixel 10_i+1) are emitting light.

[0024] The inventors of this application discovered through research that, Figure 5 As shown, Figure 5 This provides a driving timing diagram for a display panel in the related art. In the related art, during the display panel 01 displaying a frame, each row of sub-pixels 10 is typically driven sequentially according to the arrangement order along the second direction Y. For example, combined with... Figure 1 , Figure 2 , Figure 3 and Figure 5 As shown, the sub-pixels in the first row, the second row, ... the sub-pixels in the i-th row 10_i, the (i+1)-th row 10_i+1, and the (i+2)-th row 10_i+2 successively enter the reset phase t1, the data writing phase t2, and the light emission phase t3. When a row of sub-pixels starts to execute the data writing phase t2, the sub-pixels in the next row are still executing the reset phase t1.

[0025] Based on this driving method, combined with Figure 3 and Figure 5 It can be seen that at any moment when sub-pixel 10_i+1 in row i+1 is in the reset phase t1 and the data writing phase t2, at least one of sub-pixel 10_i in row i and sub-pixel 10_i+2 in row i+2 is not in the light emission phase t3. For example Figure 5 As shown, when sub-pixel 10_i+1 in row i+1 is at the start of data writing phase t2, sub-pixel 10_i in row i is in data writing phase t2, and sub-pixel 10_i+2 in row i+2 is in reset phase t1.

[0026] This causes adjacent rows of subpixels in the same area to darken simultaneously within a single frame, such as... Figure 6 As shown, Figure 6 This is a schematic diagram illustrating the brightness and darkness of a display screen in related technologies. When the image is photographed using a fast camera (shutter speed < 1 / 8000s), obvious black bars can be seen in the display screen. These black bars represent the dark state of sub-pixel rows. This results in significant fluctuations in brightness within a single frame, which is detrimental to eye protection. In this embodiment, during the reset phase t1 and / or data writing phase t2 of the (i+1)th row sub-pixel 10_i+1, the (i)th row sub-pixel 10_i is set to be in the light-emitting phase t3, and the (i+2)th row sub-pixel 10_i+2 is also in the light-emitting phase t3. Therefore, during at least a portion of the time when the (i+1)th row sub-pixel 10_i+1 is in a dark state, the two rows of sub-pixels adjacent to it and located on opposite sides of it can be in a light-emitting state. This helps to prevent multiple rows of sub-pixels in the same area from darkening simultaneously, reducing the visibility of the dark state of the (i+1)th row sub-pixel 10_i+1, weakening the difference in brightness perceived by the human eye, thereby reducing the harm of the image to the human eye and realizing the eye protection function of the display panel.

[0027] For example, such as Figure 7 As shown, Figure 7 This application provides a schematic diagram of the brightness and darkness of a display screen, showing how, when a fast camera (shutter speed < 1 / 8000s) is used to capture the image, the brightness and darkness can be seen. Figure 7 The color of the black bar is significantly lighter than Figure 6 The color of the black bar in this application embodiment can effectively reduce flickering within the frame and improve the protection of the human eye.

[0028] It should be noted that in some other embodiments, a working cycle of the pixel circuit 11 may also include other stages, such as a bias adjustment stage. As long as the pixel circuit 11 is not in the light-emitting stage t3, the sub-pixel 10 is in the dark state. In this embodiment, at any time when the (i+1)th row of sub-pixels 10_i+1 is in the dark state, the two rows of sub-pixels 10 adjacent to it and located on opposite sides of it can be made to be in the light-emitting stage t3, so as to reduce the flicker in a frame to a greater extent and further improve the eye protection capability of the display panel.

[0029] Figure 8 This is a driving timing diagram for another display panel provided in an embodiment of this application.

[0030] In one embodiment of this application, combined with Figure 1 , Figure 2 , Figure 3 and Figure 8 As shown, during the reset phase t1 and / or data writing phase t2 of sub-pixel 10_i+1 in row i+1, at least two rows of sub-pixels located on one side of sub-pixel 10_i+1 and adjacent to it are in the light emission phase t3, and at least two rows of sub-pixels located on the other side of sub-pixel 10_i+1 and adjacent to it are in the light emission phase t3.

[0031] That is, during the reset phase t1 and / or data writing phase t2 of sub-pixel 10_i+1 in row i+1, at least sub-pixel 10_i in row i and sub-pixel 10_i-1 in row i-1 are in the light-emitting phase t3, and at least sub-pixel 10_i+2 in row i+2 and sub-pixel 10_i+3 in row i+3 are in the light-emitting phase t3. In this embodiment, i ≥ 2.

[0032] In this embodiment, during the reset phase t1 and / or data writing phase t2 of the (i+1)th row sub-pixel 10_i+1, at least two rows of sub-pixels located on one side of the (i+1)th row sub-pixel 10_i+1 and adjacent to it are set to be in the light-emitting phase t3, and at least two rows of sub-pixels located on the other side of the (i+1)th row sub-pixel 10_i+1 and adjacent to it are also in the light-emitting phase t3. Then, during at least a portion of the time when the (i+1)th row sub-pixel 10_i+1 is in a dark state, at least the two "upper" rows and at least the two "lower" rows of sub-pixels of the (i+1)th row sub-pixel 10_i+1 are in a light-emitting state. This is beneficial to further reduce the visibility of the dark state of the (i+1)th row sub-pixel 10_i+1, thereby further weakening the difference between light and dark perceived by the human eye and improving the eye protection function of the display panel 01.

[0033] To facilitate understanding of the technical solution of this application, the following is combined with... Figure 2 and Figure 3 right Figure 2 The structure and operation of the pixel circuit shown are briefly explained.

[0034] like Figure 2 As shown, the pixel circuit 11 includes a driving transistor Md, a power supply voltage writing module 111, and a light emission control module 112. The input terminal of the power supply voltage writing module 111 is electrically connected to the first power supply signal line DL1, the output terminal is electrically connected to the first pole of the driving transistor Md, and the control terminal is electrically connected to the light emission control signal line EM. The power supply voltage writing module 111 is used to transmit the first power supply voltage PVDD transmitted by the first power supply signal line DL1 to the first pole of the driving transistor Md.

[0035] The input terminal of the light-emitting control module 112 is electrically connected to the second electrode of the driving transistor Md, the output terminal is electrically connected to the first electrode of the light-emitting device 12, and the control terminal is electrically connected to the light-emitting control signal line EM. The signal transmitted by the light-emitting control signal line EM controls the power supply voltage, and the switching states of the light-emitting control module 111 and the light-emitting control module 112 are the same. The second electrode of the light-emitting device 12 can receive the second power supply voltage PVEE.

[0036] The first electrode of the light-emitting device 12 can be its anode, and the second electrode of the light-emitting device 12 can be its cathode.

[0037] During the light-emitting stage t3, the light-emitting control signal line EM transmits an enable signal, and both the power supply voltage writing module 111 and the light-emitting control module 112 are in the on state.

[0038] During the reset phase t1 and the data writing phase t2, the light emission control signal line EM transmits an enable signal, and both the power supply voltage writing module 111 and the light emission control module 112 are in the off state.

[0039] For example, such as Figure 2 As shown, the power supply voltage writing module 111 includes a first transistor M1, the first terminal of the first transistor M1 is electrically connected to the first power supply voltage signal line DL1, the second terminal is electrically connected to the first terminal of the driving transistor Md, and the gate is electrically connected to the light emission control signal line EM.

[0040] The light-emitting control module 112 includes a second transistor M2, the first terminal of the second transistor M2 is electrically connected to the second terminal of the driving transistor Md, the second terminal is electrically connected to the first terminal of the light-emitting device 12, and the gate is electrically connected to the light-emitting control signal line EM.

[0041] Combination Figure 3 As shown, during the light-emitting stage t3, the light-emitting control signal line EM transmits an enable signal (such as a low-level signal), the first transistor M1 and the second transistor M2 are turned on, and the pixel circuit 11 transmits a driving current to the light-emitting device 12, driving the light-emitting device 12 to emit light. That is, the sub-pixel 10 emits light.

[0042] During the reset phase t1 and the data writing phase t2, the light emission control signal line EM transmits a non-enable signal (such as a high-level signal), the first transistor M1 and the second transistor M2 are turned off, the pixel circuit 11 stops providing driving current to the light-emitting device 12, and the light-emitting device 12 does not emit light. That is, the sub-pixel 10 does not emit light and is in a dark state.

[0043] It should be noted that the same sub-pixel row can be connected to the same emission control signal line EM. Figure 4 , Figure 8 In the timing diagram shown, during the period when the EM control signal line connected to the sub-pixel row transmits an inactive signal (such as a high-level signal), the sub-pixel in that row does not emit light and is in a dark state.

[0044] Furthermore, such as Figure 2As shown, the pixel circuit 11 also includes a first reset module 113, a data writing module 114, a threshold capturing module 115, and a second reset module 116. The input terminal of the first reset module 113 is electrically connected to the first reset voltage signal line SL1, the output terminal is electrically connected to the gate of the driving transistor Md, and the control terminal is electrically connected to the first scan line S1. The first reset module 113 is used to transmit the first reset voltage Vref1 on the first reset voltage signal line SL1 to the gate of the driving transistor Md to reset the gate of the driving transistor Md.

[0045] The input terminal of the data writing module 114 is electrically connected to the data signal line DL2, the output terminal is electrically connected to the first pole of the driving transistor Md, and the control terminal is electrically connected to the second scan line S2. The data writing module 114 is used to transmit the data voltage Vdata on the data signal line DL2 to the first pole of the driving transistor Md.

[0046] The input terminal of the threshold capture module 115 is electrically connected to the second electrode of the driving transistor Md, the output terminal is electrically connected to the gate of the driving transistor Md, and the control terminal is electrically connected to the second scan line S2. The threshold capture module 115 is used to compensate the threshold voltage of the driving transistor Md to the gate of the driving transistor Md.

[0047] The input terminal of the second reset module 116 is electrically connected to the second reset voltage signal line SL2, the output terminal is electrically connected to the first pole of the light-emitting device 12, and the control terminal is electrically connected to the second scan line S2. The second reset module 116 is used to transmit the second reset voltage Vref2 on the second reset voltage signal line SL2 to the first pole of the light-emitting device 12 to reset the first pole of the light-emitting device 12.

[0048] In one working cycle of the pixel circuit 11, the data writing stage t2 is performed after the reset stage t1, and the light emission stage t3 is performed after the data writing stage t2.

[0049] The first reset module 113 is activated during the reset phase t1, and the second reset module 116, the data writing module 114, and the threshold capture module 115 are activated during the data writing phase t2.

[0050] For example, such as Figure 2 As shown, the first reset module 113 includes a third transistor M3. The first terminal of the third transistor M3 is electrically connected to the first reset voltage signal line SL1, the second terminal is electrically connected to the gate of the driving transistor Md, and the gate is electrically connected to the first scan line S1. The data writing module 114 includes a fourth transistor M4. The first terminal of the fourth transistor M4 is electrically connected to the data signal line DL2, the second terminal is electrically connected to the first terminal of the driving transistor Md, and the gate is electrically connected to the second scan line S2.

[0051] The threshold capture module 115 includes a fifth transistor M5. The first terminal of the fifth transistor M5 is electrically connected to the second terminal of the driving transistor Md, the second terminal is electrically connected to the gate of the driving transistor Md, and the gate is electrically connected to the second scan line S2. The second reset module 116 includes a sixth transistor M6. The first terminal of the sixth transistor M6 is electrically connected to the second reset voltage signal line SL2, the second terminal is electrically connected to the first terminal of the light-emitting device 12, and the gate is electrically connected to the second scan line S2.

[0052] In this configuration, sub-pixel rows are connected to the same first scan line S1 and the same second scan line S2. Sub-pixels in the same row can simultaneously enter the reset phase t1 and the data writing phase t2.

[0053] Combination Figure 3 As shown, during the reset phase t1, the first scan line S1 transmits an enable signal (such as a low-level signal), the third transistor M3 is turned on, and the first reset voltage VREF1 is transmitted to the gate of the driving transistor Md through the turned-on third transistor M3, thus completing the reset of the gate of the driving transistor Md.

[0054] During the data writing phase t2, the first scan line S1 transmits a non-enable signal (such as a high-level signal), the second scan line S2 transmits an enable signal (such as a low-level signal), the third transistor M3 is turned off, and the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are turned on. The data voltage Vdata is transmitted to the first terminal of the driving transistor Md through the turned-on fourth transistor M4. At this time, since the gate potential of the driving transistor Md is Vref1, the driving transistor Md is turned on. The data voltage Vdata is transmitted to the gate of the driving transistor Md through the turned-on driving transistor Md and the fifth transistor M5 until the gate potential of the driving transistor Md is Vdata-|Vth|, at which point the driving transistor Md is turned off, where Vth is the threshold voltage of the driving transistor Md.

[0055] At the same time, the second reset voltage VREF2 is transmitted to the first electrode of the light-emitting device 12 through the turned-on sixth transistor M6, thus completing the reset of the first electrode of the light-emitting device 12.

[0056] Figure 9 This is a schematic diagram of the driving sequence of a display panel provided in an embodiment of this application.

[0057] In one embodiment of this application, such as Figure 9 As shown, multiple sub-pixel rows in the display panel 01 form at least one driving group 100. The same driving group 100 includes a first group of sub-pixel rows 100A and a second group of sub-pixel rows 100B. In one frame of the display panel 01, the first group of sub-pixel rows 100A and the second group of sub-pixel rows 100B are driven sequentially.

[0058] Among them, the multiple rows of sub-pixels 10 in the first group of sub-pixel rows 100A and the multiple rows of sub-pixels 10 in the second group of sub-pixel rows 100B are arranged alternately in the second direction Y.

[0059] In other words, in one frame of the display panel 01, the sub-pixels 10 in the first sub-pixel row 100A of a driving group 100 can be sequentially put into operation, and then the sub-pixels 10 in the second sub-pixel row 100B of the same driving group 100 can be sequentially put into operation. In the second direction Y, the sub-pixel rows belonging to the first sub-pixel row 100A and the sub-pixel rows belonging to the second sub-pixel row 100B of the driving group 100 are arranged alternately.

[0060] In this embodiment, the first group of sub-pixel rows 100A and the second group of sub-pixel rows 100B in the same driving group 100 are driven sequentially, and the sub-pixel rows in the first group of sub-pixel rows 100A and the sub-pixel rows in the second group of sub-pixel rows 100B are arranged alternately. This allows for staggered driving of multiple sub-pixel rows in the same driving group 100. This is beneficial because after driving the i-th row of sub-pixels 10_i and the (i+2)-th row of sub-pixels 10_i+2 into the light-emitting stage t3, the (i+1)-th row of sub-pixels 10_i+1 is then driven into the reset stage t1 or the data writing stage t2. This is beneficial because when the (i+1)-th row of sub-pixels 10_i+1 is in a dark state, the two rows of sub-pixels adjacent to it and located on opposite sides of it can be in a light-emitting state, thereby reducing the visibility of the dark state of the (i+1)-th row of sub-pixels 10_i+1.

[0061] For example, such as Figure 9 As shown, in the same driving group 100, the number of subpixel rows included in the first group of subpixel rows 100A is the same as the number of subpixel rows included in the second group of subpixel rows 100B.

[0062] Among them, the multiple rows of subpixels in the first group of subpixel rows 100A are odd-numbered rows of subpixels, and the multiple rows of subpixels in the second group of subpixel rows 100B are even-numbered rows of subpixels.

[0063] For example Figure 9 As shown, in the display panel 01, 14 rows of subpixels arranged sequentially along the second direction Y form a driving group 100, of which 7 odd-numbered rows of subpixels 10 belong to the first group of subpixel rows 100A, and 7 even-numbered rows of subpixels 10 belong to the second group of subpixel rows 100B. During the display of one frame, the odd-numbered rows of subpixels 10 in this driving group 100 enter the working process in sequence, followed by the even-numbered rows of subpixels 10.

[0064] By having the odd-numbered rows of subpixels in the driving group 100 form the first group of subpixel rows 100A, and the even-numbered rows of subpixels in the driving group 100 form the second group of subpixel rows 100B, it is beneficial to reduce the grouping complexity of each subpixel row in the driving group 100, improve the distribution regularity of the first group of subpixel rows 100A and the second group of subpixel rows 100B, and thus help reduce the complexity of interleaving the subpixel rows in the driving group 100.

[0065] Please continue to refer to this. Figure 9 In one embodiment of this application, the display panel 01 includes a plurality of drive groups 100, which are driven sequentially.

[0066] For example, such as Figure 9 As shown, the multiple drive groups 100 include a first drive group 101, a second drive group 102, etc. During the process of displaying a frame on the display panel 01, the first drive group 101, the second drive group 102, etc. are driven in sequence.

[0067] Since the number of sub-pixel rows in the display panel 01 is large, the present application embodiment makes the display panel 01 include multiple driving groups 100, which is beneficial to ensure that the number of sub-pixel rows in each driving group 100 is not too large, which is beneficial to reduce the driving difficulty of the display panel 01 and facilitates the realization that multiple adjacent sub-pixel rows will not darken at the same time.

[0068] Figure 10 This is a schematic diagram illustrating the driving sequence of another display panel provided in an embodiment of this application.

[0069] In one embodiment of this application, combined with Figure 1 and Figure 10 As shown, in the same group of sub-pixel rows, between two adjacent rows of sub-pixels in the second direction Y, there are at least two rows of sub-pixels that do not belong to that group of sub-pixel rows.

[0070] For example Figure 10 As shown, 16 rows of subpixels arranged along the second direction Y form a driving group 100. The same driving group 100 includes a first group of subpixel rows 100A, a second group of subpixel rows 100B, a third group of subpixel rows 100C, and a fourth group of subpixel rows 100D. In the same driving group 100, the first group of subpixel rows 100A includes subpixels in rows 1, 5, 9, and 13; the second group of subpixel rows 100B includes subpixels in rows 3, 7, 11, and 15; the third group of subpixel rows 100C includes subpixels in rows 2, 6, 10, and 14; and the fourth group of subpixel rows 100D includes subpixels in rows 4, 8, 12, and 16.

[0071] Combination Figure 1 and Figure 10 It can be seen that, within any two adjacent rows of subpixels in the first group of subpixel rows 100A, there are three rows of subpixels that do not belong to the first group of subpixel rows 100A. For example, between the first and fifth rows of subpixels in the first group of subpixel rows 100A, there are subpixels in the second, third, and fourth rows that do not belong to the first group of subpixel rows 100A. Similarly, within any two adjacent rows of subpixels in the second group of subpixel rows 100B, there are three rows of subpixels that do not belong to the second group of subpixel rows 100B. Within any two adjacent rows of subpixels in the third group of subpixel rows 100C, there are three rows of subpixels that do not belong to the third group of subpixel rows 103. Within any two adjacent rows of subpixels in the fourth group of subpixel rows 100D, there are three rows of subpixels that do not belong to the fourth group of subpixel rows 100D.

[0072] In this embodiment, if at least two rows of subpixels between two adjacent rows of subpixels in the same group of subpixels do not belong to that group of subpixels, then after driving two adjacent rows of subpixels in the same group of subpixels to enter the light-emitting stage t3 in sequence, the subpixel row between the two adjacent rows of subpixels can be driven to enter the reset stage t1. This is beneficial to ensure that when one subpixel row in the group of subpixels is in a dark state, at least two rows of subpixels on one side and adjacent to it are in a light-emitting state, and at least two rows of subpixels on the other side and adjacent to it are in a light-emitting state, thereby further weakening the visual effect of the dark subpixel row.

[0073] For example, in combination Figure 10 and Figure 11 As shown, Figure 11 for Figure 10 A timing diagram for a driving group shows that in the same driving group 100, the first group of sub-pixel rows 100A, the second group of sub-pixel rows 100B, the third group of sub-pixel rows 100C, and the fourth group of sub-pixel rows 100D are driven sequentially. It can be seen that when one row of sub-pixels in the first group of sub-pixel rows 100A is in a dark state (EM high level), the three rows of sub-pixels above and below that row (excluding the first row of sub-pixels) are all in an illuminated state.

[0074] For example, when the 5th row of subpixels in the first group of subpixel rows 100A is in a dark state, the 2nd, 3rd and 4th row subpixels on one side of it are in a light-emitting state (EM low level), and the 6th, 7th and 8th row subpixels on the other side are also in a light-emitting state.

[0075] In one embodiment of this application, combined with Figure 4 and Figure 9As shown, in the same driving group 100, the first group of subpixel rows 100A and the second group of subpixel rows 100B both include n rows of subpixels.

[0076] In a frame of the display panel 01, the time periods during which the light emission control signal line EM in the m rows of sub-pixels in the same group of sub-pixels transmit non-enabling signals (such as high-level signals) overlap.

[0077] Where n > m, and n and m are both positive integers.

[0078] For example, in combination Figure 4 and Figure 9 As shown, Figure 4 In this context, i can be 12, combined with... Figure 4 and Figure 9 It can be reasonably deduced that the first group of sub-pixel rows 100A includes 7 rows of sub-pixels, and the time periods for transmitting non-enabling signals (such as high-level signals) on the EM light emission control signal lines in the 1st, 3rd, 5th, 7th, 9th, and 11th rows of sub-pixels overlap. That is, n=7, m=6.

[0079] For example, in combination Figure 10 and Figure 11 As shown, the first group of sub-pixel rows 100A includes 4 rows of sub-pixels. The light emission control signal lines EM of the 1st, 5th, and 9th rows of sub-pixels overlap in the time periods when transmitting non-enabling signals (such as high-level signals). That is, n=4 and m=3.

[0080] In this embodiment, if n > m, then after each row of subpixels in the first group of subpixel rows 100A sequentially enters the working process, when driving the second group of subpixel rows 100B, the first row of subpixels in the second group of subpixel rows 100B can enter the reset stage t1 after its adjacent "upper" row of subpixels (e.g., belonging to the first group of subpixel rows 100A) and "lower" row of subpixels (e.g., belonging to the first group of subpixel rows 100A) sequentially enter the light-emitting stage t3. This is beneficial to ensure that when the subpixel row in the second group of subpixel rows 100B is in a dark state, the "upper" row of subpixels (e.g., belonging to the first group of subpixel rows 100A) and "lower" row of subpixels (e.g., belonging to the first group of subpixel rows 100A) are both in a light-emitting state, thereby reducing the visual effect of the dark subpixel rows in the second group of subpixel rows 100B.

[0081] Furthermore, when the sub-pixel row in the first group of sub-pixel rows 100A is in a dark state, the sub-pixels in the "upper" row (e.g., belonging to the second group of sub-pixel rows 100B) and the sub-pixels in the "lower" row (e.g., belonging to the second group of sub-pixel rows 100B) of that sub-pixel row are in the luminous state of the previous frame, thereby reducing the visual effect of the dark sub-pixel rows in the first group of sub-pixel rows 100A.

[0082] Optional, nm≥2.

[0083] The inventors of this application have discovered through research that when the first group of sub-pixel rows 100A and the second group of sub-pixel rows 100B are driven sequentially, the difference between n and m affects the interval between the reset phase t1 of the sub-pixel row in the second group of sub-pixel rows 100B and the light emission phase t3 of its adjacent sub-pixel rows (such as those belonging to the first group of sub-pixel rows 100A). The larger the difference between n and m, the larger this interval.

[0084] For example Figure 12 As shown, Figure 12 This application provides another display panel driving timing diagram, taking n=7 and m=5 as an example. The driving sequence of the display panel can be as follows: Figure 9 As shown, in the first driving group 101, the first group of subpixel rows 100A includes odd-numbered rows of subpixels, and the second group of subpixel rows 100B includes even-numbered rows of subpixels. The second row of subpixels is the first row of subpixels in the second group of subpixel rows 100B. Figure 12 The interval Z1 between the reset phase t1 of the second row sub-pixels and the turn-on time of the emission phase t3 of the third row sub-pixels is relative to... Figure 3 The interval between the reset phase t1 of the second row of sub-pixels and the activation time of the emission phase t3 of the third row of sub-pixels is significantly increased. Figure 3 The start time of the reset phase t1 of the second row of sub-pixels overlaps with the start time of the emission phase t3 of the third row of sub-pixels. In this embodiment, setting nm≥2 increases the dark state period of a sub-pixel row and the interval between the dark state periods of its adjacent sub-pixel rows. This improves the reliability of adjacent rows of dark sub-pixel rows being in the luminous state, thereby enhancing the visual effect of weakening the prominence of dark sub-pixel rows.

[0085] Please continue to refer to this. Figure 1 In one embodiment of this application, the display panel 01 includes multiple data signal lines DL, which extend along a second direction Y and are arranged along a first direction X.

[0086] In the same drive group 100, the data signal line DL transmits data voltage sequentially to the first group of sub-pixel rows 100A and the second group of sub-pixel rows 100B.

[0087] For example, in the same driving group 100, the first group of subpixel rows 100A includes odd-numbered rows of subpixels, and the second group of subpixel rows 100B includes even-numbered rows of subpixels. The first group of subpixel rows 100A is driven before the second group of subpixel rows 100B. The same data signal line DL transmits data voltage to the odd-numbered rows of subpixels first, and then transmits data voltage to the even-numbered rows of subpixels.

[0088] In this embodiment, the data voltage transmitted by the data signal line DL can be matched with the driving mode of the sub-pixel row to ensure that each sub-pixel receives the correct data voltage, thereby ensuring the display effect of the display panel 01.

[0089] Figure 13 This is a schematic diagram of yet another display panel provided in an embodiment of this application. Figure 14 for Figure 13 A cascaded sequence diagram of a mid-shift register unit.

[0090] In one embodiment of this application, combined with Figure 13 and Figure 14 As shown, the display panel 01 includes a scanning circuit 20, which includes multiple cascaded shift register units 21. The multiple cascaded shift register units 21 form at least one scanning group 200, and the scanning group 200 is electrically connected to the driving group 100.

[0091] For example, such as Figure 13 As shown, the display panel 01 includes a display area AA and a non-display area NA surrounding the display area AA. Sub-pixels 10 are located in the display area AA, and the scanning circuit 20 is located in the non-display area NA on one side of the display area AA. The scanning circuit 20 is electrically connected to the sub-pixel row through the gate line SC, and the same sub-pixel row is electrically connected to the same gate line SC.

[0092] In this embodiment, the gate line SC can refer to any one of the first scan line S1, the second scan line S2, and the light emission control signal line EM.

[0093] The same scanning group 200 includes a first group of shift register units 200A and a second group of shift register units 200B. The first group of shift register units 200A is electrically connected to the first group of sub-pixel rows 100A, and the second group of shift register units 200B is electrically connected to the second group of sub-pixel rows 100B. The first group of shift register units 200A and the second group of shift register units 200B output scanning signals sequentially.

[0094] In this embodiment, the scanning group 200 can transmit scanning signals to the corresponding driving group 100, thereby driving the sub-pixel rows into the working process. Within the same scanning group 200, a first set of shift register units 200A is electrically connected to the first set of sub-pixel rows 100A, and a second set of shift register units 200B is electrically connected to the second set of sub-pixel rows 100B. Thus, the first set of shift register units 200A can drive the first set of sub-pixel rows 100A, and the second set of shift register units 200B can drive the second set of sub-pixel rows 100B. By having the first set of shift register units 200A and the second set of shift register units 200B sequentially output scanning signals, the first set of sub-pixel rows 100A and the second set of sub-pixel rows 100B in the same driving group 100 can be driven sequentially.

[0095] For example, such as Figure 14 As shown, the scanning circuit 20 includes multiple scanning groups 200. The number of scanning groups 200 can be the same as the number of driving groups 100. The multiple scanning groups 200 output scanning signals sequentially.

[0096] In this way, multiple scan groups 200 can sequentially drive their corresponding drive groups 100, thereby realizing the sequential driving of multiple drive groups 100 in the display panel 01.

[0097] Furthermore, in the corresponding connected scan group 200 and drive group 100, the number of shift register unit groups in the scan group 200 can be the same as the number of sub-pixel row groups. Multiple shift register unit groups can output scan signals in sequence to realize the sequential driving of each sub-pixel row in the corresponding drive group 100.

[0098] For example Figure 14 As shown, the first scan group 201 is electrically connected to the first drive group 101. The first drive group 101 includes two sub-pixel row groups, and the first scan group 201 includes two shift register unit groups.

[0099] In one embodiment of this application, such as Figure 13 As shown, multiple shift register units 21 are arranged sequentially along the second direction Y, and the number of the shift register units 21 is the same as the number of rows of the sub-pixel rows to which they are electrically connected. For example, the shift register unit 21 electrically connected to the i-th row sub-pixel 10_i is the i-th level shift register unit 21_i.

[0100] Combination Figure 14 As shown, in the same scan group 200, multiple shift register units 21 in the first group of shift register units 200A and multiple shift register units 21 in the second group of shift register units 200B are arranged alternately in the second direction Y.

[0101] In this embodiment of the application, the shift register units 21 in different shift register unit groups are arranged alternately, which is beneficial to make the shift register unit 21 and the sub-pixel row to which it is electrically connected have the same level, thereby reducing the difficulty of connecting the shift register unit 21 and the corresponding sub-pixel row.

[0102] For example, such as Figure 14 As shown, the first scan group 201 is electrically connected to the first drive group 101. In the first drive group 101, the first group of sub-pixel rows 100A includes odd-numbered rows of sub-pixels, and the second group of sub-pixel rows 100B includes even-numbered rows of sub-pixels.

[0103] In the first scan group 201, the shift register 21 in the first group of shift register units 200A is an odd-level shift register unit, and the shift register 21 in the second group of shift register units 200B is an even-level shift register unit.

[0104] In this way, odd-numbered shift register units can be electrically connected to odd-numbered row sub-pixels, and even-numbered shift register units can be electrically connected to even-numbered row sub-pixels. This helps to reduce the routing difficulty between the shift register unit 21 and the sub-pixel row it is electrically connected to, and facilitates the implementation of the first group of shift register units 200A driving the first group of sub-pixel rows 100A composed of odd-numbered row sub-pixels, and the second group of shift register units 200B driving the second group of sub-pixel rows 100B composed of even-numbered row sub-pixels. Please continue to refer to this. Figure 14 In one embodiment of this application, both the first group of shift register units 200A and the second group of shift register units 200B include multiple shift register units 21, and the multiple shift register units 21 are cascaded in the same group of shift register units.

[0105] In other words, in the first group of shift register units 200A, each shift register unit 21 is cascaded in sequence, and in the second group of shift register units 200B, each shift register unit 21 is cascaded in sequence.

[0106] The embodiments of this application facilitate the cascading order of the shift register units 21 to be the same as the driving order of the corresponding sub-pixel rows, thereby realizing the sequential driving of each group of sub-pixel rows.

[0107] Furthermore, within the same scan group 200, the last shift register in the first shift register group 200A is cascaded with the first shift register in the second shift register group 200B.

[0108] For example Figure 14As shown, the scanning circuit 20 includes multiple scanning groups 200, among which a first scanning group 201 is included. The first scanning group 201 can be used to drive the first driving group 101. The first scanning group 201 includes 14 cascaded shift register units. The odd-numbered shift register units form the first group of shift register units 200A, and the even-numbered shift register units form the second group of shift register units 200B. The 13th-level shift register unit is the last shift register unit in the first group of shift register units 200A, and the 2nd-level shift register unit is the first shift register unit in the second group of shift register units 200B.

[0109] In this configuration, odd-numbered shift register units are cascaded sequentially, and even-numbered shift register units are cascaded sequentially. Furthermore, the last shift register unit (i.e., the 13th shift register unit) in the first group of shift register units 200A is cascaded with the first shift register unit (i.e., the 2nd shift register unit) in the second group of shift register units 200B.

[0110] In the same scan group 200, the last shift register in the first shift register 200A is cascaded with the first shift register in the second shift register 200B. Then, the first shift register 200A and the second shift register 200B can be cascaded. After the shift register 21 in the first shift register 200A outputs the scan signal in sequence, the last shift register in the first shift register 200A can provide a trigger signal to the second shift register 200B, so that the shift register in the second shift register 200B can output the scan signal in sequence without the need to provide an additional trigger signal to the second shift register 200B.

[0111] This application also provides a driving method for a display panel 01, used to drive the display panel 01 provided in the above embodiments. The structure of the display panel 01 can be as follows: Figure 1 , Figure 13 As shown, the display panel 01 includes multiple sub-pixels 10. The i-th row of sub-pixels 10_i includes multiple sub-pixels 10 arranged along the first direction X. The multiple rows of sub-pixels 10 are arranged along the second direction Y, which intersects with the first direction X. Here, i is any positive integer.

[0112] For example, the first direction X is the row direction in the display panel 01, and the second direction Y is the column direction in the display panel 01.

[0113] The driving method includes: in a frame of the display panel 01, during the period when the sub-pixel 10_i+1 in the (i+1)th row is not emitting light, driving the sub-pixel 10_i in the (i+2)th row to emit light, and driving the sub-pixel 10_i+2 in the (i+2)th row to emit light.

[0114] For example, combining Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown, during the reset phase t1 and / or data writing phase t2 of sub-pixel 10_i+1 in row i+1, sub-pixel 10_i in row i is in the light emission phase t3, and sub-pixel 10_i+2 in row i+2 is in the light emission phase t3.

[0115] In the driving method provided in this application embodiment, at least for a portion of the time when the (i+1)th row sub-pixel 10_i+1 is in a dark state, the two rows of sub-pixels adjacent to it and located on opposite sides of it are driven to be in a light-emitting state. This is beneficial to prevent multiple rows of sub-pixels in the same area from darkening simultaneously, thereby reducing the visibility of the dark state of the (i+1)th row sub-pixel 10_i+1, weakening the difference between light and dark perceived by the human eye, and thus reducing the harm of the screen to the human eye, achieving the eye protection function of the display panel.

[0116] In one embodiment of this application, the driving method further includes: in a frame of the display panel 01, during a period when the (i+1)th row of sub-pixels 10_i+1 is not emitting light, driving at least two rows of sub-pixels on one side of the (i+1)th row of sub-pixels 10_i+1 and adjacent to it to emit light, and driving at least two rows of sub-pixels on the other side of the (i+1)th row of sub-pixels 10_i+1 and adjacent to it to emit light.

[0117] For example, combining Figure 1 , Figure 2 , Figure 3 and Figure 8 As shown, during the reset phase t1 and / or data writing phase t2 of sub-pixel 10_i+1 in row i+1, sub-pixel 10_i in row i and sub-pixel 10_i-1 in row i-1 are in the light-emitting phase t3, and sub-pixel 10_i+2 in row i+2 and sub-pixel 10_i+3 in row i+3 are in the light-emitting phase t3.

[0118] In this embodiment, during at least a portion of the time when the (i+1)th row of sub-pixels 10_i+1 is in a dark state, at least the two "upper" rows and at least the two "lower" rows of sub-pixels in the (i+1)th row of sub-pixels 10_i+1 are driven to be in a light-emitting state. This helps to further reduce the visibility of the dark state of the (i+1)th row of sub-pixels 10_i+1, thereby further weakening the difference between light and dark perceived by the human eye and improving the eye protection function of the display panel 01.

[0119] Combination Figure 1 and Figure 9As shown, in one embodiment of this application, multiple sub-pixel rows in the display panel 01 form at least one driving group 100. The same driving group 100 includes a first group of sub-pixel rows 100A and a second group of sub-pixel rows 100B. Multiple rows of sub-pixels in the first group of sub-pixel rows 100A and multiple rows of sub-pixels in the second group of sub-pixel rows 100B are alternately arranged in the second direction Y.

[0120] For example, the first group of subpixel rows 100A includes odd-numbered rows of subpixels, and the second group of subpixel rows 100B includes even-numbered rows of subpixels.

[0121] The driving method also includes: in a frame of the display panel 01, sequentially driving the first group of sub-pixel rows 100A and the second group of sub-pixel rows 100B.

[0122] In this embodiment, the sub-pixel rows in the first group of sub-pixel rows 100A are arranged alternately with the sub-pixel rows in the second group of sub-pixel rows 100B. By driving the first group of sub-pixel rows 100A and the second group of sub-pixel rows 100B in sequence, multiple sub-pixel rows in the same driving group 100 can be driven in an interleaved manner. This is beneficial for driving the i-th row of sub-pixels 10_i and the (i+2)-th row of sub-pixels 10_i+2 into the light-emitting stage t3 in sequence, and then driving the (i+1)-th row of sub-pixels 10_i+1 into the reset stage t1 or the data writing stage t2. This is beneficial for ensuring that when the (i+1)-th row of sub-pixels 10_i+1 is in a dark state, the two rows of sub-pixels adjacent to it and located on opposite sides of it can be in a light-emitting state, thereby reducing the visual effect of the (i+1)-th row of sub-pixels 10_i+1 being in a dark state.

[0123] Figure 15 This is a schematic diagram of a display device provided in an embodiment of this application.

[0124] This application provides a display device 02, such as... Figure 15 As shown, the display device 02 includes the display panel 01 as provided in the above embodiments. Exemplary examples show that the display device 02 can be an electronic device such as a mobile phone, computer, television, vehicle display, or wearable display, and this application does not impose any specific limitations.

[0125] In the display device 02, during the reset phase t1 and / or data writing phase t2 of the (i+1)th row sub-pixel 10_i+1, the (i)th row sub-pixel 10_i is set to be in the light-emitting phase t3, and the (i+2)th row sub-pixel 10_i+2 is also in the light-emitting phase t3. Then, during at least a portion of the time when the (i+1)th row sub-pixel 10_i+1 is in a dark state, the two rows of sub-pixels adjacent to it and located on opposite sides of it can be in a light-emitting state. This helps to prevent multiple rows of sub-pixels in the same area from darkening simultaneously, reduces the visibility of the dark state of the (i+1)th row sub-pixel 10_i+1, weakens the difference between light and dark perceived by the human eye, thereby reducing the harm of the screen to the human eye and realizing the eye protection function of the display panel.

[0126] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A display panel, characterized in that, It includes multiple sub-pixels, each sub-pixel including an electrically connected pixel circuit and a light-emitting device. The i-th row of sub-pixels includes multiple sub-pixels arranged along a first direction. Multiple rows of sub-pixels are arranged along a second direction, which intersects with the first direction. Here, i is any positive integer. One working cycle of the pixel circuit includes a reset phase, a data writing phase, and a light emission phase. During the reset phase and / or the data writing phase of the (i+1)th row sub-pixel, the (i)th row sub-pixel is in the light emission phase, and the (i+2)th row sub-pixel is in the light emission phase.

2. The display panel according to claim 1, characterized in that, During the reset phase and / or data writing phase of the (i+1)th row of sub-pixels, at least two rows of sub-pixels located on one side of the (i+1)th row of sub-pixels and adjacent to it are in the light-emitting phase, and at least two rows of sub-pixels located on the other side of the (i+1)th row of sub-pixels and adjacent to it are in the light-emitting phase.

3. The display panel according to claim 1, characterized in that, In the display panel, multiple sub-pixel rows form at least one driving group. The same driving group includes a first group of sub-pixel rows and a second group of sub-pixel rows. In one frame of the display panel, the first group of sub-pixel rows and the second group of sub-pixel rows are driven sequentially. In this configuration, multiple rows of sub-pixels in the first group of sub-pixel rows are alternately arranged with multiple rows of sub-pixels in the second group of sub-pixel rows in the second direction.

4. The display panel according to claim 3, characterized in that, The display panel includes multiple drive groups, which are driven sequentially.

5. The display panel according to claim 3, characterized in that, In the same driving group, the number of sub-pixel rows included in the first group of sub-pixel rows is the same as the number of sub-pixel rows included in the second group of sub-pixel rows; In this group, the sub-pixels in the first group of sub-pixel rows are odd-numbered rows, and the sub-pixels in the second group of sub-pixel rows are even-numbered rows.

6. The display panel according to claim 3, characterized in that, In the same group of subpixel rows (first group or second group), between two adjacent rows of subpixels in the second direction, there are at least two rows of subpixels that do not belong to that group of subpixel rows.

7. The display panel according to claim 3, characterized in that, The pixel circuit includes: Drive transistors; A power supply voltage writing module, wherein the input terminal of the power supply voltage writing module is electrically connected to the first power signal line, the output terminal is electrically connected to the first electrode of the driving transistor, and the control terminal is electrically connected to the light emission control signal line; The light-emitting control module has an input terminal electrically connected to the second electrode of the driving transistor, an output terminal electrically connected to the first electrode of the light-emitting device, and a control terminal electrically connected to the light-emitting control signal line. During the light-emitting stage, the light-emitting control signal line transmits an enable signal, and both the power supply voltage writing module and the light-emitting control module are in the on state. During the reset phase and the data writing phase, the light emission control signal line transmits an enable signal, and both the power supply voltage writing module and the light emission control module are in a turned-off state.

8. The display panel according to claim 7, characterized in that, In the same driving group, both the first group of sub-pixel rows and the second group of sub-pixel rows include n rows of sub-pixels; In a frame of the display panel, the time periods during which the light emission control signal lines in m rows of sub-pixels in the same group of sub-pixels transmit non-enabled signals overlap. Where n > m, and n and m are both positive integers.

9. The display panel according to claim 8, characterized in that, nm≥2.

10. The display panel according to claim 3, characterized in that, The display panel includes multiple data signal lines, which extend along the second direction and are arranged along the first direction. Within the same drive group, the data signal line sequentially transmits data voltage to the first group of sub-pixel rows and the second group of sub-pixel rows.

11. The display panel according to claim 3, characterized in that, The display panel includes a scanning circuit, which includes multiple cascaded shift register units. The multiple cascaded shift register units form at least one scanning group, and the scanning group is electrically connected to the driving group. The same scanning group includes a first group of shift register units and a second group of shift register units. The first group of shift register units is electrically connected to the first group of sub-pixels, and the second group of shift register units is electrically connected to the second group of sub-pixels. The first group of shift register units and the second group of shift register units output scanning signals sequentially.

12. The display panel according to claim 11, characterized in that, The scanning circuit includes multiple scanning groups, and the multiple scanning groups output scanning signals sequentially.

13. The display panel according to claim 11, characterized in that, Multiple shift register units are arranged along the second direction. In the same scanning group, multiple shift register units in the first group of shift register units are alternately arranged with multiple shift register units in the second group of shift register units in the second direction.

14. The display panel according to claim 13, characterized in that, The shift registers in the first group of shift registers are odd-level shift registers, while the shift registers in the second group of shift registers are even-level shift registers.

15. The display panel according to claim 11, characterized in that, In the same scan group, the last shift register in the first group of shift registers is cascaded with the first shift register in the second group of shift registers.

16. The display panel according to claim 11, characterized in that, Both the first group of shift register units and the second group of shift register units include multiple shift register units, and in the same group of shift register units, the multiple shift register units are cascaded in sequence.

17. The display panel according to claim 7, characterized in that, The pixel circuit also includes: The first reset module has an input terminal electrically connected to the first reset voltage signal line, an output terminal electrically connected to the gate of the driving transistor, and a control terminal electrically connected to the first scan line. The data writing module has an input terminal electrically connected to the data signal line, an output terminal electrically connected to the first electrode of the driving transistor, and a control terminal electrically connected to the second scan line. A threshold grasping module, wherein the input terminal of the threshold grasping module is electrically connected to the second electrode of the driving transistor, the output terminal is electrically connected to the gate of the driving transistor, and the control terminal is electrically connected to the second scan line; The second reset module has an input terminal electrically connected to the second reset voltage signal line, an output terminal electrically connected to the first electrode of the light-emitting device, and a control terminal electrically connected to the second scan line; in one working cycle of the pixel circuit, the data writing stage is performed after the reset stage; Specifically, the first reset module is activated during the reset phase, and the second reset module, the data writing module, and the threshold capture module are activated during the data writing phase.

18. A driving method for a display panel, characterized in that, The display panel is a display panel as described in any one of claims 1 to 17, the display panel includes a plurality of sub-pixels, the i-th row of sub-pixels includes a plurality of sub-pixels arranged along a first direction, the plurality of rows of sub-pixels are arranged along a second direction, the second direction intersects the first direction, and i is any positive integer; the method includes: In a frame of the display panel, during the period when the (i+1)th row of sub-pixels is not emitting light, the (i)th row of sub-pixels is driven to emit light, and the (i+2)th row of sub-pixels is driven to emit light.

19. The driving method according to claim 18, characterized in that, The method further includes: In a frame of the display panel, during the period when the (i+1)th row of sub-pixels is not emitting light, at least two rows of sub-pixels on one side of the (i+1)th row of sub-pixels and adjacent to it are driven to emit light, and at least two rows of sub-pixels on the other side of the (i+1)th row of sub-pixels and adjacent to it are driven to emit light.

20. The driving method according to claim 18, characterized in that, In the display panel, multiple sub-pixel rows form at least one driving group. The same driving group includes a first group of sub-pixel rows and a second group of sub-pixel rows. Multiple rows of sub-pixels in the first group of sub-pixel rows and multiple rows of sub-pixels in the second group of sub-pixel rows are alternately arranged in the second direction. The method further includes: In one frame of the display panel, the first group of sub-pixel rows and the second group of sub-pixel rows are driven sequentially.

21. A display device, characterized in that, Includes the display panel as described in any one of claims 1-17.

Images